Method of manufacturing a semiconductor product and manufacturing system

Abstract

The present disclosure provides a semiconductor product manufacturing method and a manufacturing system. The semiconductor product manufacturing method comprises: obtaining an abnormal position on a wafer; obtaining a distance value between the abnormal position and an edge of the wafer satisfying a preset condition as a target reference distance; and controlling the wafer to rotate to a target position according to the target reference distance, and the wafer enters a preset process environment along a path defined by the target reference distance from the target position. By controlling the distance value between the abnormal position on the wafer and the edge of the wafer to satisfy the preset condition, the path of the wafer entering the preset process environment from the target position is determined, so that the range of the influence of the abnormal position on other dies of the wafer is reduced during the wafer entering the preset process environment, and the yield loss of the dies on the wafer is reduced.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method and system for manufacturing a semiconductor product. Background Technology

[0002] In semiconductor manufacturing, photolithography is a crucial process for leaving patterns on semiconductor devices. When the wafer surface is uneven, it can cause localized focus shifts during photolithography exposure, resulting in localized defocusing anomalies in the exposed image. Even after rework fails due to wafer surface unevenness, subsequent processes are still performed. During these subsequent processes, the defocused anomalies become defect splash points, expanding the affected area and reducing product yield.

[0003] Currently, the path of wafers into subsequent processes is random, leading to uncontrollable losses in product yield. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method and system for manufacturing semiconductor products.

[0006] According to a first aspect of this disclosure, a method for manufacturing a semiconductor product is provided, the method comprising:

[0007] Identify the location of anomalies on the wafer;

[0008] The distance between the abnormal location and the edge of the wafer that meets the preset conditions is obtained and used as the target reference distance;

[0009] Based on the target reference distance, the wafer is controlled to rotate to the target position, and the wafer enters the preset process environment from the target position along the path defined by the target reference distance.

[0010] In some embodiments of this disclosure, obtaining a distance value between the abnormal location and the edge of the wafer that satisfies a preset condition, as a target reference distance, includes:

[0011] Obtain multiple reference distances between the abnormal location and the edge of the wafer;

[0012] Select the reference distance that meets the preset conditions from the plurality of reference distances as the target reference distance.

[0013] In some embodiments of this disclosure, selecting a reference distance from the plurality of reference distances that meets preset conditions as a target reference distance includes:

[0014] The reference distance with the smallest value among the plurality of reference distances is selected as the target reference distance.

[0015] In some embodiments of this disclosure, obtaining multiple reference distances between the abnormal location and the edge of the wafer includes:

[0016] Multiple reference distances are obtained between the abnormal location and the edge of the wafer along the extension direction of the dicing track of the wafer.

[0017] In some embodiments of this disclosure, the cutting path extends along a first preset direction and a second preset direction, the first preset direction being perpendicular to the second preset direction; the first preset direction includes a first direction and a second direction, the first direction being opposite to the second direction; the second preset direction includes a third direction and a fourth direction, the third direction being opposite to the fourth direction;

[0018] When there are multiple abnormal locations, multiple reference distances are obtained between the abnormal locations and the edge of the wafer, including:

[0019] The first distance, second distance, third distance, and fourth distance between each of the abnormal locations and the edge of the wafer along the first direction, the second direction, the third direction, and the fourth direction are obtained respectively;

[0020] A first reference distance is obtained by summing the first distances of the multiple abnormal locations, a second reference distance is obtained by summing the second distances of the multiple abnormal locations, a third reference distance is obtained by summing the third distances of the multiple abnormal locations, and a fourth reference distance is obtained by summing the fourth distances of the multiple abnormal locations.

[0021] In some embodiments of this disclosure, obtaining a distance value between the abnormal location and the edge of the wafer that satisfies a preset condition, as a target reference distance, includes:

[0022] A circle centered at the abnormal location is internally tangent to the wafer, and the distance between the tangent point and the abnormal location is used as the target reference distance.

[0023] In some embodiments of this disclosure, obtaining abnormal locations on the wafer includes:

[0024] Obtain the flatness data of the wafer;

[0025] Based on the flatness data, the abnormal locations on the wafer are obtained.

[0026] In some embodiments of this disclosure, the method for manufacturing the semiconductor product further includes:

[0027] Obtain the marking information on the wafer;

[0028] Based on the marking information, the wafer is rotated to a preset position.

[0029] In some embodiments of this disclosure, controlling the wafer to rotate to a target position based on the target reference distance includes:

[0030] Obtain the preset path for the wafer to enter the preset process environment;

[0031] The rotation angle is determined based on the target reference distance and the preset path;

[0032] The wafer is controlled to rotate from the preset position to the target position so that the path defined by the target reference distance is parallel to the preset path.

[0033] In some embodiments of this disclosure, the preset process environment includes a wet cleaning process.

[0034] In some embodiments of this disclosure, the method for manufacturing the semiconductor product further includes:

[0035] The wafer is immersed in the cleaning machine of the wet cleaning process from the edge of the wafer along the path defined by the target reference distance from the target position, and then detaches from the cleaning machine from the edge of the wafer along the path defined by the target reference distance.

[0036] According to a second aspect of this disclosure, a semiconductor product manufacturing system is provided, the semiconductor product manufacturing system including a control device, the control device comprising:

[0037] The acquisition module is used to acquire abnormal locations on the wafer;

[0038] The processing module is used to obtain a distance value between the abnormal location and the edge of the wafer that meets a preset condition, as a target reference distance;

[0039] The control module is used to control the wafer to rotate to a target position according to the target reference distance, and to control the wafer to enter the preset process environment from the target position along the path defined by the target reference distance.

[0040] In some embodiments of this disclosure, the semiconductor product manufacturing system further includes a silicon wafer sorting machine, which is electrically connected to the control device and is used to drive the wafer to rotate to the target position and / or rotate to a preset position.

[0041] In some embodiments of this disclosure, the semiconductor product fabrication system further includes a lithography machine electrically connected to the control device, the lithography machine sending wafer flatness data to the control device.

[0042] In some embodiments of this disclosure, the semiconductor product manufacturing system further includes a cleaning machine for performing a wet cleaning process.

[0043] The semiconductor product manufacturing method and system disclosed herein control the distance between abnormal locations on the wafer and the edge of the wafer to meet preset conditions, thereby determining the path of the wafer from the target location into the preset process environment. This reduces the range of impact of abnormal locations on other dies on the wafer during the process of entering the preset process environment, thereby reducing the yield loss of dies on the wafer.

[0044] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of these embodiments. In these drawings, similar reference numerals are used to denote similar elements. The drawings described below are some embodiments of the present disclosure, but not all embodiments. Other drawings will be readily available to those skilled in the art based on these drawings without inventive effort.

[0046] Figure 1 It is a defect distribution map of a wafer.

[0047] Figure 2 It is a defect distribution map of a wafer.

[0048] Figure 3 This is a flowchart illustrating a method for manufacturing a semiconductor product according to an exemplary embodiment.

[0049] Figure 4 This is a schematic diagram illustrating the acquisition of a reference distance for a wafer according to an exemplary embodiment.

[0050] Figure 5 This is a schematic diagram illustrating the acquisition of a reference distance for a wafer according to an exemplary embodiment.

[0051] Figure 6 This is a schematic diagram illustrating the acquisition of a reference distance for a wafer according to an exemplary embodiment.

[0052] Figure 7 This is a schematic diagram illustrating the acquisition of a reference distance for a wafer according to an exemplary embodiment.

[0053] Figure 8 This is a schematic diagram illustrating a wafer entering a preset process environment according to an exemplary embodiment.

[0054] Figure 9 This is a schematic block diagram of a semiconductor product manufacturing system according to an exemplary embodiment. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the embodiments of this disclosure without creative effort are within the scope of protection of this disclosure. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0056] In semiconductor manufacturing, photolithography is a crucial process for leaving patterns on semiconductor devices. When the wafer surface is uneven, it can cause localized focus shifts during photolithography exposure, resulting in localized defocusing in the exposed image. Even after rework fails due to wafer surface unevenness, subsequent processes are still performed in the production process. These subsequent processes include, for example, cleaning. (See reference...) Figure 1 As shown, when the wafer enters the cleaning process along the path in direction a, the abnormal position E will become the point of defect spillage, which will affect the bare wafers in range A and lead to a decrease in product yield.

[0057] In related technologies, the path of a wafer into subsequent processes is random, as referenced. Figure 2 As shown, the wafer enters the cleaning process along the path in direction b, which affects the bare wafers within range B. Figure 1 and Figure 2 The abnormal position E in the wafer is in the same position on the wafer, but enters the cleaning process in different directions. This results in different numbers of bare wafers in range B and range A, meaning that the influence range of abnormal position E is different, and the product yield loss is uncontrollable.

[0058] In view of this, an exemplary embodiment of the present disclosure provides a method for manufacturing a semiconductor product, including: acquiring an abnormal location on a wafer; obtaining a distance value between the abnormal location and the edge of the wafer that satisfies a preset condition, as a target reference distance; and controlling the wafer to rotate to a target position according to the target reference distance, wherein the wafer enters a preset process environment from the target position along a path defined by the target reference distance. By controlling the distance value between the abnormal location on the wafer and the edge of the wafer to satisfy the preset condition, the path of the wafer entering the preset process environment from the target position is determined, thereby reducing the range of impact of the abnormal location on other dies on the wafer during the process of entering the preset process environment, and reducing the yield loss of dies on the wafer.

[0059] In one exemplary embodiment of this disclosure, a method for manufacturing a semiconductor product is provided, with reference to... Figure 3 As shown, Figure 3 This is a flowchart illustrating an exemplary embodiment of a method for manufacturing a semiconductor product, the method comprising the following steps:

[0060] Step S100: Obtain the location of the abnormality on the wafer;

[0061] Step S200: Obtain the distance value between the abnormal location and the edge of the wafer that meets the preset conditions, and use it as the target reference distance;

[0062] Step S300: Based on the target reference distance, control the wafer to rotate to the target position, and the wafer enters the preset process environment from the target position along the path defined by the target reference distance.

[0063] The semiconductor product manufacturing method in this embodiment can be applied to a semiconductor product manufacturing system, such as a control device for a semiconductor product manufacturing system. The control device is used to execute the method in this embodiment to control the wafer to rotate to the target position.

[0064] In step S100, during the wafer photolithography process, the surface of the wafer and the surface of the wafer stage need to be kept clean. However, when there is dirt on the surface of the wafer or the stage, it can lead to inaccurate focusing during the exposure process, resulting in localized defocusing in the exposed image. Obtaining the abnormal location on the wafer can involve identifying the location of the defocused abnormal pattern. In this embodiment, for example, a pattern scanning device can scan all patterns after wafer exposure and identify abnormal patterns, allowing the control device to obtain the abnormal location; alternatively, a sensor can detect the location of dirt on the wafer or the stage to calculate the position of the abnormal pattern on the wafer, allowing the control device to obtain the abnormal location on the wafer. By obtaining the position of the abnormal pattern on the wafer, the path or direction of the wafer entering the preset process environment can be calculated and adjusted. It is understood that there can be one or more locations on the wafer.

[0065] In step S200, since a wafer comprises multiple uncuttered dies, and its shape is generally circular, the outermost ring of dies can be considered the wafer's edge. A pattern scanning device is used to scan the wafer, measuring the distance between the abnormal location and the wafer's edge. This distance is compared to preset conditions, and the distance that meets the preset conditions is used as the target reference distance. This allows for adjusting the path or direction of the wafer as it enters the preset process environment. The preset conditions can be pre-set by technicians within the semiconductor manufacturing system. These conditions minimize the impact on wafer yield after entering the preset process environment; for example, they could be the minimum or maximum distance between the abnormal location and the wafer's edge. By controlling the target reference distance to meet the preset conditions, yield losses in subsequent process environments can be reduced.

[0066] In step S300, the wafer is rotated according to the target reference distance to adjust the distances between the abnormal position of the wafer, the edge position of the wafer, and the preset process environment, thereby determining the path for the wafer to enter the preset process environment, i.e., the path defined by the target reference distance. The target position can be, for example, the position of the wafer edge after adjustment based on the target reference distance. The preset process can be, for example, the next process after the current process is completed. For example, if the current process is wafer exposure, the preset process is the development process. In this embodiment, the wafer enters the preset process environment from the target position along the path defined by the target reference distance. For example, this can be achieved by controlling the edge of the wafer that meets the target reference distance to first enter the developing solution, and then controlling the entire wafer to be immersed in the developing solution along the path from the edge that meets the target reference distance to the abnormal position.

[0067] The wafer is rotated to the target position so that the edge of the wafer corresponding to the target reference distance enters the preset process environment first. This reduces the range of impact of defocusing abnormal patterns at abnormal positions on other dies on the wafer during the preset process environment, thereby reducing the yield loss of dies on the wafer.

[0068] In some possible implementations, step S200, obtaining a distance value between the abnormal location and the edge of the wafer that meets a preset condition, as a target reference distance, includes:

[0069] Step S210: Obtain multiple reference distances between the abnormal location and the edge of the wafer;

[0070] Step S220: Select the reference distance that meets the preset conditions from multiple reference distances as the target reference distance.

[0071] In step S210, multiple reference distances between the abnormal location and the edge of the wafer are obtained. For example, a pattern scanning device can be used to measure the distances between the abnormal location and the locations of multiple outermost dies on the wafer, respectively, to serve as multiple reference distances. By obtaining multiple reference distances, a target reference distance that meets preset conditions can be determined.

[0072] In step S220, multiple reference distances are compared with preset conditions, and the reference distance that meets the preset conditions is taken as the target reference distance. The preset conditions are those that minimize the impact on wafer yield after the wafer enters the preset process environment. For example, it could be the minimum or maximum distance between the abnormal location and the wafer edge. For instance, multiple reference distances can be compared, and the reference distance that meets the preset conditions can be selected as the target reference distance.

[0073] In some possible implementations, step S220, selecting a reference distance that meets a preset condition from multiple reference distances as the target reference distance, includes: selecting the reference distance with the smallest value from multiple reference distances as the target reference distance.

[0074] In this embodiment, when the distance between the abnormal location on the wafer and the edge of the wafer is minimized, the number of dies between the abnormal location and the edge of the wafer is minimized. At this time, the reference distance meets the preset condition and is used as the target reference distance. That is, multiple obtained reference distances are compared with each other, and the reference distance with the smallest value among the multiple reference distances is used as the target reference distance. When the wafer enters the preset process environment along the path defined by the target reference distance, that is, when the wafer enters the preset process environment along the direction with the smallest distance between the abnormal location and the edge of the wafer, the range of the defocused abnormal pattern at the abnormal location affecting other dies on the wafer can be reduced, thereby reducing the yield loss of dies on the wafer.

[0075] In some possible implementations, the reference distance with the largest value among multiple reference distances can be selected as the target reference distance. That is, the multiple obtained reference distances are compared, and the reference distance with the largest value is selected as the target reference distance. For example, in some processes, when there are abnormal patterns on the wafer, the wafer's detachment path from the process environment can affect the yield of the dies on the wafer. That is, the fewer dies between the abnormal location and the edge of the wafer when detaching from the process environment, the less yield loss of the wafer dies. In this case, when the wafer enters the preset process environment along the direction with the largest distance between the abnormal location and the edge of the wafer, the distance between the abnormal location and the edge of the wafer can be minimized when the wafer detaches from the preset process environment. This reduces the range of influence of the defocused abnormal pattern at the abnormal location on other dies on the wafer, thereby reducing the yield loss of the dies on the wafer.

[0076] In some possible implementations, step S210, obtaining multiple reference distances between the abnormal location and the edge of the wafer, includes:

[0077] Obtain multiple reference distances between the abnormal location and the edge of the wafer along the extension direction of the wafer dicing track.

[0078] Since a wafer comprises multiple arrayed dies, the channels formed by the gaps between these dies are called dicing channels. When dicing the wafer to separate each die, the dicing process is performed along these channels. In this embodiment, a pattern scanning device is used to measure multiple reference distances between the abnormal location and the wafer edge along the extension direction of the dicing channels. This ensures that the obtained target reference distance is also along the extension direction of the dicing channels, and simultaneously, the path of the wafer from the target location into the preset process environment is also along the extension direction of the dicing channels. Because the dies are arranged in an array, when the wafer enters the preset process environment along the extension direction of the dicing channels and in the direction with the minimum distance between the abnormal location and the wafer edge, the liquid in the preset process environment can wet the wafer from the edge along the dicing channels, preventing the liquid in the preset process environment from spreading irregularly on the wafer. This reduces the impact range of the abnormal pattern on the wafer and minimizes the yield loss of the dies.

[0079] In some possible implementations, refer to Figure 4 As shown, the cutting path extends along a first preset direction and a second preset direction, with the first preset direction being perpendicular to the second preset direction; the first preset direction includes a first direction and a second direction, with the first direction being opposite to the second direction; the second preset direction includes a third direction and a fourth direction, with the third direction being opposite to the fourth direction.

[0080] Since the die array is disposed on the wafer, the extension direction of the dicing track, i.e., the first preset direction and the second preset direction, can be the arrangement direction of the dies on the wafer, for example, it can be the vertical arrangement direction or the horizontal arrangement direction, respectively. (Reference) Figure 4 For example, the first preset direction and the second preset direction are Figure 4 The X or Y direction is shown in the diagram. In this embodiment, for ease of explanation, the X direction is taken as the first preset direction, and the Y direction as the second preset direction. The first and second preset directions are perpendicular to each other. Using the abnormal position E of the wafer as a reference point, the first preset direction includes a first direction and a second direction, with opposite extension directions. For example, the first direction is the leftward direction in the X direction starting from the abnormal position E of the wafer, and the second direction is the rightward direction in the X direction starting from the abnormal position E of the wafer. It can be understood that, using the abnormal position E of the wafer as a reference point, the second preset direction includes a third direction and a fourth direction, with opposite extension directions. For example, the third direction is the upper direction in the Y direction starting from the abnormal position E of the wafer, and the fourth direction is the lower direction in the Y direction starting from the abnormal position E of the wafer.

[0081] In some embodiments, when there is only one abnormal location on the wafer, four reference distances X1, X2, Y1, and Y2 are obtained between the abnormal location and the edge of the wafer along the first, second, third, and fourth directions, respectively. These four reference distances are compared with each other, and the distance that satisfies a preset condition is taken as the target reference distance. For example, in some embodiments, distance X2 is the minimum value that satisfies the preset condition, and distance X2 is taken as the target reference distance. At this time, the wafer is rotated so that the distance between the edge of the wafer corresponding to distance X2 and the preset process environment is minimized (i.e., the wafer is rotated to the target position). This ensures that when the wafer enters the preset process environment, the edge of the wafer corresponding to distance X2 enters the preset process environment first, followed by the abnormal location, and then the entire wafer is controlled to enter the preset process environment.

[0082] In other embodiments, distance X1 is the maximum value satisfying a preset condition, and distance X2 is used as the target reference distance. In this case, the wafer is rotated to minimize the distance between the edge of the wafer corresponding to distance X1 and the preset process environment (i.e., the wafer is rotated to the target position). When the wafer enters the preset process environment, the edge of the wafer corresponding to distance X1 enters the preset process environment first, followed by the abnormal location. Then, the entire wafer is controlled to enter the preset process environment, so that when the wafer leaves the preset process environment, the distance between the abnormal location and the edge of the wafer is minimized.

[0083] In some possible implementations, when there are multiple anomalous locations, step S210 involves obtaining multiple reference distances between the anomalous locations and the edge of the wafer, including:

[0084] The first distance, second distance, third distance, and fourth distance between each abnormal location and the edge of the wafer along the first direction, second direction, third direction, and fourth direction are obtained respectively;

[0085] The first reference distance is obtained by summing the first distances of multiple abnormal locations, the second reference distance is obtained by summing the second distances of multiple abnormal locations, the third reference distance is obtained by summing the third distances of multiple abnormal locations, and the fourth reference distance is obtained by summing the fourth distances of multiple abnormal locations.

[0086] In this embodiment, reference Figure 5 As shown, since there are multiple abnormal locations on the wafer, it is necessary to calculate the distances of each abnormal location from the wafer edge to calculate the target reference distance that minimizes the impact on wafer yield. For example, when there are two abnormal locations, the distances between the first abnormal location E1 and the second abnormal location E2 and the wafer edge along the first direction, the second direction, the third direction, and the fourth direction are obtained. The first distance, second distance, third distance, and fourth distance of the first abnormal location E1 are denoted as X11, X12, Y11, and Y12, respectively, and the first distance, second distance, third distance, and fourth distance of the second abnormal location E2 are denoted as X21, X22, Y21, and Y22, respectively.

[0087] Because the impact range of multiple abnormal locations on other dies on the wafer needs to be referenced during the wafer's entry into the preset process environment, the distances obtained in the same direction from multiple abnormal locations are summed, and the summed distance value is used as the reference distance for multiple abnormal locations. For example, the first distance X11 of the first abnormal location E1 and the first distance X21 of the second abnormal location E2 are summed as the first reference distance D1 between the abnormal location along the first direction and the edge of the wafer, i.e., D1 = X11 + X21. The second reference distance D2 = X12 + X22, the third reference distance D3 = Y11 + Y21, and the fourth reference distance D4 = Y12 + Y22 are obtained in a similar manner. Based on the first reference distance D1, the second reference distance D2, the third reference distance D3, and the fourth reference distance D4, the reference distance that meets the preset conditions is selected as the target reference distance.

[0088] In other embodiments, the average of first distances between multiple anomalous locations can be calculated as a first reference distance, the average of second distances between multiple anomalous locations can be calculated as a second reference distance, the average of third distances between multiple anomalous locations can be calculated as a third reference distance, and the average of fourth distances between multiple anomalous locations can be calculated as a fourth reference distance. For example, when there are two anomalous locations on the wafer, the reference distance can be... Figure 5 As shown, the average of the first distance X11 of the first anomaly position E1 and the first distance X21 of the second anomaly position E2 is calculated as the first reference distance D1, i.e., D1 = (X11 + X21) / 2. Similarly, by calculating the average of multiple distances between multiple anomaly positions and the wafer edge along the same direction, the second reference distance D2 = (X12 + X22) / 2, the third reference distance D3 = (Y11 + Y21) / 2, and the fourth reference distance D4 = (Y12 + Y22) / 2 are obtained. The reference distance that satisfies the preset conditions is selected as the target reference distance.

[0089] In some embodiments, for example, a second reference distance D2 with the smallest distance value is selected as the target reference distance, satisfying a preset condition. In other embodiments, for example, a fourth reference distance D4 with the largest distance value is selected as the target reference distance, satisfying a preset condition. Further, based on the target reference distance, a direction for controlling wafer rotation is determined to rotate the wafer to a target position, thereby reducing the range of impact of the defocused abnormal pattern at the abnormal position on other dies on the wafer, and thus reducing the yield loss of dies on the wafer.

[0090] In one exemplary embodiment, reference Figure 6 and Figure 7 As shown, in step S200, obtaining the distance value between the abnormal location and the edge of the wafer that meets preset conditions, as the target reference distance, includes:

[0091] A circle centered at the anomaly location is internally tangent to the wafer, and the distance between the tangent point and the anomaly location is used as the target reference distance.

[0092] In this embodiment, circles C1 and C2 are obtained by drawing circles with the abnormal position E as the center. Circle C1 is located inside the circular circle formed by the wafer, and the fifth reference distance D5 between the tangent point of circle C1 and the wafer and the abnormal position E is the minimum value from the abnormal position E to the edge of the wafer. The circular circle formed by the wafer is located inside circle C2, and the sixth reference distance D6 between the tangent point of circle C2 and the wafer and the abnormal position E is the maximum value from the abnormal position E to the edge of the wafer. In some embodiments, when the fifth reference distance D5, which has the smallest reference distance, is selected as the target reference distance value, the wafer is controlled to rotate so that the tangent point of circle C1 and the wafer rotates to the target position, and the wafer is controlled to enter the preset process environment from the target position along the direction from the tangent point of circle C1 and the wafer to the abnormal position E. In other embodiments, when the sixth reference distance D6 with the largest reference distance is selected as the target reference distance value, the wafer is controlled to rotate so that the tangent point between circle C2 and the wafer rotates to the target position, and the wafer is controlled to enter the preset process environment from the target position along the direction from the tangent point between circle C2 and the wafer to the abnormal position E.

[0093] In an exemplary embodiment, step S100, obtaining the abnormal location on the wafer, includes:

[0094] Step S110: Obtain wafer flatness data;

[0095] Step S120: Based on the flatness data, obtain the abnormal locations on the wafer.

[0096] In step S110, wafer flatness data is acquired, for example, by scanning the wafer surface with an image scanning device to determine the location of unevenness defects on the wafer and obtain flatness data. The image scanning device can be a standalone image scanning device or an image scanning device mounted on a lithography machine. Unevenness defects on the wafer can be, for example, wafer bumps caused by dirt adhering to the wafer surface, or wafer depressions caused by wafer process defects, etc., and this disclosure does not limit the scope of the defects.

[0097] In step S120, since the unevenness on the wafer can cause the focus of the process to shift, resulting in local defocusing of the exposed image, the location of the abnormal pattern caused by the defocusing can be calculated based on the wafer flatness data to obtain the abnormal location on the wafer.

[0098] In one exemplary embodiment, the method for manufacturing a semiconductor product further includes:

[0099] Step S410: Obtain the marking information on the wafer;

[0100] Step S420: Rotate the wafer to the preset position according to the marking information.

[0101] In this embodiment, the wafer marking information is used to precisely place the wafer at the processing location to facilitate subsequent processing steps. The wafer marking information may include, for example, the wafer's centroid and a positioning notch located at the wafer's edge. The wafer's centroid is the center of the circle formed by the wafer, and the positioning notch is located at the wafer's edge, such as a flat corner formed by a flat edge. During the wafer manufacturing process, equipment in the semiconductor product manufacturing system can correct the wafer's position based on the marking information. For example, the wafer can be rotated so that the wafer's centroid and / or the positioning notch are rotated to a designated position, thereby rotating the wafer to a preset position. The preset position can be the position where the wafer's edge is closest to a preset process environment after the technician corrects and rotates the wafer according to the marking information, based on the semiconductor process requirements, so that the wafer can enter the preset process environment.

[0102] In some possible implementations, step S300, controlling the wafer to rotate to the target position based on the target reference distance, includes:

[0103] Step S310: Obtain the preset path for the wafer to enter the preset process environment;

[0104] Step S320: Determine the rotation angle based on the target reference distance and the preset path;

[0105] Step S330: Control the wafer to rotate from the preset position to the target position so that the path defined by the target reference distance is parallel to the preset path.

[0106] In step S310, after the wafer completes the exposure process and is rotated to a preset position, it is fed into a preset process environment using equipment such as a robotic arm. In other words, the preset path for the wafer to enter the preset process environment is the same as the path from the preset position to the preset process environment. For example, when the preset position is where the wafer's positioning notch is closest to the preset process environment on the support platform, the preset path for the wafer to enter the preset process environment is as follows: the wafer edge where the positioning notch is located first enters the preset process environment, and then continues along the direction from the positioning notch to the wafer edge on the opposite side of the positioning notch. Obtaining the preset path for the wafer to enter the preset process environment can be achieved, for example, by obtaining the preset position of the wafer rotation and calculating based on that position.

[0107] In step S320, based on the target reference distance, which could be, for example, the closest or furthest distance between an abnormal location on the wafer and its edge, the abnormal location of the wafer and the wafer edge corresponding to the target reference distance can be determined. Based on the wafer edge corresponding to the preset path and the wafer edge corresponding to the target reference distance, the angle between them can be determined, with the wafer's centroid as the reference point. For example, when the wafer edge corresponding to the preset path is a positioning notch on the wafer, and the wafer edge corresponding to the target reference distance is on the opposite side of the positioning notch, the angle between them is 180°.

[0108] In step S330, the wafer is controlled to rotate from a preset position to a target position. Taking the above embodiment as an example, the wafer can be controlled to rotate 180° to rotate the edge of the wafer corresponding to the target reference distance to the edge of the wafer corresponding to the positioning notch of the original wafer, i.e., rotated to the target position. At this time, the path defined by the target reference distance is that the wafer first enters the preset process environment from the target position, i.e., the edge of the wafer corresponding to the target reference distance, and then enters the preset process environment along the direction from the edge of the wafer corresponding to the target reference distance to the abnormal position. That is, the path defined by the target reference distance is parallel to the preset path.

[0109] In some possible implementations, the preset process environment may include, for example, a wet cleaning process. A wet cleaning process is a process that uses liquid to clean the wafer. In some embodiments, the wet cleaning process is a developing process. The preset process environment may include a developer, such as tetramethylammonium hydroxide (TMAH), butyl acetate or ethanol, trichloroethylene, etc. After the wafer enters the developing process, the developer reacts with the exposed photoresist on the wafer surface, exposing the exposed pattern on the wafer to facilitate subsequent etching and other processes.

[0110] In some possible implementations, the method for manufacturing a semiconductor product further includes:

[0111] Step S510: The wafer is immersed in the cleaning machine of the wet cleaning process from the edge of the wafer along the path defined by the target reference distance from the target position, and then detached from the cleaning machine from the edge of the wafer along the path defined by the target reference distance.

[0112] refer to Figure 8As shown, the path of the wafer from the target location along the target reference distance is the path from the edge of the wafer corresponding to the target reference distance to the abnormal location. The edge of the wafer corresponding to the target reference distance is first immersed in the cleaning machine of the wet cleaning process, and the abnormal location subsequently enters the cleaning machine along the same path. Finally, the entire wafer enters the wet process environment. The cleaning machine performs wet cleaning on the wafer. After cleaning, the edge of the wafer corresponding to the target reference distance first leaves the cleaning machine, and the abnormal location subsequently leaves the cleaning machine along the same path. Finally, the entire wafer leaves the wet process environment. That is, the path of the wafer leaving the wet cleaning process is the same as the path of the wafer entering the wet cleaning process, which is also the path defined by the target reference distance. This reduces the range of influence of the defocused abnormal pattern at the abnormal location on the wafer on other dies, thereby reducing the yield loss of dies on the wafer.

[0113] In one exemplary embodiment, this disclosure provides a semiconductor product manufacturing system 100, with reference to... Figure 9 As shown, the semiconductor product fabrication system 100 is used to perform semiconductor processing of wafers. The semiconductor product fabrication system 100 includes one or more semiconductor devices, such as a control device 102. The control device 102 may be a controller or a processor. The control device 102 is used to acquire data in the corresponding devices, execute the semiconductor product fabrication method described in the above embodiments, and send control signals to the corresponding devices. The control device 102 includes:

[0114] The acquisition module is used to acquire abnormal locations on the wafer;

[0115] The processing module is used to obtain the distance value between the abnormal location and the edge of the wafer that meets the preset conditions, as the target reference distance;

[0116] The control module is used to control the wafer to rotate to the target position according to the target reference distance, and to control the wafer to enter the preset process environment from the target position along the path defined by the target reference distance.

[0117] The implementation of the control device 102 is similar to the implementation described in the above embodiments, and will not be repeated here.

[0118] In some possible implementations, refer to Figure 9 The semiconductor product manufacturing system 100 also includes a silicon wafer sorting machine 104, which is electrically connected to the control device 102. The silicon wafer sorting machine 104 is used to drive the wafer to rotate to the target position and / or rotate to the preset position.

[0119] The silicon wafer sorting machine 104 may be, for example, a silicon wafer guide machine. The silicon wafer sorting machine 104 includes mechanical devices, such as a robotic arm. The silicon wafer sorting machine 104 is electrically connected to the control device 102, for example, through a physical connection or an electromagnetic coupling connection. According to the settings of the semiconductor product manufacturing system 100, the silicon wafer sorting machine 104 can first rotate the wafer to a preset position, and then, according to the control signals sent by the control device 102, rotate the wafer to a target position. In some embodiments, the silicon wafer sorting machine 104 can also drive the wafer from the target position along a path defined by a target reference distance into a preset process environment to reduce the yield loss of bare dies on the wafer.

[0120] In some possible implementations, refer to Figure 9 The semiconductor product manufacturing system 100 also includes a lithography machine 106, which is electrically connected to a control device 102. The lithography machine 106 sends wafer flatness data to the control device 102.

[0121] The lithography machine 106 is used to perform photolithography processes on wafers, such as exposure processes. The lithography machine 106 is electrically connected to the control device 102, for example, through a physical connection or electromagnetic coupling. The lithography machine 106 can also accurately measure the wafer's thickness, surface flatness, contamination, size, and perpendicularity using camera imaging principles, image detection technology, laser, infrared, and capacitive coupling technologies, and transmit the wafer flatness data to the control device 102. The lithography machine 106 can also measure the reference distance between abnormal locations on the wafer and the wafer edge to calculate the target reference distance, and transmit this data to the control device 102.

[0122] In some possible implementations, refer to Figure 9 The semiconductor product manufacturing system 100 also includes a cleaning machine 108, which is used to perform a wet cleaning process.

[0123] The cleaning machine 108 can be a developing machine, which may include a power system, a developing solution tank, a spray pipe, a water washing tank, a temperature control system, etc. The developing machine is used to perform a wet cleaning process, such as placing developing solution in the developing solution tank so that the wafer can enter the developing solution tank for wet cleaning. The developing solution reacts with the exposed photoresist on the wafer surface, exposing the pattern on the wafer after exposure, so that subsequent etching and other processes can be performed.

[0124] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0125] In the description of this specification, references to the terms "embodiment," "exemplary embodiment," "some implementation," "illustrated implementation," "example," etc., refer to specific features, structures, materials, or characteristics described in connection with an implementation or example that are included in at least one implementation or example of this disclosure.

[0126] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0127] In the description of this disclosure, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this disclosure.

[0128] It is understood that the terms "first," "second," etc., as used in this disclosure may be used to describe various structures, but these structures are not limited by these terms. These terms are only used to distinguish one structure from another.

[0129] In one or more accompanying drawings, the same elements are represented by similar reference numerals. For clarity, many parts in the drawings are not drawn to scale. Furthermore, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be depicted in a single drawing. Many specific details of this disclosure, such as the structure, materials, dimensions, processing methods, and techniques of the devices, are described below to provide a clearer understanding of the disclosure. However, as those skilled in the art will understand, this disclosure may be implemented without adhering to these specific details.

[0130] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. A method for manufacturing a semiconductor product, characterized in that, The method for manufacturing the semiconductor product includes: Identify the location of anomalies on the wafer; Obtain the marking information on the wafer; Obtain the distance value between the abnormal location and the edge of the wafer that meets the preset conditions, and use it as the target reference distance; rotate the wafer to the preset position according to the marking information; Based on the target reference distance, the wafer is controlled to rotate to the target position, and the wafer enters the preset process environment from the target position along the path defined by the target reference distance; The process of controlling the wafer to rotate to the target position based on the target reference distance includes: Obtain the preset path for the wafer to enter the preset process environment; The rotation angle is determined based on the target reference distance and the preset path; The wafer is controlled to rotate from the preset position to the target position so that the path defined by the target reference distance is parallel to the preset path.

2. The method for manufacturing a semiconductor product according to claim 1, characterized in that, Obtaining a distance value between the abnormal location and the edge of the wafer that meets preset conditions, as a target reference distance, includes: Obtain multiple reference distances between the abnormal location and the edge of the wafer; Select the reference distance that meets the preset conditions from the plurality of reference distances as the target reference distance.

3. The method for manufacturing a semiconductor product according to claim 2, characterized in that, Selecting the reference distance from the plurality of reference distances that meets preset conditions as the target reference distance includes: The reference distance with the smallest value among the plurality of reference distances is selected as the target reference distance.

4. The method for manufacturing a semiconductor product according to claim 3, characterized in that, Obtaining multiple reference distances between the abnormal location and the edge of the wafer includes: Multiple reference distances are obtained between the abnormal location and the edge of the wafer along the extension direction of the dicing track of the wafer.

5. The method for manufacturing a semiconductor product according to claim 4, characterized in that, The cutting channel extends along a first preset direction and a second preset direction, the first preset direction being perpendicular to the second preset direction; the first preset direction includes a first direction and a second direction, the first direction being opposite to the second direction; the second preset direction includes a third direction and a fourth direction, the third direction being opposite to the fourth direction; When there are multiple abnormal locations, multiple reference distances are obtained between the abnormal locations and the edge of the wafer, including: The first distance, second distance, third distance, and fourth distance between each of the abnormal locations and the edge of the wafer along the first direction, the second direction, the third direction, and the fourth direction are obtained respectively; A first reference distance is obtained by summing the first distances of the multiple abnormal locations, a second reference distance is obtained by summing the second distances of the multiple abnormal locations, a third reference distance is obtained by summing the third distances of the multiple abnormal locations, and a fourth reference distance is obtained by summing the fourth distances of the multiple abnormal locations.

6. The method for manufacturing a semiconductor product according to claim 1, characterized in that, Obtaining a distance value between the abnormal location and the edge of the wafer that meets preset conditions, as a target reference distance, includes: A circle centered at the abnormal location is internally tangent to the wafer, and the distance between the tangent point and the abnormal location is used as the target reference distance.

7. The method for manufacturing a semiconductor product according to claim 1, characterized in that, To identify the location of anomalies on the wafer, including: Obtain the flatness data of the wafer; Based on the flatness data, the abnormal locations on the wafer are obtained.

8. The method for manufacturing a semiconductor product according to claim 1, characterized in that, The preset process environment includes a wet cleaning process.

9. The method for manufacturing a semiconductor product according to claim 8, characterized in that, The method for manufacturing the semiconductor product further includes: The wafer is immersed in the cleaning machine of the wet cleaning process from the edge of the wafer along the path defined by the target reference distance from the target position, and then detaches from the cleaning machine from the edge of the wafer along the path defined by the target reference distance.

10. A semiconductor product manufacturing system, characterized in that, The semiconductor product manufacturing system includes a control device, the control device comprising: The acquisition module is used to acquire abnormal locations on the wafer and acquire marking information on the wafer; The processing module is used to obtain a distance value between the abnormal location and the edge of the wafer that meets a preset condition, as a target reference distance; A control module is configured to rotate the wafer to a preset position according to the marking information, and to control the wafer to rotate to a target position according to the target reference distance, and to control the wafer to enter a preset process environment from the target position along a path defined by the target reference distance. The control of rotating the wafer to the target position according to the target reference distance includes: obtaining a preset path for the wafer to enter the preset process environment; determining a rotation angle based on the target reference distance and the preset path; and controlling the wafer to rotate from the preset position to the target position so that the path defined by the target reference distance is parallel to the preset path.

11. The semiconductor product manufacturing system according to claim 10, characterized in that, The semiconductor product manufacturing system also includes a silicon wafer sorting machine, which is electrically connected to the control device. The silicon wafer sorting machine is used to drive the wafer to rotate to the target position and / or rotate to the preset position.

12. The semiconductor product manufacturing system according to claim 10, characterized in that, The semiconductor product manufacturing system also includes a lithography machine, which is electrically connected to the control device, and the lithography machine sends the flatness data of the wafer to the control device.

13. The semiconductor product manufacturing system according to claim 10, characterized in that, The semiconductor product manufacturing system also includes a cleaning machine for performing a wet cleaning process.

Images