Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure relates to a semiconductor structure and a method for fabricating the same. The semiconductor structure comprises one or more memory cells, each memory cell comprising a planar channel, and a plurality of word lines arranged in parallel and spaced apart, the word lines extending along a first direction, the first direction being a vertical direction perpendicular to the planar channel, wherein the planar channel of one memory cell semi-surrounds at least two word lines. The semiconductor structure can effectively control the channel length of the planar channel by controlling the corresponding position between the planar channel and the vertical word lines, thereby ensuring or improving the electrical performance of the device.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a method for preparing the same. Background Technology

[0002] Chips are made up of transistors. Within the same area, the denser the transistors, the more advanced the chip manufacturing process. The structure of a horizontal access gate all-around transistor (also known as a horizontal access gate GAA transistor) can significantly shorten the channel length, allowing for denser transistors and enabling more advanced manufacturing processes.

[0003] However, in the fabrication of traditional horizontal all-around gate transistors, controlling the etching morphology of the side etching (Lateral Etch Technology, also known as Lateral ET) process is quite difficult, making it hard to control the gate morphology in the resulting structure and affecting the device's electrical performance. Therefore, how to improve the structure of horizontal all-around gate transistors to effectively control the gate morphology is a problem that urgently needs to be solved. Summary of the Invention

[0004] Therefore, it is necessary to provide a semiconductor structure and its fabrication method to address the shortcomings of existing technologies.

[0005] On one hand, according to some embodiments, this disclosure provides a semiconductor structure, including:

[0006] One or more memory cells, the memory cells including planar channels; and,

[0007] Multiple character lines are arranged in parallel and spaced apart; the character lines extend along a first direction, which is a vertical direction perpendicular to the planar channel;

[0008] The planar channel of the storage cell partially surrounds at least two word lines.

[0009] In some embodiments, at least two word lines are respectively disposed on opposite sides of the planar channel in the second direction, adjacent word lines are respectively located on different sides of the planar channel in the second direction, and adjacent word lines are spaced apart along a third direction on the planar channel; the first direction, the second direction and the third direction intersect each other.

[0010] In some embodiments, the ratio of the dimension of the character line in the second direction to the dimension of the planar channel in the second direction ranges from 1:2 to 2:3.

[0011] In some embodiments, the memory cell further includes a source and a drain located at opposite ends of the planar channel in the third direction and connected to the planar channel;

[0012] The word line near the source is a first word line, and the first word line is covered by a first gate dielectric layer on three consecutive sides near the planar channel; the word line near the drain is a second word line, and the second word line is covered by a second gate dielectric layer on three consecutive sides near the planar channel.

[0013] The planar channel covers three consecutive sides of the first gate dielectric layer away from the first word line and three consecutive sides of the second gate dielectric layer away from the second word line.

[0014] In some embodiments, the memory cell further includes a source and a drain located at opposite ends of the planar channel in the third direction and connected to the planar channel;

[0015] The word line near the source is a first word line, and the first word line is covered by a first gate dielectric layer on two consecutive sides near the planar channel; the word line near the drain is a second word line, and the second word line is covered by a second gate dielectric layer on two consecutive sides near the planar channel.

[0016] In some embodiments, the wall thickness of the first gate dielectric layer contacting the source portion is greater than the wall thickness of the first gate dielectric layer contacting the planar channel portion;

[0017] And / or, the wall thickness of the second gate dielectric layer contacting the drain portion is greater than the wall thickness of the second gate dielectric layer contacting the planar channel portion.

[0018] In some embodiments, the first side surface and the end face of the source electrode connected to the planar channel are located on the same plane;

[0019] And / or, the second side face and the end face of the drain electrode connected to the planar channel are located in the same plane.

[0020] In some embodiments, at least two of the word lines are respectively disposed on opposite sides of the planar channel in a second direction; the second direction intersects the first direction;

[0021] The storage unit further includes:

[0022] The source and drain are located at opposite ends of the planar channel in a third direction and are connected to the planar channel; the third direction intersects the first direction and the second direction.

[0023] And a capacitor, located on the side of the drain opposite to the planar channel;

[0024] The capacitor includes:

[0025] The first electrode is connected to the drain electrode;

[0026] A dielectric layer is formed to cover the first electrode;

[0027] The second electrode is covered by the dielectric layer.

[0028] In some embodiments,;

[0029] The first electrode has a closed capacitor pattern opening or an open capacitor pattern opening.

[0030] In some embodiments, the first electrode has a capacitor open pattern opening, which is a U-shaped opening;

[0031] The semiconductor structure also includes a support structure that at least fills the U-shaped opening.

[0032] On the other hand, according to some embodiments, this disclosure also provides a method for fabricating a semiconductor structure, including:

[0033] The initial planar channel structure is formed to create one or more memory cells;

[0034] The initial structure of the planar channel is graphically represented to form a planar channel; the planar channel has at least two open graphical openings on opposite side edges in the second direction;

[0035] A character line is formed within the open graphic opening, and the character line extends along a first direction; the first direction is a vertical direction perpendicular to the planar channel, and the first direction intersects with the second direction.

[0036] In some embodiments, forming a letter line within the open graphic opening includes:

[0037] A gate dielectric layer is formed within the open pattern opening, covering the side surface of the planar channel portion;

[0038] The word line is formed within the open pattern opening, covering the side of the gate dielectric layer opposite to the planar channel.

[0039] In some embodiments, the preparation method further includes:

[0040] A capacitor is formed at the first end of the planar channel in a third direction; the third direction intersects with the first direction and the second direction, and the capacitor has a closed opening or an open opening.

[0041] In some embodiments, the preparation method further includes:

[0042] A bit line is formed at the second end of the planar channel in a third direction; the third direction intersects the first direction and the second direction, and the bit line extends along the second direction.

[0043] In some embodiments, the number of storage units is multiple;

[0044] The initial planar channel structure forming the plurality of memory cells includes:

[0045] A stacked structure is formed by alternating layers of semiconductor layer and first sacrificial layer;

[0046] A second sacrificial layer is formed to cover the stacked structure;

[0047] The second sacrificial layer and the stacked structure are graphically represented to form a plurality of repeating units arranged in parallel at intervals; wherein, the repeating unit includes a plurality of initial planar channel structures arranged in columns along the first direction.

[0048] In some embodiments, the preparation method further includes:

[0049] A third sacrificial layer is formed within the interval between adjacent repeating units in the second direction;

[0050] The graphical representation of the initial planar channel structure, forming a planar channel, includes:

[0051] The third sacrificial layer and the repeating unit are graphically represented to form at least two first closed graphical openings at the junction of the repeating unit and the third sacrificial layer; at least one boundary of the first closed graphical opening is located within the third sacrificial layer.

[0052] A first support structure is formed within the opening of the first closed graphic;

[0053] The remaining third sacrificial layer, second sacrificial layer and first sacrificial layer are removed to form a plurality of planar channels; wherein the plurality of planar channels arranged in a row along the second direction are connected by corresponding first support structures.

[0054] In some embodiments, the step of graphically representing the initial planar channel structure to form a planar channel further includes:

[0055] A dielectric layer is formed that covers the side of the first support structure and the exposed surface of the planar channel;

[0056] Remove the first support structure to form the open graphic opening in the planar channel.

[0057] In some embodiments, the repeating unit further includes: a capacitive contact structure located at a third-direction first end of the initial planar channel structure; the third direction intersects with the first direction and the second direction, and the capacitive contact structure and the initial planar channel structure are different portions of the semiconductor layer; the dielectric layer further covers the exposed surface of the capacitive contact structure;

[0058] The preparation method further includes:

[0059] Remove the portion of the dielectric layer covering the capacitor contact structure to expose the capacitor contact structure;

[0060] A first electrode is formed to cover the exposed surface of the capacitor contact structure;

[0061] A dielectric layer is formed to cover the exposed surface of the first electrode;

[0062] A second electrode is formed to cover the dielectric layer; the second electrode, the dielectric layer, and the first electrode together constitute a capacitor.

[0063] In some embodiments, the patterning of the third sacrificial layer and the repeating unit includes: forming a second closed patterned opening in the capacitive contact structure; or, forming a third closed patterned opening in the boundary region between the capacitive contact structure and the third sacrificial layer, wherein at least one boundary of the third closed patterned opening is located within the third sacrificial layer.

[0064] The preparation method further includes: forming a second support structure within the second closed pattern opening or the third closed pattern opening; wherein, a plurality of the capacitor contact structures arranged in a row along the first direction are connected by corresponding second support structures;

[0065] Before forming the first electrode covering the exposed surface of the capacitor contact structure, the preparation method further includes: removing the second support structure.

[0066] In some embodiments, the graphical representation of the second sacrificial layer and the stacked structure includes: forming a connection unit at the same end of each of the repeating units; the connection unit includes: a plurality of connection portions arranged in a column along the first direction; the connection portions and the initial planar channel structure are different parts of the semiconductor layer, and the connection portions are located at the second end of the initial planar channel structure in the third direction;

[0067] After forming the dielectric layer, the preparation method further includes:

[0068] Remove the connecting portion to form a groove;

[0069] The trench is filled with conductive material to form a bit line.

[0070] The semiconductor structure and its fabrication method disclosed herein have at least the following beneficial effects:

[0071] In the semiconductor structure provided in this disclosure, a planar channel is employed, which facilitates the fabrication of word lines in a vertical direction perpendicular to the planar channel. Based on this, at least two word lines penetrate the same planar channel, and the planar channel partially surrounds the corresponding word lines. This allows for effective control of the channel length of the planar channel by controlling the corresponding positions between the planar channel and the vertical word lines, thereby ensuring or improving the electrical performance of the device.

[0072] The semiconductor structure fabrication method disclosed herein facilitates the fabrication of word lines in the vertical direction perpendicular to the planar channel by forming a planar channel. Based on this, at least two word lines penetrating the same planar channel are formed within at least two open pattern openings of the planar channel, with the planar channel partially enclosing the corresponding word lines. This allows for effective control of the channel length of the planar channel by controlling the corresponding positions between the planar channel and the vertical word lines, thereby ensuring or improving the electrical performance of the device. Attached Figure Description

[0073] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0074] Figure 1 This is a three-dimensional structural diagram of the semiconductor structure provided in some embodiments of this disclosure;

[0075] Figure 2 A three-dimensional structural diagram of a memory cell in a semiconductor structure provided in some embodiments of this disclosure;

[0076] Figure 3 This is a schematic diagram of a first direction, a second direction, and a third direction in a semiconductor structure provided in some embodiments of this disclosure; Figure 3 This is also a schematic diagram of the first direction, the second direction, and the third direction in the semiconductor structure fabrication method provided in some embodiments of this disclosure;

[0077] Figures 4 to 6 A top view of a memory cell in a semiconductor structure provided in some embodiments of this disclosure;

[0078] Figure 7This is a schematic flowchart illustrating the method for fabricating semiconductor structures provided in some embodiments of this disclosure;

[0079] Figure 8 This is a schematic flowchart of step S300 in a method for fabricating a semiconductor structure provided in some embodiments of this disclosure;

[0080] Figure 9 This is a schematic flowchart of step S100 in a method for fabricating a semiconductor structure provided in some embodiments of this disclosure;

[0081] Figure 10 This is a schematic flowchart of step S200 in a method for fabricating a semiconductor structure provided in some embodiments of this disclosure;

[0082] Figure 11 This is a flowchart illustrating other steps in the method for fabricating a semiconductor structure provided in some embodiments of this disclosure;

[0083] Figure 12 A flowchart illustrating other steps in the fabrication method of a semiconductor structure provided in other embodiments of this disclosure;

[0084] Figures 13 to 28 This is a three-dimensional structural diagram of the structure obtained in each step of the method for preparing a semiconductor structure according to some embodiments of this disclosure.

[0085] Explanation of reference numerals in the attached figures:

[0086] 11. Initial planar channel structure; 13. Capacitor contact structure; 14. Connection portion; 15. Trench; 21. First closed pattern opening; 22. First support structure; 23. Dielectric layer; 24. Third closed pattern opening; 25. Second support structure; 100. Memory cell; 101. Stacked structure; 101a. Semiconductor layer; 101b. First sacrificial layer; 102. Second sacrificial layer; 103. Third sacrificial layer; 110. Planar channel; 11 1. Open pattern opening; 121. Source; 122. Drain; 130. Capacitor; 130a. Closed pattern opening of capacitor; 130b. Open pattern opening of capacitor; 200. Word line; 210. First word line; 220. Second word line; 300. Gate dielectric layer; 310. First gate dielectric layer; 320. Second gate dielectric layer; 400. Bit line; 1301. First electrode; 1302. Second electrode; S. Spacing; U. Repeating cell. Detailed Implementation

[0087] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0088] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0089] It should be understood that when an element or layer is referred to as "on," "adjacent to," or "connected to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first sacrificial layer may be referred to as the second sacrificial layer, and similarly, the second sacrificial layer may be referred to as the first sacrificial layer; the first sacrificial layer and the second sacrificial layer are different sacrificial layers, for example, the first sacrificial layer may be P-type and the second sacrificial layer may be N-type, or the first sacrificial layer may be N-type and the second sacrificial layer may be P-type.

[0090] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that when the terms “comprise” and / or “comprising” are used in this specification, the presence of the stated feature, integer, step, operation, element, and / or part is established, but the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups is not excluded. Meanwhile, when used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0091] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0092] In view of the shortcomings of the prior art, this disclosure provides a semiconductor structure and a method for its fabrication, the details of which will be described in subsequent embodiments.

[0093] On the one hand, this disclosure provides a semiconductor structure according to some embodiments.

[0094] Please see Figures 1 to 2 as well as Figures 4 to 6 In some embodiments, the semiconductor structure includes one or more memory cells 100 and a plurality of word lines 200.

[0095] The storage cell 100 includes a planar channel 110. A plurality of word lines 200 are arranged in parallel and spaced apart, extending along a first direction, which is the vertical direction perpendicular to the planar channel 110. The planar channel 110 of the storage cell 100 partially surrounds at least two word lines 200.

[0096] In the semiconductor structure provided in the above embodiments, a planar channel 110 is used, which facilitates the fabrication of word lines 200 in the vertical direction perpendicular to the planar channel 110. Based on this, at least two word lines 200 penetrate the same planar channel 110, and the planar channel 110 partially surrounds the corresponding word line 200. This allows for effective control of the channel length of the planar channel 110 by controlling the corresponding positions between the planar channel 110 and the vertical word lines 200, thereby ensuring or improving the electrical performance of the device.

[0097] In the semiconductor structure provided in the above embodiments, the planar channel 110 at least partially surrounds the two corresponding word lines 200, thereby forming a bidirectional vertical annular channel device structure. This can reduce the channel length required for the planar channel 110, while also enhancing the current driving capability.

[0098] It should be noted that, in this disclosure, "semi-enclosed" refers to covering two or more consecutive sides. For example, "semi-enclosed" means that the plane channel 110 covers two or more consecutive sides of the character line 200.

[0099] This disclosure does not specifically limit the material of the word line 200. As an example, the material of the word line 200 may include, but is not limited to, polysilicon or metal gate materials, etc.

[0100] In some embodiments, the word line 200 is made of a metal gate material; as an example, the metal gate material may include, but is not limited to, a metal conductive material such as tungsten (W).

[0101] Please continue reading Figures 1 to 2 as well as Figures 4 to 6 In some embodiments, the at least two word lines 200 may be respectively disposed on opposite sides of the planar channel 110 in the second direction, adjacent word lines 200 may be respectively located on different sides of the planar channel 110 in the second direction, and adjacent word lines 200 may be spaced apart along a third direction on the planar channel 110.

[0102] In this embodiment, the first direction, the second direction, and the third direction intersect each other. Please refer to... Figure 3 Understand the first, second, and third directions involved in this disclosure. In some embodiments, the first, second, and third directions may be understood. Figure 3 The direction shown by the Z-axis is taken as the first direction. Figure 3 The direction shown by the Y-axis is taken as the second direction. Figure 3 The direction shown on the X-axis is taken as the third direction. For example... Figure 3 As shown, the first direction indicated by the Z-axis, the second direction indicated by the Y-axis, and the third direction indicated by the X-axis intersect each other.

[0103] For ease of description, all subsequent text will use the same format. Figure 3 The direction shown by the Z-axis is the first direction. Figure 3 The direction shown on the Y-axis is the second direction. Figure 3 The direction shown on the X-axis is the third direction, which will be used as an example for explanation.

[0104] Based on this, in some embodiments, the planar channel 110 extends along a third direction, and the word line 200 extends along a first direction.

[0105] This disclosure does not specifically limit the size of the character line 200. As an example, the ratio of the size of the character line 200 in the second direction to the size of the planar channel 110 in the second direction can be in the range of 1:2 to 2:3; for example, the ratio of the size of the character line 200 in the second direction to the size of the planar channel 110 in the second direction can be in the range of 1:2, 5:9, 3:5 or 2:3, etc.

[0106] In the semiconductor structure provided in the above embodiments, the ratio of the size of the word line 200 in the second direction to the size of the planar channel 110 in the second direction is limited to a range of 1:2 to 2:3. Considering the critical size limitation of the word line 200, the support effect during its fabrication process is avoided due to the word line 200 being too narrow, as well as the control capability of the word line 200 over the planar channel 110 and the current transmission capability of the word line 200.

[0107] Please continue reading Figures 4 to 6 In some embodiments, the semiconductor structure may further include a gate dielectric layer 300. The gate dielectric layer 300 is located between the word line 200 and the planar channel 110.

[0108] This disclosure does not specifically limit the material of the gate dielectric layer 300. As an example, the material of the gate dielectric layer 300 may include, but is not limited to, silicon dioxide (SiO2) or a high-k dielectric material with a dielectric constant K greater than 7.

[0109] Please continue reading Figures 1 to 2 as well as Figures 4 to 6 In some embodiments, the storage cell 100 may further include a source 121 and a drain 122. The source 121 and the drain 122 are located at opposite ends of the planar channel 110 in the third direction and are connected to the planar channel 110.

[0110] This disclosure does not specifically limit the form of the planar channel 110. As an example, the planar channel 110 can be a P-type planar channel or an N-type planar channel.

[0111] Please see Figure 5 Figure (a) in the middle and Figure 5 In Figure (c), in some embodiments, the planar channel 110 is a P-type planar channel, and the planar channel 110 also has N-type lightly doped regions (NLDD) at both ends in the third direction. The source 121 and drain 122 are respectively connected to the N-type lightly doped regions at both ends of the planar channel 110 in the third direction.

[0112] In this disclosure, for ease of description, the word line 200 near the source 121 can be defined as the first word line 210, and the word line 200 near the drain 122 can be defined as the second word line 220.

[0113] Please continue reading Figure 5In Figure (a), in some embodiments, the first gate dielectric layer 310 may cover three consecutive sides of the first word line 210 near the planar channel 110, and the second gate dielectric layer 320 may cover three consecutive sides of the second word line 220 near the planar channel 110. Furthermore, the planar channel 110 may cover three consecutive sides of the first gate dielectric layer 310 away from the first word line 210, and the planar channel 110 may also cover three consecutive sides of the second gate dielectric layer 320 away from the second word line 220.

[0114] It is understood that in the above embodiments, the gate dielectric layer 300 includes a first gate dielectric layer 310 and a second gate dielectric layer 320.

[0115] It is understood that in some other embodiments, the first word line 210 is covered with a first gate dielectric layer 310 on two consecutive sides near the planar channel 110, and the second word line 220 is covered with a second gate dielectric layer 320 on two consecutive sides near the planar channel 110.

[0116] Based on this, in this disclosure, the first gate dielectric layer 310 includes a side facing away from the first word line 210 and a side facing the first word line 210, and the second gate dielectric layer 320 also includes a side facing away from the second word line 220 and a side facing the second word line 220. For ease of description, the side of the first gate dielectric layer 310 facing away from the first word line 210 that is closer to the source 121 can be defined as the first side, and the side of the second gate dielectric layer 320 facing away from the second word line 220 that is closer to the drain 122 can be defined as the second side.

[0117] Please continue reading. Figure 5 Figure (b) in the middle and Figure 5 In Figure (c), in some embodiments, the first side is connected to the source 121, and the planar channel 110 covers the two consecutive sides of the first gate dielectric layer 310 away from the first word line 210; at the same time, the second side is connected to the drain 122, and the planar channel 110 also covers the two consecutive sides of the second gate dielectric layer 320 away from the second word line 220.

[0118] Please continue reading. Figure 5 Figure (b) in the middle and Figure 5In Figure (c), in some embodiments, the wall thickness of the portion of the first gate dielectric layer 310 that contacts the source 121 is greater than the wall thickness of the portion of the first gate dielectric layer 310 that contacts the planar channel 110; or, the wall thickness of the portion of the second gate dielectric layer 320 that contacts the drain 122 is greater than the wall thickness of the portion of the second gate dielectric layer 320 that contacts the planar channel 110; or, the wall thickness of the portion of the first gate dielectric layer 310 that contacts the source 121 is greater than the wall thickness of the portion of the first gate dielectric layer 310 that contacts the planar channel 110, and the wall thickness of the portion of the second gate dielectric layer 320 that contacts the drain 122 is greater than the wall thickness of the portion of the second gate dielectric layer 320 that contacts the planar channel 110.

[0119] Please continue reading Figure 5 Figure (b) in the middle and Figure 5 In Figure (c), in some embodiments, the first side surface and the end face of the planar channel 110 connected to the source 121 are located in the same plane; or, the second side surface and the end face of the planar channel 110 connected to the drain 122 are located in the same plane; or, the first side surface and the end face of the planar channel 110 connected to the source 121 are located in the same plane, and the second side surface and the end face of the planar channel 110 connected to the drain 122 are located in the same plane.

[0120] Please continue reading Figures 1 to 2 as well as Figure 6 In some embodiments, the storage cell 100 may further include a capacitor 130. The capacitor 130 is located on the side of the drain 122 away from the planar channel 110, and the capacitor 130 may include a first electrode, a dielectric layer, and a second electrode.

[0121] The first electrode is connected to the drain 122; the dielectric layer covers the first electrode; and the second electrode is covered by the dielectric layer.

[0122] This disclosure does not specifically limit the material of the dielectric layer. As an example, the material of the dielectric layer may include, but is not limited to, silicon dioxide, silicon nitride (SiN), silicon oxynitride (SiON), phosphosilicate glass (PSG), high-k dielectric materials, or combinations thereof.

[0123] This disclosure does not specifically limit the materials of the first electrode and the second electrode. As an example, the materials of the first electrode and the second electrode may include, but are not limited to, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten, copper (Cu), gold (Au), or combinations thereof.

[0124] This disclosure does not specifically limit the form of the first electrode, the dielectric layer, and the second electrode. As an example, the first electrode may include, but is not limited to, a planar electrode.

[0125] Please see Figure 6 Figure (a) in the middle and Figure 6 In Figure (b), in some embodiments, the first electrode may have a capacitor-closed pattern opening 130a. See also... Figures 1 to 2 In other embodiments, the first electrode may also have a capacitor open pattern opening 130b.

[0126] This disclosure does not specify the number of capacitor closed pattern openings 130a in the first electrode. The first electrode may have one to three capacitor closed pattern openings 130a; for example, the first electrode may have one, two, or three capacitor closed pattern openings 130a. Please continue reading. Figure 6 In Figure (a), in some embodiments, the number of capacitor closed pattern openings 130a in the first electrode is one; please continue reading Figure 6 In Figure (b), in some embodiments, the number of capacitor closed pattern openings 130a in the first electrode is two.

[0127] It should be noted that, in this disclosure, a closed figure refers to a figure whose edges are enclosed by closed lines; correspondingly, an open figure refers to a figure whose edges are not closed on at least one side.

[0128] Please continue reading. Figures 1 to 2 In some embodiments, the first electrode has a capacitor open pattern opening 130b, and the capacitor open pattern opening 130b is a U-shaped opening.

[0129] In the semiconductor structure provided in the above embodiments, the capacitor 130 has a U-shaped opening. The U-shaped opening and the planar channel 110 can be matched with each other in terms of process, that is, the U-shaped opening and the planar channel 110 in the capacitor 130 can be formed simultaneously in the same fabrication process. Therefore, the semiconductor structure provided in the above embodiments is easy to fabricate, which can effectively simplify the process difficulty and improve production efficiency.

[0130] In some embodiments, the semiconductor structure may further include a support structure. The support structure at least fills the U-shaped opening. A more detailed description of the support structure will follow later and will not be elaborated upon here.

[0131] On the one hand, this disclosure provides a method for preparing a semiconductor structure according to some embodiments.

[0132] Please see Figure 7 In some embodiments, the preparation method may include the following steps:

[0133] S100: The initial planar channel structure that forms one or more memory cells.

[0134] S200: Graphical planar channel initial structure, forming a planar channel; the planar channel has at least two open graphic openings on opposite side edges in the second direction.

[0135] S300: A letter line is formed within the opening of the open graphic, and the letter line extends along a first direction; the first direction is a vertical direction perpendicular to the planar channel, and the first direction intersects with the second direction.

[0136] The semiconductor structure fabrication method provided in the above embodiments facilitates the fabrication of word lines in the vertical direction perpendicular to the planar channel by forming a planar channel. Based on this, at least two word lines penetrating the same planar channel are formed within at least two open pattern openings of the planar channel, and the planar channel semi-encloses the corresponding word lines. This allows for effective control of the channel length of the planar channel by controlling the corresponding positions between the planar channel and the vertical word lines, thereby ensuring or improving the electrical performance of the device.

[0137] Please see Figure 8 In some embodiments, step S300, which involves forming a word line within the open graphic opening, may include the following steps:

[0138] S310: A gate dielectric layer is formed within an open pattern opening, covering the side of the planar channel portion.

[0139] S320: A word line is formed within an open pattern opening, covering the grid dielectric layer and facing away from the side of the planar channel.

[0140] In some embodiments, the preparation method may further include the following steps:

[0141] A capacitor is formed at the first end of a planar channel in a third direction; the third direction intersects with the first and second directions, and the capacitor has a closed opening or an open opening.

[0142] In some embodiments, the preparation method may further include the following steps:

[0143] A position line is formed at the second end of the planar channel in the third direction; the third direction intersects with the first direction and the second direction, and the position line extends along the second direction.

[0144] In some embodiments, the number of storage units is multiple.

[0145] Please see Figure 9 In some embodiments, step S100, which forms the initial planar channel structure of multiple memory cells, may include the following steps:

[0146] S110: Forming a stacked structure in which the semiconductor layer and the first sacrificial layer are alternately stacked.

[0147] S120: The second sacrificial layer that forms the covering laminate structure.

[0148] S130: A second sacrificial layer and a stacked structure are graphically represented to form multiple repeating units arranged in parallel intervals; wherein, the repeating unit includes multiple planar channel initial structures arranged in columns along the first direction.

[0149] In some embodiments, the preparation method further includes forming a third sacrificial layer between adjacent repeating units.

[0150] Please see Figure 10 In some embodiments, step S200, which graphically represents the initial structure of the planar channel to form the planar channel, may include the following steps:

[0151] S210: A third sacrificial layer and repeating units are graphically represented to form at least two first closed graphical openings on both sides of the repeating units and at the boundary of the third sacrificial layer; at least one boundary of the first closed graphical opening is located within the third sacrificial layer.

[0152] S220: A first support structure is formed within the opening of the first closed graphic.

[0153] S230: Remove the remaining third sacrificial layer, second sacrificial layer and first sacrificial layer to form multiple planar channels; wherein, the multiple planar channels arranged in a row along the second direction are connected by corresponding first support structures.

[0154] Please continue reading. Figure 10 In some embodiments, step S200, which involves graphically representing the initial structure of the planar channel to form the planar channel, may further include the following steps:

[0155] S240: Form a dielectric layer that covers the sides of the first support structure and the exposed surface of the planar channel.

[0156] S250: Remove the first support structure to form an open graphic opening in the planar channel.

[0157] In some embodiments, the repeating unit may further include a capacitive contact structure located at a first end of the third direction of the initial planar channel structure. The third direction intersects with both the first and second directions, the capacitive contact structure and the initial planar channel structure are different portions of the semiconductor layer, and the dielectric layer further covers the exposed surface of the capacitive contact structure.

[0158] Please see Figure 11 In some embodiments, the preparation method may further include the following steps:

[0159] S410: Remove the portion of the dielectric layer covering the capacitor contact structure to expose the capacitor contact structure.

[0160] S420: The first electrode forming the exposed surface of the capacitor contact structure.

[0161] S430: Form a dielectric layer covering the exposed surface of the first electrode.

[0162] S440: The second electrode forms the dielectric layer; the second electrode, the dielectric layer, and the first electrode together constitute the capacitor.

[0163] In some embodiments, step S210, which graphically visualizes the third sacrificial layer and the repeating unit, may include the following steps:

[0164] A second closed pattern opening is formed in the capacitor contact structure; or, a third closed pattern opening is formed in the boundary region between the capacitor contact structure and the third sacrificial layer, wherein at least one boundary of the third closed pattern opening is located within the third sacrificial layer.

[0165] In some embodiments, the preparation method may further include the following steps:

[0166] A second support structure is formed within the opening of the second or third closed pattern; wherein, multiple capacitive contact structures arranged in a row along the first direction are connected to each other through the corresponding second support structure.

[0167] In some embodiments, before step S420 forms the first electrode covering the exposed surface of the capacitor contact structure, the fabrication method may further include the following steps:

[0168] Remove the second support structure.

[0169] In some embodiments, step S130, which graphically visualizes the second sacrificial layer and the stacked structure, may include the following steps:

[0170] A connection unit is formed at the same end of each repeating unit. The connection unit includes a plurality of connection portions arranged in a row along a first direction. The connection portions are different from the semiconductor layer of the initial planar channel structure. The connection portions are located at the second end of the initial planar channel structure in a third direction.

[0171] Please see Figure 12 After the dielectric layer is formed in step S240, the preparation method may further include the following steps:

[0172] S510: Remove the connecting part to form a groove.

[0173] S520: The trench is filled with conductive material to form a bit line.

[0174] It should be understood that, although Figures 7 to 12The steps in the flowchart are shown sequentially as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order in which these steps are executed, and they can be performed in other orders. Figures 7 to 12 At least some of the steps in the process may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least some of the steps or stages in other steps.

[0175] To more clearly illustrate the preparation methods in some of the above embodiments, please refer to the following... Figures 1 to 6 as well as Figures 13 to 28 Understanding some embodiments of this disclosure.

[0176] In step S100, please refer to Figures 13 to 15 This forms a planar channel initial structure 11 for one or more memory cells 100.

[0177] In some embodiments, the number of storage units 100 is multiple.

[0178] As an example, the initial planar channel structure 11 of multiple memory cells 100 formed in step S100 can be specifically represented by the following steps S110 to S130:

[0179] In step S110, please refer to Figure 13 A stacked structure 101 is formed by alternating layers of semiconductor layer 101a and first sacrificial layer 101b.

[0180] In step S120, please refer to Figure 14 This forms a second sacrificial layer 102 covering the laminated structure 101.

[0181] In step S130, please refer to Figure 15 The second sacrificial layer 102 and the stacked structure 101 are graphically represented to form a plurality of repeating units U arranged in parallel intervals. The repeating unit U includes a plurality of planar channel initial structures 11 arranged in columns along the first direction.

[0182] This disclosure does not specifically limit the materials of the semiconductor layer 101a and the first sacrificial layer 101b in step S110. In some embodiments, the semiconductor layer 101a includes silicon (Si), and the first sacrificial layer 101b includes silicon germanium (SiGe).

[0183] This disclosure does not specifically limit the material of the second sacrificial layer 102 in step S120. In some embodiments, the second sacrificial layer 102 includes silicon dioxide.

[0184] As an example, in step S120, a second sacrificial layer 102 may be formed on the stacked structure 101 using a deposition (DEP) process, but not limited to this. The deposition process may include, but is not limited to, chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc. Furthermore, chemical mechanical polishing (CMP) may be used to mechanically grind the obtained second sacrificial layer 102 to make its top surface smoother, which is beneficial for subsequent patterning of the second sacrificial layer 102 and the stacked structure 101.

[0185] In some embodiments, such as Figure 15 As shown, there can be a gap S between adjacent repeating units U.

[0186] Based on this, the preparation method may further include the following steps:

[0187] A third sacrificial layer 103 is formed within the interval S between adjacent repeating units U in the second direction.

[0188] As an example, such as Figure 16 As shown, a third sacrificial layer 103 can be formed between adjacent planar channel initial structures 11.

[0189] This disclosure does not specifically limit the material of the third sacrificial layer 103 in the above steps. In some embodiments, the third sacrificial layer 103 includes silicon dioxide.

[0190] As an example, a deposition process can also be used, but is not limited to, to form a third sacrificial layer 103 between adjacent repeating units U in the above steps.

[0191] In step S200, please refer to Figures 17 to 22 A graphical planar channel initial structure 11 is formed to create a planar channel 110; the planar channel 110 has at least two open graphical openings 111 on opposite side edges in the second direction.

[0192] In some embodiments, step S200, which involves graphically creating the initial planar channel structure 11 to form the planar channel 110, can specifically be represented by the following steps S210 to S230:

[0193] In step S210, please refer to Figure 17The third sacrificial layer 103 and the repeating unit U are graphically represented, so that at least two first closed graphical openings 21 are formed on both sides of the repeating unit U and at the boundary of the third sacrificial layer 103, and at least one side boundary of the first closed graphical opening 21 is located within the third sacrificial layer 103.

[0194] In step S220, please refer to Figure 18 A first support structure 22 is formed within the opening 21 of the first closed shape.

[0195] In step S230, please refer to Figure 19 The remaining third sacrificial layer 103, second sacrificial layer 102 and first sacrificial layer 101b are removed to form multiple planar channels 110.

[0196] like Figure 19 As shown, multiple planar channels 110 arranged in a row along the second direction can be connected by corresponding first support structures 22.

[0197] This disclosure does not specifically limit the material of the first support structure 22 in step S220. In some embodiments, the material of the first support structure 22 may include silicon nitride.

[0198] In some embodiments, step S200, which involves graphically creating the initial planar channel structure 11 to form the planar channel 110, may further include the following steps S240 to S250:

[0199] In step S240, please refer to Figure 20 This forms a medium layer 23 that covers the sides of the first support structure 22 and the exposed surface of the planar channel 110.

[0200] In step S250, please refer to Figure 21 Remove the first support structure 22 to form an open graphic opening 111 in the planar channel 110.

[0201] This disclosure does not specifically limit the material of the dielectric layer 23 in step S240. In some embodiments, the material of the dielectric layer 23 may include silicon dioxide.

[0202] The steps S240 to S250 described above are used to remove the first support structure 22 in order to form the word line 200 in subsequent processes.

[0203] Please combine Figure 22 Understand the structure obtained in the aforementioned step S200. Figure 22 A schematic cross-sectional view of the structure obtained after the aforementioned patterning process of the semiconductor layer 101a in a memory cell 100 is shown.

[0204] In step S300, please refer to Figure 23A character line 200 is formed within the open graphic opening 111, and the character line 200 extends along a first direction; the first direction is a vertical direction perpendicular to the planar channel 110, and the first direction intersects with the second direction.

[0205] In some embodiments, step S300, which involves forming a word line 200 within the open graphic opening 111, can specifically be represented by the following steps S310 to S320:

[0206] In step S310, a gate dielectric layer 300 is formed within the open pattern opening 111, covering a portion of the side surface of the planar channel 110.

[0207] In step S320, word lines 200 are formed within the open pattern opening 111, covering the side of the gate dielectric layer 300 facing away from the planar channel 110.

[0208] This disclosure does not specifically limit the method of forming the gate dielectric layer 300 in step S310. As an example, processes such as thermal oxidation (dry or wet), chemical vapor deposition, or atomic layer deposition can be used to form the gate dielectric layer 300 covering part of the side of the planar channel 110 within the open pattern opening 111.

[0209] In some embodiments, please refer to Figures 24 to 25 The preparation method may further include the following steps:

[0210] A bit line 400 is formed at the second end of the planar channel 110 in the third direction, and the bit line 400 extends along the second direction.

[0211] In some embodiments, the process of graphically representing the second sacrificial layer 102 and the stacked structure 101 in step S130 may include the following step: forming a connecting unit at the same end of each repeating unit U.

[0212] For details, please refer to Figures 15 to 23 The connection unit may include a plurality of connection portions 14 arranged in a column along a first direction. It should be noted that the connection portion 14 and the initial planar channel structure 11 are different parts of the semiconductor layer 101a, and the connection portion 14 is located at the second end of the initial planar channel structure 11 in a third direction.

[0213] In some embodiments, after forming the dielectric layer 23 in step S240, the preparation method may further include the following steps S510 to S520.

[0214] In step S510, please refer to Figure 24 Remove the connecting portion 14 to form the groove 15.

[0215] In step S520, please refer to Figure 25 Conductive material is filled into the trench 15 to form bit line 400.

[0216] This disclosure does not specifically limit the method of removing the connecting portion 14 in step S510. In some embodiments, a side etching method can be used to gradually remove the connecting portion 14 by etching downwards from the third-upward surface of the connecting portion 14.

[0217] This disclosure does not specifically limit the material of bit line 400. As an example, the material of bit line 400 may include, but is not limited to, a single metal, a metal compound, or an alloy; wherein, a single metal may include copper, aluminum (Al), tungsten, gold, or silver (Ag); a metal compound may include, but is not limited to, tantalum nitride or titanium nitride; and an alloy may include, but is not limited to, an alloy material composed of at least two of copper, aluminum, tungsten, gold, or silver. In some embodiments, the material of bit line 400 is a bit line metal material, which can give bit line 400 a lower resistivity, which is beneficial for reducing the resistance of bit line 400, increasing the transmission rate of electrical signals in bit line 400, reducing the parasitic capacitance of bit line 400, and reducing heat loss to reduce power consumption.

[0218] In some embodiments, the preparation method may further include the following steps:

[0219] A capacitor 130 is formed at the first end of the planar channel 110 in the third direction.

[0220] For example, please refer to Figures 1 to 2 The capacitor 130 may have a closed graphical opening 130a or an open graphical opening 130b.

[0221] Please continue reading. Figures 1 to 2 In some embodiments, the capacitor 130 formed by the above steps has a capacitor open pattern opening 130b, and the capacitor open pattern opening 130b is a U-shaped opening.

[0222] In some embodiments, step S210, which graphically visualizes the third sacrificial layer 103 and the repeating unit U, may include the following steps:

[0223] A second closed pattern opening is formed in the capacitor contact structure 13.

[0224] Alternatively, in some other embodiments, please refer to Figure 17 Step S210, which graphically visualizes the third sacrificial layer 103 and the repeating unit U, may also include the following steps:

[0225] A third closed pattern opening 24 is formed at the junction of the capacitor contact structure 13 and the third sacrificial layer 103, and at least one side boundary of the third closed pattern opening 24 is located within the third sacrificial layer 103.

[0226] In the semiconductor structure fabrication method provided in the above embodiments, a capacitor 130 having one or more capacitor closed pattern openings 130a can be formed by forming one or more second closed pattern openings in the capacitor contact structure 13; for example, a capacitor 130 can be fabricated by forming one second closed pattern opening in the capacitor contact structure 13. Figure 6 The capacitor 130 shown in Figure (a) has a capacitor closed pattern opening 130a; alternatively, it can be prepared by forming two second closed pattern openings in the capacitor contact structure 13. Figure 6 The capacitor 130 shown in Figure (b) has two capacitor closed pattern openings 130a.

[0227] In the semiconductor structure fabrication method provided in the above embodiments, a capacitor 130 with an open pattern opening 130b can be formed by forming a third closed pattern opening 24 in the junction region of the capacitor contact structure 13 and the third sacrificial layer 103; for example, a capacitor 130 is fabricated as shown in the example. Figure 27 The capacitor shown is 130.

[0228] In some embodiments, please refer to Figure 18 The preparation method may further include the following steps:

[0229] A second support structure 25 is formed within the opening of the second or third closed shape 24.

[0230] like Figure 19 As shown, multiple capacitor contact structures 13 arranged in a row along the first direction are connected by corresponding second support structures 25.

[0231] This disclosure does not specifically limit the material of the second support structure 25 in the above steps. In some embodiments, the material of the second support structure 25 may include silicon nitride.

[0232] In some embodiments, please refer to Figure 26 Before forming the first electrode covering the exposed surface of the capacitor contact structure 13 in step S420, the preparation method may further include the following steps:

[0233] Remove the second support structure 25.

[0234] In some embodiments, please continue reading Figure 19 The repeating unit U may also include a capacitor contact structure 13 located at the first end of the third-direction planar channel initial structure 11. It should be noted that the capacitor contact structure 13 and the planar channel initial structure 11 are different parts of the semiconductor layer 101a.

[0235] In some embodiments, please continue reading Figure 20The dielectric layer 23 also covers the exposed surface of the capacitor contact structure 13.

[0236] As an example, capacitor 130 may include a first electrode 1301, a dielectric layer, and a second electrode 1302.

[0237] In some embodiments, the preparation method may further include the following steps S410 to S440.

[0238] In step S410, please refer to Figure 26 Remove the portion of the dielectric layer 23 covering the capacitor contact structure 13, exposing the capacitor contact structure 13.

[0239] In step S420, please refer to Figure 27 This forms the first electrode on the exposed surface of the capacitor contact structure 13.

[0240] In step S430, a dielectric layer is formed to cover the exposed surface of the first electrode.

[0241] In step S440, please refer to Figure 28 A second electrode is formed by coating a dielectric layer; the second electrode, the dielectric layer, and the first electrode together constitute capacitor 130.

[0242] It should be noted that the methods for preparing the semiconductor structure in the embodiments of this disclosure can all be used to prepare the corresponding semiconductor structure. Therefore, the technical features between the method embodiments and the structure embodiments can be substituted and supplemented for each other without conflict, so that those skilled in the art can learn the technical content of this disclosure.

[0243] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0244] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A semiconductor structure, characterized in that, include: One or more memory cells, the memory cells including planar channels; and, Multiple character lines, set in parallel intervals; The character line extends along a first direction, which is a vertical direction perpendicular to the planar channel; Wherein, the planar channel of the storage cell partially surrounds at least two word lines; The memory cell also includes a source and a drain located at opposite ends of the planar channel in a third direction and connected to the planar channel; The word line near the source is a first word line, and the first word line is covered by a first gate dielectric layer on two consecutive sides near the planar channel; the word line near the drain is a second word line, and the second word line is covered by a second gate dielectric layer on two consecutive sides near the planar channel. The wall thickness of the first gate dielectric layer in contact with the source portion is greater than the wall thickness of the first gate dielectric layer in contact with the planar channel portion; And / or, the wall thickness of the second gate dielectric layer contacting the drain portion is greater than the wall thickness of the second gate dielectric layer contacting the planar channel portion.

2. The semiconductor structure according to claim 1, characterized in that, At least two of the character lines are respectively disposed on opposite sides of the planar channel in the second direction, adjacent character lines are respectively located on different sides of the planar channel in the second direction, and adjacent character lines are spaced apart along the third direction on the planar channel; the first direction, the second direction and the third direction intersect each other.

3. The semiconductor structure according to claim 2, characterized in that, The ratio of the dimension of the character line in the second direction to the dimension of the planar channel in the second direction ranges from 1:2 to 2:

3.

4. The semiconductor structure according to claim 2, characterized in that, The storage cell also includes a source and a drain located at opposite ends of the planar channel in the third direction and connected to the planar channel; The word line near the source is a first word line, and the first word line is covered by a first gate dielectric layer on three consecutive sides near the planar channel; the word line near the drain is a second word line, and the second word line is covered by a second gate dielectric layer on three consecutive sides near the planar channel. The planar channel covers three consecutive sides of the first gate dielectric layer away from the first word line and three consecutive sides of the second gate dielectric layer away from the second word line.

5. The semiconductor structure according to claim 1, characterized in that, The side of the first gate dielectric layer away from the first word line includes a first side near the source electrode, and the first side is located in the same plane as the end face of the planar channel connecting the source electrode; And / or, the side of the second gate dielectric layer away from the second word line includes a second side near the drain electrode, the second side being in the same plane as the end face of the drain electrode connected to the planar channel.

6. The semiconductor structure according to any one of claims 1 to 3, characterized in that, At least two of the character lines are respectively disposed on opposite sides of the planar channel in the second direction; the second direction intersects the first direction; The storage unit further includes: The source and drain are located at opposite ends of the planar channel in a third direction and are connected to the planar channel; the third direction intersects the first direction and the second direction. And a capacitor, located on the side of the drain opposite to the planar channel; The capacitor includes: The first electrode is connected to the drain electrode; A dielectric layer is formed to cover the first electrode; The second electrode is covered by the dielectric layer.

7. The semiconductor structure according to claim 6, characterized in that, The first electrode has a closed capacitor pattern opening or an open capacitor pattern opening.

8. The semiconductor structure according to claim 6, characterized in that, The first electrode has a capacitor open pattern opening, which is a U-shaped opening; The semiconductor structure also includes a support structure that at least fills the U-shaped opening.

9. A method for fabricating a semiconductor structure, characterized in that, include: The initial planar channel structure is formed to create one or more memory cells; The initial structure of the planar channel is graphically represented to form the planar channel; The planar channel has at least two open graphic openings on opposite side edges in the second direction; A character line is formed within the open graphic opening, and the character line extends along a first direction; the first direction is a vertical direction perpendicular to the planar channel, and the first direction intersects with the second direction; The number of the storage units is multiple; The initial planar channel structure forming the plurality of memory cells includes: A stacked structure is formed by alternating layers of semiconductor layer and first sacrificial layer; A second sacrificial layer is formed to cover the stacked structure; The second sacrificial layer and the stacked structure are graphically represented to form a plurality of repeating units arranged in parallel at intervals; wherein, the repeating unit includes a plurality of planar channel initial structures arranged in columns along the first direction; The preparation method further includes: A third sacrificial layer is formed within the interval between adjacent repeating units in the second direction; The graphical representation of the initial planar channel structure, forming a planar channel, includes: The third sacrificial layer and the repeating unit are graphically represented to form at least two first closed graphical openings at the junction of the repeating unit and the third sacrificial layer; at least one boundary of the first closed graphical opening is located within the third sacrificial layer. A first support structure is formed within the opening of the first closed graphic; The remaining third sacrificial layer, second sacrificial layer and first sacrificial layer are removed to form a plurality of planar channels; wherein the plurality of planar channels arranged in a row along the second direction are connected by corresponding first support structures.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The process of forming letter lines within the open graphic opening includes: A gate dielectric layer is formed within the open pattern opening, covering the side surface of the planar channel portion; The word line is formed within the open pattern opening, covering the side of the gate dielectric layer opposite to the planar channel.

11. The method for preparing a semiconductor structure according to claim 9, characterized in that, Also includes: A capacitor is formed at the first end of the planar channel in the third direction; The third direction intersects with the first direction and the second direction, and the capacitor has a closed opening or an open opening.

12. The method for preparing a semiconductor structure according to claim 9, characterized in that, Also includes: A bit line is formed at the second end of the planar channel in the third direction; The third direction intersects with the first direction and the second direction, and the bit line extends along the second direction.

13. The method for preparing a semiconductor structure according to claim 9, characterized in that, The process of graphically representing the initial structure of the planar channel to form a planar channel further includes: A dielectric layer is formed that covers the side of the first support structure and the exposed surface of the planar channel; Remove the first support structure to form the open graphic opening in the planar channel.

14. The method for preparing a semiconductor structure according to claim 13, characterized in that, The repeating unit further includes: a capacitive contact structure located at the first end of the third direction of the initial planar channel structure; the third direction intersects with the first direction and the second direction, and the capacitive contact structure and the initial planar channel structure are different parts of the semiconductor layer; the dielectric layer also covers the exposed surface of the capacitive contact structure; The preparation method further includes: Remove the portion of the dielectric layer covering the capacitor contact structure to expose the capacitor contact structure; A first electrode is formed to cover the exposed surface of the capacitor contact structure; A dielectric layer is formed to cover the exposed surface of the first electrode; A second electrode is formed to cover the dielectric layer; the second electrode, the dielectric layer, and the first electrode together constitute a capacitor.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that, The graphical representation of the third sacrificial layer and the repeating unit includes: forming a second closed graphical opening in the capacitive contact structure; or forming a third closed graphical opening in the boundary region between the capacitive contact structure and the third sacrificial layer, wherein at least one boundary of the third closed graphical opening is located within the third sacrificial layer; The preparation method further includes: forming a second support structure within the second closed pattern opening or the third closed pattern opening; wherein, a plurality of the capacitor contact structures arranged in a row along the first direction are connected by corresponding second support structures; Before forming the first electrode covering the exposed surface of the capacitor contact structure, the preparation method further includes: removing the second support structure.

16. The method for preparing a semiconductor structure according to claim 14, characterized in that, The graphical representation of the second sacrificial layer and the stacked structure includes: forming a connection unit at the same end of each of the repeating units; the connection unit includes: a plurality of connection portions arranged in a column along the first direction; the connection portions and the initial planar channel structure are different parts of the semiconductor layer, and the connection portions are located at the second end of the initial planar channel structure in the third direction; After forming the dielectric layer, the preparation method further includes: Remove the connecting portion to form a groove; The trench is filled with conductive material to form a bit line.

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