High frequency signal detection module and linear high frequency transmitter

Abstract

The application discloses a high-frequency signal detection module and a linear high-frequency transmitter, and belongs to the technical field of detection. The application comprises a high-frequency signal detection circuit, an interface circuit, a control processor and a high-frequency signal control circuit. The high-frequency signal detection circuit samples, extracts, arranges waveforms and detects amplitudes of high-frequency signals (DDS). The interface circuit receives, transmits, isolates and converts frame synchronization signals, bus signals and debugging signals. The high-frequency signal control circuit controls the on-off of high-frequency signals. The control processor receives control instructions and frame synchronization signals from a host computer, detects the amplitudes and frequencies of high-frequency signals, and schedules the timing of the whole detection process and control process. The application can accurately detect the amplitudes and frequencies of input high-frequency signals according to specific timing requirements, and controls the on-off of high-frequency signals according to the detection results, so as to protect the working safety of the linear high-frequency transmitter.

Description

Technical Field

[0001] This invention belongs to the field of detection technology, specifically relating to a high-frequency signal detection module and a linear high-frequency transmitter. Background Technology

[0002] In high-power linear high-frequency transmitter applications, the transmitter linearly amplifies the input high-frequency signal (DDS) to achieve the required amplitude. When the transmitter operates in the linear region and is far from the saturation point, large fluctuations in the input signal will cause significant fluctuations in the transmitter's output. If protection is not timely, this can have an overpower effect on the transmitter itself and the antenna feeder system, potentially leading to arcing, breakdown, or burnout. Therefore, we desire a stable input high-frequency signal (DDS) amplitude, or amplitude fluctuations limited to a certain range. Thus, it is necessary to monitor the high-frequency signal (DDS) amplitude input to the transmitter in real time and quickly cut off the DDS input when it exceeds a certain threshold to protect the transmitter and antenna feeder system.

[0003] In specific application scenarios, high-frequency transmitters output in working frames, each frame having a slightly different duration. The operating frequency and power amplitude of the high-frequency transmitter also differ across these frames. The operating frequency of the high-frequency transmitter is determined by the input high-frequency signal (DDS), while the power amplitude is controlled by the transmitter according to commands.

[0004] Because high-frequency transmitters have stringent harmonic control requirements, an effective solution is to use low-pass filters to remove high-order harmonic components. However, high-frequency transmitters have a wide operating bandwidth, reaching several harmonics, making it difficult for a single low-pass filter to cover the entire frequency band. Therefore, the transmitter's operating bandwidth is artificially divided into several sub-bands, each using a separate low-pass filter to remove high-order harmonic components. This method solves the problem of wide-band harmonic filtering, but it also introduces another issue: the low-pass filter must be matched to the operating frequency. If the operating frequency is outside the low-pass filter's band, insertion loss and VSWR will increase sharply, potentially leading to damage or burnout of the low-pass filter and power amplifier unit in severe cases.

[0005] When the system is operating, the main control computer simultaneously instructs the high-frequency transmitter and excitation source of the next frame's operating frequency via the network. Upon arrival of the frame synchronization signal, the excitation source switches its output high-frequency signal (DDS) to the target frequency, and the high-frequency transmitter also switches to its corresponding target sub-band. The frequency of the high-frequency signal (DDS) will match the filter sub-band. If network packet loss or other anomalies occur, the high-frequency signal (DDS) output by the excitation source may become mismatched with the transmitter's filter sub-band, potentially causing damage to the filter or power amplifier unit. Therefore, real-time monitoring of the high-frequency signal (DDS) output by the excitation source is necessary. When its frequency does not match the set band, the high-frequency signal (DDS) should be quickly cut off to protect the high-frequency transmitter from damage. Summary of the Invention

[0006] The purpose of this invention is to provide a high-frequency signal detection module that can accurately detect the amplitude and frequency of the high-frequency signal (DDS) input to the transmitter according to specific timing requirements, and control the on / off state of the high-frequency signal (DDS) based on the detection results, so as to protect the safe operation of the linear high-frequency transmitter.

[0007] Specifically, on the one hand, the present invention provides a high-frequency signal detection module, including a high-frequency signal detection circuit, an interface circuit, a control processor, and a high-frequency signal control circuit, wherein the high-frequency signal detection circuit, the interface circuit, and the high-frequency signal control circuit are all connected to the control processor;

[0008] The high-frequency signal detection circuit samples, extracts, shapes, and detects the amplitude of the high-frequency signal (DDS).

[0009] The interface circuit receives, transmits, isolates, and converts frame synchronization signals, bus signals, and debug signals.

[0010] The high-frequency signal control circuit controls the on / off state of the high-frequency signal (DDS);

[0011] The control processor includes a power supply chip, an FPGA, a crystal oscillator, and a FLASH memory. The power supply chip is connected to the input power supply, and its output is connected to the FPGA, crystal oscillator, and FLASH memory to provide power. The crystal oscillator is connected to the FPGA to provide a clock reference. The FLASH memory is connected to the FPGA to provide storage space. The FPGA receives and parses the frame synchronization signal converted by the interface circuit, communicates with the host computer in real time through the bus interface circuit, receives control commands, performs amplitude and frequency detection on the high-frequency signal (DDS), controls the on / off state of the high-frequency signal (DDS) based on the detection results, uploads the amplitude and frequency detection results of the high-frequency signal (DDS), and performs timing scheduling for the entire detection and control process.

[0012] Furthermore, the high-frequency signal detection circuit includes a coupler, a power divider, a shaping circuit, and an amplitude detection circuit;

[0013] The coupler is connected in series in the radio frequency link where the high-frequency signal (DDS) is located. The coupling interface of the coupler is connected to the input port of the power divider. The output port 1 of the power divider is connected to the shaping circuit. The output port 2 of the power divider is connected to the amplitude detection circuit. The output port of the shaping circuit is connected to the control processor. The output port of the amplitude detection circuit is connected to the control processor.

[0014] Furthermore, the interface circuit includes a frame synchronization signal interface circuit, a bus interface circuit, and a debugging interface circuit;

[0015] The frame synchronization signal interface circuit is connected to the frame synchronization input signal link, and the output terminal of the frame synchronization signal interface circuit is connected to the control processor I / O.

[0016] The bus interface circuit is connected to the system application bus input link, and the output of the bus interface circuit is connected to the control processor.

[0017] The debugging interface circuit is connected to the control processor.

[0018] Furthermore, the amplitude detection of the high-frequency signal (DDS) includes:

[0019] The FPGA receives the detection voltage output from the amplitude detection circuit, performs analog-to-digital conversion, and fits the correlation between the amplitude-related digital quantity and the true amplitude. When the amplitude-related digital quantity exceeds a set upper threshold, the control processor immediately sends a high-frequency switch control signal to cut off the input of the high-frequency signal (DDS). When the amplitude-related digital quantity is lower than a set lower threshold, the control processor only sends an alarm message to indicate that the input high-frequency signal (DDS) amplitude is low, but does not cut off the input of the high-frequency signal (DDS).

[0020] Furthermore, the frequency detection of the high-frequency signal (DDS) includes:

[0021] Determine when the high-frequency signal (DDS) appears, and enter a measurement window of a set duration after the high-frequency signal (DDS) appears;

[0022] The FPGA receives the high-frequency signal (DDS) processed by the shaping circuit and counts the high-frequency signal (DDS) within a set measurement window period. That is, it samples and judges the high-frequency signal (DDS) with a rising edge of a clock. One rising edge means that one cycle has occurred. Based on the number of cycles N of the high-frequency signal (DDS) measured within the set measurement window period, the frequency value f = N × 20 kHz is calculated.

[0023] Furthermore, the step of using a frame synchronization pulse signal to determine when the high-frequency signal (DDS) appears specifically includes:

[0024] When the control processor detects the rising edge of the frame synchronization pulse signal, it loads the set frequency value of the current frame previously received by the control processor, and then waits for the set time before assuming that the high-frequency signal (DDS) has appeared.

[0025] Furthermore, the method of using short pulse signals to determine when a high-frequency signal (DDS) appears specifically includes:

[0026] A counter Cnt is set up. When the high-frequency signal (DDS) is detected, Cnt = 0. When the high-frequency signal (DDS) is not detected, Cnt starts counting. It is assumed that one count is made every 1 μs. When the count reaches the set count value, the set count value is kept unchanged until the high-frequency signal (DDS) appears and then becomes 0.

[0027] A flag signal Cnt Puls is defined. When the counter Cnt equals the set count value, Cnt Puls = 1; otherwise, Cnt Puls = 0. A short pulse is then set based on the falling edge of Cnt Puls changing from "1" to "0" to indicate the appearance of the next frame high-frequency signal (DDS).

[0028] Furthermore, the high-frequency signal detection module simultaneously processes the high-frequency signal (DDS) as follows:

[0029] The high-frequency signal (DDS) is determined by using a frame synchronization pulse signal: when the control processor detects the rising edge of the frame synchronization pulse signal, it loads the set frequency value of the current frame previously received by the control processor, and then waits for the set time before considering the arrival of the high-frequency signal (DDS).

[0030] Short pulse signals are used to determine when a high-frequency signal (DDS) appears: A counter Cnt is set. When the high-frequency signal (DDS) is detected, Cnt = 0. If the high-frequency signal (DDS) is not detected, Cnt starts counting. Assuming that one count is made every 1 μs, the count remains unchanged until the high-frequency signal (DDS) appears, and then becomes 0.

[0031] A flag signal Cnt Puls is defined. When the counter Cnt equals the set count value, Cnt Puls = 1; otherwise, Cnt Puls = 0. A short pulse is then set based on the falling edge of Cnt Puls changing from "1" to "0" to indicate the appearance of the next frame high-frequency signal (DDS).

[0032] The control processor performs a "phase OR" operation on the frame synchronization pulse signal and the short pulse indicating the appearance of the next frame high-frequency signal (DDS), and uses the first rising edge of the processing result as the identifier signal for starting measurement within the set measurement window period.

[0033] Furthermore, when the high-frequency signal (DDS) appears, it is first determined whether the high-frequency signal (DDS) exists, and after waiting for a set period of time, the frequency of the high-frequency signal (DDS) is detected.

[0034] On the other hand, the present invention also provides a linear high-frequency transmitter, including the above-mentioned high-frequency signal detection module.

[0035] The beneficial effects of the high-frequency signal detection module and linear high-frequency transmitter of the present invention are as follows:

[0036] The high-frequency signal detection module of the present invention can monitor the amplitude of the high-frequency signal (DDS) input to the linear high-frequency transmitter in real time. When the amplitude exceeds a certain threshold, the high-frequency signal detection module can quickly cut off the input of the high-frequency signal (DDS) before the linear high-frequency transmitter starts working, thus protecting the linear high-frequency transmitter or antenna feeder system from overpower failure.

[0037] Due to harmonic filtering and other considerations, linear high-frequency transmitters are divided into several sub-bands in the frequency domain. The operating frequency of the input high-frequency signal (DDS) needs to match the operating sub-band of the linear high-frequency transmitter. At this point, the system insertion loss and VSWR of the linear high-frequency transmitter are within a reasonable range. When the operating frequency of the input high-frequency signal (DDS) does not match the operating sub-band of the linear high-frequency transmitter, the system insertion loss and VSWR of the linear high-frequency transmitter will increase sharply. In severe cases, this can cause overheating or total reflection damage to the internal radio frequency components of the linear high-frequency transmitter. The high-frequency signal detection module of this invention can monitor the frequency of the input high-frequency signal (DDS) in real time. When a certain deviation occurs in its frequency, the high-frequency signal detection module can quickly cut off the input of the high-frequency signal (DDS) before the linear high-frequency transmitter starts operating, protecting the internal radio frequency components of the linear high-frequency transmitter.

[0038] The control processor performs a phase-OR operation on the short pulses of the frame synchronization pulse signal and the marker high-frequency signal (DDS). The first rising edge of the processing result is used as the marker signal to begin measurement within a 50μs measurement window. When the high-frequency signal (DDS) appears, its presence is first determined, and then frequency detection is performed on the high-frequency signal (DDS) after a 20μs delay. This avoids the unstable initial period of the high-frequency signal (DDS) in linear frequency modulation mode. Practice has shown that the measurement method and results obtained by combining the two signal appearance determination methods are more stable and accurate. Attached Figure Description

[0039] Figure 1 This is a timing diagram and measurement schematic diagram of the high-frequency signal (DDS) in this embodiment.

[0040] Figure 2 This is a schematic diagram of a high-frequency signal detection module in this embodiment.

[0041] Figure 3 This is a schematic diagram of the high-frequency signal (DDS) shaping circuit in this embodiment.

[0042] Figure 4 This is a schematic diagram of high-frequency signal (DDS) amplitude detection in this embodiment.

[0043] Figure 5 This is a schematic diagram of the CAN bus interface design circuit in this embodiment.

[0044] Figure 6 This is a block diagram of the control processor in this embodiment.

[0045] Figure 7This is a schematic diagram of the amplitude detection ADC sampling in this embodiment, where (a) is a schematic diagram of the detected voltage waveform obtained by the amplitude detection circuit, (b) is a schematic diagram of the sampling circuit structure, (c) is a schematic diagram of the signal waveform after sampling, (d) is a schematic diagram of the sampled waveform after processing by the holding circuit, (e) is a schematic diagram of the quantized voltage waveform, and (f) is a schematic diagram of the encoded voltage value.

[0046] Figure 8 This is a schematic diagram of high-frequency signal (DDS) frequency detection in this embodiment.

[0047] Figure 9 This is a schematic diagram of the high-frequency signal (DDS) period counting principle in this embodiment.

[0048] Figure 10 This is a schematic diagram illustrating the principle of high-frequency signal (DDS) detection in this embodiment.

[0049] Figure 11 This is a schematic diagram of the linear frequency modulation signal testing method in this embodiment.

[0050] Figure 12 This is a schematic diagram of the optocoupler isolation circuit in this embodiment. Detailed Implementation

[0051] The present invention will now be described in further detail with reference to the embodiments and the accompanying drawings.

[0052] One embodiment of the present invention is a high-frequency signal detection module, which is suitable for high-power linear high-frequency transmitters that have strict requirements on the amplitude and frequency of the input signal.

[0053] like Figure 1 As shown, the input signal of a linear high-frequency transmitter includes a high-frequency signal (DDS), a frame synchronization signal (Mgs), and a time-width synchronization signal (M0). The timing relationship between these three follows a specific requirement. The linear high-frequency transmitter operates in working frames, each with a variable duration, ranging from hundreds of milliseconds to tens of seconds. Within each working frame, the high-frequency signal (DDS) oscillates according to the time-width synchronization signal, lasts for tens of milliseconds, and then stops. The number of time-width synchronization signals is typically 64 or an integer multiple thereof; that is, within a working frame, the high-frequency signal (DDS) consists of a pulse train of 64 or an integer multiple thereof. The amplitude and frequency of the output signal of the linear high-frequency transmitter are different in different working frames, controlled by system commands.

[0054] like Figure 1As shown, after the first frame synchronization signal (Mgs) arrives, the system waits 500μs for the first time-width synchronization signal (M0) to arrive, and then waits another 70μs for the high-frequency signal (DDS) to start oscillating. That is, the high-frequency signal (DDS) starts oscillating 570μs after the first frame synchronization signal (Mgs) arrives, operates for tens of milliseconds, and then stops outputting. The second time-width synchronization signal (M0) arrives 10μs later, and the high-frequency signal (DDS) starts oscillating a second time after another 70μs, and so on. The high-frequency signal (DDS) outputs 64 pulses or multiples thereof before stopping outputting, waiting for the second frame synchronization signal (Mgs) to arrive. Within the second working frame, the operating frequency of the high-frequency signal (DDS) will change according to system requirements.

[0055] The operational information for each frame, including power and frequency, is communicated to the linear high-frequency transmitter in advance via bus or network. After receiving the operational information, the linear high-frequency transmitter waits for the frame synchronization signal (Mgs) to trigger and activate the operational information. Then, it waits for the input high-frequency signal (DDS) to start oscillating before performing amplitude and frequency detection on the high-frequency signal (DDS).

[0056] The amplitude of the high-frequency signal (DDS) should be limited to a certain range. When it exceeds the upper limit, the high-frequency signal (DDS) input should be cut off immediately and a fault message indicating that the input is too large should be given. When it is below the lower limit, the high-frequency signal (DDS) input should not be cut off, but a warning message indicating that the input is too low should be given.

[0057] like Figure 1 As shown, frequency detection of the high-frequency signal (DDS) is performed only on the first pulse after the frame synchronization pulse, and the measurement process must be completed within tens of μs. The frequency measurement result is compared with the operating frequency received by the linear high-frequency transmitter. If the measurement result differs from the operating frequency by more than ±500kHz, it is considered a frequency error fault. When a frequency error fault occurs, the high-frequency signal (DDS) input should be immediately cut off, and a frequency error message should be provided. The high-frequency signal (DDS) input cutoff caused by a frequency error generally lasts for one frame. When the next working frame arrives, the fault is cleared, and the frequency information of the high-frequency signal (DDS) is re-detected. If the frequency is normal, the high-frequency signal (DDS) input will be reopened; if a frequency error occurs, the high-frequency signal (DDS) input cutoff will continue.

[0058] The high-frequency signal detection module of this invention includes a high-frequency signal detection circuit, an interface circuit, a control processor, and a high-frequency signal control circuit. For example... Figure 2As shown, the high-frequency signal detection circuit, interface circuit, and high-frequency signal control circuit are all connected to the control processor. The high-frequency signal detection circuit is mainly used for sampling, extracting, amplitude detection, and waveform shaping of the high-frequency signal (DDS). The interface circuit is mainly used for receiving, transmitting, isolating, and converting frame synchronization signals, bus signals, and debugging signals. The high-frequency signal control circuit is a sub-functional component of the high-frequency signal detection module, mainly used for controlling the on / off state of the high-frequency signal (DDS). The control processor is the core control component of the high-frequency signal detection module, mainly used for receiving control commands from the host computer and the frame synchronization signal converted by the interface circuit, detecting the amplitude and frequency of the high-frequency signal (DDS), controlling the input of the high-frequency signal (DDS), storing and uploading the detection results, and scheduling the entire detection and control process.

[0059] I. High-frequency signal detection circuit

[0060] The high-frequency signal detection circuit mainly consists of a coupler, a power divider, a shaping circuit, and an amplitude detection circuit. The coupler is connected in series in the radio frequency link where the high-frequency signal (DDS) is located. The coupling interface of the coupler is connected to the input port of the power divider. Output port 1 of the power divider is connected to the shaping circuit. Output port 2 of the power divider is connected to the amplitude detection circuit. The output port of the shaping circuit is connected to the control processor. The output port of the amplitude detection circuit is also connected to the control processor.

[0061] Couplers are primarily used for sampling high-frequency signals (DDS). The sampled signal should accurately reflect the key information of the main signal. Preferably, the circuit design should select a coupler with low insertion loss, good coupling flatness, and good directivity (or isolation). Regarding the selection of coupling degree, to reduce the impact on the main high-frequency signal (DDS), the coupling degree cannot be too small. On the other hand, under the condition of fixed detection resolution, to improve detection accuracy, it is desirable to obtain a sufficiently high amplitude of the sampled signal, which requires appropriately reducing the coupling degree. Since the amplitude of the input high-frequency signal (DDS) generally does not exceed 50 milliwatts, considering power tolerance and size, the coupler selection does not need to be too large. In this embodiment, the selected coupler is DOQ-20-4ZFM, with a coupling degree of 20dB, a power tolerance of 1W, and a bandwidth that covers the usage requirements.

[0062] A power divider is a multi-port network with reciprocal power transmission. Its main function is to split the signal from the combining port into two signals of equal or unequal power, which are then output from the distribution port. Power dividers are classified into equal-power 0° power dividers, equal-power 90° power dividers, equal-power 180° power dividers, and unequal-power 0° power dividers, etc. The main specifications of a power divider include frequency range, maximum power handling capacity, isolation, amplitude balance, and insertion loss. In this embodiment, an equal-power 0° power divider is selected, and a power handling capacity of only 1W is sufficient to meet the requirements.

[0063] A shaping circuit is used to process an input high-frequency signal (DDS) from a sinusoidal waveform into a square wave of the same frequency, which is easier for digital signal processing. For example... Figure 3 As shown. In this invention, the Schmitt trigger is a commonly used solution for pulse waveform transformation. Schmitt triggers can be used for waveform transformation, pulse shaping, pulse amplitude discrimination, and other applications. Currently, commonly used Schmitt triggers are constructed from digital integrated circuit chips, and their output waveform is a unipolar high- and low-level rectangular wave.

[0064] An amplitude detection circuit is used to detect the amplitude of a high-frequency signal (DDS) and provides a DC voltage related to the amplitude of the DDS. The amplitude detection circuit includes a detector, a transport amplifier, etc., where the detector is a logarithmic detector, and the power level of its input high-frequency signal should be within the "square-law range," such as... Figure 4 As shown, this will result in a relatively obvious logarithmic relationship between the output voltage generated by the detector and the coupled power. Beyond this range, the circuit's sensitivity gradually decreases. This "square-law range" is also known as the dynamic range of the power detector. The detector cannot detect excessively low signal power, as such signals may fall below the detector's noise floor, significantly increasing measurement errors. Conversely, the detector cannot detect excessively high signal power, as this may cause detector saturation or even damage. If the detector gain is low, the voltage range of the high-frequency signal (DDS) after detection is small. Accurately detecting changes in signal power places high demands on the resolution of the downstream ADC (Analog-to-Digital Converter). To resolve this contradiction, an operational amplifier can be added after the detector circuit to proportionally amplify the detected voltage to a larger set dynamic range. This can improve the power detection accuracy under fixed ADC resolution conditions.

[0065] II. Interface Circuit

[0066] The interface circuit includes a frame synchronization signal interface circuit, a bus interface circuit, and a debug interface circuit, which receive, transmit, isolate, and convert frame synchronization signals, bus signals, and debug signals. The frame synchronization signal interface circuit is connected to the frame synchronization signal input, and its output is connected to the control processor I / O. In this embodiment, the bus interface circuit is connected to the system application bus input link, and its output is connected to the control processor. The debug interface circuit is connected to the control processor.

[0067] The frame synchronization signal interface circuit is mainly used for receiving and converting frame synchronization signals. Frame synchronization signals are generally TTL pulses with a width of 1μs, which have high requirements for transmission distance and timing. Therefore, a differential signal format is used to effectively solve problems such as anti-interference, electromagnetic interference suppression, and accurate timing. Differential transmission converts the unbalanced TTL signal into a balanced differential signal, typically done by a single transmitting IC; differential reception converts the balanced differential signal back into an unbalanced TTL signal, typically done by a single receiving IC. In this embodiment of the invention, the frame synchronization signal interface circuit mainly includes a receiving IC and a connection line termination matching circuit. The frame synchronization signal interface circuit sends the converted TTL frame synchronization signal to the control processor for use as a timing trigger pulse signal.

[0068] In this embodiment, the bus interface circuit refers to the CAN bus interface circuit, which is mainly used for the reception, transmission, isolation, and protection of CAN signals. It is understood that other bus forms, such as 422 bus and 232 bus, can also be used for the bus interface circuit. In this embodiment, the number of CAN bus nodes is large, and interference is complex. The CAN bus has strict requirements for common-mode interference, generally requiring the common-mode power supply to be between -7V and 12V. If the common-mode voltage exceeds this range, it will affect the normal communication of the CAN nodes. The CAN bus interface circuit is generally designed according to the following principles: 1) Add common-mode suppressors to the CANL and CANH channels; 2) Connect 22pF capacitors in parallel with the signal ground of CANL and CANH; 3) In high-power devices with extremely strong interference, if the first two measures are ineffective, a 2Ω resistor and a 0.68pF capacitor can be connected in series between the CAN bus signal ground and the chassis. The CAN bus has a high impedance to signal ground, typically tens of kΩ, and network transmission between buses can introduce induced coupling voltage spikes, which can damage or destroy the CAN interface chip. Therefore, a transient voltage suppressor (TVS) needs to be added to the CAN bus input for protection. Figure 5As shown, in this embodiment of the invention, a classic CAN bus interface circuit design is adopted. The transient voltage suppressor NUP2105LT1G is connected to the CANL and CANH channels and is connected to the signal ground. The 2Ω resistor and 0.68pF capacitor are connected to the bus signal ground and the chassis. The 22pF capacitor is connected to the CANL and CANH channels and is connected to the signal ground. The common-mode suppressor B82799S0513N001 is connected to the CANL and CANH channels and is connected to the CAN transceiver chip MAX3057ASA.

[0069] The debug interface circuit (JTAG interface) is an international standard test protocol (IEEE 1149.1 compliant) primarily used for chip hardware and software testing, programming downloads, and in-circuit logic analysis. Most advanced devices currently support the JTAG protocol, such as DSPs and FPGAs. A standard JTAG interface has four lines: TMS (mode select), TCK (clock), TDI (data input), and TDO (data output). Originally used for chip testing, JTAG is now also commonly used to implement ISP (In-System Programmer) for programming devices such as FLASH memory.

[0070] III. Control Processor

[0071] The control processor receives control commands from the host computer and frame synchronization signals converted by the interface circuit. It performs amplitude and frequency detection on the high-frequency signal (DDS), controls the on / off state of the high-frequency signal (DDS) based on the detection results, stores and uploads the detection results, and schedules the entire detection and control process.

[0072] In this invention, the control processor includes a power supply chip, an FPGA, a crystal oscillator, and a FLASH memory, etc. Figure 6 As shown. In Figure 6 In this configuration, the power chip is connected to an external input power supply, and the output of the power chip is connected to the FPGA, crystal oscillator, FLASH memory, etc., to provide them with power; the crystal oscillator is connected to the FPGA to provide a clock reference for the FPGA; and the FLASH memory is connected to the FPGA to provide storage space for the FPGA.

[0073] An FPGA, or Field-Programmable Gate Array, is the core control module of a control processor. It's a hardware-reconfigurable chip whose internal structure can be changed through programming. An FPGA is a digital circuit that can perform tasks that other digital circuits can. Its programmability means its logic circuitry can be modified, and it's also erasable and rewritable, not disposable. The flexibility and high speed of FPGAs give them a unique advantage in digital signal processing applications. The FPGA is responsible for receiving and parsing the frame synchronization signal converted by the interface circuit, communicating with the host computer in real time through the bus interface circuit, receiving control commands, performing amplitude and frequency detection on the high-frequency signal (DDS), controlling the on / off state of the DDS based on the detection results, uploading the amplitude and frequency detection results, and timing the entire detection and control process.

[0074] Amplitude detection of the high-frequency signal (DDS) includes: the FPGA receiving the detection voltage output from the amplitude detection circuit, performing analog-to-digital conversion, and fitting the correlation between the amplitude-related digital quantity and the true amplitude; when the amplitude-related digital quantity exceeds a set upper threshold, the control processor immediately sends a high-frequency switch control signal to cut off the input of the high-frequency signal (DDS); when the amplitude-related digital quantity is lower than a set lower threshold, the control processor only sends an alarm message to indicate that the amplitude of the input high-frequency signal (DDS) is low, but does not cut off the input of the high-frequency signal (DDS).

[0075] like Figure 7 As shown in (a), combined with the high-frequency signal (DDS) amplitude detection algorithm, the detected voltage output by the amplitude detection circuit is sent to the on-chip ADC analog-to-digital converter (ADC) of the FPGA. In the ADC, the detected voltage is first sampled, which converts the continuously changing analog quantity over time into a time-discrete analog quantity. Figure 7 (b) is the sampling circuit structure, where the transmission gate is controlled by the sampling signal s(t). During the pulse width τ of s(t), the transmission gate is turned on, and the output of f(t) is f. s (t), sampling complete. The sampled signal waveform is as follows: Figure 7 As shown in (c), analysis reveals that the higher the frequency of the sampled signal s(t), the more accurately the sampled waveform reflects the changes in the input signal. Converting the analog signal obtained from the sampling circuit to a digital signal requires a certain amount of time. To provide a stable value for the subsequent quantization and encoding process, each acquired analog signal must be held for a period of time by a holding circuit. The sampled waveform after processing by the holding circuit is shown below. Figure 7As shown in (d), during the A / D conversion process, the voltage output of the sample-and-hold signal needs to be normalized to the corresponding discrete level in a certain approximate way. This conversion process is called numerical quantization. Quantization is to convert each voltage value in the stepped analog signal into an integer multiple of a certain smallest unit, so that it can be represented by digital quantities. The quantized voltage waveform is shown in (d). Figure 7 As shown in (e). Finally, the quantized values ​​are encoded. Encoding involves representing the quantization result (i.e., integer multiples) using binary digits. The encoded voltage value is shown below. Figure 7 As shown in (f). A key specification of an ADC (Analog-to-Digital Converter) is its resolution, typically expressed in bits, such as 8-bit, 10-bit, or 16-bit. Higher bit counts indicate higher ADC resolution. The amplitude digital value after ADC conversion is sent to the processor, where it can be read, stored, processed, corrected, and compared. Since sampling coupling, frequency response, and insertion loss can affect the accuracy of amplitude detection, the processor needs to fit the correlation between the input amplitude digital value and the true amplitude. This fitting includes amplitude curve fitting and frequency curve fitting. After this processing, the correlation between the sampled amplitude digital value and the true amplitude is clarified, meaning the sampled digital value accurately reflects the true amplitude data.

[0076] Frequency detection of a high-frequency signal (DDS) includes: determining when the high-frequency signal (DDS) appears; after the high-frequency signal (DDS) appears, waiting for a period of time before entering a measurement window of a set duration; the FPGA receives the high-frequency signal (DDS) output by the shaping circuit and counts the high-frequency signal (DDS) within the set measurement window, that is, sampling and judging the high-frequency signal (DDS) with a rising edge of a clock. One rising edge means that one cycle has occurred. The frequency value is calculated based on the number of cycles of the measured high-frequency signal (DDS) within the set measurement window.

[0077] This invention can use a frame synchronization pulse signal to determine when the high-frequency signal occurs, specifically including:

[0078] like Figure 8 As shown, when the control processor detects the rising edge of the frame synchronization pulse signal, it loads the previously received frame set frequency value and waits 570μs before assuming the high-frequency signal (DDS) has appeared. After the high-frequency signal (DDS) appears, a 50μs measurement window is entered after a waiting period. The FPGA receives the high-frequency signal (DDS) output from the shaping circuit and counts it within the 50μs measurement window. The counting principle is to sample and judge the high-frequency signal (DDS) using the rising edge of a clock. Figure 9In this embodiment of the invention, a high-frequency clock frequency of 200MHz is selected. The signal under test is sampled using the rising edge of the 200MHz clock. Since the digital system only has two states, "0" and "1", a change from "0" to "1" will occur at the rising edge of the signal under test. By comparing the registers, it can be determined that a rising edge has occurred in the signal under test. One rising edge means one cycle has occurred. Based on the number of cycles N of the high-frequency signal (DDS) under test measured within the 50μs measurement window, the frequency value f = N × 20kHz is calculated.

[0079] In actual measurements, it was found that when the system uses a linear frequency modulated signal, if the 50μs measurement begins immediately after the high-frequency signal (DDS) appears, the measurement results will have a large error. The reason for this is likely that the excitation source may require a stabilization process after being turned off and then back on. The solution is to first determine the presence of the high-frequency signal (DDS) after it appears, wait for a period of time, and then start counting the high-frequency signal (DDS) within the 50μs measurement window. For example... Figure 8 The 20μs before the initial 50μs, the gray portion, is used to determine the presence of a high-frequency signal (DDS) and to avoid the unstable initial phase of the DDS in linear frequency modulation mode. During this time, the DDS is relatively stable, resulting in more accurate measurements. This 20μs period can also be used to determine the presence of the signal. When counting the DDS within the 50μs measurement window, a 50μs high-level signal can be generated first, during which the processor is controlled to count the DDS. Assuming the number of cycles of the DDS measured in these 50μs is N, since 1 second ÷ 50μs = 20kHz, the number of cycles in 1 second is the frequency of the DDS. Therefore, based on the measured number of cycles N, the frequency value f = N × 20kHz is calculated. Assuming the measured number of cycles N in 50μs is 500, the measured frequency of the DDS is f = 500 × 20kHz = 10MHz. Therefore, it can be seen that the theoretical accuracy of the high-frequency signal (DDS) frequency value obtained with a measurement window of 50μs is 20kHz, or the measurement resolution is 20kHz. That is, if one number is undercounted or overcounted within 50μs, the final result will differ by 20kHz. Considering that the detection threshold is 500kHz, the detection accuracy is 20kHz ÷ 500kHz = 4%, which is within an acceptable range.

[0080] Furthermore, in Figure 1In the high-frequency signal timing diagram shown, a frame synchronization pulse signal is used to determine when the high-frequency signal (DDS) appears. For example, the method for determining the appearance of the high-frequency signal (DDS) is based on the system's operating principle that it will inevitably appear 570μs after the frame synchronization signal. However, during system operation, the frame synchronization signal may occasionally be lost. In this case, it is impossible to determine the appearance time of the next frame high-frequency signal (DDS), and the frequency will inevitably be judged incorrectly. To prevent this from happening, this invention also provides a method for determining when the high-frequency signal (DDS) appears using a short pulse signal, which determines the appearance time of the next frame high-frequency signal (DDS) when there is no frame synchronization signal. The principle is as follows: Figure 10 As shown, according to Figure 9 The presence of a high-frequency signal (DDS) can be determined by sampling the input high-frequency signal (DDS) using a 200MHz internal clock. However, determining the start of the next frame requires a more complex method. First, a counter Cnt is set. When a high-frequency signal (DDS) is detected, Cnt = 0. If no high-frequency signal (DDS) is detected, Cnt starts counting, assuming one count per μs. When the count reaches a set value (e.g., 575 μs), it remains at that set value until the high-frequency signal (DDS) appears, at which point it becomes 0. A flag signal Cnt Puls is also set. When the counter Cnt equals the set value (e.g., Cnt = 575 μs), Cnt Puls = 1; otherwise, Cnt Puls = 0. A short pulse (DDS In) is generated based on the falling edge of Cnt Puls changing from "1" to "0". The appearance of this short pulse indicates the presence of the high-frequency signal (DDS) in the next frame. Since the M0 interval within each frame is only 80μs, it will not cause the counter Cnt to count to 575μs, so there will be no short pulse of DDS In, and therefore no misjudgment will occur.

[0081] Furthermore, in combination Figure 1 , Figure 10 , Figure 11 By combining a linear frequency modulated signal detection algorithm, two methods are used to determine when the high-frequency signal (DDS) appears and measurement begins: frame synchronization signal detection and short pulse detection to identify the appearance of the high-frequency signal (DDS). Only by considering both methods in a unified manner can the measurement results be guaranteed to be accurate and without missing frames. The implementation method is as follows: Figure 11As shown, the high-frequency signal (DDS) is processed using a combination of two methods: judging by the frame synchronization pulse signal and judging by the short pulse signal indicating the appearance of the high-frequency signal (DDS). The frame synchronization pulse signal and the short pulse indicating the appearance of the high-frequency signal (DDS) are ORed. The processor performs an OR operation on these two conditions. Detecting either pulse is sufficient to initiate the measurement. The first rising edge of the processing result is used as the marker signal to begin measurement within the set measurement window (50 μs). Practice has shown that the combined method and results are more stable and accurate.

[0082] Preferably, when the high-frequency signal (DDS) appears, the presence or absence of the high-frequency signal (DDS) is first determined, and then the frequency of the high-frequency signal (DDS) is detected after a delay of 20μs. At this time, the high-frequency signal (DDS) is relatively stable, and the measurement result is more accurate. At the same time, this 20μs can also be used to determine the presence or absence of the signal, which can avoid the initial unstable period of the high-frequency signal (DDS) in linear frequency modulation mode.

[0083] A crystal oscillator is used to provide a fixed-frequency clock synchronization signal to an FPGA. It is fundamental to the operation of the FPGA chip. Generally speaking, the higher the crystal oscillator frequency, the faster the FPGA chip operates. A crystal oscillator consists of a crystal and its driving circuit. The choice of crystal oscillator frequency is related to the amplitude, power consumption, and speed of the FPGA's internal circuitry, and needs to be selected based on the actual system requirements and stability requirements.

[0084] FLASH memory is used to store programs for FPGAs. After the operator completes the program, it is downloaded to the FPGA via the JTAG interface. The FPGA receives the data, verifies its accuracy, and writes it into the FLASH memory, completing the program update and storage. Each time power is supplied, the program in the FLASH memory is loaded into the FPGA and executed. FLASH memory is non-volatile memory, capable of retaining data for a long time even without a current supply. Its storage characteristics are similar to a hard drive. FLASH memory can be erased, written to, and reprogrammed. Write operations to FLASH memory can only be performed on empty or erased cells.

[0085] IV. High-frequency signal control circuit

[0086] High-frequency signal control circuits include high-frequency switches, optocoupler isolation circuits, etc.

[0087] High-frequency switches are used for cutting off high-frequency signals (DDS). Connected in series in the DDS transmission link, they are driven by control signals output from the FPGA and can quickly cut off the DDS input. High-frequency switches typically use PIN diode switches. These switches utilize the near-conduction or deactivation impedance characteristics of PIN diodes under DC forward and reverse bias to control the switching of high-frequency signal channels.

[0088] Optocoupler isolation circuits are primarily used for output isolation of high-frequency switch drive signals. Considering interference immunity and providing necessary protection for the FPGA, the I / O switching signals output by the FPGA should not directly drive the switching circuit; optocoupler isolation is required before driving high-frequency switches. The principle of optocoupler isolation is to utilize the photoelectric effect to convert electrical signals into optical signals, which are then transmitted to another circuit, thereby achieving signal isolation. Figure 12 A typical optocoupler isolation circuit is shown in the figure. The optocoupler isolation chip is connected to the FPGA, the optocoupler isolation chip is connected to a transient voltage suppressor (TVS), the transient voltage suppressor (TVS) is connected to capacitor C14, the transient voltage suppressor (TVS) is connected to resistor R81, and resistor R81 is connected to a high-frequency switching circuit. Figure 12 In the circuit, when DOUT1 is low, the LED of V3 is turned on. Through optical coupling, the photodiode at terminals 3-4 of V3 generates current, thereby controlling SW+ and SW- to achieve connection in the circuit.

[0089] The high-frequency signal detection module of the present invention can monitor the amplitude of the high-frequency signal (DDS) input to the linear high-frequency transmitter in real time. When the amplitude exceeds a certain threshold, the high-frequency signal detection module can quickly cut off the input of the high-frequency signal (DDS) before the linear high-frequency transmitter starts working, thus protecting the linear high-frequency transmitter or antenna feeder system from overpower failure.

[0090] Due to harmonic filtering and other considerations, linear high-frequency transmitters are divided into several sub-bands in the frequency domain. The operating frequency of the input high-frequency signal (DDS) needs to match the operating sub-band of the linear high-frequency transmitter. At this point, the system insertion loss and VSWR of the linear high-frequency transmitter are within a reasonable range. When the operating frequency of the input high-frequency signal (DDS) does not match the operating sub-band of the linear high-frequency transmitter, the system insertion loss and VSWR of the linear high-frequency transmitter will increase sharply. In severe cases, this can cause overheating or total reflection damage to the internal radio frequency components of the linear high-frequency transmitter. The high-frequency signal detection module of this invention can monitor the frequency of the input high-frequency signal (DDS) in real time. When a certain deviation occurs in its frequency, the high-frequency signal detection module can quickly cut off the input of the high-frequency signal (DDS) before the linear high-frequency transmitter starts operating, protecting the internal radio frequency components of the linear high-frequency transmitter.

[0091] Frequency detection employs two methods: frame synchronization pulse signal judgment and short pulse judgment based on the appearance of a high-frequency signal (DDS). The control processor performs a "phase OR" operation on these two methods, using the first rising edge of the result as the marker signal to begin measurement within a 50μs measurement window. When the high-frequency signal (DDS) appears, its presence is first determined, and then frequency detection is performed after a 20μs delay. This avoids the initial unstable period of the high-frequency signal (DDS) in linear frequency modulation mode. Practice has proven that the measurement method and results combining these two judgment methods are more stable and accurate.

[0092] While the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the invention. Any equivalent changes or modifications made without departing from the spirit and scope of the invention are also within the scope of protection of the invention. Therefore, the scope of protection of the present invention should be determined by the claims of this application.

Claims

1. A high-frequency signal detection module, characterized in that, It includes a high-frequency signal detection circuit, an interface circuit, a control processor, and a high-frequency signal control circuit, all of which are connected to the control processor. The high-frequency signal detection circuit samples, extracts, shapes the waveform, and detects the amplitude of the high-frequency signal. The interface circuit receives, transmits, isolates, and converts frame synchronization signals, bus signals, and debug signals. The high-frequency signal control circuit controls the on / off state of the high-frequency signal; The control processor includes a power supply chip, an FPGA, a crystal oscillator, and a FLASH memory; the power supply chip is connected to the input power supply, and the output of the power supply chip is connected to the FPGA, the crystal oscillator, and the FLASH memory to provide power to them; the crystal oscillator is connected to the FPGA to provide a clock reference for the FPGA; the FLASH memory is connected to the FPGA to provide storage space for the FPGA. The FPGA receives and parses the frame synchronization signal converted by the interface circuit, communicates with the host computer in real time through the bus interface circuit, receives control commands, performs amplitude and frequency detection on the high-frequency signal, controls the on / off state of the high-frequency signal based on the detection results, uploads the amplitude and frequency detection results of the high-frequency signal, and performs timing scheduling for the entire detection and control process. The frequency detection of the high-frequency signal includes: determining when the high-frequency signal appears; when the high-frequency signal appears, counting the high-frequency signal within a set measurement window period, that is, sampling and judging the high-frequency signal using a rising edge of a clock. One rising edge means that one cycle has appeared. Based on the number of high-frequency signal occurrence cycles N measured within the set measurement window period, the frequency value f = N × 20 kHz is calculated. Simultaneously, the high-frequency signal is processed as follows: The high-frequency signal is determined by using a frame synchronization pulse signal: when the control processor detects the rising edge of the frame synchronization pulse signal, it loads the set frequency value of the current frame previously received by the control processor, and then waits for a set time before considering the arrival of the high-frequency signal. Short pulse signals are used to determine when a high-frequency signal appears: A counter Cnt is set up. When the high-frequency signal is detected, Cnt = 0. If the high-frequency signal is not detected, Cnt starts counting. Assuming that it counts one number every 1μs, when the count reaches the set count value, it remains unchanged until the high-frequency signal appears and then becomes 0. A flag signal Cnt Puls is set. When the counter Cnt equals the set count value, Cnt Puls = 1; otherwise, Cnt Puls = 0. A short pulse is set according to the falling edge of Cnt Puls changing from "1" to "0" to indicate the appearance of the high-frequency signal in the next frame. The control processor performs a "phase OR" operation on the frame synchronization pulse signal and the short pulse indicating the occurrence of the high-frequency signal of the next frame, and uses the first rising edge of the processing result as the identification signal for starting measurement within the set measurement window period.

2. The high-frequency signal detection module according to claim 1, characterized in that, The high-frequency signal detection circuit includes a coupler, a power divider, a shaping circuit, and an amplitude detection circuit. The coupler is connected in series in the radio frequency link where the high-frequency signal is located. The coupling interface of the coupler is connected to the input port of the power divider. The output port 1 of the power divider is connected to the shaping circuit. The output port 2 of the power divider is connected to the amplitude detection circuit. The output port of the shaping circuit is connected to the control processor. The output port of the amplitude detection circuit is connected to the control processor.

3. The high-frequency signal detection module according to claim 1, characterized in that, The interface circuit includes a frame synchronization signal interface circuit, a bus interface circuit, and a debug interface circuit; The frame synchronization signal interface circuit is connected to the frame synchronization input signal link, and the output terminal of the frame synchronization signal interface circuit is connected to the control processor I / O. The bus interface circuit is connected to the system application bus input link, and the output of the bus interface circuit is connected to the control processor. The debugging interface circuit is connected to the control processor.

4. The high-frequency signal detection module according to claim 1, characterized in that, The amplitude detection of the high-frequency signal includes: The FPGA receives the detection voltage output from the amplitude detection circuit, performs analog-to-digital conversion, and fits the correlation between the amplitude-related digital quantity and the true amplitude. When the amplitude-related digital quantity exceeds a set upper threshold, the control processor immediately sends a high-frequency switch control signal to cut off the input of the high-frequency signal. When the amplitude-related digital quantity is lower than a set lower threshold, the control processor only sends an alarm message to indicate that the input high-frequency signal amplitude is low, but does not cut off the input of the high-frequency signal.

5. The high-frequency signal detection module according to any one of claims 1-4, characterized in that, When the high-frequency signal appears, first determine whether the high-frequency signal is present, and wait for a set period of time before performing amplitude and frequency detection on the high-frequency signal.

6. A linear high-frequency transmitter, characterized in that, Includes the high-frequency signal detection module according to any one of claims 1-5.

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