A USB-PD based physical layer codec transceiving system

Abstract

The application relates to a USB-PD-based physical layer codec transceiving system, which comprises a sending part, a receiving part and a PHY layer control register module, the sending part comprises a receiving check module, a sequence generation module, a CC driving module, an idle detection module and a sending control unit, the receiving part comprises a CC determination and filtering module, a BMC decoding and 64-bit preamble detection module, a sequence detection module and a receiving control unit. In the system, a multi-byte information stream parallel check code generation method with adjustable check speed is used to perform CRC check code calculation on protocol layer data, so that the sending stability of the system is improved; the output signal of the CC determination and filtering module is detected by the idle detection module to determine whether the current bus is idle, so that the message collision risk is reduced; the PHY layer control register module adopts a register reading and writing control mode, so that the universality and portability of the system are improved.

Description

Technical Field

[0001] This invention belongs to the field of digital integrated circuit technology, specifically relating to a physical layer encoding and decoding transceiver system based on USB-PD. Background Technology

[0002] With the development of electronic technology, various portable devices have emerged in an endless stream, and the power demand of these portable devices is also increasing. Therefore, in 2019, the USB-IF organization released the USB Type-C Power Delivery Protocol 3.1 (hereinafter referred to as the PD protocol), a higher-power transmission protocol based on the Type-C interface, which can support a maximum power transmission of 240W (48V / 5A), meeting the power supply needs of most mobile devices. The data transmission verification method in this protocol standard adopts a 32-bit cyclic redundancy check (CRC) method. The total data packet after verification is encoded using 4b5b (4-bit data to 5-bit symbols, 4b5b), and finally encoded using Biphase Mark Coding (BMC) before transmission. The above encoding and decoding methods greatly improve the stability and accuracy of fast charging systems. As a communication standard, it has been widely used.

[0003] Currently, mainstream verification and encoding / decoding systems employ single-bit sequential CRC verification, 4b5b encoding / decoding using single-channel combinational logic, and BMC decoding using a high-frequency sampling clock and fixed discrimination value sampling. Furthermore, different encoding / decoding operating systems are used depending on the specific upper-layer design requirements.

[0004] The latest version 3.1 of the USB PD protocol supports sending extended messages of up to 260 bytes at a time. However, if a single-bit pipelined CRC checksum and a single-channel 4b5b encoding / decoding checksum are used, data preparation before transmission will consume more time. Therefore, for fast charging systems requiring rapid response, power negotiation stability will be reduced. Secondly, existing USB physical layer encoding / decoding transceiver systems are highly specialized, generally exhibiting poor versatility and portability. Summary of the Invention

[0005] To address the aforementioned problems in the existing technology, this invention provides a physical layer encoding / decoding transceiver system based on USB-PD. The technical problem to be solved by this invention is achieved through the following technical solution:

[0006] This invention provides a physical layer codec transceiver system based on USB-PD, comprising: a transmitting section, a receiving section, and a PHY layer control register module. The transmitting section includes a receive verification module, a sequence generation module, a CC driver module, an idle detection module, and a transmit control unit. The receiving section includes a CC determination and filtering module, a BMC decoding and 64-bit preamble detection module, a sequence detection module, and a receive control unit.

[0007] The receiving verification module is used to perform CRC check code calculation on the protocol layer data using a multi-byte information stream parallel check code generation method with adjustable verification speed to obtain the check code, and to encode the protocol layer data and the check code using 4b5b to obtain encoded data.

[0008] The sequence generation module is used to implement three control modes according to the control signal, and to perform BMC encoding on the encoded data or special sequence code according to the requirements of the transmission mode to obtain the encoded signal;

[0009] The CC driver module is used to drive the encoded signal and load it into the CC channel;

[0010] The idle detection module is used to detect the output signal of the CC determination and filtering module to determine whether the current bus is idle and obtain the determination result.

[0011] The transmit control unit is used to switch between different states according to the value of the PHY layer control register module register to send control signals to the receive verification module, the sequence generation module, the CC driver module and the idle detection module;

[0012] The CC determination and filtering module is used to convert the analog signal on the CC channel into a digital signal using a hysteresis comparison method, and then perform digital filtering on the digital signal to obtain a filtered signal.

[0013] The BMC decoding and 64-bit preamble detection module is used to perform BMC decoding on the filtered signal during the non-transmission phase and to perform preamble sequence detection on the decoded data to obtain valid detection data.

[0014] The sequence detection module is used to receive the valid detection data, and when the valid detection data is a regular message, it sequentially performs 4b5b decoding and CRC verification of the message content until the EOP end code is received, and receives the comparison result of the CRC verification result being the same as the fixed check code to obtain a valid ordinary message;

[0015] The receiving control unit is used to detect the valid detection data to identify the message header, message content, and EOP end code. When the valid detection data is a special message, it sends a modify register value signal to the PHY layer control register module. When the CRC check result is the same as the check code, it sends a modify regular message reception valid bit register value signal to the PHY layer control register module. When the CRC check result is different from the fixed check code, it sends a reset signal to the BMC decoding and 64-bit preamble detection module and the sequence detection module.

[0016] The PHY layer control register module is used to send control signals to the transmitting control unit and the receiving control unit through register read and write operations according to the control signals from the upper layer, and to send feedback signals to the upper layer.

[0017] In one embodiment of the present invention, the receiving verification module includes a top-level control logic module, several bytes of memory, several dual-channel 4b5b encoding modules, a checksum generation module, and a memory module, wherein,

[0018] The top-level control logic module is used to determine the data receiving speed, the length of data received in each cycle, and the length of the last group of data based on the length of the protocol layer data, and to select different calculation modes based on different data lengths;

[0019] The several-byte memory is used to store received data in a one-to-one correspondence according to different data lengths;

[0020] The check code generation module is used to perform CRC check code calculation on the received data according to the calculation mode and adopts a multi-byte information stream parallel check code generation method with adjustable check speed to obtain the check code.

[0021] The plurality of dual-channel 4b5b encoding modules are used to encode the received data in 4b5b format according to different data lengths, and to encode the check code at the same time to obtain the encoded data.

[0022] The memory module is used to store the encoded data.

[0023] In one embodiment of the present invention, the checksum generation module includes a plurality of 8-bit XOR units, a plurality of registers, a plurality of CRC32 checksum generation units, an addition control unit, a 32-bit selector, a 32-bit remainder register, and a 32-bit checksum result register. The number of the plurality of 8-bit XOR units, the number of the plurality of registers, and the number of the plurality of CRC32 checksum generation units are all the same as the length of the data received in each cycle.

[0024] The plurality of 8-bit XOR units are used to perform an XOR operation on the output data of the addition control unit and the corresponding byte of the received data one by one to obtain a plurality of XOR operation results; the output data of the addition control unit includes the initial value or part or all of the remainder value generated in the previous verification cycle;

[0025] The registers are used to store the XOR operation results of the several sets in a one-to-one correspondence;

[0026] The plurality of CRC32 check generation units are used to generate remainder results by combining logic on the plurality of XOR operation results in a one-to-one correspondence, thereby obtaining a plurality of remainder results;

[0027] The addition control unit is used to perform modulo-2 addition on the several remainder results and the value in the 32-bit remainder register according to the corresponding number of bytes to obtain the remainder value;

[0028] The 32-bit selector is used to input an initial value during the first verification and to input the remainder value after each verification.

[0029] The 32-bit remainder register is used to store the initial value during the first verification and output the initial value to the addition control unit, and to store the remainder value after each verification and output the remainder value to the addition control unit.

[0030] The 32-bit check result register is used to store the remainder value to form the check code.

[0031] In one embodiment of the present invention, when the check byte is greater than 4, the recursive formula of the check code is:

[0032]

[0033] When the check byte is less than 4, the recursive formula for the check code is:

[0034] R(x) y-1 = (M(x) y-1 x 32 +[R(x) y-2 ] H x 8n modG 33 (x)+[R(x)y -2 ] L x 8n

[0035] Where, M(x) y-1 Let R(x) represent the 8n input values ​​for the remainder of the y-th iteration. y-2 This represents the 32-bit remainder result of the (y-1)th iteration of the remainder calculation, m. y-1, where i represents the i-th binary value of the 8n input values ​​after the remainder is taken in the y-th iteration, and r y-2，3 The third digit of x represents the 32-bit remainder of the lower y-1th cycle. i+32 G represents the order of magnitude of the corresponding number of bits in the current loop calculation. 33 (x) represents the divisor polynomial in cyclic division, [R(x)] y-2 ] H This represents the result of the previous round of modulo operation, [R(x)]. y-2 ] L x represents the result of the previous modulo operation that is not included in the current modulo operation. 8n This indicates that the order of magnitude of the remainder result from the previous round is carried over to the next round of calculation, depending on the change in the number of bytes checked each time.

[0036] In one embodiment of the present invention, the control methods include: initiating the transmission of a regular message sequence by calling the encoded data, directly initiating the transmission of a special sequence code, and stopping the transmission of the current message.

[0037] In one embodiment of the present invention, the different states include: default state, receiving state, idle determination state, waiting for idle state, sending waiting state, sending state, waiting to stop state, hard set state, and closed channel state.

[0038] In one embodiment of the present invention, the switching of the different states includes:

[0039] When the upper layer writes a send request signal to the PHY layer control register module, the internal state machine of the send control unit switches from the default state to the receive state.

[0040] Upon receiving the storage completion signal from the receiving verification module, the internal state machine of the transmitting control unit transitions from the receiving state to the idle determination state.

[0041] When the idle detection module determines that the waiting timeout has occurred, the internal state machine of the transmission control unit transitions from the idle determination state to the waiting idle state; when the idle detection module determines that the device is idle, the internal state machine of the transmission control unit transitions from the idle determination state to the transmission waiting state.

[0042] In the waiting idle state, the stored messages to be sent in the receiving verification module are cleared, and after the bus becomes idle, the internal state machine of the sending control unit jumps from the waiting idle state to the default state.

[0043] When the bus is busy in the transmit waiting state, the internal state machine of the transmit control unit jumps from the transmit waiting state to the wait idle state. When the bus is idle, the internal state machine of the transmit control unit enters the transmit state from the transmit waiting state.

[0044] In the sending state, after the sequence generation module finishes sending the message, the internal state machine of the sending control unit jumps from the sending state to the default state;

[0045] In the sending state, when the PHY layer control register module sends a hard reset message instruction, the internal state machine of the sending control unit jumps from the sending state to the Hard Set state; when the PHY layer control register module sends a hard reset message instruction and the sequence generation module is sending a message, the internal state machine of the sending control unit jumps from the sending state to the waiting stop state; when the sequence generation module finishes sending messages, the internal state machine of the sending control unit jumps from the waiting stop state to the Hard Set state; when the hard reset sending flag is set, the internal state machine of the sending control unit jumps from the Hard Set state to the idle determination state to send a hard reset message.

[0046] After the hard reset message is sent, the internal state machine of the transmission control unit jumps from the transmission state to the closed channel state.

[0047] In one embodiment of the present invention, the sequence detection module includes a first shift register, a dual-channel 4b5b decoding module, a second shift register, a verification module, and a storage module, wherein,

[0048] The first shift register is used to store the valid detection data;

[0049] The dual-channel 4b5b decoding module is used to perform 4b5b decoding of the message content when the message header is a regular message, to obtain a decoded message;

[0050] The second shift register is used to store the decoded message;

[0051] The verification module is used to perform CRC verification on the decoded message and obtain the CRC verification result.

[0052] The storage module is used to store the valid ordinary message when the CRC check result is the same as the fixed check code.

[0053] In one embodiment of the present invention, the verification module is used to perform CRC verification on the decoded message using a single-byte information stream CRC verification method to obtain the CRC verification result.

[0054] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0055] In this invention, a physical layer encoding / decoding transceiver system based on USB-PD employs a parallel checksum generation method for multi-byte information streams with adjustable checksum speed in the receiving verification module to calculate CRC checksums for protocol layer data. This corrects the time required for data verification and encoding from data of different lengths, further improving the system's transmission stability. For transmission collisions in a CC single-channel half-duplex system, an idle detection module detects the output signal of the CC determination and filtering module to determine whether the current bus is idle. This complete and efficient collision avoidance mechanism greatly reduces the risk of message collisions. The PHY layer control register module uses a register read / write control mode, which can be used in dedicated integrated circuits or independently controlled by CPU software, further enhancing the system's versatility and portability. Attached Figure Description

[0056] Figure 1 This is a schematic diagram of the 3-bit CRC checksum generation process provided in an embodiment of the present invention;

[0057] Figure 2 This is a schematic diagram of BMC encoding provided in an embodiment of the present invention;

[0058] Figure 3 This is a schematic diagram of the PD protocol data packet format provided in an embodiment of the present invention;

[0059] Figure 4 This is a schematic diagram of a single-bit CRC check provided in an embodiment of the present invention;

[0060] Figure 5 A schematic diagram of a physical layer encoding / decoding transceiver system based on USB-PD is provided for an embodiment of the present invention;

[0061] Figure 6 A circuit diagram of a four-byte adjustable information stream parallel checksum generation circuit provided in an embodiment of the present invention;

[0062] Figure 7 This is a diagram of a single-byte information stream CRC check structure provided in an embodiment of the present invention;

[0063] Figure 8 This is a flowchart of the transmission control state in a transmission control unit provided in an embodiment of the present invention. Detailed Implementation

[0064] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0065] Example 1

[0066] To better understand the novel physical layer encoding and decoding transceiver system based on USB PD provided in this embodiment of the invention, the verification technology, encoding and decoding technology and data packet format included in the system will be briefly introduced first.

[0067] CRC checksum is an additional code used to check the correctness of data transmission. It has a very strong error correction and detection capability and can theoretically detect all burst errors that are less than or equal to the length of the check bits. In addition, because its internal logic operation uses XOR operation, its encoding and decoding circuits are relatively simple, so it is widely used in serial data communication.

[0068] CRC checksums employ a new operational rule – modulo-2 arithmetic. Modulo-2 arithmetic is similar to the four basic arithmetic operations, but without carry and borrow in basic addition and subtraction; therefore, it's simply the result of an XOR operation. Modulo-2 multiplication has the same calculation process as ordinary multiplication; the only difference is that partial product addition is performed modulo-2 addition, and similarly, subtracting remainders from division is performed modulo-2 subtraction. The use of XOR plus shift operations in CRC checksums simplifies implementation in digital logic and reduces resource consumption. Please refer to [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of the 3-bit CRC checksum generation process provided in an embodiment of the present invention.

[0069] 4b5b encoding is a line coding method that maps every 4 data bits to 5 symbol bits, transmitting data to the target device through these symbol bits. During transmission, these symbols maintain the AC balance of the line, minimizing the waveform's spectrum and reducing the DC component variation to less than 10% of the nominal center point. In the PD protocol, the remaining combinations of these 5 symbols can form corresponding special symbols to provide emergency negotiation between systems, further enhancing the protocol's reliability. The following diagram shows the relationship between the 5 symbol bits and the corresponding data and special symbols.

[0070] Table 1

[0071]

[0072] BMC encoding is a phase modulation encoding technique that mixes data with clock signals. Its characteristics include a level transition at the beginning of each data input, a level transition in the middle of a logic 1 bit cycle, and no level transition within a logic 0 bit cycle. Figure 2 As shown, Figure 2 This is a schematic diagram of BMC encoding provided in an embodiment of the present invention. This encoding method can complete the correct transmission of data information using only one data line, and the DC component is kept at the rated center point.

[0073] Please see Figure 3 , Figure 3 This is a schematic diagram of the PD protocol data packet format provided in an embodiment of the present invention. Figure 3 The message header and message content are the content that the protocol itself needs to send and receive. They consist of a 64-bit alternating zero-and-one preamble, a SOP* sequence code with four sets of special encoded symbols, a 4b5b encoded message header, a 4b5b encoded message content, a 4b5b encoded CRC checksum, and a special encoded EOP end-of-line code. Before encoding, the message header, message content, and checksum are all in bytes, and the total message length is within 264 bytes.

[0074] Traditional CRC checks employ a single-bit serial verification method in this system. One example is... Figure 4 As shown, Figure 4 This is a schematic diagram of a single-bit CRC check provided in an embodiment of the present invention. Each byte needs to be fed bit by bit into a shift register. The time consumed before sending data varies depending on the data length during bit-by-bit calculation. Since the maximum data length of the PD3.1 protocol has reached 264 bytes, reducing the transmission time is crucial to improving the stability of the fast charging system.

[0075] Please see Figure 5 , Figure 5 This is a schematic diagram of a physical layer encoding / decoding transceiver system based on USB-PD, provided as an embodiment of the present invention.

[0076] The USB-PD-based physical layer codec transceiver system includes a transmitting section, a receiving section, and a PHY layer control register module 510. The transmitting section includes a receiving verification module 501, a sequence generation module 502, a CC driver module 503, an idle detection module 504, and a transmitting control unit (TX controller) 505. The receiving section includes a CC determination and filtering module 506, a BMC decoding and 64-bit preamble detection module 507, a sequence detection module 508, and a receiving control unit (RX controller) 509.

[0077] Specifically, the receiving verification module 501 is used to perform CRC check code calculation on the protocol layer data using a multi-byte information stream parallel check code generation method with adjustable verification speed to obtain the check code, and to perform 4b5b encoding on the protocol layer data and the check code to obtain the encoded data.

[0078] In one specific embodiment, the receiving verification module 501 is responsible for receiving data sent from the protocol layer and performing CRC checksum calculation, 4b5b encoding, and storage of the verification data. It mainly includes a top-level control logic module, a several-byte memory (n*8 bits), several (n) dual-channel 4b5b encoding modules, a checksum generation module, and a memory module. The top-level control logic module determines the data receiving speed, the length of data received in each cycle, and the length of the last data group based on the length of the protocol layer data, and selects different calculation modes according to different data lengths. The several-byte memory stores the received data one-to-one according to different data lengths. The checksum generation module calculates the CRC checksum of the received data using a multi-byte information stream parallel checksum generation method with adjustable verification speed, according to the calculation mode. The several dual-channel 4b5b encoding modules include n dual-channel 4b5b encoding logic units, used to perform 4b5b encoding on the received data one-to-one according to different data lengths, and simultaneously encode the checksum to obtain encoded data. The memory module is used to store encoded data. It uses a first-in-first-out (FIFO) memory with adjustable input bit length, where Size = message maximum longth.

[0079] Specifically, the receive verification module 501 is mainly controlled by the internal top-level control logic module to adjust the receiving speed and storage order. The top-level control logic module can be started and stopped by the transmit control unit 505. After starting, it performs range judgment on the value of the transmit data byte length register in the PHY layer control register module 510, selects the corresponding number of receive verification bytes based on the result, and adjusts its operation mode based on the remainder of the number of bytes received each time according to the length of the data to be received, to ensure an error-free verification result. It can be understood that, firstly, the top-level control logic module inside the receive verification module 501 determines the receiving speed, the length of data received in each cycle, and the length of the last group of data based on the length of the received data written by the protocol layer in the PHY layer control register 510, selects the corresponding number of receive memories, and simultaneously sends each received data to the corresponding number of 4b5b encoding modules and check code generation modules. Then, the 4b5b encoding generated by combinational logic is stored in the memory module. This continues until the last group of data encoding is stored in the memory module and verified, and then the finally generated 32-bit check code is stored in the memory module. Since the data length is not an integer multiple of the number of bytes received per cycle, the length of the last group of data must be less than or equal to the number of bytes received per cycle. Therefore, the internal control logic module needs to change the corresponding receiving length and algorithm mode to generate the correct checksum in order to receive the last group of data.

[0080] Specifically, the checksum generation module employs a multi-byte information stream parallel checksum generation algorithm with adjustable checksum speed, and the calculation mode for the corresponding number of bytes can be selected by the top-level control logic module. The receiving verification module 501 informs the sending control unit 505 when the message and the finally generated 32-bit checksum are encoded and stored.

[0081] In this embodiment, the receiving verification module 501 can achieve intelligent and stable data processing speed because the top-level control logic module selects the calculation mode corresponding to the number of bytes, so that the data receiving end can effectively identify the data within the corresponding time.

[0082] The sequence generation module 502 is used to implement three control modes according to the control signal, and to perform BMC encoding on the encoded data or special sequence code according to the requirements of the transmission mode to obtain the encoded signal.

[0083] Specifically, the sequence generation module 502 performs three control functions based on the control signals from the transmission control unit 505: it initiates the transmission of a regular message sequence by calling the coded data already prepared in the first-in-first-out (FIFO) memory of the receive verification module 501; it directly initiates the transmission of a special sequence code; and it stops transmitting the current message, stopping transmission after the current byte of data has been transmitted and feeding back a stop signal to the transmission control unit 505 for the next step. Further, the sequence generation module sequentially sends the corresponding data to the BMC encoding module for encoding according to the requirements of the transmission format, and the encoded signal is then sent to the CC driver module 503.

[0084] CC driver module 503 is used to drive the encoded signal and load it into the CC channel.

[0085] Specifically, the CC drive module 503 is responsible for starting and stopping its own drive function according to the enable signal of the transmission control unit 505. During the startup period, it is responsible for driving the signal encoded in the sequence generation module 502 and loading it into the CC channel.

[0086] The idle detection module 504 is used to detect the output signal of the CC determination and filtering module 506 to determine whether the current bus is idle and obtain the determination result.

[0087] Specifically, the idle detection module 504 is responsible for determining whether the bus is currently idle by detecting the output signal of the CC determination and filtering module 506 when the sending control unit 505 requests to send data.

[0088] The transmit control unit 505 is used to switch between different states according to the value of the register in the PHY layer control register module 510 to send control signals to the receive verification module 501, sequence generation module 502, CC driver module 503 and idle detection module 504, thereby controlling the receive verification module 501, sequence generation module 502, CC driver module 503 and idle detection module 504 to complete the transmit task set in the PHY layer control register 510.

[0089] CC determination and filtering module 506 is used to convert the analog signal on the CC channel into a digital signal by using hysteresis comparison, and then perform digital filtering on the digital signal to obtain a filtered signal, which is then sent to BMC decoding and 64-bit preamble detection module 507.

[0090] The BMC decoding and 64-bit preamble detection module 507 is used to perform BMC decoding on the filtered signal from the CC determination and filtering module 506 during the non-transmission phase, and to perform preamble sequence detection on the decoded data to obtain valid detection data. The BMC decoding and 64-bit preamble detection module 507 is also used to notify the receiving control unit 509 after successfully detecting 32 groups of zero-one sequences, and to send the subsequently received data to the sequence detection module 508. Furthermore, the reset of the BMC decoding and 64-bit preamble detection module 507 is controlled by the transmitting control unit 509.

[0091] The sequence detection module 508 is used to receive valid detection data, and when the valid detection data is a regular message, it sequentially performs 4b5b decoding and CRC verification of the message content until the EOP end code is received, and receives the comparison result of the CRC verification result and the fixed check code to obtain a valid ordinary message.

[0092] Specifically, the sequence detection module 508 is responsible for detecting the data following the preamble sequence in the data packet to identify the message header, message content, and EOP end code composed of special symbol codes. When a special message consisting solely of special symbol codes is received, no further detection of the message content and EOP end code is performed. Upon receiving a regular message composed of special symbol codes, 4b5b decoding and CRC verification of the message content are performed until the EOP end code is received. The final checksum is then compared, and if accurate, the regular message reception is considered valid.

[0093] In one specific embodiment, the sequence detection module 508 includes a first shift register (10 bits), a dual-channel 4b5b decoding module, a second shift register (8 bits), a verification module, and a storage module. The first shift register stores valid detection data. The dual-channel 4b5b decoding module performs 4b5b decoding on the message content when the message header is a regular message, obtaining a decoded message. The second shift register stores the decoded message. The verification module performs CRC verification on the decoded message, obtaining the CRC verification result. The storage module stores valid ordinary messages when the CRC verification result matches the fixed checksum; it uses a first-in-first-out (FIFO) memory where Size = message maximum length.

[0094] In the sequence detection module 508, since the data receiving speed is much slower than the verification speed, the verification module uses the single-byte information stream CRC verification method to perform CRC verification on the decoded message.

[0095] The specific process of the sequence detection module 508 is as follows: After receiving a valid preamble sequence from the BMC decoding and 64-bit preamble detection module 507, each valid 1-bit data received is sent to a 10-bit first shift register. When 5 bits of data are shifted in for the first time, the EOP end code is checked. Whenever 10 bits of data are shifted in, the data is used for special symbol code detection or sent to the dual-channel 4b5b decoding module for decoding. After the preamble is valid, the first two groups of 10-bit data are identified as special message types by the receive control unit 509, and the corresponding register value in the PHY layer control register 510 is directly modified to notify the protocol layer. After the first two groups of 10-bit data following the validity of the preamble are identified as regular message type by the receiving control unit 509, data reception and verification begin. After each 10-bit data is received, it is decoded by dual-channel 4b5b and the decoded information is sent to the verification module and the first-in-first-out (FIFO) memory. When the EOP end code is received in the 10-bit shift register, the receiving control unit 509 checks whether the final check code is the same as the fixed check code. If they are the same, the message is considered accurate and the corresponding regular message reception valid bit register in the PHY layer control register 510 is modified. If they are different, the receiving control unit 509 resets the receiving unit, that is, resets the BMC decoding and 64-bit preamble detection module 507 and the sequence detection module 508.

[0096] The receiving control unit 509 detects valid data to identify the message header, message content, and EOP end code. When the valid data is a special message, it sends a modify register value signal to the PHY layer control register module 510. When the CRC check result is the same as the fixed checksum, it sends a modify register value signal to the PHY layer control register module 510 to modify the valid bits register value of the regular message reception. When the CRC check result is different from the fixed checksum, it sends a reset signal to the BMC decoding and 64-bit preamble detection module 507 and the sequence detection module 508. In essence, the receiving control unit 509 controls the corresponding received message sequence based on the signals from the BMC decoding and 64-bit preamble detection module 507 and the sequence detection module 508. When the received data is valid, it modifies the register value in the PHY layer control register module 510 to inform the top layer.

[0097] The PHY layer control register module 510 is used to send control signals to the transmitting control unit 505 by reading and writing registers according to the control signals from the upper layer. The PHY layer control register module 510 is also used to modify the internal register values ​​according to the received commands and send feedback signals to the upper layer.

[0098] In this embodiment, the PHY layer control register module 510 is responsible for the control of the physical layer by the upper layer and the feedback of the physical layer to the upper layer. By reading and writing the corresponding registers, the entire physical layer has strong versatility and portability.

[0099] In this embodiment, based on the USB-PD physical layer encoding and decoding transceiver system, taking into account the large variation range of the latest protocol length, the receiving verification module employs a multi-byte information stream parallel checksum generation method with adjustable verification speed to calculate CRC checksums for protocol layer data. The sending data speed can be adjusted in real time according to different data lengths and remaining checksum data, correcting the time required for data verification and encoding from data of different lengths, further improving the system's transmission stability. For transmission collisions in the CC single-channel half-duplex system, an idle detection module detects the output signal of the CC determination and filtering module to determine whether the current bus is idle, employing a complete and efficient collision avoidance mechanism, greatly reducing the risk of message collisions. The PHY layer control register module adopts a register read / write control mode, which can be used in dedicated integrated circuits or independently controlled by CPU software, further improving the system's versatility and portability.

[0100] Example 2

[0101] Based on Example 1, please refer to Figure 6 , Figure 6 The circuit structure diagram of the four-byte adjustable information stream parallel check code generation circuit provided in the embodiment of the present invention.

[0102] Specifically, the checksum generation module employs a multi-byte adjustable information stream parallel CRC checksum generation unit, which includes several 8-bit XOR units, several registers, several CRC32 checksum generation units, an adder control unit, a 32-bit selector, a 32-bit remainder register, and a 32-bit checksum result register. The number of 8-bit XOR units, registers, and CRC32 checksum generation units are all the same as the length of the received data in each cycle. The 8-bit XOR units are used to perform a one-to-one XOR operation between the output data of the adder control unit and the corresponding byte of the received data, obtaining several sets of XOR results. The output data of the adder control unit includes the initial value and part or all of the remainder values ​​generated in the previous checksum cycle. The registers are used to store several sets of XOR results in a one-to-one correspondence. The CRC32 checksum generation units are used to generate remainder results from the several sets of XOR results using combinational logic, obtaining several remainder results. The adder control unit performs a modulo-2 addition operation on the remainder results and the value in the 32-bit remainder register according to the corresponding number of bytes, obtaining the remainder value. A 32-bit selector is used to input the initial value during the first check and the remainder value after each check. A 32-bit remainder register is used to store the initial value during the first check and output it to the addition control unit, and to store the remainder value after each check and output it to the addition control unit. A 32-bit check result register is used to store the remainder value to form a checksum.

[0103] It should be noted that, Figure 6 This is a specific implementation of a multi-byte adjustable information stream parallel CRC checksum generation unit, with a maximum parallel computing speed of 4 bytes per clock cycle. Due to the scalability of the PD protocol, in the future, as the data length of the PD protocol increases, a larger number of bytes can be selected for parallel computing. Figure 6 This is just one representative implementation case.

[0104] This embodiment first describes the implementation method of the adjustable information flow parallel checksum generation algorithm. The data information is arranged from high to low bits in a left-to-right order, and the corresponding number of bits is sequentially extracted from the high bits to the low bits according to a single n checksum bytes for encoding, represented by a polynomial M(x). The binary numbers encoded initially are m_8n-1, m_8n-2, ..., m_0, expressed as a polynomial:

[0105]

[0106] Where M(x)0 represents the binary code polynomial data fed into the loop for the first time, m 0i x represents the value of the i-th bit of the binary polynomial data first fed into the loop calculation. iThis indicates the order of magnitude of the i-th bit in the current loop calculation, and n represents the number of check bytes sent in each loop.

[0107] The polynomial for subsequent piecewise calculations is expressed as:

[0108]

[0109] Where, M(x) y-1 This represents the binary code polynomial data corresponding to the y-th iteration of the calculation, m y-1,i This represents the j-th bit of the binary code polynomial data calculated in the y-th iteration.

[0110] Then, a shift operation is performed, and the expression corresponding to shifting the input data left by 32 bits is:

[0111]

[0112] Where, x 32 This indicates that the input data is shifted 32 bits to the higher-order bits, x i+32 This indicates the order of magnitude of the (i+32)th bit after the shift.

[0113] According to the CRC-32 specification, the generator polynomial 04C11B7H forms a 33-bit polynomial G. 33 (x):

[0114] G 33 (x)=x 32 +x 26 +…+x 2 +x 1 +1(04C11B7H) (4)

[0115] Where, x 26 This indicates that the 26th bit is 1, x 2 This indicates that the second digit is 1, x 1 This indicates that the first bit is 1, 1 indicates that the 0th bit is 1, and 04C11B7H indicates the hexadecimal code of the corresponding 33 bits of data.

[0116] The shifted pair G 33 (x) is divided modulo 2 to obtain the first remainder polynomial:

[0117]

[0118] The 32-bit result of each remainder is grouped into groups of eight bits each, from highest to lowest order, defined as follows:

[0119] R(x) y =R(x) y,3 +R(x) y,2+R(x) y,1 +R(x) y,0 (6)

[0120] Where, R(x) y Let R(x) represent the result of the (y+1)th modulo operation. y,3 Let R(x) represent the 31st to 24th bits of the result of the (y+1)th 32-bit modulo operation. y,2 Let R(x) represent the 23rd to 16th bits of the 32-bit modulo result of the (y+1)th time. y,1 Let R(x) represent the 15th to 8th bits of the 32-bit modulo result of the (y+1)th time. y,0 This represents the 7th to 0th bits of the 32-bit remainder result of the (y+1)th time.

[0121] Next, before performing the operation on the second group of multi-byte bytes and the remainder result, align them bit-by-bit according to the modulo-2 addition operation method to obtain:

[0122] M(x)1x 32 +R(x)0x 8n (7)

[0123] Where M(x)1 represents the polynomial of the second set of input data, R(x)0 represents the result of the first 32-bit modulo operation, and x 8n This indicates a shift operation that takes 8n bits of data and feeds into the loop for each iteration, based on the remainder result of the previous operation.

[0124] When the check byte n is greater than 4, the remainder result needs to be shifted up to the higher bits and padded with zeros to align with the higher bits of the second group. The recursive formula for the check code is obtained through calculation:

[0125]

[0126] When the check byte n is less than 4, the low-order remainders that cannot be aligned can be excluded from subsequent remainders and only included in the final result merging, thus obtaining the recursive formula for the check code:

[0127] R(x) y-1 = (M(x) y-1 x 32 +[R(x) y-2 ] H x 8n modG 33 (x)+[R(x) y-2 ] L x 8n (9)

[0128] Where, M(x) y-1 Let R(x) represent the 8n input values ​​for the remainder of the y-th iteration. y-2This represents the 32-bit remainder result of the (y-1)th iteration of the remainder calculation, m. y-1，i Let r represent the i-th binary value of the 8n input values ​​after the remainder is taken in the y-th iteration of the loop. y-2，3 The third digit of x represents the 32-bit remainder of the lower y-1th cycle. i+32 G represents the order of magnitude of the corresponding number of bits in the current loop calculation. 33 (x) represents the divisor polynomial in cyclic division, [R(x)] y-2 ] H This represents the result of the previous round of modulo operation, [R(x)]. y-2 ] L x represents the result of the previous modulo operation that is not included in the current modulo operation. 8n This indicates that the order of magnitude of the remainder result from the previous round is carried over to the next round of calculation, depending on the change in the number of bytes checked each time.

[0129] Therefore, based on the above reasoning, an example is designed, such as... Figure 6 As shown.

[0130] Please see Figure 7 , Figure 7 This is a CRC check structure diagram for a single-byte information stream provided in an embodiment of the present invention. This embodiment further uses... Figure 7 The CRC check method shown in the single-byte information stream mode is expanded to... Figure 6 The multi-byte adjustable scheme will be explained.

[0131] As can be seen from the USB PD verification method, it uses a 32-bit CRC checksum with an initial value of 32'HFFFFFFFF and an inverted verification result. This 32-bit initial value is the initial value of the remainder register at the start of the operation. Based on the aforementioned mathematical algorithm, this 32-bit initial value is equivalent to pre-setting a remainder of the same order of magnitude as the highest 32 bits of the data being verified. Therefore, the 32-bit remainder register needs to be reset to 32'HFFFFFFFF before each data verification.

[0132] Based on the aforementioned mathematical algorithm derivation, when the number of checks is 8 bits each time, when starting the information flow, it is necessary to perform a modulo-2 addition operation (i.e., an XOR operation) on the high eight bits of the reserved remainder data 8'hFF and the input high eight bits of data, and then send it into the byte register. After that, the value of the byte register is used as the value of bits 33 to 40 of the dividend in the modulo-2 division operation, and 32'H 04C1 1DB7h is used as the divisor in the modulo-2 division operation, thereby performing CRC check. The lower 32 bits of the dividend are zero by default, so the 32-bit remainder can be generated based on the eight bits of data through combinational logic. The highest bit of the newly obtained 32-bit remainder is consistent with the next eight bits of data to be sent and the highest bit of the remaining 24-bit remainder. Therefore, the high 24 bits of the 32-bit remainder obtained by the single-byte CRC check generation logic module are XORed with the low 24 bits in the remainder register, and then combined with the low 8 bits of the 32-bit remainder obtained by the single-byte CRC check generation logic module to form a new remainder, which is then sent to the 32-bit remainder register. In addition, the high eight bits are sent to the 8-bit XOR unit to perform XOR calculation with the newly received data. This process is repeated until the last byte of data arrives and is sent to the single-byte register. After receiving the end signal, the final data is sent to the check result register, and the check result is output.

[0133] Similarly, when the number of data to be checked each time is 16 bits, the initial data needs to be XORed with all-one data, then stored in two byte registers, and its 16 bits are used as the 33rd to 48th bits of the dividend in the modulo-2 division operation with a divisor of 32'H 04C1 1DB7h. Therefore, the corresponding combinational logic unit can be used to obtain the 32-bit remainder result, and then XORed with the lower 16 bits of the remainder register shifted left by 16 bits to obtain a new remainder. The higher 16 bits of the new remainder are then XORed with the input data, and this process is repeated to obtain the final 32-bit CRC check code.

[0134] Therefore, changing the amount of input data each time only requires modifying the combinational logic after the byte register, as well as changing the operation and allocation of the obtained remainder and the stored remainder, to achieve different numbers of checks in a single cycle. Based on the above characteristics, a design was developed... Figure 6The circuit structure shown is a four-byte adjustable information stream parallel checksum generation circuit. Unlike the aforementioned 16-bit information stream operation, the data XORed with each data stream is divided into bytes, the 32-bit remainder of the corresponding byte is calculated, and then modulo-2 addition is performed to obtain the final remainder. This significantly reduces the waste of modules requiring different combinational logic for different data streams. The specific implementation process is as follows: Upon initial startup, the addition control unit generates a number D[31:0] consisting entirely of 1s, performs an XOR operation with the received data, and stores it in a register with the same number of input bytes. The corresponding number of logic units will generate corresponding remainder results. The addition control unit performs modulo-2 addition on each remainder result and the value of the corresponding remainder register based on the corresponding number of bytes to obtain a new remainder value, which is then sent to the input terminal and remainder register corresponding to the next data quantity. This process is repeated until the data verification is completed.

[0135] This embodiment can perform one effective calculation within one clock cycle and adjust the computing speed in real time. It can ignore whether the data length is divisible by the corresponding number of bytes, and has extremely high versatility and portability.

[0136] Example 3

[0137] Based on Example 1, please refer to Figure 8 , Figure 8 This is a flowchart of the transmission control state in a transmission control unit provided in an embodiment of the present invention.

[0138] The different states implemented by the transmit control unit 505 include: default state IDLE, receive state, idle determination state, waiting for idle state, transmit waiting state, transmit state, waiting for stop state, hard set state, and closed channel state.

[0139] The specific process for the transmission control unit 505 to switch between different states is as follows:

[0140] When the upper layer writes a send request signal to the PHY layer control register module 510, the internal state machine of the send control unit 505 transitions from the default state IDLE to the receive state. In the receive state, the send control unit 505 controls the receive verification module 501 to start receiving and processing data. When the receive verification module 501 finishes receiving and verifying the data and storing it, it sends a storage completion signal to the send control unit 505.

[0141] When the storage completion signal is received from the receiving verification module 501, the internal state machine of the sending control unit 505 switches from the receiving state to the idle determination state, and at this time the idle detection module 504 is started.

[0142] The idle detection module 504 primarily determines whether the output signal of the CC determination and filtering module 506 has flipped more than three times within a specified time. Once idle is detected, the idle flag is immediately cleared and the idle determination is repeated. If the output signal of the CC determination and filtering module 506 flips more than three times within the specified time, the idle detection module 504 determines that the wait has timed out. In this case, the internal state machine of the transmission control unit 505 transitions from the idle determination state to the idle waiting state. If the output signal of the CC determination and filtering module 506 does not flip more than three times within the specified time, the idle detection module 504 determines that the device is idle. In this case, the internal state machine of the transmission control unit 505 transitions from the idle determination state to the transmission waiting state.

[0143] Furthermore, when the sending control unit 505 enters the waiting idle state, it clears the stored messages to be sent in the memory module of the receiving verification module 501, i.e., the first-in-first-out memory FIFO, and the internal state machine of the sending control unit 505 jumps from the waiting idle state to the default state IDLE. At the same time, it modifies the PHY layer control register 510 to indicate that the status message is discarded but the bus is currently idle.

[0144] When the transmit control unit 505 enters the transmit waiting state, it starts a waiting timer to meet the minimum time interval requirement between messages in the protocol. During the waiting period, if the idle flag bit of the idle detection module 504 is low, it is considered that the bus is busy, and the internal state machine of the transmit control unit 505 jumps from the transmit waiting state to the wait idle state. However, if the bus is idle during the waiting period, the internal state machine of the transmit control unit 505 enters the transmit state from the transmit waiting state.

[0145] In the sending state, the sending control unit 505 controls the sequence generation module 502 to start the linear sequence machine to send the corresponding message sequence. After the sequence generation module 502 finishes sending the message, the internal state machine of the sending control unit 505 transitions from the sending state to the default state IDLE.

[0146] Because the PD protocol requires a hard reset mechanism that can be sent at any time and can interrupt the current transmission, a Hard Set state is added. When the PHY layer control register module 510 sends a hard reset message instruction, the internal state machine of the transmission control unit 505 immediately jumps from the transmission state to the Hard Set state. When the PHY layer control register module 510 sends a hard reset message instruction and the sequence generation module 502 is transmitting a message, the internal state machine of the transmission control unit 505 jumps from the transmission state to the waiting-to-stop state, stops transmitting, waits for the current byte message to finish transmitting, and sets the hard reset transmission flag. When the sequence generation module 502 finishes transmitting the message, the internal state machine of the transmission control unit 505 jumps from the waiting-to-stop state to the Hard Set state. After the hard reset transmission flag is set, the internal state machine of the transmission control unit 505 jumps from the Hard Set state to the idle judgment state, which is the same as that for normal message transmission, to transmit the hard reset message.

[0147] After the hard reset message is sent, the internal state machine of the transmit control unit 505 jumps from the transmit state to the closed channel state, no longer drives the bus to send and receive messages, closes the transmit end, and waits for the PHY layer control register 510 to indicate a reset before entering the default state again.

[0148] In this embodiment, the two phases of idle determination state and waiting for idle state ensure that even if a new message is received before this, there is enough time for the upper layer to process it. In order to prevent transmission collisions in the CC single-channel half-duplex system, idle detection and secondary waiting are integrated into the transmission control system, and a complete and efficient collision avoidance mechanism is proposed, which greatly reduces the risk of message collisions.

[0149] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A USB-PD based physical layer codec transceiver system, characterized in that, Comprise: The sending part, the receiving part and the PHY layer control register module (510), the sending part includes the receiving check module (501), the sequence generation module (502), the CC drive module (503), the idle detection module (504) and the sending control unit (505), the receiving part includes the CC determination and filter module (506), the BMC decoding and 64bit preamble detection module (507), the sequence detection module (508) and the receiving control unit (509), wherein, The receiving check module (501) is used for CRC check code calculation of protocol layer data by using the parallel check code generation method of the check speed adjustable multi-byte information stream, and 4b5b encoding of the protocol layer data and the check code to obtain the encoding data; The sequence generation module (502) is used for realizing three kinds of control forms according to the control signal, and carrying out BMC encoding on the encoding data or special sequence code to obtain the encoding signal according to the requirement of the sending form; The CC drive module (503) is used for driving the encoding signal and loading it to the CC channel; The idle detection module (504) is used for detecting the output signal of the CC determination and filter module (506) to determine whether the current bus is idle, to obtain the determination result; The sending control unit (505) is used for switching between different states according to the value of the PHY layer control register module (510) register to send the control signal to the receiving check module (501), the sequence generation module (502), the CC drive module (503) and the idle detection module (504); The CC determination and filter module (506) is used for converting the analog signal on the CC channel into a digital signal by using the hysteresis comparison method, and obtaining the filter signal after digital filtering the digital signal; The BMC decoding and 64bit preamble detection module (507) is used for BMC decoding of the filter signal in the non-sending stage, and preamble sequence detection of the decoded data to obtain the effective detection data; The sequence detection module (508) is used for receiving the effective detection data, and when the effective detection data is a regular message, sequentially carrying out 4b5b decoding of the message content and CRC check until receiving the EOP end code, and receiving the CRC check result and the comparison result that the fixed check code is the same, to obtain the effective ordinary message; The receiving control unit (509) is configured to detect the valid detection data to identify a message header, message content and an EOP end code, send a register value modification signal to the PHY layer control register module (510) when the valid detection data is a special message, send a regular message receiving valid bit register value modification signal to the PHY layer control register module (510) when the CRC check result is the same as the fixed check code, and send a reset signal to the BMC decoding and 64-bit preamble detection module (507) and the sequence detection module (508) when the CRC check result is not the same as the fixed check code. The PHY layer control register module (510) is configured to send control signals to the sending control unit (505) and the receiving control unit (509) and send a feedback signal to the upper layer by means of register reading and writing according to a control signal of the upper layer.

2. The USB-PD based physical layer codec transceiving system according to claim 1, wherein, The receiving check module (501) comprises a top layer control logic module, a plurality of byte memories, a plurality of double-channel 4b5b encoding modules, a check code generation module and a memory module, wherein The top layer control logic module is configured to judge a data receiving speed, a length of received data in each period and a length of the last group of data according to the length of the protocol layer data, and select different calculation modes according to different data lengths. The plurality of byte memories are configured to store the received data one by one according to different data lengths. The check code generation module is configured to calculate a check code by means of a check speed adjustable multi-byte information stream parallel check code generation method according to the calculation mode. The plurality of double-channel 4b5b encoding modules are configured to encode the received data and the check code one by one according to different data lengths to obtain the encoded data. The memory module is configured to store the encoded data.

3. The USB-PD based physical layer codec transceiving system of claim 2, wherein, The check code generation module comprises a plurality of 8-bit XOR units, a plurality of registers, a plurality of CRC32 check generation units, an addition control unit, a 32-bit selector, a 32-bit remainder register and a 32-bit check result register, the number of the plurality of 8-bit XOR units, the number of the plurality of registers and the number of the plurality of CRC32 check generation units are the same as the length of the received data in each period, wherein The plurality of 8-bit XOR units are configured to perform XOR operation on the output data of the addition control unit and the corresponding bytes of the received data one by one to obtain a plurality of groups of XOR operation results; the output data of the addition control unit comprises an initial value or part or all of the remainder values generated in the last check cycle; The plurality of registers are configured to store the plurality of groups of XOR operation results one by one; The plurality of CRC32 check generation units are configured to generate remainder results by means of combination logic one by one to obtain a plurality of remainder results. The addition control unit is configured to perform modulo-2 addition operation on the several remainder results and the value in the 32-bit remainder register according to corresponding byte number, to obtain the remainder value; The 32-bit selector is configured to input an initial value at the first time of checking, and input the remainder value after each time of checking; The 32-bit remainder register is configured to store the initial value at the first time of checking and output the initial value to the addition control unit, and store the remainder value after each time of checking and output the remainder value to the addition control unit; The 32-bit checking result register is configured to store the remainder value to form the check code.

4. The USB-PD based physical layer codec transceiving system according to claim 3, wherein, When the checking byte is greater than 4, the recursive formula of the check code is: When the checking byte is less than 4, the recursive formula of the check code is: R(x) y-1 = (M(x) y-1 x 32 + [R(x) y-2 ] H x 8n ) mod G 33 (x) + [R(x) y-2 ] L x 8n where M(x) y-1 represents 8n input values of the yth cycle modulo, R(x) y-2 represents the 32-bit remainder result of the y-1th cycle modulo, m y-1，i represents the i-th binary value of the 8n input values of the yth cycle modulo, r y-2，3 represents the third binary value of the 32-bit remainder of the low y-1th cycle modulo, x i+32 represents the order of magnitude of the corresponding binary in the current cycle calculation, G 33 (x) represents the divisor polynomial of the cycle division, [R(x) y-2 ] H represents the last round of remainder results participating in the current remainder operation, [R(x) y-2 ] L represents the last round of remainder results not participating in the current remainder operation, x 8n represents the order of magnitude of the last round of remainder results entering the next round of operation according to the change of the number of each check byte.

5. The USB-PD based physical layer codec transceiving system of claim 1, wherein, The control mode includes: starting to send a normal message sequence by calling the encoded data, directly starting to send a special sequence code, and stopping to send a current message.

6. The USB-PD based physical layer codec transceiving system of claim 1, wherein, The different states include: a default state, a receiving state, an idle judgment state, a waiting idle state, a sending waiting state, a sending state, a waiting stop state, a Hard Set state and a close channel state.

7. The USB-PD based physical layer codec transceiving system of claim 6, wherein, The switching of the different states includes: When the upper layer writes a sending request signal to the PHY layer control register module (510), the internal state machine of the sending control unit (505) jumps from the default state to the receiving state; When a storage completion signal of the receiving checking module (501) is received, the internal state machine of the sending control unit (505) jumps from the receiving state to the idle judgment state; When the judgment result of the idle detection module (504) is waiting timeout, the internal state machine of the sending control unit (505) jumps from the idle judgment state to the waiting idle state; when the judgment result of the idle detection module (504) is idle, the internal state machine of the sending control unit (505) jumps from the idle judgment state to the sending waiting state; In the waiting idle state, the storage message to be sent in the receiving checking module (501) is emptied, and after the bus is idle, the internal state machine of the sending control unit (505) jumps from the waiting idle state to the default state; In the sending waiting state, when the bus is busy, the internal state machine of the sending control unit (505) jumps from the sending waiting state to the waiting idle state; when the bus is idle, the internal state machine of the sending control unit (505) jumps from the sending waiting state to the sending state; In the sending state, when the message sending of the sequence generation module (502) is completed, the internal state machine of the sending control unit (505) jumps from the sending state to the default state; In the sending state, the internal state machine of the sending control unit (505) jumps from the sending state to the Hard Set state when the PHY layer control register module (510) sends a hard reset message instruction; the internal state machine of the sending control unit (505) jumps from the sending state to the waiting stop state when the PHY layer control register module (510) sends a hard reset message instruction and the sequence generation module (502) is sending a message; the internal state machine of the sending control unit (505) jumps from the waiting stop state to the Hard Set state after the sequence generation module (502) finishes sending a message; the internal state machine of the sending control unit (505) jumps from the Hard Set state to the idle determination state to send a hard reset message after a hard reset sending flag is set; The internal state machine of the sending control unit (505) jumps from the sending state to the closed channel state after a hard reset message is sent.

8. The USB-PD based physical layer codec transceiving system of claim 1, wherein, The sequence detection module (508) comprises a first shift register, a dual-channel 4b5b decoding module, a second shift register, a check module, and a storage module, wherein, The first shift register is used to store the valid detection data; The dual-channel 4b5b decoding module is used to perform 4b5b decoding on the message content when the message header is a regular message, to obtain a decoded message; The second shift register is used to store the decoded message; The check module is used to perform CRC check on the decoded message, to obtain the CRC check result; The storage module is used to store the valid regular message when the CRC check result is the same as the fixed check code.

9. The USB-PD based physical layer codec transceiving system of claim 8, wherein, The check module is used to perform CRC check on the decoded message by using a single-byte information stream CRC check method, to obtain the CRC check result.

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