Semiconductor device

Abstract

A semiconductor device is provided with a base region of a second conductivity type disposed between a drift region and an upper surface of a semiconductor substrate, a first lifetime region disposed closer to a lower surface side of the drift region than the base region, and a second lifetime region configured to be sandwiched between the first lifetime regions in a first direction parallel to the upper surface of the semiconductor substrate and have a longer carrier lifetime than the first lifetime regions, a width of the second lifetime region in the first direction being 0.2 times or more of a thickness of the first lifetime region in a second direction perpendicular to the upper surface of the semiconductor substrate.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Previously, it was known that in semiconductor devices equipped with freewheeling diodes (FWDs), techniques were used to adjust carrier lifetime by forming lattice defects in the semiconductor substrate (see, for example, Patent Documents 1 and 2).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-31155

[0004] Patent Document 2: Japanese Patent Application Publication No. 2020-120121 Summary of the Invention

[0005] Technical issues

[0006] In semiconductor devices, it is desirable to suppress snapback.

[0007] Technical solution

[0008] To address the aforementioned issues, a semiconductor device is provided in a first aspect of the present invention. The semiconductor device may include a semiconductor substrate having an upper surface and a lower surface, and having a drift region of a first conductivity type. Any of the aforementioned semiconductor devices may include a diode portion disposed on the semiconductor substrate. In any of the aforementioned semiconductor devices, the diode portion may have a base region of a second conductivity type disposed between the drift region and the upper surface of the semiconductor substrate. In any of the aforementioned semiconductor devices, the diode portion may have a first lifetime region disposed on the drift region side closer to the lower surface of the semiconductor substrate than the base region. In any of the aforementioned semiconductor devices, the diode portion may have a second lifetime region disposed between the first lifetime regions in a first direction parallel to the upper surface of the semiconductor substrate, and having a carrier lifetime longer than the carrier lifetime of the first lifetime regions. In any of the aforementioned semiconductor devices, the width of the second lifetime region in the first direction may be greater than the width W (μm) shown by equation (1).

[0009] W = 0.21 × T1 + 3.3··· (1)

[0010] Wherein, T1 is the thickness of the first lifetime region in the second direction perpendicular to the upper surface.

[0011] In any of the above semiconductor devices, the width of the second lifetime region in the first direction can be 7 μm or more.

[0012] In any of the above semiconductor devices, the width of the second lifetime region in the first direction can be less than 12 μm.

[0013] In any of the aforementioned semiconductor devices, the diode portion may have one or more second lifetime regions. The sum of the widths of the one or more second lifetime regions in the first direction may be less than 0.1 times the width of the diode portion in the first direction.

[0014] Any of the above-mentioned semiconductor devices may include a transistor portion disposed on the semiconductor substrate and arranged in the first direction in a manner aligned with the diode portion.

[0015] In any of the above-described semiconductor devices, the diode portion and the transistor portion may have a plurality of trench portions arranged at intervals in the first direction.

[0016] Any of the above-described semiconductor devices may include a transistor portion disposed on the semiconductor substrate and arranged in a third direction parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction, and arranged with the diode portion.

[0017] In any of the above-described semiconductor devices, the diode portion and the transistor portion may have a plurality of trench portions arranged at intervals in the third direction.

[0018] In any of the above semiconductor devices, at least a portion of the trench portion of the diode portion may be disposed above the first lifetime region, and the distance between the second lifetime region and the transistor portion in the first direction is greater than the distance between the lower end of the trench portion and the first lifetime region in the second direction.

[0019] In any of the semiconductor devices described above, the diode portion may have two or more second lifetime regions arranged at intervals in the first direction.

[0020] In any of the above-described semiconductor devices, the second lifetime region may also be sandwiched between the first lifetime regions in a third direction that is parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction.

[0021] In any of the above semiconductor devices, the width of the second lifetime region in the third direction can be more than 0.2 times the thickness of the first lifetime region in the second direction.

[0022] In any of the above-described semiconductor devices, the width of the second lifetime region in the first direction can be more than 3% of the diffusion length of electrons in the semiconductor substrate.

[0023] In any of the above semiconductor devices, the thickness of the first lifetime region in the second direction can be less than 100 μm.

[0024] In any of the above-described semiconductor devices, the width of the second lifetime region in the first direction can be more than 0.2 times the thickness of the first lifetime region in the second direction perpendicular to the upper surface of the semiconductor substrate.

[0025] In any of the aforementioned semiconductor devices, the first lifetime region may contain hydrogen. In any of the aforementioned semiconductor devices, the first lifetime region may contain helium.

[0026] In any of the aforementioned semiconductor devices, the first lifetime region may be disposed in both the diode portion and the transistor portion. In the transistor portion of any of the aforementioned semiconductor devices, the ratio of the area of ​​the second lifetime region 200 surrounded by the first lifetime region to the area of ​​the first lifetime region 204 may be less than the ratio of the area of ​​the second lifetime region 200 surrounded by the first lifetime region to the area of ​​the first lifetime region in the diode portion.

[0027] In any of the above-described semiconductor devices, the first lifetime region may be provided in both the diode portion and the transistor portion. In any of the above-described semiconductor devices, a second lifetime region may be provided inside the first lifetime region of the diode portion. In any of the above-described semiconductor devices, a second lifetime region may not be provided inside the first lifetime region of the transistor portion.

[0028] In any of the above-described semiconductor devices, a plurality of trench portions may be provided on the upper surface of the semiconductor substrate in a direction greater than 0 degrees and less than 90 degrees relative to the first direction.

[0029] It should be noted that the above description of the invention does not list all the essential features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention. Attached Figure Description

[0030] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention.

[0031] Figure 2 yes Figure 1 An enlarged view of region D in the image.

[0032] Figure 3 It is shown Figure 2 A diagram of an example of the ee section.

[0033] Figure 4 This is a diagram illustrating an example of the VI characteristics of the diode section 80 in the comparative example when it is forward-biased.

[0034] Figure 5This is a diagram showing an example of the configuration of the first lifetime region 204 and the second lifetime region 200 in the diode section 80.

[0035] Figure 6 This is an enlarged cross-sectional view of the vicinity of the second lifetime region 200.

[0036] Figure 7 It is shown Figure 6 The figure shows an example of the distribution of carrier lifetime, vacancy density, and helium chemical concentration at the ff line.

[0037] Figure 8 It is shown Figure 6 The figure shows an example of the distribution of carrier lifetime, vacancy density, and helium chemical concentration at the gg line.

[0038] Figure 9 It is shown Figure 6 The distribution of carrier lifetime, vacancy density, and helium chemical concentration at the hh line is shown in the figure.

[0039] Figure 10 These are other examples of enlarged cross-sectional views near the second lifetime region 200.

[0040] Figure 11A Show Figure 10 The diagram shows the distribution of net doping concentration (A), hydrogen chemical concentration (B), lattice defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along the hh line in the semiconductor device 100 of the illustrated embodiment.

[0041] Figure 11B These are other examples of enlarged cross-sectional views near the second lifetime region 200.

[0042] Figure 11C Show Figure 11B The diagram shows the distribution of net doping concentration (A), hydrogen chemical concentration (B), lattice defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along the hh line in the semiconductor device 100 of the illustrated embodiment.

[0043] Figure 11D These are other examples of enlarged cross-sectional views near the second lifetime region 200.

[0044] Figure 12 This is a diagram illustrating an example of the VI characteristics of the diode section 80 when it is in forward conduction.

[0045] Figure 13 This is a graph showing the trade-off between the forward voltage Vf and the reverse recovery loss Err in the diode section 80.

[0046] Figure 14This is a diagram showing the relationship between the width W1 of the second lifetime region 200 and the foldback amount (SB amount).

[0047] Figure 15 This is a diagram showing whether a foldback occurs when the thickness T1 of the first lifetime region 204 and the width W1 of the second lifetime region 200 are changed.

[0048] Figure 16A This is a diagram showing another configuration example of the first lifetime region 204 and the second lifetime region 200 in the diode section 80.

[0049] Figure 16B This is a diagram showing another configuration example of the first lifetime region 204 and the second lifetime region 200 in the diode section 80.

[0050] Figure 16C This is a diagram showing another configuration example of the first lifetime region 204 and the second lifetime region 200 in the diode section 80.

[0051] Figure 17 This is a diagram showing whether a foldback occurs when the number of second lifetime regions 200 included in a diode section 80 and the width W1 of each second lifetime region 200 are varied.

[0052] Figure 18 This is a diagram showing an example of the configuration of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0053] Figure 19 This is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0054] Figure 20 This is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0055] Figure 21 This is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0056] Figure 22A This is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0057] Figure 22B This is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0058] Figure 23A This is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0059] Figure 23BThis is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0060] Figure 24 This is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0061] Figure 25 This is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0062] Figure 26 This is a diagram showing other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane.

[0063] Symbol Explanation

[0064] 10···Semiconductor substrate, 11···Well region, 12···Emitter region, 14···Base region, 15···Contact region, 16···Accumulation region, 18···Drift region, 19···Lower surface-side lifetime region, 20···Buffer zone, 21···Upper surface, 22···Collector region, 23···Lower surface, 24···Collector electrode, 26···High concentration region, 29···Linear portion, 30···Dummy trench portion, 31···Front end portion, 32···Dummy insulating film, 34···Dummy conductive portion, 38···Interlayer insulating film, 39···Linear portion, 40···Gate trench portion, 41···Front end portion, 42···Gate insulating film, 44···Gate conductive portion 52···Emitter electrode, 54···Contact hole, 60, 61···Mesa section, 70···Transistor section, 80···Diode section, 81···Extension region, 82···Cathode region, 85···Line, 90···Edge termination structure section, 100···Semiconductor device, 130···Outer periphery gate wiring, 131···Active side gate wiring, 160···Active section, 162···End edge, 164···Gate pad, 200···Second lifetime region, 202···Lattice defect, 204···First lifetime region, 220, 222, 224···Region, 230···Line, 240···Region, 250···Characteristic, 251···Characteristic Detailed Implementation

[0065] The present invention will now be described through embodiments thereof, but these embodiments do not limit the invention as defined in the claims. Furthermore, not all combinations of the features described in the embodiments are necessarily required for the technical solution of the invention.

[0066] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper," and the other side as "lower." One of the two main surfaces of the substrate, layer, or other component is referred to as the upper surface, and the other as the lower surface. The directions "upper" and "lower" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0067] In this specification, orthogonal coordinate axes of X, Y, and Z are sometimes used to illustrate technical matters. Orthogonal coordinate axes only determine the relative positions of constituent elements and do not limit specific directions. For example, the Z-axis is not limited to representing the height direction relative to the ground. It should be noted that the +Z-axis direction and the -Z-axis direction are opposite to each other. When the Z-axis direction is not specified as positive or negative, it refers to a direction parallel to both the +Z-axis and -Z-axis.

[0068] In this specification, the orthogonal axes parallel to the upper and lower surfaces of the semiconductor substrate are designated as the X-axis and Y-axis. The axis perpendicular to the upper and lower surfaces of the semiconductor substrate is designated as the Z-axis. In this specification, the direction of the Z-axis is sometimes referred to as the depth direction. Additionally, in this specification, the direction parallel to the upper and lower surfaces of the semiconductor substrate, including the X-axis and Y-axis, is sometimes referred to as the horizontal direction.

[0069] Sometimes the region extending from the center of the semiconductor substrate along its depth direction to the top surface of the semiconductor substrate is called the top surface side. Similarly, sometimes the region extending from the center of the semiconductor substrate along its depth direction to the bottom surface of the semiconductor substrate is called the bottom surface side.

[0070] In the context of this specification, the terms "same" or "equal" may also include cases with errors caused by manufacturing deviations, etc. Such errors may be, for example, within 10%.

[0071] In this specification, the conductivity type of the doped region is described as P-type or N-type. In this specification, "impurity" sometimes specifically refers to either an N-type donor or a P-type acceptor, and sometimes is referred to as a dopant. In this specification, doping refers to introducing a donor or acceptor into a semiconductor substrate, thereby creating a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type.

[0072] In this specification, doping concentration refers to the concentration of donors or acceptors at thermal equilibrium. In this specification, net doping concentration refers to the actual concentration obtained by adding the donor concentration as the concentration of positive ions and the acceptor concentration as the concentration of negative ions, taking into account charge polarity. As an example, if the donor concentration is set to N... D Set the acceptor concentration to N A Then the actual net doping concentration at any position becomes N. D -NA In this specification, the net doping concentration is sometimes described as the doping concentration only.

[0073] Donors have the function of supplying electrons to semiconductors. Acceptors have the function of accepting electrons from semiconductors. Donors and acceptors are not limited to impurities themselves. For example, VOH defects, which are formed by the combination of vacancies (V), oxygen (O), and hydrogen (H) in semiconductors, function as electron-supplying donors. In this specification, VOH defects are sometimes referred to as hydrogen donors.

[0074] In this specification, the semiconductor substrate is uniformly distributed with N-type body donors. Body donors are donors formed by dopants that are contained substantially uniformly within the ingot during the manufacture of the raw material for the semiconductor substrate. In this example, the body donors are elements other than hydrogen. Dopants for body donors may be, for example, phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the body donor is phosphorus. The body donors are also contained within P-type regions. The semiconductor substrate can be a wafer cut from a semiconductor ingot or a chip obtained by monolithizing wafers. The semiconductor ingot can be manufactured by any of the Czochralski process (CZ process), magnetic field applied Czochralski process (MCZ process), or floating zone melting process (FZ process). In this example, the ingot is manufactured by the MCZ process. The substrate manufactured by the MCZ process contains an oxygen concentration of 1 × 10⁻⁶. 17 ~7×10 17 / cm 3 The oxygen concentration in the substrate manufactured by the FZ method is 1×10⁻⁶. 15 ~5×10 16 / cm 3 The side with a higher oxygen concentration tends to more readily generate hydrogen donors. The bulk donor concentration can be the chemical concentration of bulk donors distributed throughout the semiconductor substrate, or a value between 90% and 100% of that chemical concentration. Alternatively, an undoped substrate, free of dopants such as phosphorus, can be used as the semiconductor substrate. In this case, the bulk donor concentration (D0) of the undoped substrate is, for example, 1 × 10⁻⁶. 10 / cm 3 Above and 5×10 12 / cm 3 The bulk donor concentration (D0) of the undoped substrate is preferably 1 × 10⁻⁶. 11 / cm 3 The above. The bulk donor concentration (D0) of the undoped substrate is preferably 5 × 10⁻⁶. 12 / cm 3 The following should be noted: the concentrations used in this invention can be values ​​at room temperature. As an example, the values ​​at room temperature can be those at 300 K (Kelvin) (approximately 26.9°C).

[0075] In this specification, "P+" or "N+" refers to a doping concentration higher than that of "P" or "N" type. "P-" or "N-" refers to a doping concentration lower than that of "P" or "N" type. Similarly, "P++" or "N++" refers to a doping concentration higher than that of "P+" or "N+" type. Unless otherwise specified, the units used in this specification are in the SI unit system. Sometimes length is expressed in cm, but calculations can be performed after conversion to meters (m).

[0076] In this specification, chemical concentration refers to the atomic density of impurities measured independently of the electroactivated state. Chemical concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be determined by voltage-capacitance measurement (CV method). Alternatively, the carrier concentration measured by diffusion resistance measurement (SR method) can be used as the net doping concentration. The carrier concentration measured by CV or SR methods can be set to a value under thermal equilibrium conditions. Furthermore, in the N-type region, since the donor concentration is sufficiently greater than the acceptor concentration, the carrier concentration in this region can be used as the donor concentration. Similarly, in the P-type region, the carrier concentration in this region can be used as the acceptor concentration. In this specification, the doping concentration in the N-type region is sometimes referred to as the donor concentration, and the doping concentration in the P-type region is sometimes referred to as the acceptor concentration.

[0077] When the concentration distribution of donor, acceptor, or net dopant has a peak, the peak value can be taken as the concentration of the donor, acceptor, or net dopant in that region. When the concentration of donor, acceptor, or net dopant is almost uniform, the average concentration of donor, acceptor, or net dopant in that region can be taken as the concentration of the donor, acceptor, or net dopant. In this specification, concentration per unit volume is expressed in atoms / cm³. 3 or / cm 3 This unit is used to describe the concentration of donors or acceptors, or the chemical concentration, within a semiconductor substrate. The specification of "atoms" can be omitted.

[0078] The carrier concentration measured by the SR method can be lower than the donor or acceptor concentration. During the measurement of diffusion resistance, the carrier mobility of the semiconductor substrate is sometimes lower than that of the crystalline state within the range of current flow. This decrease in carrier mobility is caused by the dispersion of carriers due to crystal structure disorder caused by lattice defects, etc.

[0079] The donor or acceptor concentration calculated from the carrier concentration measured by the CV or SR method can be lower than the chemical concentration of the element representing the donor or acceptor. As an example, in silicon semiconductors, the donor concentration of phosphorus or arsenic (which are donors) or the acceptor concentration of boron (which is an acceptor) is about 99% of their chemical concentration. On the other hand, the donor concentration of hydrogen (which is a donor) in silicon semiconductors is about 0.1% to 10% of the chemical concentration of hydrogen.

[0080] Figure 1 This is a top view illustrating an example of a semiconductor device 100 according to one embodiment of the present invention. Figure 1 The image shows the positions obtained by projecting each component onto the upper surface of the semiconductor substrate 10. Figure 1 The diagram shows only a portion of the components of the semiconductor device 100, with some components omitted.

[0081] Semiconductor device 100 includes a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. The semiconductor substrate 10 has end edges 162 when viewed from above. In this specification, "viewed from above" refers to the view from the upper surface side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two sets of end edges 162 that are opposite each other when viewed from above. Figure 1 In the diagram, the X and Y axes are parallel to one end edge 162. Additionally, the Z axis is perpendicular to the upper surface of the semiconductor substrate 10.

[0082] An active portion 160 is provided on the semiconductor substrate 10. The active portion 160 is a region in which a main current flows along the depth direction between the upper and lower surfaces of the semiconductor substrate 10 when the semiconductor device 100 is operating. An emitter electrode is provided above the active portion 160, but... Figure 1 The active portion 160 may refer to the region that overlaps with the emitter electrode when viewed from above. Alternatively, the region sandwiched between the active portions 160 when viewed from above may also be included within the active portions 160.

[0083] The active section 160 includes a transistor section 70 containing transistor elements such as an IGBT (Insulated Gate Bipolar Transistor). The active section 160 may also include a diode section 80 containing diode elements such as a freewheeling diode (FWD). Figure 1 In this example, transistor sections 70 and diode sections 80 are alternately arranged along a predetermined alignment direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. The semiconductor device 100 in this example is a reverse-conducting IGBT (RC-IGBT).

[0084] exist Figure 1 In this specification, the area where the transistor section 70 is arranged is marked with the symbol "I", and the area where the diode section 80 is arranged is marked with the symbol "F". In this specification, the direction perpendicular to the arrangement direction when viewed from above is sometimes referred to as the extension direction (in...). Figure 1 (The middle direction is the Y-axis direction). The transistor section 70 and the diode section 80 may each have a long side in the extending direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extending directions of the transistor section 70 and the diode section 80 may be the same as the long side direction of each trench section described later.

[0085] The diode portion 80 has an N+ type cathode region in the area contacting the lower surface of the semiconductor substrate 10. In this specification, the area where the cathode region is provided is referred to as the diode portion 80. That is, the diode portion 80 is the area that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in the area other than the cathode region. In this specification, sometimes an extension region 81 extending the diode portion 80 along the Y-axis direction to the gate wiring described later is also included in the diode portion 80. A collector region is provided on the lower surface of the extension region 81.

[0086] The transistor section 70 has a P+ type collector region in the region that contacts the lower surface of the semiconductor substrate 10. In addition, the transistor section 70 has an N-type emitter region, a P-type base region, and a gate structure having a gate conductive portion and a gate insulating film periodically arranged on the upper surface side of the semiconductor substrate 10.

[0087] Semiconductor device 100 may have one or more pads above semiconductor substrate 10. In this example, semiconductor device 100 has a gate pad 164. Semiconductor device 100 may also have anode pads, cathode pads, and current sensing pads, etc. Each pad is located near an edge 162. "Near an edge 162" refers to the area between edge 162 and the emitter electrode when viewed from above. When mounting semiconductor device 100, each pad can be connected to external circuitry via wiring such as wires.

[0088] A gate potential is applied to the gate pad 164. The gate pad 164 is electrically connected to the conductive portion of the gate trench portion of the active portion 160. The semiconductor device 100 includes gate wiring connecting the gate pad 164 to the gate trench portion. Figure 1 In the diagram, the gate wiring is marked with a slanted shaded line.

[0089] The gate wiring in this example includes a peripheral gate wiring 130 and an active-side gate wiring 131. The peripheral gate wiring 130 is disposed between the active portion 160 and the edge 162 of the semiconductor substrate 10 when viewed from above. In this example, the peripheral gate wiring 130 surrounds the active portion 160 when viewed from above. The area surrounded by the peripheral gate wiring 130 when viewed from above can be considered as the active portion 160. Furthermore, a well region is formed below the gate wiring. The well region is a P-type region with a higher concentration than the base region described later, and is formed from the upper surface of the semiconductor substrate 10 to a depth deeper than the base region. The area surrounded by the well region when viewed from above can be considered as the active portion 160.

[0090] The peripheral gate wiring 130 is connected to the gate pad 164. The peripheral gate wiring 130 is disposed above the semiconductor substrate 10. The peripheral gate wiring 130 may be a metal wiring including aluminum.

[0091] An active-side gate wiring 131 is provided in the active portion 160. By providing the active-side gate wiring 131 in the active portion 160, the deviation of the wiring length measured from the gate pad 164 in each region of the semiconductor substrate 10 can be reduced.

[0092] The peripheral gate wiring 130 and the active-side gate wiring 131 are connected to the gate trench portion of the active portion 160. The peripheral gate wiring 130 and the active-side gate wiring 131 are disposed above the semiconductor substrate 10. The peripheral gate wiring 130 and the active-side gate wiring 131 can be wiring formed from semiconductors such as polysilicon doped with impurities.

[0093] The active-side gate wiring 131 can be connected to the outer peripheral gate wiring 130. In this example, the active-side gate wiring 131 is configured to extend along the X-axis from the outer peripheral gate wiring 130 sandwiching the active portion 160 to the outer peripheral gate wiring 130 of the other side, in a manner that crosses approximately the center of the active portion 160 in the Y-axis direction. When the active portion 160 is divided using the active-side gate wiring 131, the transistor portion 70 and the diode portion 80 can be alternately arranged in the X-axis direction in each divided region.

[0094] The semiconductor device 100 may also include a temperature sensing unit (not shown) that is a PN junction diode formed of polysilicon or the like, and a current sensing unit (not shown) that simulates the operation of a transistor unit provided in the active unit 160.

[0095] In this example, the semiconductor device 100, when viewed from above, has an edge termination structure 90 between the active portion 160 and the edge 162. The edge termination structure 90 is disposed between the peripheral gate wiring 130 and the edge 162. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 may include at least one of a protective ring surrounding the active portion 160 in a ring shape, a field plate, and a surface electric field reducing element.

[0096] Figure 2 yes Figure 1 An enlarged view of region D is shown. Region D includes the transistor section 70, the diode section 80, and the active-side gate wiring 131. The semiconductor device 100 of this example includes a gate trench section 40, a dummy trench section 30, a well region 11, an emitter region 12, a base region 14, and a contact region 15 disposed inside the upper surface side of the semiconductor substrate 10. The gate trench section 40 and the dummy trench section 30 are examples of trench sections. Furthermore, the semiconductor device 100 of this example includes an emitter electrode 52 and an active-side gate wiring 131 disposed above the upper surface of the semiconductor substrate 10. The emitter electrode 52 and the active-side gate wiring 131 are disposed separately from each other.

[0097] An interlayer insulating film is disposed between the emitter electrode 52 and the active-side gate wiring 131 and the upper surface of the semiconductor substrate 10, but... Figure 2 (Omitted). In this example, the interlayer insulating film has contact holes 54 provided in a manner that penetrates the interlayer insulating film. Figure 2 In the middle, each contact hole 54 is marked with a slanted shaded line.

[0098] The emitter electrode 52 is disposed above the gate trench portion 40, the dummy trench portion 30, the well region 11, the emitter region 12, the base region 14, and the contact region 15. The emitter electrode 52 contacts the emitter region 12, the contact region 15, and the base region 14 on the upper surface of the semiconductor substrate 10 through a contact hole 54. Additionally, the emitter electrode 52 is connected to a dummy conductive portion within the dummy trench portion 30 through a contact hole disposed in the interlayer insulating film. The emitter electrode 52 can be connected to the dummy conductive portion of the dummy trench portion 30 at its front end in the Y-axis direction. The dummy conductive portion of the dummy trench portion 30 may not be connected to the emitter electrode 52 and the gate conductive portion, or it may be controlled to have a potential different from that of the emitter electrode 52 and the gate conductive portion.

[0099] The active-side gate wiring 131 is connected to the gate trench portion 40 through a contact hole provided in the interlayer insulating film. The active-side gate wiring 131 can be connected to the gate conductive portion of the gate trench portion 40 at the front end 41 in the Y-axis direction. The active-side gate wiring 131 is not connected to the dummy conductive portion within the dummy trench portion 30.

[0100] The emitter electrode 52 is formed of a material containing metal. Figure 2 The diagram shows the area where the emitter electrode 52 is disposed. For example, at least a portion of the emitter electrode 52 is formed of aluminum or an aluminum-silicon alloy such as AlSi, AlSiCu, or other metal alloys. The emitter electrode 52 may have a barrier metal formed of titanium and / or titanium compounds in a lower layer beneath the region formed of aluminum or the like. Furthermore, a plug formed by embedding tungsten or the like in contact with the barrier metal and aluminum or the like may be provided within the contact hole.

[0101] Well region 11 is provided in a manner that overlaps with the active-side gate wiring 131. Well region 11 is also provided with a predetermined width in a region that does not overlap with the active-side gate wiring 131. In this example, well region 11 is provided separately from the end of contact hole 54 in the Y-axis direction towards the active-side gate wiring 131. Well region 11 is a region of the second conductivity type with a higher doping concentration than base region 14. In this example, base region 14 is P-type and well region 11 is P+ type.

[0102] The transistor section 70 and the diode section 80 each have a plurality of trench sections arranged in the arrangement direction. In this example, the transistor section 70 alternately provides one or more gate trench sections 40 and one or more dummy trench sections 30 along the arrangement direction. In this example, the diode section 80 has a plurality of dummy trench sections 30 arranged along the arrangement direction. In this example, the diode section 80 does not have a gate trench section 40.

[0103] In this example, the gate trench portion 40 may have two straight portions 39 (the portion of the trench is straight along the extension direction) extending in an extension direction perpendicular to the arrangement direction, and a front end portion 41 connecting the two straight portions 39. Figure 2 The extension direction in the middle is the Y-axis direction.

[0104] At least a portion of the front end portion 41 is preferably curved when viewed from above. Connecting the ends of the two straight portions 39 in the Y-axis direction to each other via the front end portion 41 can mitigate the electric field concentration at the ends of the straight portions 39.

[0105] In the transistor section 70, a dummy trench section 30 is disposed between two adjacent straight sections 39 of the gate trench section 40. One dummy trench section 30 or multiple dummy trench sections 30 may be disposed between two adjacent straight sections 39. The dummy trench section 30 may have a straight shape extending in the extension direction, or it may have the same straight section 29 and front end portion 31 as the gate trench section 40. Figure 2 The semiconductor device 100 shown includes both a dummy trench portion 30 with a straight shape and no front end portion 31, and a dummy trench portion 30 with a front end portion 31.

[0106] The diffusion depth of the well region 11 can be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. The ends of the gate trench portion 40 and the dummy trench portion 30 in the Y-axis direction are located in the well region 11 when viewed from above. That is, at the ends of each trench portion in the Y-axis direction, the bottom of each trench portion in the depth direction is covered by the well region 11. This mitigates the electric field concentration at the bottom of each trench portion.

[0107] Mesa-shaped portions are provided between the trench portions in the alignment direction. A mesa-shaped portion refers to the area within the semiconductor substrate 10 sandwiched between the trench portions. As an example, the upper end of the mesa-shaped portion is the upper surface of the semiconductor substrate 10. The lower end of the mesa-shaped portion has the same depth as the lower end of the trench portion. In this example, the mesa-shaped portion is configured to extend along the trench in the extension direction (Y-axis direction) on the upper surface of the semiconductor substrate 10. In this example, a mesa-shaped portion 60 is provided in the transistor portion 70, and a mesa-shaped portion 61 is provided in the diode portion 80. In this specification, the term "mesa-shaped portion" refers to each mesa-shaped portion 60 and mesa-shaped portion 61.

[0108] A base region 14 is provided on each mesa. The region of the base region 14 exposed on the upper surface of the semiconductor substrate 10 within the mesa that is most closely positioned to the active-side gate wiring 131 is designated as base region 14-e. Figure 2 The diagram shows a base region 14-e disposed at one end of each isthmus in the extending direction, but a base region 14-e is also disposed at the other end of each isthmus. In each isthmus, in the region sandwiched between the base regions 14-e when viewed from above, at least one of a first conductivity type emitter region 12 and a second conductivity type contact region 15 can be disposed. In this example, the emitter region 12 is N+ type, and the contact region 15 is P+ type. The emitter region 12 and the contact region 15 can be disposed in the depth direction between the base region 14 and the upper surface of the semiconductor substrate 10.

[0109] The mesa portion 60 of the transistor portion 70 has an emitter region 12 exposed on the upper surface of the semiconductor substrate 10. The emitter region 12 is configured to contact the gate trench portion 40. The mesa portion 60 that contacts the gate trench portion 40 may have a contact region 15 exposed on the upper surface of the semiconductor substrate 10.

[0110] The contact area 15 and the emitter area 12 in the platform 60 are respectively configured to extend from one side of the groove in the X-axis direction to the other side of the groove. As an example, the contact area 15 and the emitter area 12 of the platform 60 are alternately arranged along the extension direction of the groove (Y-axis direction).

[0111] In other examples, the contact area 15 and the emitter area 12 of the platform 60 can be configured as stripes along the extension direction (Y-axis direction) of the groove. For example, the emitter area 12 is provided in the area that contacts the groove, and the contact area 15 is provided in the area sandwiched between the emitter areas 12.

[0112] An emitter region 12 is not provided on the mesa 61 of the diode section 80. A base region 14 and a contact region 15 may be provided on the upper surface of the mesa 61. A contact region 15 may be provided on the upper surface of the mesa 61 between the base regions 14-e, in a manner that contacts each of the base regions 14-e. A base region 14 may be provided on the upper surface of the mesa 61 between the contact regions 15. The base region 14 may be disposed throughout the entire area between the contact regions 15.

[0113] A contact hole 54 is provided above each mesa surface. The contact hole 54 is disposed in the region sandwiched between the base regions 14-e. In this example, the contact hole 54 is disposed above each region of the contact region 15, the base region 14, and the emitter region 12. The contact hole 54 is not disposed in the region corresponding to the base regions 14-e and the well region 11. The contact hole 54 may be disposed at the center in the arrangement direction (X-axis direction) of the mesa surface 60.

[0114] In the diode section 80, an N+ type cathode region 82 is provided in the region adjacent to the lower surface of the semiconductor substrate 10. A P+ type collector region 22 can be provided on the lower surface of the semiconductor substrate 10 in the region where the cathode region 82 is not provided. The cathode region 82 and the collector region 22 are located between the lower surface 23 of the semiconductor substrate 10 and the buffer zone 20. Figure 2 In the diagram, the boundary between the cathode region 82 and the collector region 22 is shown by a dashed line.

[0115] The cathode region 82 is configured to be located away from the well region 11 in the Y-axis direction. This ensures a sufficient distance between the cathode region 82 and the P-type region (well region 11) with a high doping concentration and formed to a deep depth, thereby improving breakdown voltage. In this example, the end of the cathode region 82 in the Y-axis direction is configured to be further away from the well region 11 than the end of the contact hole 54 in the Y-axis direction. In other examples, the end of the cathode region 82 in the Y-axis direction may be located between the well region 11 and the contact hole 54.

[0116] Figure 3 It is shown Figure 2 A diagram showing an example of the ee cross section. The ee cross section is the XZ plane passing through the emitter region 12 and the cathode region 82. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross section.

[0117] An interlayer insulating film 38 is disposed on the upper surface of the semiconductor substrate 10. The interlayer insulating film 38 is a film comprising at least one layer of an insulating film such as silicate glass containing impurities such as boron or phosphorus, a thermally oxidized film, or other insulating films. The interlayer insulating film 38 has a layer of... Figure 2 Contact hole 54 as described in the diagram.

[0118] The emitter electrode 52 is disposed above the interlayer insulating film 38. The emitter electrode 52 contacts the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The collector electrode 24 is disposed on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum. In this specification, the direction (Z-axis direction) connecting the emitter electrode 52 and the collector electrode 24 is referred to as the depth direction.

[0119] The semiconductor substrate 10 has an N-type or N-type drift region 18. The drift region 18 is disposed in each transistor section 70 and diode section 80.

[0120] In the mesa 60 of the transistor section 70, an N+ type emitter region 12 and a P- type base region 14 are sequentially disposed from the upper surface 21 side of the semiconductor substrate 10. A drift region 18 is disposed below the base region 14. An N+ type accumulation region may be disposed in the mesa 60. The accumulation region is disposed between the base region 14 and the drift region 18. The accumulation region is an N+ type region with a higher doping concentration than the drift region 18. By providing a high-concentration accumulation region between the drift region 18 and the base region 14, the carrier injection enhancement effect (IE effect) can be improved, thereby reducing the turn-on voltage. The accumulation region may be configured to cover the entire lower surface of the base region 14 in each mesa 60. The accumulation region may also be disposed in each mesa 61 of the diode section 80.

[0121] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is configured to contact the gate trench 40. The emitter region 12 may contact the trenches on both sides of the mesa 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0122] The base region 14 is located below the emitter region 12. In this example, the base region 14 is configured to contact the emitter region 12. The base region 14 may contact the groove portions on both sides of the mesa 60.

[0123] A P-type base region 14 is provided on the mesa 61 of the diode section 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. The base region 14 of the diode section 80 is sometimes referred to as the anode region 14.

[0124] In each transistor section 70 and diode section 80, an N+ type buffer 20 may be provided below the drift region 18. The doping concentration of the buffer 20 is higher than that of the drift region 18. The buffer 20 may have a concentration peak with a higher doping concentration than that of the drift region 18. The doping concentration of the concentration peak refers to the doping concentration at the apex of the concentration peak. Alternatively, the doping concentration of the drift region 18 may be the average doping concentration in a region where the doping concentration distribution is almost flat.

[0125] The buffer 20 may have two or more concentration peaks in the depth direction (Z-axis direction) of the semiconductor substrate 10. The concentration peaks of the buffer 20 may be set at the same depth position as, for example, the chemical concentration peaks of hydrogen (proton) or phosphorus. The buffer 20 may function as a field cutoff layer to prevent the depletion layer extending from the lower end of the base region 14 from reaching the P+ type collector region 22 and the N+ type cathode region 82.

[0126] In the transistor section 70, a P+ type collector region 22 is provided below the buffer 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain acceptors different from the base region 14. The acceptor of the collector region 22 is, for example, boron.

[0127] In the diode section 80, an N+ type cathode region 82 is provided below the buffer zone 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donors of the cathode region 82 are, for example, hydrogen or phosphorus. It should be noted that the elements that become donors and acceptors in each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed on the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 can contact the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum.

[0128] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the upper surface 21 side of the semiconductor substrate 10. Each trench portion is configured to extend from the upper surface 21 of the semiconductor substrate 10 through the base region 14 and reach below the base region 14. In regions where at least one of the emitter region 12, contact region 15, and accumulation region is provided, each trench portion also extends through these doped regions. The trench portion extending through the doped regions is not limited to being manufactured in the order of forming the trench portion after forming the doped region. The case where doped regions are formed between the trench portions after the trench portions are formed is also included in the case where the trench portion extends through the doped region.

[0129] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0130] The gate trench portion 40 has a gate trench, a gate insulating film 42, and a gate conductive portion 44 disposed on the upper surface 21 of the semiconductor substrate 10. The gate insulating film 42 is disposed to cover the inner wall of the gate trench. The gate insulating film 42 can be formed by oxidizing or nitriding the semiconductor of the inner wall of the gate trench. The gate conductive portion 44 is disposed inside the gate trench at a position further inward than the gate insulating film 42. That is, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0131] The gate conductive portion 44 can be configured to be longer than the base region 14 in the depth direction. The gate trench portion 40 at this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. If a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface in the base region 14 that contacts the gate trench portion 40.

[0132] The dummy trench portion 30 can have the same structure as the gate trench portion 40 in this cross-section. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 disposed on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 is electrically connected to the emitter electrode 52. The dummy insulating film 32 is disposed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is disposed inside the dummy trench and is located further inward than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 can be formed of the same material as the gate conductive portion 44. For example, the dummy conductive portion 34 can be formed of a conductive material such as polysilicon. The dummy conductive portion 34 can have the same length in the depth direction as the gate conductive portion 44.

[0133] In this example, the gate trench portion 40 and the dummy trench portion 30 are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. It should be noted that the bottom of the dummy trench portion 30 and the gate trench portion 40 can be a downwardly convex curved surface (curved in cross-section). In this specification, the depth of the lower end of the gate trench portion 40 is defined as Zt.

[0134] The semiconductor device 100 in this example includes a first lifetime region 204 for adjusting charge carrier lifetime. In this example, the first lifetime region 204 is a region where the lifetime of charge carriers is locally small. Charge carriers are electrons or holes. Sometimes, charge carriers are simply referred to as charge carriers. The first lifetime region 204 may be a region where the carrier lifetime exhibits a minimum value in the depth direction of the semiconductor substrate 10.

[0135] A first lifetime region 204 is disposed on the upper surface 21 side of the semiconductor substrate 10. The first lifetime region 204 is disposed in the diode section 80. The first lifetime region 204 may also be disposed in a portion of the transistor section 70. Figure 3 In the example, a first lifetime region 204 is provided in the region of the transistor section 70 that contacts the diode section 80.

[0136] By injecting charged particles such as helium into the semiconductor substrate 10, lattice defects 202 are formed near the injection site. Figure 3 The lattice defect 202 at the injection site of charged particles is schematically marked with an ×. In regions where a large number of lattice defects 202 remain, the carrier lifetime is shortened because the carriers are captured by the lattice defects 202. By adjusting the carrier lifetime, characteristics such as the turn-off time and reverse recovery loss of the diode section 80 can be adjusted. By injecting charged particles such as helium into the semiconductor substrate 10, lattice defects 210 such as vacancies are formed near the injection site. The lattice defect 202 generates recombination centers. The lattice defect 202 can be dominated by vacancies such as single-atom vacancies (V) and diatomic vacancies (VV), can be dislocations, can be inter-lattice atoms, or can be transition metals. For example, the atom adjacent to the vacancy has a dangling bond. In a broader sense, the lattice defect 202 can also contain donors and / or acceptors, but in this specification, the lattice defect 202 dominated by vacancies is sometimes referred to as a vacancy-type lattice defect, a vacancy-type defect, or simply a lattice defect. In this specification, lattice defects 202 are sometimes referred to as recombination centers that facilitate carrier recombination, and are simply called recombination centers or lifetime control bodies. Lifetime control bodies can be formed by implanting helium ions into the semiconductor substrate 10. In this case, the helium chemical concentration can be used as the density of lattice defects 202. In this example, the helium chemical concentration can be used as the density of lattice defects 202.

[0137] On the other hand, if a first lifetime region 204 is provided in the diode section 80, the number of holes injected from the anode region 14 and the number of electrons injected from the cathode region 82 decrease in the first lifetime region 204 when the diode section 80 is forward-biased. Therefore, sometimes the potential difference at the PN junction between the anode region 14 and the drift region 18 is difficult to become less than the built-in potential, and a positive voltage foldback occurs in the low-current operating region. In particular, if the first lifetime region 204 is provided throughout the entire diode section 80 in the X-axis direction, the hole density and electron density in the region on the upper surface 21 side of the diode section 80 become difficult to increase, and a foldback becomes more likely to occur.

[0138] Figure 4 This is a diagram illustrating an example of the VI characteristics of the diode section 80 in the comparative example during forward conduction. In this example, the diode section 80 has a first lifetime region 204 provided throughout the entire X-axis direction. Figure 4 The diagram shows the relationship between the forward current If of the diode section 80 and the anode-cathode voltage Vak. Additionally, in... Figure 4 The diagram illustrates VI characteristics, representing several examples of different carrier lifetimes in the first lifetime region 204. The carrier lifetime in the first lifetime region 204 can be adjusted by the dosage of charged particles such as helium injected into the semiconductor substrate 10. A higher dosage of charged particles such as helium results in a higher density of lattice defects formed on the semiconductor substrate 10, and a shorter carrier lifetime.

[0139] When the entire diode section 80 is provided with a first lifetime region 204, if the carrier lifetime of the first lifetime region 204 is reduced, sometimes... Figure 4 As shown, a fallback occurs in characteristic VI. For example... Figure 4 As shown, foldback is the phenomenon where current increase is suppressed in the low-current operating region during forward conduction until the voltage Vak reaches a predetermined value, and the current increases sharply at the point when the voltage Vak exceeds the predetermined value. In the low-current operating region, the majority carrier density (electron density in this example) required for the potential difference of the PN junction to exceed the internal potential needs to increase. To supply the electron density required to exceed the internal potential, a shorter carrier lifetime necessitates a higher anode-cathode voltage Vak. If the potential difference of the PN junction exceeds the internal potential, minority carrier injection begins, the forward current increases, and the resistance of diode section 80 decreases. As a result, the anode-cathode voltage Vak decreases, resulting in conductivity modulation, and foldback occurs in characteristic VI.

[0140] The VI waveform in the high-current operating region is approximated by a straight line 85. In this specification, the difference (V2-V1) between the voltage V1 when the current If = 0 in the straight line 85 and the peak voltage V2 in the foldback is sometimes referred to as the foldback amount (SB amount). In the semiconductor device 100, the foldback is suppressed by adjusting the configuration of the first lifetime region 204 in the diode section 80.

[0141] Figure 5 This is a diagram showing an example of the configuration of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. Figure 5 The XZ cross-section is shown through a portion of the diode section 80 and a portion of the transistor section 70. Figure 5 In this diagram, the interlayer insulating film 38, emitter electrode 52, and collector electrode 24 disposed above and below the semiconductor substrate 10 are omitted. Figure 5 Lattice defect 202 is omitted, and the shading for dummy conductive part 34 and gate conductive part 44 is also omitted.

[0142] In this example, the diode section 80 has a first lifetime region 204 and a second lifetime region 200 in the region on the upper surface 21 side of the semiconductor substrate 10. The first lifetime region 204 is disposed in the drift region 18, which is closer to the lower surface 23 side of the semiconductor substrate 10 than the base region 14. The first lifetime region 204 can be disposed at a position lower than the lower end of the dummy trench section 30. A plurality of first lifetime regions 204 can be provided in the diode section 80, which are separately arranged in the X-axis direction. The width of a first lifetime region 204 in the X-axis direction can be greater than the width of a mesa sandwiched between two trench sections.

[0143] The second lifetime region 200 is configured to be sandwiched between the first lifetime regions 204 in a first direction (the X-axis direction in this example) parallel to the upper surface 21 of the semiconductor substrate 10. The first lifetime region 204 and the second lifetime region 200 are located at the same position in the depth direction (Z-axis direction) of the semiconductor substrate 10.

[0144] The second lifetime region 200 is a region where the carrier lifetime is longer than that of the first lifetime region 204. In this example, the carrier lifetime of the second lifetime region 200 can be the same as that of the drift region 18. That is, the second lifetime region 200 can be the drift region 18 that remains after the first lifetime region 204 was not formed. In other examples, the carrier lifetime of the second lifetime region 200 can be shorter than that of the drift region 18.

[0145] The lattice defect density of the second lifetime region 200 is lower than that of the first lifetime region 204. The lattice defect density of the second lifetime region 200 can be the same as or higher than that of the drift region 18. The concentration of impurities such as helium in the second lifetime region 200 can be lower than that in the first lifetime region 204. The concentration of impurities such as helium in the second lifetime region 200 can be the same as or higher than that of the drift region 18. In this example, the impurities in the impurity concentration can be impurities that cause lattice defects that reduce carrier lifetime. For example, impurities can be atoms other than those of the semiconductor substrate 10, or inter-lattice atoms of the semiconductor substrate 10. Furthermore, impurities can be n-type or p-type dopants, impurities that do not contribute to conductivity (e.g., helium, argon), or metal atoms (platinum, gold, etc.). Alternatively, lattice defects that reduce carrier lifetime can also be vacancies or inter-lattice atoms that do not contain impurities.

[0146] Regarding the second lifetime region 200, since the carrier lifetime is longer than that of the first lifetime region 204, electrons or holes can easily pass through. By providing the second lifetime region 200 in the diode section 80 as in this example, when the diode section 80 is forward-biased, electrons injected from the cathode region 82 and holes injected from the anode region 14 can pass through the second lifetime region 200. Electrons that have passed through the second lifetime region 200 diffuse in the XY plane and extend above the first lifetime region 204. Holes that have passed through the second lifetime region 200 diffuse in the XY plane and extend below the first lifetime region 204. As a result, when the diode section 80 is forward-biased, especially during low-current operation, the electron density in the region closer to the upper surface 21 than the first lifetime region 204 and the hole density in the region closer to the lower surface 23 than the first lifetime region 204 can be increased. Consequently, conductivity modulation can occur without increasing the anode-cathode voltage Vak, thus suppressing foldback. In this example, a second lifetime region 200 is provided in a diode section 80. The second lifetime region 200 can be disposed at the center in the X-axis direction of the diode section 80.

[0147] Figure 6This is an enlarged cross-sectional view of the vicinity of the second lifetime region 200. The width of the second lifetime region 200 in the first direction (X-axis direction in this example) is defined as W1. The thickness of the first lifetime region 204 in the second direction (Z-axis direction in this example) perpendicular to the upper surface 21 of the semiconductor substrate 10 is defined as T1. The width W1 of the second lifetime region 200 is at least 0.2 times the thickness of the first lifetime region 204. If the width W1 of the second lifetime region 200 is too small, electrons or holes passing through the second lifetime region 200 are easily captured by lattice defects 202 on both sides of the first lifetime region 204. The lattice defects 202 that capture electrons or holes may have trap energy levels. Furthermore, if the thickness T1 of the first lifetime region 204 becomes large, electrons or holes passing through the second lifetime region 200 are easily captured by the lattice defects 202 of the first lifetime region 204. To address this, by making the width W1 of a second lifetime region 200 at least 0.2 times the thickness of the first lifetime region 204, the amount of electrons and holes passing through the second lifetime region 200 can be ensured. The width W1 can be at least 0.25 times, 0.3 times, 0.4 times, 0.5 times, 1 time, or 2 times the thickness T1.

[0148] However, if the second lifetime region 200 is too large, the reverse recovery time of the diode section 80 will increase, and the reverse recovery charge and reverse recovery loss will also increase. In the diode section 80, it is preferable that the total width of the second lifetime region 200 in the X-axis direction is smaller than the total width of the first lifetime region 204. The total width of the second lifetime region 200 in the X-axis direction of the diode section 80 can be less than 10% of the width of the diode section 80 in the X-axis direction, or less than 5%.

[0149] A diode section 80 may have one second lifetime region 200, or it may have multiple second lifetime regions 200 arranged separately in the X-axis direction. The width W1 of each second lifetime region 200 may be 7 μm or more. By increasing the width W1 of the second lifetime region 200, it is possible to suppress the capture of electrons or holes by lattice defects 202 of the first lifetime regions 204 on both sides when electrons or holes pass through the second lifetime region 200. The width W1 may be 8 μm or more, or 9 μm or more. The width W1 may be 12 μm or less. If the width W1 is too large, the turn-off time of the diode section 80 increases, and the reverse recovery loss increases. The width W1 may be 11 μm or less, or 10 μm or less.

[0150] The spacing of the groove portions (in this example, a dummy groove portion 30) in the X-axis direction is defined as W2. The spacing of the groove portions can be the spacing at the center of the groove portions in the X-axis direction. The width W1 of the second life zone 200 can be greater than the spacing W2 of the groove portions. That is, the width W1 of the second life zone 200 can be greater than the table surface width of the table surface sandwiched between two adjacent groove portions in the X-axis direction. The width W1 can be more than 1.2 times, more than 1.5 times, or more than 2 times the spacing W2. The width W1 can be less than 10 times, less than 5 times, or less than 3 times the spacing W2.

[0151] Figure 7 It is shown Figure 6 This is a diagram illustrating the distribution of carrier lifetime, vacancy density, and helium chemical concentration at the ff line. The ff line is a straight line parallel to the X-axis and passes through two first lifetime regions 204 and one second lifetime region 200. The carrier lifetime in the first lifetime region 204 is defined as τ1, and the carrier lifetime in the second lifetime region 200 is defined as τ2. The carrier lifetime τ1 can be the minimum value of the carrier lifetime in the first lifetime region 204. The carrier lifetime τ2 can be the maximum value of the carrier lifetime in the second lifetime region 200. The carrier lifetime τ2 can be the same as or less than the carrier lifetime in the drift region 18. The carrier lifetime in the drift region 18 can be the value at the center of the depth direction of the drift region 18, or it can be the average value.

[0152] The position where the carrier lifetime becomes τa is set as the boundary position between the first lifetime region 204 and the second lifetime region 200. τa is a value greater than τ1 and less than τ2. τa can be the same as either τ1 or τ2, or it can be a value obtained by multiplying either τ1 or τ2 by a predetermined coefficient. τa can be a value slightly greater than τ1, an average of τ1 and τ2, or other values. Alternatively, the position where the carrier lifetime becomes greater than τ1 can be set as the boundary position between the first lifetime region 204 and the second lifetime region 200. The carrier lifetime τ2 of the second lifetime region 200 can be more than 10 times, more than 100 times, or more than 1000 times the carrier lifetime τ1 of the first lifetime region 204. As an example, the carrier lifetime τ1 is less than 100 ns, and the carrier lifetime τ2 is more than 1 μs. τ1 can be less than 10 ns, and τ2 can be more than 10 μs.

[0153] The vacancy density in the first lifetime region 204 is set as V1, and the vacancy density in the second lifetime region 200 is set as V2. The vacancy density V1 can be the maximum value of the vacancy density in the first lifetime region 204. The vacancy density V2 can be the minimum value of the vacancy density in the second lifetime region 200. The vacancy density V2 can be the same as or greater than the vacancy density in the drift region 18. The vacancy density in the drift region 18 can be the value at the center of the depth direction of the drift region 18, or it can be the average value.

[0154] The location where the vacancy density becomes Va can be set as the boundary between the first lifetime region 204 and the second lifetime region 200. Va is a value above V2 and below V1. Va can be the same as either V1 or V2, or it can be a value obtained by multiplying either V1 or V2 by a predetermined coefficient. Va can be a value slightly less than V1, it can be the average of V1 and V2, or it can be other values. Alternatively, the location where the vacancy density becomes less than V1 can be set as the boundary between the first lifetime region 204 and the second lifetime region 200.

[0155] The helium chemical concentration in the first lifetime region 204 is set as H1, and the helium chemical concentration in the second lifetime region 200 is set as H2. The helium chemical concentration H1 can be the maximum value of the helium chemical concentration in the first lifetime region 204. The helium chemical concentration H2 can be the minimum value of the helium chemical concentration in the second lifetime region 200. The helium chemical concentration H2 can be the same as or greater than the helium chemical concentration in the drift region 18. The helium chemical concentration in the drift region 18 can be the value at the center of the depth direction of the drift region 18, or it can be the average value.

[0156] The boundary between the first lifetime region 204 and the second lifetime region 200 can be defined as the position where the helium chemical concentration is Ha. Ha is a value greater than H2 and less than H1. Ha can be the same as either H1 or H2, or it can be a value obtained by multiplying either H1 or H2 by a predetermined coefficient. Ha can be a value slightly less than H1, the average of H1 and H2, or other values. Alternatively, the boundary between the first lifetime region 204 and the second lifetime region 200 can be defined as the position where the helium chemical concentration becomes less than H1. In the case of lattice defects formed by injecting charged particles other than helium, the boundary between the first lifetime region 204 and the second lifetime region 200 can be determined based on the chemical concentration of the charged particles.

[0157] Figure 8 It is shown Figure 6The graph shows the distribution of carrier lifetime, vacancy density, and helium chemical concentration at the gg line. The gg line is a straight line that crosses the first lifetime region 204 along the Z-axis. In this example, the first lifetime region 204 is sandwiched between drift regions 18 along the Z-axis. In this example, the carrier lifetime of drift region 18 is τ2, the vacancy density is V2, and the helium chemical concentration is H2.

[0158] The position where the carrier lifetime τa is defined can be set as the boundary between the first lifetime region 204 and the drift region 18. The carrier lifetime τa and... Figure 7 The example described is the same. The location where the carrier lifetime becomes less than τ2 can also be defined as the boundary between the first lifetime region 204 and the drift region 18. Similarly, the location where the vacancy density becomes Va can be defined as the boundary between the first lifetime region 204 and the drift region 18. The vacancy density Va and... Figure 7 The example described is the same. The location where the vacancy density becomes greater than V² can also be defined as the boundary between the first lifetime region 204 and the drift region 18. Similarly, the location where the helium chemical concentration becomes Ha can be defined as the boundary between the first lifetime region 204 and the drift region 18. The helium chemical concentration Ha and... Figure 7 The example described is the same. Alternatively, the location where the helium chemical concentration becomes greater than H2 can be defined as the boundary between the first lifetime region 204 and the drift region 18. The carrier lifetime distribution in the first lifetime region 204 can be a distribution that decreases with a Gaussian function starting from τ2. The vacancy density distribution in the first lifetime region 204 can be a distribution that increases with a Gaussian function starting from V2. The helium chemical concentration distribution in the first lifetime region 204 can be a distribution that increases with a Gaussian function starting from H2.

[0159] Figure 9 It is shown Figure 6 The graph shows an example of the distribution of carrier lifetime, vacancy density, and helium chemical concentration at the hh line. The hh line is a straight line that crosses the second lifetime region 200 in the Z-axis direction. In this example, the second lifetime region 200 is sandwiched between drift regions 18 in the Z-axis direction.

[0160] In this example, the carrier lifetime of the second lifetime region 200 and the drift region 18 is τ2, the vacancy density is V2, and the helium chemical concentration is H2. In other examples, such as Figure 9 As shown by the dashed line, the carrier lifetime of the second lifetime region 200 can be less than that of the drift region 18. For example... Figure 9 As shown by the dashed line, the vacancy density in the second lifetime region 200 can be higher than that in the drift region 18. For example... Figure 9As shown by the dashed line, the helium chemical concentration in the second lifetime region 200 can be higher than that in the drift region 18. The carrier lifetime distribution in the second lifetime region 200 can be a distribution that decreases with a Gaussian function starting from τ2. The vacancy density distribution in the second lifetime region 200 can be a distribution that increases with a Gaussian function starting from V2. The helium chemical concentration distribution in the second lifetime region 200 can be a distribution that increases with a Gaussian function starting from H2.

[0161] Figure 10 This is another example of an enlarged cross-sectional view near the second lifetime region 200. In this example, the first lifetime region 204 is formed by implanting hydrogen ions into the semiconductor substrate 10. If hydrogen ions are implanted, lattice defects 202 are formed in the passage regions through which the hydrogen ions pass. Hydrogen ions can be implanted from the upper surface 21 of the semiconductor substrate 10. The first lifetime region 204 can be formed up to the upper surface 21 of the semiconductor substrate 10. The structure other than the first lifetime region 204 is the same as any of the embodiments described in this specification.

[0162] When the first lifetime region 204 is formed to extend up to the upper surface 21 of the semiconductor substrate 10, the thickness T1 is the distance from the lower end of the first lifetime region 204 to the upper surface 21. As explained in this specification, the width W1 of the second lifetime region 200 can be determined based on this thickness T1. The distance in the depth direction from the depth position of the density peak of the lattice defect 202 to the lower end of the first lifetime region 204 is defined as T1'. 2×T1' can also be used as the thickness T1 of the first lifetime region 204.

[0163] Figure 11A Show Figure 10 The diagrams show the distributions of net doping concentration (A), hydrogen chemical concentration (B), lattice defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along the hh line in the semiconductor device 100 of the illustrated embodiment. The horizontal axis in each distribution diagram indicates the position in the depth direction. In this example, hydrogen ions are injected from the upper surface 21 to the depth position Ps to form a first lifetime region 204. Additionally, the buffer zone 20 has multiple doping concentration peaks. Figure 11A In the middle, in order of distance from the lower surface 23, Pb1 to Pb4 have doping concentration peaks at depth positions respectively. In addition, a lower surface-side lifetime region 19 formed by irradiation with charged particles such as helium is provided at depth position Kb.

[0164] Distribution diagram (A) shows the actual doping concentration distribution of the electroactivated donors and acceptors. In this example, a hydrogen donor concentration of N is set at position Ps. p The peak. Figure 11AIn the process, the region where the peak is located is designated as the high-concentration region 26. The doping concentration of a portion of the region on the lower surface 23 than position Ps is designated as the doping concentration N0. The doping concentration N0 can be the bulk donor concentration. The bulk donor of the semiconductor substrate 10 can be phosphorus, antimony, or arsenic, or it can have a bulk acceptor (boron, aluminum, indium, etc.) at a level not exceeding the bulk donor concentration.

[0165] In the distribution diagram (A), the N-type region with a higher doping concentration than the drift region 18 is designated as N+ type. The doping concentration of at least a portion of the drift region 18 between positions Ps and Pb4 can be lower than the doping concentration of the drift region 18 further up the surface 21 than position Ps. Hydrogen ions injected from the upper surface 21 of the semiconductor substrate 10 pass through the drift region 18 on the upper surface 21 side. Therefore, the doping concentration of this drift region 18 can become higher than the doping concentration N0 of the semiconductor substrate 10 due to residual hydrogen donors. The average doping concentration of the drift region 18 on the upper surface 21 side can be less than three times the doping concentration N0 of the semiconductor substrate 10.

[0166] Hydrogen ions are implanted from the lower surface 23 of the semiconductor substrate 10 at positions Pb4, Pb3, Pb2, and Pb1. Therefore, the doping concentration in the region further down the lower surface 23 than position Pb4 can be higher as a whole than the doping concentration N0 of the semiconductor substrate 10. That is, the doping concentration (donor concentration in this example) of the drift region 18, which is sandwiched between two hydrogen donor peaks (in this example, the peaks of the hydrogen donors at positions Ps and Pb4 respectively), is the lowest in the depth direction. The doping concentration (donor concentration in this example) of this region sandwiched between the two hydrogen donor peaks is the doping concentration N0 of the semiconductor substrate 10, and the doping concentration distribution can be substantially flat. A substantially flat doping concentration distribution can be defined as a region where, relative to a predetermined proportion of the distance between positions Ps and Pb4, the concentration difference between the maximum and minimum doping concentrations is less than 50% of the average doping concentration in that region. The predetermined ratio can be any value within the range of 50% to 80% relative to the distance between position Ps and position Pb4. Through hydrogen donors, the doping concentration from position Ps to the upper surface 21 and from position Pb4 to the lower surface 23 can become higher than the doping concentration N0 of the semiconductor substrate 10. It should be noted that the cathode region 82 in this example is formed by implanting phosphorus and allowing it to diffuse or by electroactivating it.

[0167] like Figure 11A As shown by the dashed line, an N+ type accumulation zone 16 can be provided between the anode zone 14 and the drift zone 18. The accumulation zone 16 can be continuously provided from one of two adjacent groove portions in the X-axis direction to the other in each stage.

[0168] Distribution diagram (B) shows the concentration of the chemical properties of the injected hydrogen (hydrogen chemical concentration). Each peak of the hydrogen chemical concentration has a tail on the main surface side where hydrogen ions were injected. In this example, the peak of the hydrogen chemical concentration at position Ps has a tail S on the upper surface 21 side. That is, in this example, the hydrogen chemical concentration distribution on the upper surface 21 side gradually and monotonically decreases from the first position Ps to the upper surface 21. The tail S can be provided throughout the drift region 18 and the anode region 14.

[0169] In this example, the hydrogen chemical concentration distribution from position Ps to the lower surface 23 has a steeper tail than the tail S. That is, the hydrogen chemical concentration distribution is located on the upper surface 21 side than position Ps and on the lower surface 23 side than position Ps, showing an asymmetric distribution.

[0170] Furthermore, the hydrogen chemical concentration peaks at positions Pb4, Pb3, Pb2, and Pb1 each exhibit a tail S' on the lower surface 23 side. The hydrogen chemical concentration peaks at positions Pb4, Pb3, Pb2, and Pb1 each exhibit a steeper tail on the upper surface 21 side, compared to the tail S'. In other words, the hydrogen chemical concentration peaks at positions Pb4, Pb3, Pb2, and Pb1 show an asymmetric distribution on both the upper surface 21 side and the lower surface 23 side, both of which are closer to their respective positions.

[0171] It should be noted that the hydrogen chemical concentration can be minimized between the position closest to the lower surface 23 (position Ps in this example) among the positions where hydrogen ions are injected from the upper surface 21 (position Pb4 in this example) and the position closest to the upper surface 21 among the positions where hydrogen ions are injected from the lower surface 23 (position Pb4 in this example). The position where the sum of the hydrogen diffusion distribution at position Ps and the hydrogen diffusion distribution at position Pb4 is minimized is the position where the hydrogen chemical concentration is minimized. Alternatively, the position where the hydrogen chemical concentration is minimized can be located in a region sandwiched between the peaks of the two hydrogen donors (position Ps and position Pb4 in this example), and the doping concentration shows a generally flat doping concentration distribution of the doping concentration N0 of the semiconductor substrate 10. Alternatively, the position where the hydrogen chemical concentration is minimized can also be the upper surface 21.

[0172] Distribution diagram (C) shows the lattice defect density after annealing under predetermined conditions following hydrogen ion implantation into the semiconductor substrate 10. Position Z0 is defined as the location where the net doping concentration of the high-concentration region 26 is approximately equal to the doping concentration N0 of the semiconductor substrate 10, closer to the lower surface 23 than position Ps. The lattice defect density on the side closer to the lower surface 23 than position Z0 can be a sufficiently small value Nr0. A sufficiently small lattice defect density Nr0 means a value with a low lattice defect density to the extent that the carrier lifetime is not less than τ0 described below. As an example, if the concentration of vacancies or double vacancies is defined as Nr0, Nr0 can be less than or equal to 1 × 10⁻⁶ at a temperature of 300 K. 12 atoms / cm 3 It can also be 1×10 11 atoms / cm 3 Below, it can also be 1×10 10 atoms / cm 3 Below, at the position J0 of the pn junction between the anode region 14 and the drift region 18 or the accumulation region 16, the lattice defect density can be higher than Nr0.

[0173] In the vicinity of position Ps and in the region extending from the upper surface 21 to position Ps, lattice defects caused by the passage of hydrogen ions are formed. This allows the formation of a first lifetime region 204. However, near position Ps, since the lattice defects are hydrogen-capped, the distribution of the lattice defect density has a different shape than the distribution of the hydrogen chemical concentration. For example, the position Ps of the hydrogen chemical concentration peak does not coincide with the position Ks of the lattice defect density peak. In this example, the position Ks of the lattice defect density peak is located closer to the upper surface 21 of the semiconductor substrate 10 than the position Ps of the hydrogen chemical concentration peak. The lattice defect density can decrease monotonically on the side closer to the upper surface 21 than on the side closer to position Ks. The lattice defect density can decrease monotonically more steeply on the side closer to the lower surface 23 than on the side closer to the upper surface 21.

[0174] Near the peak position Ps of the hydrogen chemical concentration, a large number of hydrogen atoms end dangling bonds such as vacancies and double vacancies. Therefore, the lattice defect density near the peak position Ps becomes very small compared to the lattice defect density at the peak position Ks. In this specification, the width of the distribution showing concentrations greater than 1% of the peak concentration is referred to as the 1% full width or FW1%M. The vicinity of the peak position Ps can refer to the region within the 1% full width centered on the peak position Ps. The peak position Ks of the lattice defect density can be located at a shallower position than the 1% full width centered on the peak position Ps.

[0175] The distance D between the peak position Ks of the lattice defect density and the peak position Ps of the hydrogen chemical concentration is determined based on the distance hydrogen diffuses within the semiconductor substrate 10 due to annealing. Distance D can be less than 40 μm, less than 20 μm, or less than 10 μm. Distance D can be greater than 1 μm, greater than 3 μm, or greater than 5 μm. Distance D can be greater than or equal to 1% of the full width of the hydrogen chemical concentration. Distance D can be greater than or equal to 1% of the full width of the net doping concentration at position Ps. In this case, 1% of the full width of the net doping concentration is the width of the peak at 0.01 Np. The value of distance D can be any combination of any of the above upper and lower limits. As an example, the lattice defect density distribution can be observed by measuring the density distribution of vacancies / double vacancies using positron annihilation.

[0176] The depth at which the lattice defect density first coincides with Nr0, from the upper surface 21 towards the lower surface 23, is set as Z1. The first lifetime region 204 can be set from the upper surface 21 to position Z1. Figure 10 As explained, the thickness T1 can be defined as the distance from the upper surface 21 to position Z1. In other examples, twice the distance T' from position Ks to position Z1 can also be used as the thickness T1. In this example, the first lifetime region 204 contains hydrogen donors.

[0177] A peak of lattice defect density (lower surface-side lifetime region 19) can be configured from the lower surface 23 up to position Pb4. In this example, a peak of lattice defect density (lower surface-side lifetime region 19) is configured at position Kb between positions Pb2 and Pb1. The peak of lattice defect density at position Kb mainly includes lattice defects formed when helium ions are injected from the lower surface 23 between positions Pb2 and Pb1. In this example, no peak of lattice defect density is set on the side closer to the lower surface 23 than position Pb4, except at position Kb.

[0178] For example, hydrogen ions are implanted into positions Pb4, Pb3, Pb2, and Pb1, and the semiconductor substrate 10 is annealed under a first condition. This results in peaks in the hydrogen chemical concentration distribution at positions Pb4, Pb3, Pb2, and Pb1. Subsequently, hydrogen ions are implanted into position Ps, and helium ions are implanted between positions Pb2 and Pb1, and the semiconductor substrate 10 is annealed under a second condition. The annealing temperature of the second condition is lower than that of the first condition. Most of the lattice defects generated by implanting hydrogen ions into positions Pb4, Pb3, Pb2, and Pb1 are sealed by the higher-temperature annealing. Conversely, the lattice defects generated by implanting hydrogen ions into position Ps are sealed by the lower-temperature annealing. On the other hand, since hydrogen is also abundant near position Pb1, the lattice defects generated by injecting helium ions between positions Pb2 and Pb1 are also capped near position Pb1, but the lattice defect density has a peak between positions Pb2 and Pb1.

[0179] In this example, the hydrogen chemical concentration peak at position Ps does not have any other hydrogen chemical concentration peaks on the side where hydrogen ions are injected (the upper surface 21 side in this example). On the other hand, the hydrogen chemical concentration peak at position Pb2 has other hydrogen chemical concentration peaks (position Pb1) on the side where helium ions are injected (the lower surface 23 side in this example). The integral value of the lattice defect density on the side closer to the upper surface 21 than position Ps can be greater than the integral value of the lattice defect density on the side closer to the lower surface 23 than position Pb2. It should be noted that the lattice defect density at position Kb can be set as the helium chemical concentration.

[0180] Distribution diagram (D) shows the carrier lifetime distribution after annealing under predetermined conditions following the implantation of hydrogen ions into the semiconductor substrate 10. The carrier lifetime distribution is a shape obtained by flipping the vertical axis of the lattice defect density distribution. For example, the position where the carrier lifetime reaches its minimum coincides with the central peak position Ks of the lattice defect density. It should be noted that the carrier lifetime of the semiconductor device 100 can reach its maximum value τ0 in the region within the range of FW1%M centered on the peak position Ps of the hydrogen chemical concentration. The maximum value τ0 can be the carrier lifetime in the drift region 18, which is closer to the lower surface 23 than the peak position Ps of the hydrogen chemical concentration. The carrier lifetime of the semiconductor device 100 can reach its maximum value τ0 in the region within the range of FW1%M centered on the respective peak positions Ps, Pb4, Pb3, Pb2, and Pb1 of the hydrogen chemical concentration.

[0181] On the side closer to the lower surface 23 than position Z0, the carrier lifetime can be a sufficiently large value τ0. A sufficiently large carrier lifetime τ0 can be the carrier lifetime without intentionally introducing defects, primarily lifetime control bodies or vacancies and / or double vacancies, into the semiconductor substrate 10. At a temperature of 300 K, τ0 can be greater than 10 μs or greater than 30 μs. As an example, τ0 is 10 μs. At position J0 of the pn junction between the anode region 14 and the drift region 18 or the accumulation region 16, the carrier lifetime can be less than τ0.

[0182] Distribution diagram (E) shows the carrier mobility distribution after annealing under predetermined conditions following hydrogen ion implantation into the semiconductor substrate 10. On the side closer to the lower surface 23 than position Z0, the carrier mobility can be the mobility μ0 under ideal crystal structure conditions. As an example, in the case of silicon at a temperature of 300 K, the electron mobility μ0 is 1360 cm⁻¹. 2 / (Vs), the hole is 495cm 2 / (Vs). At the location J0 of the pn junction between the anode region 14 and the drift region 18 or the accumulation region 16, the carrier mobility can be less than μ0.

[0183] The location where the carrier mobility reaches a minimum value can coincide with the central peak position Ks of the lattice defect density. Furthermore, the location where the carrier mobility reaches a minimum value coincides with the central peak position Kb of the lattice defect density. Within the region of FW1%M centered on the peak positions Ps, Pb4, Pb3, Pb2, and Pb1 of the hydrogen chemical concentration, the carrier mobility of the semiconductor device 100 can reach a maximum value μ0.

[0184] Distribution diagram (F) shows the carrier concentration distribution after annealing under predetermined conditions following hydrogen ion implantation into the semiconductor substrate 10. As an example, the carrier concentration can be measured using the diffusion resistance measurement method (SR measurement). In the SR measurement method, the diffusion resistance is converted to specific resistance, and the carrier concentration is calculated based on the specific resistance. If the specific resistance is set as ρ (Ω·cm), and the mobility is set as μ (cm²), then... 2 / (V·s)), let the elementary charge be q(C), and the carrier concentration be N( / cm). 3 If ), then it is represented by N = 1 / (μqρ).

[0185] In the SR measurement method, the value of the ideal crystallization state of the semiconductor substrate 10 is used as the carrier mobility. However, if damage remains in the semiconductor substrate 10 due to ion implantation, the crystallization state of the semiconductor substrate 10 collapses, becoming a disordered state, and the mobility actually decreases. The reduced mobility should be used as the mobility in the SR measurement, but it is difficult to measure the value of the reduced mobility. Therefore, in the SR measurement of the example in the distribution diagram (F), the ideal value is used as the mobility. Therefore, the denominator of the above formula for carrier concentration becomes larger, and the mobility decreases. That is, in the distribution diagram (F), the measured carrier concentration decreases overall in the region where hydrogen ions pass (the region from the lower end of the anode region 14 of the semiconductor substrate 10 to the high concentration region 26). However, in the high concentration region 26 near the hydrogen ion range Ps, due to the high hydrogen chemical concentration, the disordered state is mitigated by the hydrogen capping effect, and the mobility approaches the value of the crystallization state. Furthermore, hydrogen donors are formed. Therefore, the carrier concentration becomes higher than the carrier concentration N0 of the semiconductor substrate 10.

[0186] In the region where hydrogen ions pass through (the region from the lower end of the anode region 14 of the semiconductor substrate 10 to near position Ps), the measured carrier concentration decreases overall. However, in the region closer to the lower surface 23 than position Pb4, the carrier concentration is higher than the substrate concentration N0 due to the overall high hydrogen chemical concentration.

[0187] In this example, the lattice defect density of the annealed semiconductor device 100 decreases around the peak position Ps of the hydrogen chemical concentration. Therefore, the carrier lifetime near the peak position Ps of the hydrogen chemical concentration increases, almost becoming τ0.

[0188] Additionally, as an example, the hydrogen chemical concentration at peak position Pb1 is the highest throughout the entire semiconductor substrate 10. If the maximum value of the hydrogen chemical concentration at peak position Pb1 is greater than or equal to 1 × 10⁻⁶... 15 atoms / cm 3 Then the concentration of hydrogen diffusing to the upper surface 21 increases. At this time, hydrogen diffuses to position Ps. As a result, the dangling bonds formed by vacancies or double vacancies at position Ps are sealed not only by hydrogen injected into position Ps at maximum concentration from the upper surface 21, but also by hydrogen moving from position Pb1 through diffusion. Thus, the lattice defect density can reliably become Nr0 near the peak of the doping concentration distribution at position Ps, and the carrier lifetime at position Ps can be τ0.

[0189] Figure 11B These are other examples of enlarged cross-sectional views near the second lifetime region 200. This example is related to... Figure 10The difference in this example is that hydrogen ions are injected from the lower surface 23 side to the upper surface 21 side (e.g., the lower end of the trench or near the upper surface 21) to form a first lifetime region 204. The distance T1 from the lower surface 23 to the end of the first lifetime region 204 on the upper surface 21 side can be greater than half the thickness of the semiconductor substrate 10 in the Z-axis direction. In this example, the distance T1 is comparable to the thickness of the first lifetime region 204. Figure 10 Similarly, the distance in the depth direction from the depth position of the density peak of the lattice defect 202 to the upper end of the first lifetime region 204 is defined as T1'. The thickness T1 of the first lifetime region 204 can also be 2×T1'.

[0190] Figure 11C Show Figure 11B The diagram shows the distribution of net doping concentration (A), hydrogen chemical concentration (B), lattice defect density (C), carrier lifetime (D), carrier mobility (E), and carrier concentration (F) along the hh line in the semiconductor device 100 of the illustrated embodiment. On the buffer 20 side of the drift region 18, at least one of the doping concentration and carrier concentration can become higher than the bulk donor concentration. The buffer 20 side of the drift region 18 refers to the side closer to the buffer 20 in the depth direction than the center of the drift region 18. Figure 11C In the example, a region is provided in the drift region 18 that is in contact with the buffer 20, where at least one of the doping concentration and the carrier concentration is higher than the bulk donor concentration.

[0191] Figure 11D These are other examples of enlarged cross-sectional views near the second lifetime region 200. This example is related to... Figure 10 and Figure 11B The difference in this example is that the first lifetime region 204 is formed over the entire length from the upper surface 21 to the lower surface 23. In this example, the first lifetime region 204 can be formed by injecting hydrogen ions or helium from the upper surface 21 through the lower surface 23, or by injecting hydrogen ions or helium from the lower surface 23 through the upper surface 21. In this example, the first lifetime region 204 can be formed by irradiation with an electron beam. The thickness T1 of the first lifetime region 204 in this example is the same as the thickness of the semiconductor substrate 10. As an example, the width of the region where the density of lattice defects 202 is above a predetermined value can be set as T1. The predetermined value of the density of lattice defects 202 can be set as 1 × 10⁻⁶. 14 / cm 3Alternatively, a predetermined value for the density of lattice defects 202 can be set as the doping concentration value of the drift region 18. As another example, the width of the region where the carrier concentration, as determined by SR, is lower than the doping concentration of the drift region 18 can be set as T1. The doping concentration of the drift region 18 can be the bulk donor concentration, the concentration of the difference between the bulk donor and bulk acceptor concentrations, the sum of the bulk donor and hydrogen donor concentrations, or the sum of the difference between the bulk donor and bulk acceptor concentrations and the hydrogen donor concentration.

[0192] Figure 12 This is a diagram illustrating an example of the VI characteristics of the diode section 80 when it is in forward conduction. Figure 12 The characteristic 250 shown is... Figure 4 The comparative examples shown have the same characteristics. In the comparative examples, the second lifetime region 200 is not provided. Figure 12 The characteristic 251 shown is as follows Figures 5 to 9 As explained, this is an example of a diode section 80 having a second lifetime region 200. In the example of characteristic 251, the width W1 of the second lifetime region 200 is 8 μm, the thickness T1 of the first lifetime region 204 is 30 μm, and the ratio W1 / T1 is approximately 0.27. For characteristics 250-1 and 251-1, the carrier lifetime in the first lifetime region 204 is the same; for characteristics 250-2 and 251-2, the carrier lifetime in the first lifetime region 204 is the same; for characteristics 250-3 and 251-3, the carrier lifetime in the first lifetime region 204 is the same. Figure 12 As shown, by providing a second lifetime region 200, even if the carrier lifetime of the first lifetime region 204 is reduced, foldback can be suppressed. Therefore, foldback can be suppressed while reducing the reverse recovery loss of the diode section 80.

[0193] Figure 13 This is a graph showing the trade-off between the forward voltage Vf and the reverse recovery loss Err in diode section 80. Figure 13 The diagram shown in circles is as follows Figures 5 to 9 As explained, this characteristic occurs when a second lifetime region 200 is provided in a diode section 80. Figure 13 The diagram shown in squares illustrates the characteristics without the second lifetime region 200. In the example shown in black squares, a foldback occurs.

[0194] like Figure 13 As shown, even with the second lifetime region 200 provided, the same compromise characteristics as without the second lifetime region 200 can be obtained. Furthermore, in regions with short carrier lifetimes, the occurrence of backflips can be suppressed by providing the second lifetime region 200.

[0195] Figure 14 This is a graph showing the relationship between the width W1 of the second lifetime region 200 and the foldback amount (SB amount). In this example, as... Figures 5 to 9 As explained, a second lifetime region 200 is provided in a diode section 80. In this example, the thickness T1 of the first lifetime region 204 is 30 μm. It can be seen that the foldback amount is reduced by increasing the width W1 of the second lifetime region 200. In particular, if the width W1 of the second lifetime region 200 exceeds 7 μm, the foldback amount is significantly reduced, and if the width W1 becomes 11 μm or more, the foldback amount becomes 0.

[0196] The width W1 of the second lifetime region 200 can be 7 μm or more. The width W1 can be 8 μm or more, 10 μm or more, or 11 μm or more. The ratio W1 / T1 of the width W1 of the second lifetime region 200 to the thickness T1 of the first lifetime region 204 can be 0.23 or more, 0.27 or more, 0.33 or more, or 0.37 or more. Alternatively, the width W1 of the second lifetime region can be 12 μm or less. The ratio W1 / T1 can be 0.4 or less.

[0197] Figure 15 This is a diagram showing whether a foldback occurs when the thickness T1 of the first lifetime region 204 and the width W1 of the second lifetime region 200 are changed. Figure 15 The circled diagram illustrates a boundary example where no foldback occurs. In regions 220, 222, and 224, which have a larger width W1 (or smaller thickness T1) compared to this boundary example, no foldback occurs.

[0198] In region 222, the IE effect is weakened due to the large thickness T1 of the first lifetime region 204, resulting in an excessively high forward voltage Vf. In region 224, the IE effect is strengthened even in the low-current operating region due to the small thickness T1 of the first lifetime region 204, resulting in an excessively low forward voltage Vf. Therefore, the thickness T1 of the first lifetime region 204 and the width W1 of the second lifetime region 200 are preferably set within the range of region 220. Region 220 is a region where the width W1 is greater than the width W (μm) defined by line 230. Line 230 is given by equation (1).

[0199] W = 0.21 × T1 + 3.3··· (1)

[0200] As described above, if the thickness T1 of the first lifetime region 204 is too large, the IE effect weakens. The thickness T1 can be less than the thickness in the depth direction (Z-axis direction) of the drift region 18. Furthermore, the thickness T1 can be less than 100 μm, less than 60 μm, or less than 40 μm. The thickness T1 is greater than 0. However, if the thickness T1 is too small, the IE effect also strengthens in the low-current operating region, and the forward voltage Vf becomes too low. The thickness T1 can be greater than 10 μm, greater than 15 μm, or greater than 20 μm.

[0201] Figure 16A This is a diagram showing another configuration example of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. Besides the configuration of the first lifetime region 204 and the second lifetime region 200, it is similar to... Figures 1 to 15 The same applies to any of the methods described herein.

[0202] In this example, the semiconductor device 100 includes two or more second lifetime regions 200 in a diode section 80. Each second lifetime region 200 is arranged with a gap in a first direction (the X-axis direction in this example). A first lifetime region 204 is disposed between two second lifetime regions 200. The width W1 of each second lifetime region 200 can be... Figures 1 to 15 The width W1 described herein is the same. By setting two or more second lifetime regions 200, it is possible to homogenize the electron density closer to the top than the first lifetime region 204. Electrons can pass through in a manner that disperses them across multiple second lifetime regions 200.

[0203] It should be noted that, in Figures 1 to 16A In the examples described, the sum of the widths W1 of the more than one second lifetime region 200 included in a diode section 80 in the first direction (the X-axis direction in this example) can be less than 0.1 times the width WD of the diode section 80 in the first direction. If the sum of the widths W1 becomes too large, the turn-off time of the diode section 80 becomes longer, and the reverse recovery loss increases. The sum of the widths W1 can also be less than 0.05 times the width WD. The sum of the widths W1 can be more than 0.001 times the width WD, or more than 0.01 times the width WD.

[0204] The diode section 80 has a plurality of trench sections (in this example, dummy trench sections 30) disposed above the first lifetime region 204. The distance D2 between the second lifetime region 200 and the transistor section 70 in the first direction (in this example, the X-axis direction) can be greater than or equal to the distance D1 between the lower end of the trench section (in this example, the dummy trench section 30) and the first lifetime region 204 in the second direction (in this example, the Z-axis direction). This trench section can be the dummy trench section 30 closest to the transistor section 70 among the plurality of dummy trench sections 30 of the diode section 80. The end of the transistor section 70 in the X-axis direction is the boundary portion between the collector region 22 and the cathode region 82. By ensuring the distance D2, the diffusion of electrons injected from the cathode region 82 into the transistor section 70 can be suppressed, and the outflow to the emitter electrode 52 through the n-type channel formed in the base region 14 of the transistor section 70 can be reduced. The distance D2 can be more than 1.5 times or more than 2 times the distance D1.

[0205] Two or more second lifetime regions 200 can be arranged at equal intervals in the first direction. In other examples, the interval W3 between the second lifetime regions 200 can be less than the distance D2. With this configuration, the distance D2 can also be increased. In this example, the interval W3 between the second lifetime regions 200 is the width of the first lifetime region 204 in the first direction. Any one of the second lifetime regions 200 can be positioned at the center of the diode section 80 in the first direction. As a result, electrons or holes are injected symmetrically with respect to the center of the diode section 80, and the carrier concentration in the diode section 80 becomes substantially uniformly distributed.

[0206] Figure 16B This is a diagram showing another configuration example of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. This example is related to... Figure 16A The difference in the example is that the first lifetime region 204 and the second lifetime region 200 are formed on the lower surface 23 side. The first lifetime region 204 and the second lifetime region 200 can be formed inside the buffer zone 20, can be formed in both the buffer zone 20 and the cathode region 82, or can be formed in both the buffer zone 20 and the collector region 22. (Compared to...) Figure 11B Similarly, the distance in the depth direction from the depth position of the density peak of the lattice defect 202 to the upper end of the first lifetime region 204 is defined as T1'. The thickness T1 of the first lifetime region 204 can also be 2 × T1'. Thus, uniform injection of electrons or holes in the first direction can suppress backlash.

[0207] Figure 16C This is a diagram showing another configuration example of the first lifetime region 204 and the second lifetime region 200 in the diode section 80. This example is related to... Figure 16BThe difference in the example is that the first lifetime region 204 and the second lifetime region 200 are formed on the lower surface 23 side of the drift region 18. The distance T1 from the lower surface 23 to the end of the first lifetime region 204 on the upper surface side can be less than half the thickness of the semiconductor substrate 10 in the Z-axis direction. In the case where the first lifetime region 204 is formed by implanting hydrogen ions, etc., from the lower surface 23, the distance T1 is comparable to the thickness of the first lifetime region 204. Figure 11B Similarly, the distance in the depth direction from the depth position of the density peak of the lattice defect 202 to the upper end of the first lifetime region 204 is defined as T1'. The thickness T1 of the first lifetime region 204 can also be 2×T1'.

[0208] Figure 17 This is a diagram showing whether a foldback occurs when the number of second lifetime regions 200 included in a diode section 80 and the width W1 of each second lifetime region 200 are varied. Figure 17 The circled area in the diagram illustrates a boundary example where no foldback occurs. No foldback occurs in region 240, which has a wider width W1 than this boundary example. In the case of multiple second lifetime regions 200, the multiple second lifetime regions 200 are arranged at equal intervals in the first direction. In this example, the thickness T1 of the first lifetime region 204 is 30 μm.

[0209] If the number of second lifetime zones is 200 ( Figure 17 Increasing the number of regions on the horizontal axis allows for the suppression of the tendency to fold back even when the width W1 of the second lifetime region 200 is reduced. However, even when the number of second lifetime regions 200 is increased to more than 4, the width W1 of the second lifetime region 200 required to prevent fold back does not decrease.

[0210] The width W1 of a second lifetime region 200 can be 8 μm or more. The width W1 can be 0.27 times or more the thickness T1 of the first lifetime region 204. Furthermore, even when only one second lifetime region 200 is provided in a single diode section 80, foldback can be suppressed as long as the width W1 is approximately 12 μm. The width W1 can be 12 μm or less. The width W1 can be 0.4 times or less the thickness T1 of the first lifetime region 204.

[0211] Figure 18 This diagram illustrates an example configuration of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the first lifetime region 204 and the second lifetime region 200 are stripe shapes with long sides in a third direction (the Y-axis direction in this example) that is parallel to the upper surface 21 of the semiconductor substrate 10 and perpendicular to the first direction (the X-axis direction in this example). The first lifetime region 204 and the second lifetime region 200 may have the same length as the cathode region 82 in the Y-axis direction, or they may be longer than the cathode region 82.

[0212] In this example, the diode section 80 and the transistor section 70 are arranged in a first direction (X-axis direction). Additionally, as... Figure 2 As shown, the trench portions (gate trench portion 40 and dummy trench portion 30) are arranged at intervals in the first direction (X-axis direction). In this example, the long side direction of the first lifetime region 204 and the second lifetime region 200 is the same as the long side direction of the trench portion. In addition, the long side direction of the first lifetime region 204 and the second lifetime region 200 is the same as the long side direction of the diode portion 80 (or cathode region 82).

[0213] Figure 19 This diagram illustrates another configuration example of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the Y-axis direction is the first direction, and the X-axis direction is the third direction. That is, the first lifetime region 204 and the second lifetime region 200 in this example are arranged in the Y-axis direction. The first lifetime region 204 and the second lifetime region 200 in this example have a striped shape with a long side in the X-axis direction (third direction). The first lifetime region 204 and the second lifetime region 200 may have the same length as the diode section 80 in the X-axis direction, or they may be longer than the diode section 80.

[0214] In this example, the diode section 80 and the transistor section 70 are arranged in a third direction (X-axis direction). Furthermore, the trench sections (gate trench section 40 and dummy trench section 30) are arranged at intervals in a third direction (X-axis direction). In this example, the long side directions of the first lifetime region 204 and the second lifetime region 200 are orthogonal to the long side directions of the trench sections. Additionally, the long side directions of the first lifetime region 204 and the second lifetime region 200 are orthogonal to the long side direction of the diode section 80 (or the cathode region 82). This arrangement helps to suppress foldback while reducing the reverse recovery loss of the diode section 80.

[0215] Figure 20 This is a diagram showing another configuration example of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the second lifetime region 200 is also sandwiched between the first lifetime regions 204 in a third direction (in this example, the Y-axis direction) that is parallel to the upper surface 21 of the semiconductor substrate 10 and perpendicular to the first direction (in this example, the X-axis direction).

[0216] As an example, multiple first lifetime regions 204 can be discretely configured in both the X-axis and Y-axis directions. Figure 20 In this example, the first lifetime region 204, which is rectangular when viewed from above, is discretely configured along both the X-axis and Y-axis directions. The second lifetime region 200 in this example is a lattice structure in which portions extending along the X-axis and Y-axis intersect when viewed from above.

[0217] In other examples, multiple second lifetime regions 200 may be discretely configured along both the X-axis and Y-axis directions. For example, the second lifetime regions 200, which are rectangular when viewed from above, may be discretely configured along both the X-axis and Y-axis directions.

[0218] In this example, the width of the second lifetime region 200 in the Y-axis direction is set to W2. Width W2 satisfies the following conditions: Figures 1 to 19 The width W1 is the same as described above. For example, the width W2 is more than 0.2 times the thickness T1 of the first lifetime region 204. However, the width W2 can also be different from the width W1. The widths W1 and W2 are in... Figures 1 to 19 Within the range of the conditions for the width W1 described herein, the values ​​can be different from each other. This configuration also allows for the suppression of foldbacks while reducing the reverse recovery loss of the diode section 80.

[0219] Figure 21 This is a diagram showing another configuration example of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the first lifetime region 204 is sandwiched between the second lifetime region 200 in a first direction (the X-axis direction in this example) and a third direction (the Y-axis direction in this example) parallel to the upper surface 21 of the semiconductor substrate 10.

[0220] As an example, multiple second lifetime regions 200 can be discretely configured in both the X-axis and Y-axis directions. Figure 21 In this example, the second lifetime region 200, which is rectangular when viewed from above, is discretely arranged along both the X-axis and Y-axis directions. The first lifetime region 204 in this example is a lattice structure where portions extending along the X-axis and Y-axis intersect when viewed from above. This configuration also helps to suppress foldbacks while reducing the reverse recovery loss of the diode section 80.

[0221] A second lifetime region 200 may be disposed inside the first lifetime region 204 of the diode section 80. The second lifetime region 200 may or may not be disposed inside the first lifetime region 204 of the transistor section 70. Disposing of the second lifetime region 200 inside the first lifetime region 204 means that the second lifetime region 200 is surrounded by the first lifetime region 204 when viewed from above. The ratio of the area S2_t of the second lifetime region 200 surrounded by the first lifetime region 204 in the transistor section 70 to the area S1_t of the first lifetime region 204 is set as S2_t / S1_t. The ratio of the area S2_d of the second lifetime region 200 surrounded by the first lifetime region 204 in the diode section 80 to the area S1_d of the first lifetime region 204 is set as S2_d / S1_d. The ratio S2_t / S1_t may be less than the ratio S2_d / S1_d. The ratio S2_t / S1_t can be less than 50%, less than 20%, or less than 10% of the ratio S2_d / S1_d. The area S2_t can also be 0. When the body diode of the transistor section 70 is energized, a large number of charge carriers are injected. However, by reducing the second lifetime region 200 inside the first lifetime region 204 of the transistor section 70 or by not providing the second lifetime region 200 inside the first lifetime region 204 of the transistor section 70, the lifetime of these charge carriers can be shortened.

[0222] Figure 22A This is a diagram illustrating other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the configuration of multiple second lifetime regions 200 is similar to... Figure 21 The examples differ. Other structures are different. Figure 21 The examples are the same.

[0223] exist Figure 21 In this example, multiple second lifetime regions 200 are arranged in a configuration along the X-axis and Y-axis directions. Figure 22A In this example, multiple second lifetime regions 200 are arranged along two directions different from both the X and Y axes. This configuration also allows for the suppression of foldbacks while reducing the reverse recovery loss of the diode section 80.

[0224] A second lifetime region 200 can be disposed inside the first lifetime region 204 of the diode section 80. The second lifetime region 200 can be disposed inside the first lifetime region 204 of the transistor section 70, or it can be omitted. With this configuration, it is possible to suppress foldback while reducing the reverse recovery loss of the diode section 80.

[0225] Figure 22B This is a diagram illustrating other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the configuration of multiple second lifetime regions 200 is similar to... Figure 22AThe examples differ. The configuration of multiple second lifetime zones 200 can be non-symmetric or random.

[0226] Figure 23A This is a diagram illustrating other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the configuration of the plurality of first lifetime regions 204 is similar to... Figure 20 The examples differ. Other structures are different. Figure 20 The examples are the same.

[0227] exist Figure 20 In this example, multiple first lifetime regions 204 are arranged in a configuration along the X-axis and Y-axis directions. Figure 23A In this example, multiple first lifetime regions 204 are arranged along two directions different from both the X and Y axes. This configuration also allows for the suppression of foldbacks while reducing the reverse recovery loss of the diode section 80.

[0228] In this example, the second lifetime region 200 is a grid-like structure where the portion extending along the X-axis intersects with the portion extending along the Y-axis when viewed from above. The widths W1 and W2 of the second lifetime region 200 can be widths in directions orthogonal to the extension direction of the second lifetime region 200. In this example, the width of the second lifetime region 200 extending along the Y-axis in the X-axis direction is set as W1, and the width of the second lifetime region 200 extending along the X-axis in the Y-axis direction is set as W2.

[0229] Figure 23B This is a diagram illustrating other configuration examples of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the configuration of the plurality of first lifetime regions 204 is similar to... Figure 23A The examples differ. The configuration of multiple first lifetime regions 204 can be non-symmetric or random.

[0230] Figure 24 This diagram illustrates another configuration example of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the extension directions of the first lifetime region 204 and the second lifetime region 200 are different from both the X-axis and Y-axis directions. Other structures are the same as any of the configurations described in this specification.

[0231] In this example, first lifetime regions 204 and second lifetime regions 200 are alternately arranged along a first direction orthogonal to the extension direction of each lifetime region. In this example, the first direction differs from both the X-axis and Y-axis directions. The trench portions of the transistor portion 70 and the diode portion 80 are configured to extend along the Y-axis direction (i.e., have a long side). Therefore, multiple trench portions extend on the upper surface 21 of the semiconductor substrate 10 in a direction greater than 0 degrees and less than 90 degrees relative to the first direction. This angle can be 15 degrees or more, 30 degrees or more, or 45 degrees or more. Alternatively, it can be 75 degrees or less, 60 degrees or less, or 45 degrees or less. With this configuration, it is possible to suppress foldback while reducing the reverse recovery loss of the diode portion 80.

[0232] Figure 25 This is a diagram illustrating another configuration example of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the annular first lifetime region 204 and the annular second lifetime region 200 are alternately configured in a concentric circle shape. In this example, the width of the second lifetime region 200 extending along the Y-axis direction in the X-axis direction is set to W1, and the width of the second lifetime region 200 extending along the X-axis direction in the Y-axis direction is set to W2.

[0233] A second lifetime region 200 can be disposed inside the first lifetime region 204 of the diode section 80. The second lifetime region 200 can be disposed inside the first lifetime region 204 of the transistor section 70, or it can be omitted. With this configuration, it is possible to suppress foldback while reducing the reverse recovery loss of the diode section 80.

[0234] Figure 26 This is a diagram illustrating another configuration example of the first lifetime region 204 and the second lifetime region 200 in the XY plane. In this example, the Y-axis direction is the first direction, and the X-axis direction is the third direction. That is, in this example, the first lifetime region 204 and the second lifetime region 200 are arranged in the Y-axis direction.

[0235] In this example, the first lifetime region 204 and the second lifetime region 200 have striped-shaped portions with long sides in the X-axis direction (third direction). The two ends of the first lifetime region 204 in the X-axis direction are disposed on the transistor section 70. The two ends of the second lifetime region 200 in the X-axis direction are disposed on the diode section 80 or the boundary between the diode section 80 and the transistor section 70. This configuration also allows for the suppression of foldback while reducing the reverse recovery loss of the diode section 80.

[0236] exist Figures 1 to 26In the examples described, the widths W1 and W2 of the second lifetime region 200 can be 3% or more of the diffusion length of charge carriers in the semiconductor substrate 10. The diffusion length of charge carriers in the semiconductor substrate 10 can, for example, be the diffusion length of charge carriers in a region where lifetime control is not implemented. The region where lifetime control is not implemented can, for example, be a drift region 18 that is not either the first lifetime region 204 or the second lifetime region 200. The diffusion length of charge carriers can be the diffusion length of electrons, the diffusion length of holes, or a bipolar diffusion length. As described above, sometimes when electrons pass through the second lifetime region 200, they combine with lattice defects 202 on both sides of the first lifetime region 204. By making the widths W1 and W2 of the second lifetime region 200 a predetermined ratio or more relative to the electron diffusion length, it is possible to suppress the combination of electrons with lattice defects 202.

[0237] Electron diffusion length L n It is given by equation (2).

[0238] L n =(D n τ n ) 0.5 ··· (2)

[0239] Among them, D n The electron diffusion coefficient (cm) 2 / s), τ n The lifetime of an electron (s).

[0240] Diffusion coefficient D n It is given by equation (3).

[0241] D n =(k B Tμ n ) / q··· (3)

[0242] Where, k B Boltzmann constant (1.38 × 10⁻⁶) -23 (J / K)), T is temperature (K), μ n Electron mobility (cm) in semiconductor substrate 10 2 / Vs), q is the elementary charge (1.60×10 -19 (C)). Hole diffusion length L p It is given by equation (4).

[0243] L p =(D p τ p ) 0.5 ··· (4)

[0244] Among them, D pThe diffusion coefficient of holes (cm) 2 / s), τ p The electron lifetime (s). Diffusion coefficient D. p It is given by equation (5).

[0245] D p =(k B Tμ p ) / q··· (5)

[0246] Where, μ p Hole mobility (cm) in semiconductor substrate 10 2 / Vs).

[0247] The bipolar diffusion length is given by equation (6).

[0248] L a =(D a τ HL ) 0.5 ··· (6)

[0249] Among them, D a The bipolar diffusion coefficient (cm) 2 / s), D a =2D n D p / (D n +D p ). τ HL For high injection level lifetime (s), τ HL =τ n +τ p .

[0250] When the semiconductor substrate 10 is a silicon substrate and the temperature T is -40℃, it can be τ n 1×10 -5 (s), μ n 2600 (cm) 2 / Vs), D n It is 52.25 (cm) 2 / s), L n The value is 230 (μm). When the semiconductor substrate 10 is a silicon substrate and the temperature T is -40℃, τ p 1×10 -5 (s), μ p 860 (cm) 2 / Vs), D p It is 17.36 (cm) 2 / s), L p It is 126 (μm). When the semiconductor substrate 10 is a silicon substrate and the temperature T is -40℃, it can be τ. HL2×10 -5 (s), D a It is 26.06 (cm) 2 / s), L a It is 228.3 (μm).

[0251] The widths W1 and W2 of the second lifetime region 200 can be more than 3% or more of the diffusion length of carriers in the semiconductor substrate 10.

[0252] The present invention has been described above using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. As will be clearly understood from the claims, such modifications or improvements can also be included within the technical scope of the present invention.

[0253] It should be noted that the execution order of actions, sequences, steps, stages, etc., in the apparatus, system, program, and method shown in the claims, specification, and drawings can be implemented in any order, as long as there is no specific indication of "before" or "before," and as long as the output of the previous process is not used in the later process. Even if the flow of actions in the claims, specification, and drawings is described using terms such as "firstly," "next," etc., for convenience, it does not mean that they must be implemented in that order.

Claims

1. A semiconductor device, characterized in that, have: A semiconductor substrate having an upper surface and a lower surface, and having a drift region of a first conductivity type; and A diode portion is disposed on the semiconductor substrate. The diode section has: A base region of the second conductivity type is disposed between the drift region and the upper surface of the semiconductor substrate; A first lifetime region is disposed in the drift region on the lower surface side of the semiconductor substrate, which is closer to the base region than the base region. as well as A second lifetime region is configured to be sandwiched between the first lifetime regions in a first direction parallel to the upper surface of the semiconductor substrate, wherein the carrier lifetime of the second lifetime region is longer than that of the first lifetime region. The width of the second lifetime region in the first direction is greater than the width W shown by equation (1), where the unit of width W is μm. W = 0.21 × T1 + 3.3··· (1) Wherein, T1 is the thickness of the first lifetime region in the second direction perpendicular to the upper surface, and the unit of thickness is μm.

2. The semiconductor device according to claim 1, characterized in that, The width of the second lifetime region in the first direction is 7 μm or more.

3. The semiconductor device according to claim 1, characterized in that, The width of the second lifetime region in the first direction is less than 12 μm.

4. The semiconductor device according to claim 1, characterized in that, The diode section has one or more second lifetime regions. The sum of the widths of one or more second lifetime regions in the first direction is less than 0.1 times the width of the diode portion in the first direction.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that, It also includes a transistor section disposed on the semiconductor substrate and arranged in a manner aligned with the diode section in the first direction.

6. The semiconductor device according to claim 5, characterized in that, The diode portion and the transistor portion have a plurality of trench portions arranged at intervals in the first direction.

7. The semiconductor device according to any one of claims 1 to 4, characterized in that, It also includes a transistor portion disposed on the semiconductor substrate and arranged in a third direction parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction, along with the diode portion.

8. The semiconductor device according to claim 7, characterized in that, The diode portion and the transistor portion have a plurality of trench portions arranged at intervals in the third direction.

9. The semiconductor device according to claim 6, characterized in that, At least a portion of the trench portion of the diode is disposed above the first lifetime region. In the first direction, the distance between the second lifetime region and the transistor portion is greater than or equal to the distance between the lower end of the trench portion and the first lifetime region in the second direction.

10. The semiconductor device according to any one of claims 1 to 4, characterized in that, The diode section has two or more second lifetime regions arranged at intervals in the first direction.

11. The semiconductor device according to any one of claims 1 to 4, characterized in that, The second lifetime region is also sandwiched between the first lifetime regions in a third direction that is parallel to the upper surface of the semiconductor substrate and perpendicular to the first direction.

12. The semiconductor device according to claim 11, characterized in that, The width of the second lifetime region in the third direction is more than 0.2 times the thickness of the first lifetime region in the second direction.

13. The semiconductor device according to any one of claims 1 to 4, characterized in that, The width of the second lifetime region in the first direction is more than 3% of the diffusion length of charge carriers in the semiconductor substrate.

14. The semiconductor device according to any one of claims 1 to 3, characterized in that, The thickness of the first lifetime region in the second direction is less than the thickness of the drift region in the second direction.

15. The semiconductor device according to any one of claims 1 to 4, characterized in that, The width of the second lifetime region in the first direction is more than 0.2 times the thickness of the first lifetime region in the second direction perpendicular to the upper surface of the semiconductor substrate.

16. The semiconductor device according to claim 6, characterized in that, The width of the first life zone is greater than the width of the platform sandwiched between adjacent groove portions.

17. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first lifetime region contains hydrogen.

18. The semiconductor device according to any one of claims 1 to 4, characterized in that, The first lifetime region contains helium.

19. The semiconductor device according to claim 5, characterized in that, The first lifetime region is disposed in the diode portion and the transistor portion. The ratio of the area of ​​the second lifetime region surrounded by the first lifetime region in the transistor portion to the area of ​​the first lifetime region is less than the ratio of the area of ​​the second lifetime region surrounded by the first lifetime region in the diode portion to the area of ​​the first lifetime region.

20. The semiconductor device according to claim 5, characterized in that, A second lifetime region is provided inside the first lifetime region of the diode portion. The second lifetime region is not provided inside the first lifetime region of the transistor portion.

21. The semiconductor device according to any one of claims 1 to 4, characterized in that, It has a plurality of trench portions extending on the upper surface of the semiconductor substrate in a direction greater than 0 degrees and less than 90 degrees relative to the first direction.

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