Substrates and electronic devices

Abstract

A substrate includes a device region and at least one binding region, the binding region is adjacent to any edge of the substrate relative to the device region. The substrate includes a substrate, a plurality of device groups, a plurality of signal line groups and a plurality of bridges. The plurality of device groups are arranged along a first direction and a second direction respectively. The first direction and the second direction are intersected, and the first direction and the second direction are parallel to the substrate. One device group includes at least one electronic element. One signal line group includes a plurality of signal lines, the plurality of signal lines all extend along the second direction, and the plurality of signal lines are arranged spaced apart along the first direction. The bridge includes a conductive portion. At least two signal lines in at least one signal line group are electrically connected by the conductive portion. And / or, at least one signal line in at least one signal line group includes at least two sub-portions arranged spaced apart along the second direction, and adjacent two sub-portions in the same signal line are electrically connected by the conductive portion. At least part of the area of any bridge away from the side of the substrate can reflect light.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a substrate and an electronic device. Background Technology

[0002] A substrate typically includes electronic components and signal lines, with the signal lines electrically connected to the electronic components to enable signal transmission. Summary of the Invention

[0003] On one hand, a substrate is provided. The substrate has multiple edges. The substrate includes a device region and at least one bonding region, the bonding region being adjacent to any edge of the substrate relative to the device region. The substrate includes a substrate, multiple device groups, multiple signal line groups, and multiple bridging portions. The multiple device groups are located on one side of the substrate and are located in the device region. The multiple device groups are arranged along a first direction and a second direction, respectively. The first and second directions intersect and are parallel to the substrate. Each device group includes at least one electronic component. The multiple signal line groups are located on the same side of the substrate as the multiple device groups. Each signal line group includes multiple signal lines. The multiple signal lines all extend along the second direction and are spaced apart along the first direction. Any signal line extends from the bonding region to the device region and is electrically connected to a column of device groups arranged along the second direction. The multiple bridging portions are located on the same side of the substrate as the multiple device groups, and at least one bridging portion is located in the device region. The bridging portion includes a conductive portion. At least two signal lines in at least one signal line group are electrically connected through the conductive portion. And / or, at least one signal line in at least one group of signal lines includes at least two sub-sections spaced apart along a second direction, with adjacent sub-sections of the same signal line electrically connected by a conductive portion. At least a portion of any bridging portion on the side away from the substrate may reflect light.

[0004] In some embodiments, at least a portion of the conductive portion on the surface away from the substrate can reflect light.

[0005] In some embodiments, the bridging portion further includes a first encapsulation portion that covers the conductive portion. The material of the first encapsulation portion includes at least one of a light-transmitting material and a reflective material.

[0006] In some embodiments, the bridging portion further includes a first encapsulation portion that covers the conductive portion. At least a portion of the surface of the first encapsulation portion away from the substrate can reflect light.

[0007] In some embodiments, the conductive portion includes a main body and two connecting portions. The two connecting portions are respectively connected to both ends of the main body. The maximum distance between the surface of the main body facing the substrate and the substrate is greater than the maximum distance between the surface of either connecting portion facing the substrate and the substrate.

[0008] In some embodiments, the orthographic projection of the main body onto the substrate is a first rectangle, the length of which ranges from 0.5 mm to 25 mm, and the width of which ranges from 0.2 mm to 3 mm. And / or, the orthographic projection of any connecting portion onto the substrate is a second rectangle, the length of which ranges from 0.2 mm to 3 mm, and the width of which ranges from 0.2 mm to 3 mm.

[0009] In some embodiments, the maximum distance between the surface of the main body facing the substrate and the surface of the connecting portion facing the substrate is a first distance, the value of which ranges from 0.1 mm to 0.8 mm. And / or, the maximum distance between the surface of the main body away from the substrate and the surface of the connecting portion facing the substrate is a second distance, the value of which ranges from 0.2 mm to 1 mm.

[0010] In some embodiments, the substrate further includes a first reflective layer. The first reflective layer is located on the side of the plurality of device groups, the plurality of signal line groups, and the plurality of bridging portions away from the substrate. The first reflective layer has a plurality of first functional regions. The orthographic projection of the bridging portions onto the substrate is located within the range of the orthographic projection of the first functional regions onto the substrate. The first reflective layer has a plurality of first linear slots, any one of which penetrates the first reflective layer in a direction perpendicular to the substrate. The first functional regions are enclosed by a plurality of mutually spaced first linear slots.

[0011] In some embodiments, the ratio of the area of ​​the orthographic projection of any bridging portion onto the substrate to the area of ​​the first functional region where the orthographic projection of the bridging portion onto the substrate is located ranges from 0.5 to 2.

[0012] In some embodiments, the length of the first linear slit ranges from 1 mm to 5 mm, and the width of the first linear slit ranges from 50 μm to 300 μm.

[0013] In some embodiments, the first reflective layer has a plurality of second linear slits, any one of which penetrates the first reflective layer in a direction perpendicular to the substrate, and any one of the second linear slits is located in the first functional region. The orthographic projection of the edge of the second linear slit onto the substrate at least partially overlaps with the orthographic projection of the bridging portion onto the substrate.

[0014] In some embodiments, the ratio of the length of the second linear slit to the length of the longest side of the bridging portion ranges from 0.9 to 1.5.

[0015] In some embodiments, the length of the second linear slit ranges from 1 mm to 35 mm, and the width of the second linear slit ranges from 50 μm to 300 μm.

[0016] In some embodiments, the electronic component includes an optical component, and the substrate further includes a second encapsulation portion that covers the optical component, and the material of the second encapsulation portion is a light-transmitting material. A first reflective layer has a first through-hole, and the orthographic projection of the optical component onto the substrate is located within the area enclosed by the orthographic projection of the edge of the first through-hole onto the substrate.

[0017] In some embodiments, the electronic component includes a non-optical component, and the substrate further includes a third encapsulation portion covering the non-optical component, and a first reflective layer covering the third encapsulation portion.

[0018] In some embodiments, the first reflective layer has a second functional region, and at least a portion of the orthographic projection of a non-optical element onto the substrate is located in the second functional region. The first reflective layer has a plurality of third linear slits, any one of which penetrates the first reflective layer in a direction perpendicular to the substrate, and any one of the third linear slits is located in the second functional region. The orthographic projection of the edge of the third linear slit onto the substrate overlaps with at least a portion of the orthographic projection of the non-optical element onto the substrate.

[0019] In some embodiments, at least two third linear slots are located in the same second functional area, and the edges of the at least two third linear slots located in the same second functional area are arranged in an X-shape on the substrate.

[0020] In some embodiments, the two third linear slots are located within the same second functional area. The ratio of the length of the third linear slot to the maximum size of the non-optical element ranges from 0.9 to 2.5. And / or, the ratio of the length of the third linear slot to the maximum size of the third package portion ranges from 0.9 to 2.5.

[0021] In some embodiments, the conductive part is a chip resistor or conductive adhesive.

[0022] On the other hand, an electronic device is provided. The electronic device includes a substrate as described above. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this disclosure, the accompanying drawings used in some embodiments of this disclosure will be briefly described below. Obviously, the drawings described below are only drawings of some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams and are not intended to limit the actual size of the product, the actual flow of the method, the actual timing of the signals, etc. involved in the embodiments of this disclosure.

[0024] Figure 1A This is a structural diagram of an electronic device according to some embodiments; Figure 1BThis is a structural diagram of an electronic device according to some other embodiments; Figure 2A This is a structural diagram of a substrate according to some embodiments; Figure 2B This is a structural diagram of a substrate according to some other embodiments; Figure 2C This is a structural diagram of a device group according to some embodiments; Figure 2D This is a structural diagram of a driver chip and device group according to some embodiments; Figure 2E This is a structural diagram of the driver chip and device group according to some other embodiments; Figure 3A This is a structural diagram of a substrate according to some other embodiments; Figure 3B This is a structural diagram of a substrate according to some other embodiments; Figure 4A This is a structural diagram of a substrate according to some other embodiments; Figure 4B This is a structural diagram of a substrate according to some other embodiments; Figure 4C This is a partial structural diagram of a substrate according to some embodiments; Figure 4D This is a partial structural diagram of a substrate according to some other embodiments; Figure 4E for Figure 4D A magnified view of a portion of the Q3 region; Figure 5A This is a diagram showing the positional relationship between a first trace segment and a second reflective layer according to some embodiments; Figure 5B for Figure 5A A cross-sectional view along the AA direction; Figure 5C This is a diagram showing the positional relationship between the first trace segment and the second reflective layer according to some other embodiments; Figure 5D for Figure 5C A cross-sectional view along the BB direction; Figure 6A This is a structural diagram of a substrate according to some other embodiments; Figure 6B This is a structural diagram of a substrate according to some other embodiments; Figure 6C This is a structural diagram of the bridging portion according to some embodiments; Figure 6D This is a partial structural diagram of a substrate according to some other embodiments; Figure 6E This is a partial structural diagram of a substrate according to some other embodiments; Figure 6F This is a structural diagram of a substrate according to some other embodiments; Figure 6G This is a structural diagram of a substrate according to some other embodiments; Figure 7A for Figure 6F A sectional view along the C1-C1 direction; Figure 7B for Figure 6F Another sectional view along the C1-C1 direction; Figure 7C for Figure 6F Another sectional view along the C1-C1 direction; Figure 7D for Figure 6F Another sectional view along the C1-C1 direction; Figure 7E This is a structural diagram of a substrate according to some other embodiments; Figure 8A This is a structural diagram of a substrate according to some other embodiments; Figure 8B This is a structural diagram of the conductive part according to some embodiments; Figure 8C This is a structural diagram of the conductive portion according to some other embodiments; Figure 8D This is a structural diagram of the conductive part according to some other embodiments; Figure 9A for Figure 6G A sectional view along the C2-C2 direction; Figure 9B for Figure 6G Another sectional view along the C2-C2 direction; Figure 9C for Figure 6G Another sectional view along the C2-C2 direction; Figure 9D This is a structural diagram of a substrate according to some other embodiments; Figure 9E for Figure 9D A sectional view along the D1-D1 direction; Figure 9F for Figure 9D A sectional view along the D2-D2 direction; Figure 9G This is a structural diagram of a substrate according to some other embodiments. Detailed Implementation

[0025] The technical solutions in some embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments provided in this disclosure are within the scope of protection of this disclosure.

[0026] Unless the context otherwise requires, throughout the specification and claims, the term "comprise" and its other forms, such as the third-person singular "comprises" and the present participle "comprising," are interpreted as open-ended and encompassing, meaning "including, but not limited to." In the description of the specification, terms such as "one embodiment," "some embodiments," "exemplary embodiments," "example," "specific example," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with that embodiment or example is included in at least one embodiment or example of this disclosure. The illustrative representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics mentioned may be included in any suitable manner in any one or more embodiments or examples.

[0027] Hereinafter, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of embodiments of this disclosure, unless otherwise stated, "a plurality of" means two or more.

[0028] In describing some embodiments, the terms "connection" and their derivatives may be used. For example, the term "connection" may be used in describing some embodiments to indicate that two or more components are in direct physical or electrical contact with each other.

[0029] "At least one of A, B and C" has the same meaning as "at least one of A, B or C", both including the following combinations of A, B and C: only A, only B, only C, combinations of A and B, combinations of A and C, combinations of B and C, and combinations of A, B and C.

[0030] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0031] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the average value within an acceptable range of deviation from the given value, wherein the acceptable range of deviation is determined by a person skilled in the art taking into account the measurement under discussion and the error associated with the measurement of the given quantity (i.e., the limitations of the measurement system).

[0032] As used herein, “parallel,” “perpendicular,” and “equal” include the described situation and situations that are similar to the described situation, within an acceptable deviation range, which is determined by those skilled in the art taking into account the measurement under discussion and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, “parallel” includes absolute parallelism and approximate parallelism, where an acceptable deviation range for approximate parallelism may be, for example, within 5°; “perpendicular” includes absolute perpendicularity and approximate perpendicularity, where an acceptable deviation range for approximate perpendicularity may also be, for example, within 5°; “equal” includes absolute equality and approximate equality, where an acceptable deviation range for approximate equality may be, for example, a difference between the two equals being less than or equal to 5% of either one.

[0033] It should be understood that when a layer or element is referred to as being on another layer or substrate, it can mean that the layer or element is directly on the other layer or substrate, or that there is an intermediate layer between the layer or element and the other layer or substrate.

[0034] This document describes exemplary embodiments with reference to cross-sectional views and / or plan views, which are idealized exemplary drawings. In the drawings, the thickness of layers and regions is enlarged for clarity. Therefore, variations in shape relative to the drawings are contemplated due to, for example, manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing processes. For example, etched regions shown as rectangular would typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to show the actual shapes of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

[0035] Figure 1A This is a structural diagram of an electronic device according to some embodiments.

[0036] like Figure 1A As shown, embodiments of this disclosure provide an electronic device 200. In some examples, the electronic device 200 may be a product with image display capabilities. For example, the electronic device 200 may be used to display static images, such as pictures or photographs. The electronic device 200 may also be used to display dynamic images, such as videos or game footage.

[0037] In some examples, electronic device 200 may be a laptop computer, mobile phone, wireless device, personal data assistant (PDA), handheld or portable computer, GPS receiver / navigator, camera, MP4 video player, camcorder, game console, watch, clock, calculator, television monitor, flat panel display, computer monitor, automotive display (e.g., odometer display, etc.), navigator, cockpit controller and / or display, display of camera view (e.g., display of a rearview camera in a vehicle), electronic photograph, electronic billboard or sign, projector, packaging and aesthetic structure (e.g., display of an image of a piece of jewelry), etc.

[0038] In other examples, electronic device 200 may also be a product that does not have image display capabilities.

[0039] The embodiments disclosed herein do not further limit the electronic device 200. The following example illustrates the electronic device 200 as a product with image display function.

[0040] Figure 1B This is a structural diagram of an electronic device according to some other embodiments.

[0041] like Figure 1B As shown, in some embodiments, the electronic device 200 may include a substrate 100 and a display panel 210. For example, the substrate 100 is used to emit light outward, and the display panel 210 is located on the light-emitting side of the substrate 100 and is used to display image information.

[0042] In some examples, the display panel 210 is a liquid crystal display panel, and the substrate 100 is used to provide backlight to the display panel 210.

[0043] In some examples, substrate 100 can be used to emit white or blue light. Display panel 210 can filter or convert the light emitted by substrate 100 to obtain red, green, and blue light, enabling electronic device 200 to display full-color images.

[0044] The following description uses display panel 210 as an example of an LCD display panel.

[0045] In some examples, such as Figure 1BAs shown, the display panel 210 includes an array substrate 216, an opposing substrate 214, and a liquid crystal layer 212 located between the array substrate 216 and the opposing substrate 214. Understandably, light emitted from the substrate 100 can pass through the array substrate 216 and illuminate the liquid crystal layer 212. The liquid crystal layer 212 contains liquid crystal molecules. By controlling the deflection angle of the liquid crystal molecules, the intensity of light passing through the liquid crystal layer 212 and illuminating the opposing substrate 214 can be controlled, thereby enabling the electronic device 200 to perform image display functions.

[0046] In some examples, when substrate 100 is used to emit white light, the opposing substrate 214 may include a red filter film, a green filter film, and a blue filter film. By controlling the intensity of light irradiated onto the red filter film, the green filter film, and the blue filter film, different intensities of red light, green light, and blue light can be obtained, enabling the electronic device 200 to display color images.

[0047] In other examples, when substrate 100 is used to emit blue light, the opposing substrate 214 may include a color conversion film. For example, the color conversion film may be a quantum dot film. Blue light irradiated by a red quantum dot film can be converted into red light. Blue light irradiated by a green quantum dot film can be converted into green light. The resulting red and green light from the quantum dot film, mixed with the blue light emitted by substrate 100, enables the electronic device 200 to achieve full-color graphic display.

[0048] In some other examples, when substrate 100 is used to emit blue light, the opposing substrate 214 may not include the quantum dot film, while substrate 100 may include the quantum dot film. For example, the quantum dot film may be disposed on the side of substrate 100 away from substrate 101 where the light-emitting device (e.g., electronic component 120) is located. In some examples, display panel 210 includes a common electrode and a plurality of pixel electrodes. An electric field can be formed between the common electrode and each pixel electrode. By controlling the voltage value of each pixel electrode, the strength of the electric field formed between the common electrode and each pixel electrode can be controlled, thereby controlling the deflection angle of the liquid crystal molecules in liquid crystal layer 212, that is, controlling the intensity of light passing through liquid crystal layer 212.

[0049] In some examples, pixel electrodes may be disposed on array substrate 216. Common electrodes may be disposed on array substrate 216 or opposing substrate 214.

[0050] Figure 2A This is a structural diagram of a substrate according to some embodiments. Figure 2B This is a structural diagram of a substrate according to some other embodiments. Figure 2C This is a structural diagram of a device group according to some embodiments. Figure 2D This is a structural diagram of a driver chip and device group according to some embodiments. Figure 2E This is a structural diagram of a driver chip and device assembly according to some other embodiments. Referring below... Figures 2A-2E The substrate 100 will be illustrated with an example.

[0051] In some embodiments, such as Figure 2A and Figure 2B As shown, the substrate 100 has multiple edges P. Understandably, the edges P of the substrate 100 can be straight segments or curved segments. In some examples, such as... Figure 2A and Figure 2B As shown, the substrate 100 can be square or rectangular, that is, the substrate 100 can have four edges P.

[0052] In other examples, the substrate 100 may also be polygonal or other irregular shapes. The embodiments of this disclosure do not further limit the shape of the substrate 100 or the number of edges P that the substrate 100 has.

[0053] like Figure 2A and Figure 2B As shown, the substrate 100 includes a device region AA and at least one bonding region BB, with the bonding region BB being close to any edge P of the substrate 100 relative to the device region AA.

[0054] Understandably, the bonding region BB is adjacent to the edge of the device region AA near the bonding region BB. It should be noted that in the accompanying drawings of this disclosure, [the following text is incomplete and requires further context to translate accurately]. Figure 2A and Figure 2B For example, the edge of the device area AA and the edge of the bonding area BB are set apart from each other in the dashed box, just to clearly distinguish the device area AA and the bonding area BB, without further limiting the edge positions of the device area AA and the bonding area BB.

[0055] The bonding region BB is located relative to any edge P of the device region AA near the substrate 100. That is, the bonding region BB can be located between the device region AA and any edge P.

[0056] In some examples, such as Figure 2A and Figure 2B As shown, the bonding region BB is located on one side of the device region AA along the second direction Y. For example, the second direction Y can be a vertical direction.

[0057] In some examples, such as Figure 2A As shown, the number of bound zones (BBs) can be one. In other examples, such as... Figure 2B As shown, the number of bound areas (BBs) can also be multiple. For example, there can be two, three, or four bound areas (BBs).

[0058] Understandably, such as Figure 2BAs shown, when there are multiple bonding areas BB, the multiple bonding areas BB are located on the same side of the device area AA, that is, the multiple bonding areas BB are all set on the same edge P.

[0059] In some examples, such as Figure 2B As shown, when there are multiple binding areas (BBs), these BBs can be spaced apart along a first direction X. For example, the first direction X can be horizontal, and it can be perpendicular to the second direction Y. Understandably, the multiple binding areas (BBs) can be spaced at the same distance, or the spacing between any two adjacent binding areas (BBs) can be different.

[0060] like Figure 2A and Figure 2B As shown, the substrate 100 includes a substrate 101 and a plurality of device groups 110. The plurality of device groups 110 are located on one side of the substrate 101 and are located in device region AA. The plurality of device groups 110 are arranged along a first direction X and a second direction Y, respectively, the first direction X and the second direction Y intersecting each other and being parallel to the substrate 101. Each device group 110 includes at least one electronic component 120.

[0061] In some examples, substrate 101 is a rigid substrate. In other examples, substrate 101 is a flexible substrate. For example, the material of substrate 101 includes any one of plastic, FR-4 grade material, resin, glass, quartz, polyimide (PI), or polymethyl methacrylate (PMMA).

[0062] Understandably, multiple device groups 110 are located on the same side of substrate 101 and within device region AA. In some examples, the multiple device groups 110 are spaced apart along a first direction X, and the spacing between adjacent device groups 110 is the same or approximately the same along the first direction X. The multiple device groups 110 are spaced apart along a second direction Y, and the spacing between adjacent device groups 110 is the same or approximately the same along the second direction Y. Thus, as... Figure 2A and Figure 2B As shown, multiple device groups 110 can be arranged in rows along the first direction X and in columns along the second direction Y. Understandably, the multiple rows of device groups 110 are spaced apart along the second direction Y, and the multiple columns of device groups 110 are spaced apart along the first direction X.

[0063] It should be noted that, in order to clearly show the structure of the substrate 100 in the accompanying drawings of this disclosure, only the four-row, three-column device group 110 is shown (e.g., Figure 2A), or it shows a four-row, six-column device group 110 (e.g. Figure 2B The present disclosure does not impose further limitations on the number and arrangement of device groups 110 in the embodiments thereof.

[0064] Understandably, a device group 110 may include one electronic component 120 or multiple electronic components 120.

[0065] In some examples, when a device group 110 includes multiple electronic components 120, the multiple electronic components 120 can be components of the same type or components of different types. For example, when the substrate 100 is used to emit light, the electronic components 120 can be light-emitting devices. The multiple light-emitting devices included in a device group 110 can be used to emit light of the same color, or the multiple light-emitting devices included in a device group 110 can be used to emit light of multiple different colors. Alternatively, among the multiple electronic components 120 included in a device group 110, some (one or more) are light-emitting devices for emitting light, while others (one or more) are other components (such as sensor chips) to perform other functions.

[0066] In some examples, such as Figure 2A and Figure 2B As shown, a device group 110 may include six electronic components 120. In other examples, such as Figure 2C As shown, a device group 110 may also include four electronic components 120. In other examples, a device group 110 may also include two, three, or five electronic components 120. It is understood that the number of electronic components 120 included in different device groups 110 may be the same or different. The embodiments of this disclosure do not further limit the number of electronic components 120 in a device group 110.

[0067] In some examples, such as Figure 2C As shown, when a device group 110 includes four electronic components 120, the distance between two adjacent electronic components 120 along the first direction X is approximately 13.775 mm.

[0068] In some examples, such as Figure 2A and Figure 2B As shown, when a device group 110 includes multiple electronic components 120, the multiple electronic components 120 can be arranged in a matrix form. That is, the multiple electronic components 120 can be arranged at the four vertices of a rectangle or square, which improves the regularity of the arrangement of the multiple electronic components 120.

[0069] In other examples, when a device group 110 includes multiple electronic components 120, the multiple electronic components 120 in a device group 110 can also be arranged at the vertices of a hexagon, octagon, or other irregular shapes. Alternatively, the multiple electronic components 120 in a device group 110 can also be arranged in a circle or ellipse, etc., to meet different usage requirements.

[0070] In some examples, such as Figure 2C As shown, multiple electronic components 120 in device group 110 are electrically connected via connecting lines 112. For example, there are multiple connecting lines 112, and the multiple electronic components 120 in a device group 110 can be connected in series via multiple connecting lines 112. In this way, providing an electrical signal to any one electronic component 120 in a device group 110 can provide electrical signals to all electronic components 120 in the device group 110, improving the wiring convenience of the substrate 100.

[0071] As described above, in some examples, substrate 100 can be used to provide a light source. In this case, electronic component 120 can be a light-emitting device. For example, electronic component 120 can be a light-emitting diode (LED).

[0072] In some examples, electronic component 120 can be any of a conventional LED, a mini LED, or a micro LED.

[0073] For example, a conventional LED is an LED with a size greater than or equal to 500 μm. A Mini LED is an LED with a size greater than or equal to 100 μm and less than 500 μm. A Micro LED is an LED with a size less than 100 μm. In some examples, the size of a Micro LED can be less than or equal to 50 μm.

[0074] In some examples, the electronic components 120 in each device group 110 can be used to emit light of the same color, for example, the electronic components 120 in each device group 110 can all be used to emit white light, or the electronic components 120 in each device group 110 can all be used to emit blue light, so that the substrate 100 can emit light of a specific color.

[0075] In some examples, the luminous intensity of each electronic component 120 in a device group 110 is the same. The luminous intensity of the electronic components 120 in different device groups 110 can be the same or different. By controlling the luminous intensity of the electronic components 120 in different device groups 110, the brightness of different areas of the substrate 100 can be controlled to meet different application requirements.

[0076] As described above, in some embodiments, the electronic device 200 includes a substrate 100 and a display panel 210, in which case the substrate 100 can be used to provide a light source. In other embodiments, the electronic device 200 may not include the display panel 210, but only the substrate 100. In this case, the substrate 100 is used to display image information, and the electronic components 120 in each device group 110 can emit light of different colors.

[0077] For example, when the substrate 100 is used to display image information, some (one or more) of the various device groups 110 emit red light, another group of device groups 110 emits green light, and yet another group of device groups 110 emits blue light. By controlling the light emission intensity of the electronic components 120 in different device groups 110, different intensities of red, green, and blue light can be obtained, enabling the electronic device 200 to achieve full-color image display.

[0078] The embodiments disclosed herein are illustrated by taking the substrate 100 as an example of a light source providing component for an electronic device 200.

[0079] In some examples, such as Figure 2A and Figure 2B As shown, the substrate 100 also includes a plurality of signal line groups 130. The plurality of signal line groups 130 and the plurality of device groups 110 are located on the same side of the substrate 101. Each signal line group 130 includes a plurality of signal lines 131. The plurality of signal lines 131 extend along a second direction Y, and are spaced apart along a first direction X. Any signal line 131 extends from the bonding region BB to the device region AA, and any signal line 131 is electrically connected to a row of device groups 110 arranged along the second direction Y.

[0080] It is understandable that the lengths of the multiple signal lines 131 are not exactly the same. The length of some signal lines 131 along the second direction Y is approximately equal to the length of a group of devices 110 along the second direction Y, while the length of other signal lines along the second direction Y is less than the length of a group of devices along the second direction Y.

[0081] Understandably, multiple signal line groups 130 and multiple device groups 110 are located on the same side of substrate 101, such that signal lines 131 in signal line group 130 can be electrically connected to device group 110.

[0082] In some examples, multiple signal line groups 130 are arranged on the same layer, that is, multiple signal line groups 130 are arranged on the same conductive layer. Understandably, in addition to multiple signal line groups 130, other traces (such as connecting lines 112) can also be arranged on the conductive layer.

[0083] In other examples, the signal lines 131 in the multiple signal line groups 130 can be disposed on different conductive layers. For example, the signal lines 131 in the multiple signal line groups 130 can be disposed on two conductive layers respectively.

[0084] Understandably, multiple signal line groups 130 are disposed on different conductive layers, which increases the routing flexibility of the signal lines 131. However, if the orthographic projections of two signal lines 131 located on different conductive layers overlap on the substrate 101, a short circuit is likely to occur, affecting the yield of the substrate 100. Furthermore, since the substrate 100 includes at least two conductive layers, it also increases the number of fabrication steps for the substrate 100, thereby increasing the production cost of the substrate 100.

[0085] Understandably, the arrangement of multiple signal line groups 130 on the same layer can reduce the steps of patterning the conductive layer, thereby simplifying the fabrication process of the substrate 100, reducing the number of masks, lowering the cost of the substrate 100, and also reducing the occurrence of defects such as short circuits in the substrate 100, thus improving the yield of the substrate 100.

[0086] The embodiments of this disclosure are illustrated by taking the arrangement of multiple signal line groups 130 on the same layer as an example.

[0087] like Figure 2A As shown, a signal line group 130 includes multiple signal lines 131. Understandably, the signal lines 131 are used to transmit signals, such as analog or digital electrical signals. In some examples, multiple signal line groups 130 can be used to transmit different signals or the same signal. Each signal line 131 in a signal line group 130 is used to transmit the same signal.

[0088] In some examples, signal line 131 is made of metal or a metal alloy. For example, the material of signal line 131 may include copper or aluminum to improve the conductivity of signal line 131.

[0089] In some examples, the number of signal lines 131 included in each signal line group 130 may be the same or different. The spacing between any two adjacent signal lines 131 in a signal line group 130 along the first direction X may be the same or different.

[0090] In some examples, the bonding area BB is provided with bonding pins (not shown in the figure). There can be multiple bonding pins, which are spaced apart along the first direction X. The signal line 131 is electrically connected to the bonding pins in the bonding area BB.

[0091] For example, such as Figure 2A and Figure 2B As shown, one end of any signal line 131 is electrically connected to a bonding pin in the bonding area BB, and the other end extends along the second direction Y (or along the first direction X and the second direction Y) to extend from the bonding area BB to the device area AA, and is electrically connected to a column of device groups 110 arranged along the second direction Y. It can be understood that the signal line 131 can be directly electrically connected to the electronic components 120 in the device group 110, or it can be electrically connected to the electronic components 120 in the device group 110 through other components or conductive patterns.

[0092] In some examples, at least one signal line 131 is disposed between two rows of device groups 110 spaced apart along a first direction X to improve the area utilization of the substrate 101.

[0093] In some examples, such as Figure 2A As shown, there is one bonding area BB, and multiple bonding pins are provided within one bonding area BB. For example, different signal line groups 130 are electrically connected to different bonding pins to reduce mutual interference during signal transmission. Multiple signal lines 131 in the same signal line group 130 can be electrically connected to one bonding pin or multiple bonding pins.

[0094] In some examples, when there is one bonding area BB, the number of signal lines 131 in a signal line group 130 is the same as the number of columns formed by the device group 110. That is, as... Figure 2A As shown, when multiple device groups 110 are arranged in three columns along the second direction Y, a signal line group 130 includes three signal lines 131. Understandably, the three signal lines 131 in a signal line group 130 can be electrically connected to three bonded pins or to one bonded pin.

[0095] In other examples, such as Figure 2B As shown, there are multiple binding areas BB. Multiple signal lines 131 in a signal line group 130 are electrically connected to one of the multiple binding areas BB.

[0096] For example, such as Figure 2BAs shown, signal line group 130 includes a first signal line group 130a, a second signal line group 130b, and a third signal line group 130c. The first signal line group 130a includes a first signal line 131a, the second signal line group 130b includes a second signal line 131b, and the third signal line group 130c includes a third signal line 131c.

[0097] It should be noted that the first signal line group 130a, the second signal line group 130b, and the third signal line group 130c are only used to distinguish the three signal line groups 130 that are connected to different bonding areas BB, and do not further limit the signal line groups 130. The first signal line 131a, the second signal line 131b, and the third signal line group 130c are only used to distinguish the signal line 131 in the first signal line group 130a, the second signal line group 130b, and the third signal line group 130c, and do not further limit the signal line 131.

[0098] In some examples, the first signal line group 130a, the second signal line group 130b, and the third signal line group 130c are used to transmit the same signal.

[0099] For example, such as Figure 2B As shown, the binding area BB includes the first binding area BB1, the second binding area BB2, and the third binding area BB3. It should be noted that the first binding area BB1, the second binding area BB2, and the third binding area BB3 are only used to distinguish three different binding areas BB, and do not further limit the binding areas BB.

[0100] For example, such as Figure 2B As shown, multiple first signal lines 131a in the first signal line group 130a are electrically connected to the bonding pins in the first bonding area BB1. Multiple second signal lines 131b in the second signal line group 130b are electrically connected to the bonding pins in the second bonding area BB2. A third signal line 131c in the third signal line group 130c is electrically connected to the bonding pins in the third bonding area BB3. In this way, multiple signal lines 131a in one signal line group 130 can be electrically connected to one of the multiple bonding areas BB.

[0101] This configuration allows different bonding areas BB to transmit signals to different signal line groups 130, reducing mutual interference during signal transmission and improving the reliability of the substrate 100.

[0102] In some examples, such as Figure 2BAs shown, a signal line 131 (e.g., first signal line 131a) in a signal line group 130 (e.g., first signal line group 130a) is electrically connected to a bonding pin in a bonding area BB (e.g., first bonding area BB1) near the signal line group 130. This reduces the length of the signal line 131, lowers the voltage drop of the signal line 131, and improves the reliability of signal transmission. Furthermore, it also reduces the amount of material used in the signal line 131, thereby reducing the cost of the substrate 100.

[0103] In some examples, such as Figure 2A As shown, the substrate 100 also includes a first driver chip 103. The first driver chip 103 is electrically connected to at least one device group 110. That is, in some examples, such as Figure 2D As shown, the first driver chip 103 is electrically connected to only one device group 110. In other examples, such as Figure 2E As shown, the first driving chip 103 is electrically connected to a plurality of (e.g., four) device groups 110 arranged sequentially along the second direction Y.

[0104] Understandably, a signal line 131 may be electrically connected to the first driver chip 103, or to a device group 110 or multiple device groups 110.

[0105] In some examples, a plurality of device groups 110 arranged along the second direction Y are electrically connected to a first driver chip 103. In other examples, the plurality of device groups 110 arranged along the second direction Y are electrically connected to a plurality of first driver chips 103 respectively. For example, when the plurality of device groups 110 arranged along the second direction Y are electrically connected to a plurality of first driver chips 103 respectively, the plurality of first driver chips 103 electrically connected to a row of device groups 110 are spaced apart along the second direction Y.

[0106] Figure 3A This is a structural diagram of a substrate according to some other embodiments. Figure 3B This is a structural diagram of a substrate according to some other embodiments.

[0107] As described above, the substrate 100 includes multiple signal line groups 130. Refer to the following... Figure 3A and Figure 3B Let's continue with an example of signal line group 130.

[0108] In some examples, such as Figure 3A and Figure 3B As shown, the plurality of signal line groups 130 include a first voltage line group 150, which includes a plurality of first voltage lines 151. For example, the first voltage lines 151 are used to power electronic components 120 in various device groups 110.

[0109] For example, such as Figure 3A and Figure 3B As shown, one end of the first voltage line 151 is electrically connected to the bonding pin in the bonding area BB, and the other end extends to the device area AA and is electrically connected to a column of devices 110 arranged along the second direction Y. That is, the column of devices 110 arranged along the second direction Y shares a first voltage line 151.

[0110] In some examples, such as Figure 3A As shown, the device area AA includes a central area AA1 and an edge area AA2, with the edge area AA2 surrounding the central area AA1. Multiple device groups 110 are located in the central area AA1, and a portion (one or more) of the signal lines 131 may be located only in the edge area AA2, while another portion (one or more) of the signal lines 131 may be located in both the edge area AA2 and the central area AA1.

[0111] For example, such as Figure 3A As shown, the edge region AA2 located between the central region AA1 and the binding region BB along the second direction Y can be defined as the lower edge region AA22; the two edge regions adjacent to the lower edge region AA22 along the second direction Y and located on both sides of the central region AA1 along the first direction X can be defined as the side edge regions AA21. That is, edge region AA2 includes the side edge region AA21 and the lower edge region AA22. For example, the lower edge region AA22 can also be called the fanout region.

[0112] In some examples, such as Figure 3A As shown, a first voltage line 151 in the first voltage line group 150 may be located in the side edge region AA21.

[0113] In some examples, such as Figure 3A As shown, the substrate 100 also includes a circuit board 107, which is electrically connected to the bonding area BB. For example, Figure 3A As shown, circuit board 107 includes a flexible printed circuit board (FPC) 105 and a printed circuit board (PCB) 106. One end of the flexible printed circuit board 105 is bonded to a bonding pin in the bonding area BB, and the other end is bonded to the printed circuit board 106, so that signals can be transmitted between multiple signal line groups 130 and the printed circuit board 106, thereby realizing the driving of multiple device groups 110.

[0114] In some examples, an external power supply to the substrate 100 is electrically connected to a first voltage line 151 via a printed circuit board 106 and bonding pins, enabling the power supply to power electronic components 120 in a group of devices 110 via the first voltage line 151.

[0115] In some examples, such as Figure 3A and Figure 3B As shown, the multiple signal line groups 130 also include a second voltage line group 160, which includes multiple second voltage lines 161. For example, the second voltage line (GND) 161 is used to ground the first driver chip 103.

[0116] In some examples, such as Figure 3A and Figure 3B As shown, one end of the second voltage line 161 is electrically connected to the bonding pin in the bonding area BB, and the other end extends to the device area AA and is electrically connected to the first driver chip 103. As can be seen from the above, the first driver chip 103 is electrically connected to the device group 110, so that the second voltage line 161 can be electrically connected to the device group 110 through the first driver chip 103.

[0117] In some examples, such as Figure 3A As shown, a second voltage line 161 in the second voltage line group 160 may be located in the side edge region AA21.

[0118] In some examples, such as Figure 3A and Figure 3B As shown, the substrate 100 also includes a second driver chip 104. For example, the second driver chip 104 may be disposed on a printed circuit board 106. For example, the second driver chip 104 is a Tx IC (Transmit Integrated Circuit), and the first driver chip 103 is an Rx IC (Receive Integrated Circuit). The signal emitted by the second driver chip 104 is transmitted to the first driver chip 103 through bonding pins and signal line group 130 (e.g., second voltage line group 160), thereby driving the device group 110.

[0119] In some examples, one end of the second voltage line 161 is electrically connected to the ground port of the second driver chip 104 through the bonding pin of the bonding area BB, and the other end is electrically connected to the ground port of the first driver chip 103 to ground the first driver chip 103.

[0120] In some examples, such as Figure 3B As shown, when a column of devices 110 arranged along the second direction Y is electrically connected to a plurality of first driving chips 103, the plurality of first driving chips 103 electrically connected to the same column of devices 110 can share a second voltage line 161.

[0121] In some examples, such as Figure 3A and Figure 3B As shown, the multiple signal line groups 130 also include a power line group 135, which includes multiple power lines 132.

[0122] In some examples, the power line (Pwr) 132 is used to power the first driver chip 103. For example, ... Figure 3A and Figure 3B As shown, one end of the power line 132 is electrically connected to the bonding pin in the bonding area BB, and the other end extends to the device area AA and is electrically connected to the power port of the first driver chip 103. As can be seen from the above, the first driver chip 103 is electrically connected to the device group 110, enabling the power line 132 to be electrically connected to the device group 110 through the first driver chip 103.

[0123] In some examples, such as Figure 3B As shown, when a column of devices 110 arranged along the second direction Y is electrically connected to a plurality of first driving chips 103, the plurality of first driving chips 103 electrically connected to the same column of devices 110 can share a power line 132.

[0124] In some examples, such as Figure 3A As shown, the multiple signal line groups 130 also include a data line group 136, which includes multiple data lines 133.

[0125] In some examples, the Data cable (full name: Data) 133 is used to transmit data signals. For example, such as... Figure 3A As shown, one end of the data line 133 is electrically connected to the bonding pin in the bonding area BB, and the other end extends to the device area AA and is electrically connected to the first driver chip 103. As can be seen from the above, the first driver chip 103 is electrically connected to the device group 110, so that the data line 133 can be electrically connected to the device group 110 through the first driver chip 103.

[0126] In some examples, the second driver chip 104 has a first data port to the Nth data port. One end of a data line 133 is electrically connected to the first data port of the second driver chip 104 via a bonding pin and a printed circuit board 106, and the other end is electrically connected to the data port of one or more first driver chips 103 electrically connected to a column of device groups 110. One end of another data line 133 is electrically connected to the second data port of the second driver chip 104 via a bonding pin and a printed circuit board 106, and the other end is electrically connected to the data port of one or more first driver chips 103 electrically connected to another column of device groups 110, and so on, up to the Nth data port. Understandably, N is a positive integer. In some examples, the value of N is the same as the number of columns of device groups 110 arranged along the second direction Y.

[0127] In some examples, such as Figure 3B As shown, a first driver chip 103 is electrically connected to a device group 110. For example, a plurality of first driver chips 103 electrically connected to a device group 110 include a first first driver chip 103a, a second first driver chip 103b, a third first driver chip 103c, and so on up to the m-th first driver chip 103m. Understandably, the plurality of first driver chips 103 are cascaded.

[0128] It should be noted that the first first driver chip 103a, the second first driver chip 103b, the third first driver chip 103c, and so on up to the mth first driver chip 103m are only used to distinguish the multiple first driver chips 103 that are electrically connected to a column of device groups 110, and do not further limit the first driver chip 103.

[0129] For example, the first driver chip 103a to the m-th driver chip 103m are sequentially moved away from the bonding area BB along the second direction Y. Understandably, m is greater than 3 and m is a positive integer.

[0130] In some examples, such as Figure 3A and Figure 3B As shown, the multiple signal line groups 130 also include input / output line groups 137, which include input / output lines (also called addressing signal lines) 134.

[0131] For example, such as Figure 3B As shown, the first driver chip 103 has an input port Din and an output port Dout. In some examples, such as... Figure 3B As shown, there are multiple input / output lines 134. One end of one input / output line 134 is electrically connected to the input port of the second driver chip 104 via a bonding pin, and the other end is electrically connected to the input port Din of the first driver chip 103a. One end of another input / output line 134 is electrically connected to the output port Dout of the first driver chip 103a, and the other end is electrically connected to the input port Din of the second driver chip 103b. Another input / output line 134 is electrically connected to the output port Dout of the second driver chip 103b, and the other end is electrically connected to the input port Din of the third driver chip 103c, and so on, until the m-th first driver chip 103m that is furthest from the bonding region BB along the second direction Y.

[0132] In some examples, the output terminal Dout of the m-th first driver chip 103m is electrically connected to the bonding pin in the bonding area BB via the input / output line 134. That is, multiple first driver chips 103 (e.g., the first first driver chip 103a to the m-th first driver chip 103m) electrically connected to a group of devices 110 are cascaded via the input / output line 134.

[0133] In this way, the signal output by the second driver chip 104 can be transmitted to multiple first driver chips 103 through the input / output line 134, and then fed back to the second driver chip 104 through the input / output line 134, so that the second driver chip 104 can drive multiple first driver chips 103.

[0134] In some examples, such as Figure 3A As shown, the input / output line 134 surrounds the second voltage line 161 to save wiring space and improve the area utilization of the substrate 101.

[0135] In some examples, such as Figure 3B As shown, the first driver chip 103 includes a logic control module 1031. For example, the logic control module 1031 may include logic circuitry. In some examples, signals on input / output lines 134 can be input to the logic control module 1031 via input port Din. In some examples, signals on power lines 132 can be input to the logic control module 1031 via the power port of the first driver chip 103 (the port connected to power line 132). Understandably, the logic control module 1031 can drive electronic components 120 according to the received signals.

[0136] In some examples, substrate 100 also includes an electrostatic loop 108 (see [reference]). Figure 2A An electrostatic loop 108 is disposed around multiple device groups 110 and electrically connected to a bonding area BB. For example, both ends of the electrostatic loop 108 are electrically connected to bonding pins within the bonding area BB, thereby enabling the electrostatic loop 108 to not only surround multiple device groups 110, but also multiple signal line groups 130 electrically connected to the multiple device groups 110.

[0137] Understandably, the electrostatic loop 108 can release static electricity, thereby protecting the multiple device groups 110 and the multiple signal line groups 130 and improving the reliability of the substrate 100.

[0138] Figure 4A This is a structural diagram of a substrate according to some other embodiments. Figure 4B This is a structural diagram of a substrate according to some other embodiments. Figure 4C This is a partial structural diagram of a substrate according to some embodiments. Figure 4D This is a partial structural diagram of a substrate according to some other embodiments.

[0139] In some examples, such as Figure 4A and Figure 4B As shown, the substrate 100 includes a second reflective layer 194. The second reflective layer 194 is located on the side of the plurality of signal line groups 130 away from the substrate 101 and covers the plurality of signal line groups 130 (that is, covers the plurality of signal lines 131). It can be understood that since the connecting line 112 is disposed in the same layer as the plurality of signal line groups 130, the second reflective layer 194 can also cover the connecting line 112.

[0140] For example, the second reflective layer 194 is an insulating reflective material. On the one hand, the second reflective layer 194 can provide electrical isolation, reducing the risk of short circuits and other malfunctions in the substrate 100. On the other hand, the second reflective layer 194 can reflect light (such as light emitted by the electronic component 120), thereby increasing the brightness of the substrate 100 and reducing the power consumption of the substrate 100.

[0141] In addition, the second reflective layer 194 covers multiple signal line groups 130 and multiple connecting lines 112, which can also protect the multiple signal line groups 130 and multiple connecting lines 112 and extend the service life of the substrate 100.

[0142] In some examples, the material of the second reflective layer 194 includes white ink. For example, the material of the second reflective layer 194 may include at least one of photosensitive white ink and curable white ink.

[0143] In some examples, the second reflective layer 194 has a first solder hole M2 that penetrates the second reflective layer 194 in a direction perpendicular to the substrate 101 to expose a portion of the signal line 131. Examples include... Figure 4A and Figure 4B As shown, the area of ​​signal line 131 exposed by the first solder hole M2 can be called the first solder pad 1312.

[0144] In some examples, a signal line 131 may have multiple first pads 1312. In other examples, a signal line 131 may have only one first pad 1312. In still other examples, a signal line 131 may not have any first pads 1312.

[0145] As described above, the first driver chip 103 can be electrically connected to multiple signal lines 131. In some examples, the first driver chip 103 is located on the side of the signal line 131 away from the substrate 101, and the first driver chip 103 has multiple pins, one pin being soldered to a first pad 1312.

[0146] In some examples, the first driver chip 103 may have four pins, enabling it to be soldered to four first pads 1312. In other examples, the first driver chip 103 may have six, eight, or twelve pins, etc. The embodiments of this disclosure do not further limit the number of pins on the first driver chip 103.

[0147] In some examples, such as Figure 4C and Figure 4D As shown, the input / output line 134 includes an input line 1341 and an output line 1342. The four pins of the first driver chip 103 are respectively soldered to the first pad 1312 on the input line 1341, the first pad 1312 on the output line 1342, the first pad 1312 on the second voltage line 161, and the first pad 1312 on the power line 132.

[0148] In some examples, a first solder hole M2 can expose multiple (e.g., four) first pads 1312 soldered to the first driver chip 103. In other examples, multiple (e.g., four) first pads 1312 soldered to the first driver chip 103 are exposed by multiple first solder holes M2.

[0149] In some examples, the size of the first pad 1312 is positively correlated with the size of the pins of the first driver chip 103. That is, the larger the size of the pins of the first driver chip 103, the larger the area of ​​the first pad 1312 projected onto the substrate 101, so that the pins of the first driver chip 103 can be soldered to the first pad 1312.

[0150] In some examples, the areas of the multiple first pads 1312 projected onto the substrate 101 may be the same or different.

[0151] In some examples, the ratio of the area of ​​the pin of the first driver chip 103 projected onto the substrate 101 to the area of ​​the first pad 1312 soldered to the pin of the first driver chip 103 projected onto the substrate 101 ranges from 0.8 to 2.

[0152] In some examples, the area of ​​the pins of the first driver chip 103 projected onto the substrate 101 may be smaller than the area of ​​the first pad 1312, which is soldered to the pins of the first driver chip 103, projected onto the substrate 101, in order to improve the ease of soldering the pins of the first driver chip 103 to the first pad 1312.

[0153] For example, the ratio of the area of ​​the pin of the first driver chip 103 projected onto the substrate 101 to the area of ​​the first pad 1312 soldered to the pin of the first driver chip 103 projected onto the substrate 101 can be 0.9, 1.0, 1.5 or 1.8, etc.

[0154] In some examples, a second welding hole M3 is also provided on the second reflective layer 194 (see Figure 7E The second solder hole M3 penetrates the second reflective layer 194 in a direction perpendicular to the substrate 101 to expose a portion of the connection line 112. For example, the area on the connection line 112 exposed by the second solder hole M3 can be referred to as the second pad 1313 (see [link to documentation]). Figure 6F and Figure 6G ).

[0155] In some examples, electronic component 120 includes two pins, one of which is soldered to a second pad 1313 on a connection line 112, and the other pin is soldered to a second pad 1313 on another connection line 112. This allows multiple electronic components 120 to be connected in series via multiple connection lines 112.

[0156] In some examples, a second solder hole M3 exposes two second pads 1313 that are soldered to the electronic component 120. In other examples, the two second pads 1313 that are soldered to the electronic component 120 are exposed by two second solder holes M3 respectively.

[0157] In some examples, the size of the second pad 1313 is positively correlated with the size of the pins of the electronic component 120. That is, the larger the size of the pins of the electronic component 120, the larger the area of ​​the second pad 1313 projected onto the substrate 101, so that the pins of the electronic component 120 can be soldered to the second pad 1313.

[0158] In some examples, the areas of the multiple second pads 1313 projected onto the substrate 101 may be the same or different.

[0159] In some examples, the ratio of the area of ​​the pin of electronic component 120 projected onto substrate 101 to the area of ​​the second pad 1313 soldered to the pin of electronic component 120 projected onto substrate 101 ranges from 0.8 to 2.

[0160] In some examples, the area of ​​the pins of electronic component 120 projected onto substrate 101 may be smaller than the area of ​​the second pad 1313 to which the pins of electronic component 120 are soldered projected onto substrate 101, in order to improve the ease of soldering the pins of electronic component 120 to the second pad 1313.

[0161] For example, the ratio of the area of ​​the pin of electronic component 120 projected onto substrate 101 to the area of ​​the second pad 1313 soldered to the pin of electronic component 120 projected onto substrate 101 can be 0.9, 1.0, 1.5 or 1.8, etc.

[0162] The following example illustrates the preparation method of substrate 100.

[0163] In some examples, the substrate 101 is made of glass. For instance, a buffer layer 102 (see [reference]) can be formed on one side of the substrate 101 using a magnetron sputtering process. Figure 7E For example, the buffer layer can be a PVX layer (Passivation layer).

[0164] A conductive layer is formed on the side of the buffer layer 102 away from the substrate 101. For example, the material of the conductive layer includes copper. In some examples, a magnetron sputtering process can be used to form the conductive layer on the side of the buffer layer 102 away from the substrate 101. In other examples, an electroplating process can also be used to form the conductive layer on the side of the buffer layer 102 away from the substrate 101. In still other examples, both magnetron sputtering and electroplating processes can be used to form the conductive layer on the side of the buffer layer 102 away from the substrate 101.

[0165] The conductive layer is patterned through processes such as cleaning, coating, baking, imaging, developing, hard baking, etching, and stripping to form multiple signal line groups 130 and multiple connecting lines 112.

[0166] A passivation layer 109 is formed on the side of the patterned conductive layer away from the substrate 101 (see [reference]). Figure 7E Understandably, the passivation layer 109 is made of insulating material, serving both to protect the conductive layer and to provide electrical isolation. Understandably, the passivation layer 109 can expose the pads (including the first pad 1312 and the second pad 1313, etc.).

[0167] A second reflective layer 194 is formed on the side of the passivation layer 109 away from the substrate 101. The second reflective layer 194 can cover the conductive layer (that is, cover multiple signal line groups 130 and multiple connection lines 112) to provide electrical isolation and also to reflect light.

[0168] In some examples, printing, 3D printing, or exposure and development processes (such as LDI exposure, full name: Laser Direct Imaging) can be used to directly form a patterned second reflective layer 194 on the side of the passivation layer 109 away from the substrate 101, so that the first solder hole M2 can expose the first solder pad 1312 and the second solder hole M3 can expose the second solder pad 1313, which simplifies the fabrication process of the substrate 100 and reduces the cost of the substrate 100.

[0169] In other examples, a photoresist layer can be formed on the side of the second reflective layer 194 away from the conductive layer using processes such as coating, imaging, and development. The photoresist layer is then patterned using an etching process to expose the second reflective layer 194 at the locations where openings (including the first solder hole M2 and the second solder hole M3) are required. The exposed second reflective layer 194 is then removed using an etching process to form the first solder hole M2 and the second solder hole M3, allowing the first solder hole M2 to expose the first pad 1312 and the second solder hole M3 to expose the second pad 1313.

[0170] Figure 4E for Figure 4D A magnified view of the Q3 region.

[0171] The inventors of this disclosure have discovered the following technical problems in the above embodiments.

[0172] As can be seen from the above, a portion (one or more) of the signal lines 131 need to be electrically connected to multiple first driver chips 103 arranged along the second direction Y. Taking power line 132 as an example, for instance... Figure 4D and Figure 4E As shown, a portion of the power line 132 is routed (e.g. Figure 4D and Figure 4E The first trace segment 131d shown in the figure needs to be placed between two adjacent first pads 1312 along the first direction X.

[0173] Understandably, since the first trace segment 131d is located between two adjacent first pads 1312, the width of the first trace segment 131d (e.g., the width along the first direction X) is small, which increases the risk of breakage of the first trace segment 131d, affects the current value that the first trace segment 131d can carry, and also leads to an increase in the heat dissipation of the first trace segment 131d, reducing the reliability of the substrate 100.

[0174] Figure 5A This is a diagram showing the positional relationship between the first trace segment and the second reflective layer according to some embodiments. Figure 5B for Figure 5AA cross-sectional view along the AA direction. Figure 5C This is a diagram showing the positional relationship between the first trace segment and the second reflective layer according to some other embodiments. Figure 5D for Figure 5C A cross-sectional view along the BB direction.

[0175] In some examples, such as Figure 5A and Figure 5B As shown, when the first solder hole M2 is formed using printing, 3D printing, or exposure and development processes, one first solder hole M2 can expose multiple (e.g., four) first pads 1312. Understandably, the first trace segment 131d is located between two adjacent first pads 1312, so that the first trace segment 131d can also be exposed by the first solder hole M2.

[0176] Since the distance between the two adjacent first pads 1312 and the first trace segment 131d located between the two adjacent first pads 1312 is small, and both the first pads 1312 and the first trace segment 131d are exposed by the first soldering hole M2, when the first driver chip 103 is soldered to the first pads 1312, solder (e.g., solder) can easily fall between the first pads 1312 and the first trace segment 131d, causing a short circuit between the first pads 1312 and the first trace segment 131d.

[0177] In other examples, such as Figure 5C and Figure 5D As shown, a second reflective layer 194 can be formed first, and then a process such as photolithography can be used to pattern the second reflective layer 194 to form a first solder hole M2, so that only one first solder pad 1312 can be exposed by one first solder hole M2. That is, the second reflective layer 194 can cover the first trace segment 131d located between two adjacent first solder pads 1312, reducing the risk of short circuit between the first trace segment 131d and the first solder pad 1312 caused by solder.

[0178] However, photolithography and other processes require the use of photomasks, which complicates the process and increases the cost of the substrate 100. Furthermore, the thickness of the second reflective layer 194 is approximately 50μm to 60μm (e.g., 55μm), while the height of the solder pins of the first driver chip 103 is approximately 15μm or even smaller (e.g., 8μm). Therefore, setting the second reflective layer 194 to cover the first trace segment 131d increases the difficulty of soldering between the pins of the first driver chip 103 and the first pad 1312, causing poor contact on the substrate 100 and affecting its reliability.

[0179] Furthermore, when the distance between two adjacent first pads 1312 is small, even if a first solder hole M2 exposes only one first pad 1312, the first trace segment 131d cannot be set between two adjacent first pads 1312, which increases the wiring difficulty of the substrate 100.

[0180] For example, taking a distance of 70 μm between two adjacent first pads 1312 and a width of 30 μm for the first trace segment 131d, when the first trace segment 131d is located in the middle between two adjacent first pads 1312, the distance between the first trace segment 131d and the first pad 1312 is 20 μm. However, in conventional designs, the distance between the first trace segment 131d and the first pad 1312 needs to be greater than or equal to 42 μm.

[0181] That is, when the distance between two adjacent first pads 1312 is small, even if the second reflective layer 194 is provided to cover the first trace segment 131d, the solder will cause the first trace segment 131d to short-circuit with the first pad 1312 during soldering, reducing the yield of the substrate 100.

[0182] Furthermore, taking a substrate 100 with a size of 34 inches (for example, a square substrate 100 with a diagonal length of 34 inches) as an example, multiple signal line groups 130 are located in the same conductive layer, which results in a longer signal line 131 and increases the risk of signal line 131 breaking.

[0183] Figure 6A This is a structural diagram of a substrate according to some other embodiments. Figure 6B This is a structural diagram of a substrate according to some other embodiments. Figure 6C This is a structural diagram of a bridging portion according to some embodiments. Figure 6D This is a partial structural diagram of a substrate according to some other embodiments. Figure 6E This is a partial structural diagram of a substrate according to some other embodiments. Figure 6F This is a structural diagram of a substrate according to some other embodiments. Figure 6G This is a structural diagram of a substrate according to some other embodiments.

[0184] Based on this, in some embodiments, such as Figure 6A and Figure 6B As shown, the substrate 100 also includes a plurality of bridging portions 140. The plurality of bridging portions 140 are located on the same side of the substrate 101 as the plurality of device groups 110, and at least one bridging portion 140 is located in the device region AA. The bridging portion 140 includes a conductive portion 147.

[0185] As described above, multiple signal line groups 130 and multiple device groups 110 are located on the same side of the substrate 101. Multiple bridging portions 140 and multiple device groups 110 are located on the same side of the substrate 101. Thus, multiple bridging portions 140, multiple signal line groups 130, and multiple device groups 110 are all located on the same side of the substrate 101.

[0186] Understandably, the second reflective layer 194 covers multiple signal line groups 130, and a portion of the bridging portion 140 is located on the side of the second reflective layer 194 away from the substrate 101.

[0187] In some examples, a portion (one or more) of the plurality of bridging portions 140 are located in device region AA, and another portion (one or more) are located in bonding region BB. In other examples, all of the plurality of bridging portions 140 are located in device region AA. In some examples, a single bridging portion 140 may be located in both device region AA and bonding region BB.

[0188] In some examples, such as Figure 6C As shown, the bridging portion 140 can extend along a first direction X, a second direction Y, or a direction intersecting the first direction X (or the second direction Y). For example, the acute angle formed between the extension direction of the bridging portion 140 and the first direction X (or the second direction Y) can be greater than 0° and less than 90°. Understandably, the extension directions of multiple bridging portions 140 can be the same or different.

[0189] In some examples, such as Figure 6C As shown, the length L5 of the bridging portion 140 ranges from 1mm to 30mm. For example, the length L5 of the bridging portion 140 can range from 5mm to 25mm, 10mm to 20mm, or 13mm to 18mm, etc. For example, the length L5 of the bridging portion 140 can be 5mm, 10mm, 15mm, 20mm, or 25mm, etc. Multiple bridging portions 140 can have the same or different lengths L5.

[0190] like Figure 6A and Figure 6B As shown, the bridging portion 140 includes a conductive portion 147. Understandably, the conductive portion 147 serves to conduct electricity. In some examples, such as... Figure 6A As shown, the conductive part 147 is made of a conductive material, such as copper or aluminum. In other examples, such as... Figure 6B As shown, the conductive part 147 can also be a resistor or a capacitor.

[0191] Understandably, such as Figure 6BAs shown, taking the conductive part 147 as a resistor as an example, the resistor may include a solder part 1473. In some examples, the solder part 1473 includes the resistor leads. In other examples, the solder part 1473 includes solder (e.g., solder) coated on the resistor leads in addition to the resistor leads. In still other examples, the solder part 1473 may only include solder. For example, there may be two solder parts 1473, each soldered to one of two third pads 1314.

[0192] Understandably, the conductive portions 147 in the multiple bridging portions 140 may be the same or different.

[0193] At least one bridging portion 140 is located in device region AA, such that at least one conductive portion 147 can be located in device region AA, thereby enabling the conductive portion 147 to be electrically connected to signal line 131.

[0194] In some examples, such as Figure 6D As shown, at least two signal lines 131 in at least one signal line group 130 are electrically connected through a conductive part 147.

[0195] Understandably, after at least two signal lines 131 in a signal line group 130 are electrically connected through the conductive portion 147, the voltage drop of the signal lines 131 can be reduced, thereby facilitating a reduction in the width of the signal lines 131 along the first direction X. As can be seen from the above, as... Figure 6D As shown, signal line 131 can be located within the side edge region AA21. Therefore, by electrically connecting the signal line 131 located within the side edge region AA21 in a signal line group 130 to other signal lines 131 in the same group via the conductive portion 147, the width of the signal line 131 located within the side edge region AA21 can be reduced, thereby reducing the width of the side edge region AA21 and facilitating the realization of a narrow bezel on the substrate 100.

[0196] Furthermore, by electrically connecting at least two signal lines 131 in a signal line group 130 through the conductive portion 147, the voltage drop of the signal line 131 is reduced, the thickness of the signal line 131 is reduced, the amount of material used in the signal line 131 is reduced, and the cost of the substrate 100 is reduced.

[0197] As can be seen from the above, in some examples, a portion (one or more) of the signal lines 131 need to extend along the first direction X within the lower edge region AA22 before they can extend along the second direction Y to the central region AA1 and be electrically connected to the device group 110.

[0198] In some examples, such as Figure 6DAs shown, at least one conductive portion 147 is located in the central region AA1, and at least two signal lines 131 in a signal line group 130 can be electrically connected within the central region AA1 through the conductive portion 147. This allows multiple electrically connected signal lines 131 to be electrically connected together to bonding pins within the bonding region BB. On one hand, this eliminates the need for the signal lines 131 to extend along the first direction X within the lower edge region AA22, reducing the space occupied by the signal lines 131 within the lower edge region AA22 and thus reducing the width of the lower edge region AA22, thereby facilitating the realization of a narrow bezel on the substrate 100. On the other hand, it also improves the ease of electrical connection between multiple signal lines 131 and bonding pins, thereby improving the wiring convenience of the substrate 100.

[0199] In some examples, such as Figure 6D As shown, a conductive portion 147, which electrically connects at least two signal lines 131, is located between two adjacent device groups 110 along the second direction Y. This arrangement allows the conductive portion 147 to be located outside the area where the device group 110 is located, reducing the impact of the conductive portion 147 on the light emission of the electronic components 120 in the device group 110 and improving the reliability of the substrate 100.

[0200] It is understood that device group 110 includes multiple electronic components 120, and the region where device group 110 is located refers to the closed virtual region formed by connecting the boundaries of the outermost electronic components 120 of device group 110 sequentially in a clockwise or counterclockwise direction. In some examples, when the multiple electronic components 120 in device group 110 are arranged in a matrix, the region where device group 110 is located is rectangular, and all the multiple electronic components 120 in device group 110 are located within this rectangular region.

[0201] In other examples, the conductive portion 147 that electrically connects at least two signal lines 131 may also overlap with the area where the device group 110 is located, improving the wiring flexibility of the substrate 100.

[0202] That is, by providing at least two signal lines 131 in at least one signal line group 130 electrically connected through the conductive portion 147, the width of the signal line 131 along the first direction X is reduced, thereby reducing the width of the side frame of the substrate 100. Furthermore, by enabling at least two signal lines 131 in a signal line group 130 to be electrically connected within the central region AA1, when the signal line 131 is electrically connected to the bonding region BB, it is not necessary to extend along the first direction X within the lower edge region AA22, thus reducing the width of the lower edge region AA22 and consequently reducing the width of the lower frame of the substrate 100. In addition, providing at least two signal lines 131 in at least one signal line group 130 electrically connected through the conductive portion 147 also reduces the thickness of the signal line 131, thereby reducing the amount of material used for the signal line 131 and lowering the cost of the substrate 100.

[0203] As described above, the multiple signal line groups 130 include a first voltage line group 150 and a second voltage line group 160. In some examples, such as... Figure 6D As shown, at least two first voltage lines 151 in the first voltage line group 150 can be electrically connected via the conductive portion 147. At least two second voltage lines 161 in the second voltage line group 160 can also be electrically connected via the conductive portion 147. In other examples, in addition to the first voltage line group 150 and the second voltage line group 160, other signal line groups 130 (e.g., power line group 135 or input / output line group 137) may also have at least two signal lines 131 (e.g., power line 132 or input / output line 134) electrically connected via the conductive portion 147.

[0204] In some examples, such as Figure 6D As shown, taking the first voltage line 151 located within the edge region AA21 as an example, the first voltage line 151 located within the edge region AA21 is electrically connected to other first voltage lines 151 in the first voltage line group 150 through the conductive part 147, so that the width of the first voltage line 151 located within the edge region AA21 along the first direction X can be reduced to 0.5mm~10mm. For example, the width of the first voltage line 151 along the first direction X can be 0.5mm, 1mm, 5mm, or 6.412mm, etc.

[0205] As can be seen from the above, if Figure 6E As shown, multiple electronic components 120 in device group 110 are electrically connected via connecting lines 112. In some examples, such as Figure 6F As shown, multiple interconnects 112 in a device group 110 are spaced apart. One pin of electronic component 120 is soldered to a second pad 1313 on one interconnect 112, and another pin is soldered to a second pad 1313 on another interconnect 112. This allows electronic component 120 to be located within region Q5 after being soldered to the interconnects 112 (see the diagram showing the positional relationship between electronic component 120 and interconnect 112). Figure 6E Similarly, such as Figure 6F As shown, after the first driver chip 103 is soldered to the first pad 1312, it can be located in the Q4 region.

[0206] In some examples, such as Figure 6D and Figure 6E As shown, the substrate 100 also includes a conductive pattern 170, which is disposed on the same layer as the plurality of signal line groups 130 and the plurality of connecting lines 112. In some examples, the plurality of signal line groups 130, the plurality of connecting lines 112 and the plurality of conductive patterns 170 are on the same layer and made of the same material.

[0207] Understandably, "same layer" refers to forming a whole layer structure using a single film deposition process, and then using a patterning process to form specific patterns in different areas. Depending on the specific pattern, the patterning process may include at least one exposure, development, or etching process, and the individual specific patterns may be continuous or discontinuous, and these specific patterns may also have different heights or different thicknesses.

[0208] In some examples, such as Figure 6D As shown, signal line 131 can be electrically connected to bonding area BB through conductive pattern 170. Understandably, since conductive pattern 170 has a strong current carrying capacity, setting signal line 131 to be electrically connected to bonding pin in bonding area BB through conductive pattern 170 improves the reliability of the electrical connection between signal line 131 and bonding pin.

[0209] In some examples, the conductive pattern 170 has a width of approximately 12.5 mm along the first direction X to improve the current carrying capacity of the conductive pattern 170, thereby improving the reliability of the electrical connection between the signal line 131 and the bonding pin.

[0210] In some examples, such as Figure 6E As shown, at least two signal lines 131 in a signal line group 130 are electrically connected via a conductive pattern 170 and a conductive portion 147. Understandably, since the conductive pattern 170 is conductive, it can compensate for the voltage drop of the signal line 131.

[0211] In other words, by electrically connecting the conductive pattern 170 to the signal line 131, the resistance of the signal transmission path (i.e., the electrically connected signal line 131 and conductive pattern 170) can be reduced, thus reducing the voltage drop of the signal transmission path (i.e., the electrically connected signal line 131 and conductive pattern 170), and consequently reducing the voltage drop of the signal line 131. This reduces signal loss during transmission, improves signal transmission reliability, and enhances the luminous efficiency of the electronic component 120.

[0212] Understandably, since the voltage drop of the signal line 131 can be reduced after the conductive pattern 170 is electrically connected to the signal line 131, even if the width of the signal line 131 along the first direction X is small, or the thickness of the signal line 131 is small, the voltage drop of the signal line 131 can still meet the requirements through the compensation effect of the conductive pattern 170.

[0213] In other words, by setting the conductive pattern 170 to be electrically connected to the signal line 131, on the one hand, it is beneficial to reduce the width of the signal line 131 along the first direction X, thereby reducing the space occupied by the signal line 131 on the substrate 101, improving the wiring convenience of the substrate 100, and facilitating the realization of a narrow bezel of the substrate 100. On the other hand, it is also beneficial to reduce the thickness of the signal line 131, thereby reducing the amount of material used for the signal line 131 and reducing the cost of the substrate 100.

[0214] For example, the area of ​​the orthographic projection of the conductive pattern 170 on the substrate 101 can be set to be different according to different needs, thereby improving the applicability of the substrate 100.

[0215] In some examples, such as Figure 6F As shown, at least one signal line 131 in at least one signal line group 130 includes at least two sub-sections 1311 spaced apart along the second direction Y, and two adjacent sub-sections 1311 in the same signal line 131 are electrically connected through a conductive portion 147.

[0216] As can be seen from the above, a portion (one or more) of the signal lines 131 includes a first trace segment 131d, which is located between two adjacent first pads 1312. This increases the risk of the first trace segment 131d breaking and also increases the risk of a short circuit between the first trace segment 131d and the first pad 1312.

[0217] In some examples, such as Figure 6F As shown, two sub-sections 1311 of the same signal line 131 are spaced apart along the second direction Y, and other signal lines 131 (e.g., the second voltage line 161) are located between the two spaced sub-sections 1311. It can be understood that by setting two adjacent sub-sections 1311 of the same signal line 131 to be electrically connected through the conductive portion 147, it is not necessary to set a first trace segment 131d between two adjacent first pads 1312.

[0218] Understandably, by electrically connecting the two sub-parts 1311 through the conductive part 147, the first trace segment 131d is not required. On the one hand, this avoids the first trace segment 131d located between two adjacent first pads 1312 from breaking or overheating, thus improving the reliability of the substrate 100. On the other hand, it avoids short circuits between the first trace segment 131d and the first pad 1312, thus improving the yield of the substrate 100. Furthermore, since there is no first trace segment 131d between two adjacent first pads 1312, a first solder hole M2 can be provided to expose multiple first pads 1312, simplifying the substrate 100 manufacturing process and reducing the cost of the substrate 100.

[0219] Furthermore, by electrically connecting the two sub-parts 1311 through the conductive portion 147, the length of each sub-part 1311 can be shortened, reducing the risk of breakage or overheating due to excessive length of the signal line 131, and improving the reliability of the substrate 100. Understandably, the sub-parts 1311 included in a signal line 131 can have the same or different lengths. The spacing between two adjacent sub-parts 1311 along the second direction Y can be the same or different.

[0220] In some examples, the conductive portion 147 is located on one side of two adjacent first pads 1312 along the first direction X.

[0221] Understandably, by adjusting the width and thickness of the conductive portion 147, its current-carrying capacity can be adjusted. In some examples, the width and thickness of the conductive portion 147 can be increased to give it a larger current-carrying capacity. Understandably, the greater the current-carrying capacity of the conductive portion 147, the smaller the current-carrying capacity of the sub-portion 1311 can be, which helps to reduce the width and thickness of the sub-portion 1311 along the first direction X, thereby facilitating the achievement of a narrow bezel on the substrate 100 and reducing the cost of the substrate 100.

[0222] In other examples, the width and thickness of the conductive portion 147 can be reduced to give the conductive portion 147 a smaller current carrying capacity, thereby meeting different application requirements and improving the applicability of the substrate 100.

[0223] As described above, the substrate 100 includes a second reflective layer 194, which covers a plurality of signal line groups 130. In some examples, the second reflective layer 194 has a third solder hole M4 (see [reference]). Figure 8A The third welding hole M4 penetrates the second reflective layer 194 in a direction perpendicular to the substrate 101 to expose a portion of the sub-part 1311. For example, as shown... Figure 6G As shown, the area of ​​sub-part 1311 exposed by the second welding hole M3 can be referred to as the third welding pad 1314.

[0224] In some examples, a subsection 1311 may have multiple third pads 1314, while in other examples, a subsection 1311 may have only one third pad 1314.

[0225] One end of the conductive part 147 is soldered to the third pad 1314 on one sub-part 1311, and the other end is soldered to the third pad 1314 on another sub-part 1311, so that the two sub-parts 1311 arranged at intervals along the second direction Y can be electrically connected through the conductive part 147.

[0226] In some examples, a second solder hole M3 exposes a third pad 1314, allowing the second reflective layer 194 to cover the trace between the two third pads 1314, preventing short circuits between the conductive portion 147 and the trace between the two third pads 1314, and improving the reliability of the substrate 100. Understandably, the passivation layer 109 can expose the third pad 1314.

[0227] In some examples, the areas of the multiple third pads 1314 projected onto the substrate 101 may be the same or different.

[0228] In some examples, the size of the third pad 1314 is positively correlated with the size of the end of the conductive portion 147 that is soldered to the third pad 1314. That is, the larger the area of ​​the end of the conductive portion 147 that is soldered to the third pad 1314 projected onto the substrate 101, the larger the area of ​​the third pad 1314 projected onto the substrate 101.

[0229] In some examples, the area of ​​the end of the conductive portion 147 soldered to the third pad 1314 projected onto the substrate 101 is rectangular, with a length of 1.5 mm and a width of 1 mm. For example, the ratio of the area of ​​the end of the conductive portion 147 soldered to the third pad 1314 projected onto the substrate 101 to the area of ​​the third pad 1314 soldered to that end of the conductive portion 147 projected onto the substrate 101 ranges from 0.8 to 2.

[0230] In some examples, the area of ​​the end of the conductive portion 147 that is soldered to the third pad 1314 and projected onto the substrate 101 may be smaller than the area of ​​the third pad 1314 that is soldered to one end of the conductive portion 147 and projected onto the substrate 101.

[0231] For example, the ratio of the area of ​​the end of the conductive part 147 that is soldered to the third pad 1314 projected onto the substrate 101 to the area of ​​the third pad 1314 that is soldered to the end of the conductive part 147 projected onto the substrate 101 can be 0.9, 1.0, 1.5 or 1.8, etc.

[0232] In some examples, at least a portion of any bridging portion 140 on the side away from the substrate 101 can reflect light.

[0233] As can be seen from the above, the substrate 100 can be used to provide a light source. The second reflective layer 194 covers multiple signal line groups 130 and multiple connecting lines 112, which can play a reflective role, improve the brightness of the substrate 100, and reduce the power consumption of the substrate 100.

[0234] Understandably, a portion of the bridging portion 140 is located on the side of the second reflective layer 194 away from the substrate 101, meaning that the bridging portion 140 can cover a portion of the second reflective layer 194. Therefore, at least a portion of the side of any bridging portion 140 away from the substrate 101 can reflect light.

[0235] This reduces the intensity of light absorbed by the bridging portion 140, improves the appearance of black spots or shadows on the substrate 100 caused by the bridging portion 140, reduces the impact of the bridging portion 140 on the brightness of the substrate 100, and improves the optical performance of the substrate 100. In other words, by providing at least a portion of any bridging portion 140 on the side away from the substrate 101 that can reflect light, the utilization rate of light incident on the area where the bridging portion 140 is located on the substrate 100 can be improved.

[0236] Understandably, the side of the bridging portion 140 away from the substrate 101 can be the surface of the bridging portion 140 away from the substrate 101, or it can be the position between the surface of the bridging portion 140 away from the substrate 101 and the surface of the bridging portion 140 close to the substrate 101.

[0237] In some examples, at least a portion of the surface of the conductive portion 147 on the side away from the substrate 101 can reflect light.

[0238] In some examples, at least a portion of the surface of the conductive portion 147 away from the substrate 101 can be set to white, so that at least a portion of the conductive portion 147 away from the substrate 101 can reflect light.

[0239] As described above, the conductive portion 147 can be a conductive material, a capacitor, or a resistor. In some examples, when the conductive portion 147 is made of a conductive material, it can be made of white conductive material to reflect light. In some examples, taking the conductive portion 147 as a resistor, the surface of the resistor away from the substrate 101 can be made white to reflect light.

[0240] Understandably, by providing at least a portion of the conductive portion 147 on the surface away from the substrate 101, light can be reflected, thereby improving the utilization rate of light incident on the area where the bridging portion 140 is located on the substrate 100, improving the brightness uniformity of the substrate 100 at different locations, and also improving the brightness of the substrate 100, reducing the power consumption of the substrate 100, and improving the optical performance of the substrate 100.

[0241] Understandably, in different bridging portions 140, the shape and area of ​​the reflective region on the surface of the conductive portion 147 away from the substrate 101 can be the same or different. In some examples, the entire area of ​​the surface of each bridging portion 140 away from the substrate 101 can reflect light.

[0242] Figure 7A for Figure 6F A sectional view along the C1-C1 direction. Figure 7B for Figure 6F Another sectional view along the C1-C1 direction. Figure 7C for Figure 6F Another sectional view along the C1-C1 direction. Figure 7D for Figure 6F Another sectional view along the C1-C1 direction.

[0243] It should be noted that, Figures 7A-7D In different embodiments, Figure 6F A sectional view along the C1-C1 direction. See below for reference. Figures 7A-7D Let's continue to illustrate the bridging part 140 with examples.

[0244] As described above, a third solder hole M4 is provided on the second reflective layer 194, and the exposed portion 1311 of the third solder hole M4 can form a third solder pad 1314. In some examples, such as Figure 7A As shown, the edge of the third welding hole M4 is spaced apart from the edge of the sub-part 1311. In other examples, such as Figure 7B As shown, the edge of the third welding hole M4 overlaps with the edge of the sub-part 1311.

[0245] In some examples, such as Figures 7A-7D As shown, the bridging portion 140 further includes a first encapsulation portion 148, which covers the conductive portion 147. The material of the first encapsulation portion 148 includes at least one of a light-transmitting material and a reflective material.

[0246] Understandably, the first encapsulation portion 148 covers the conductive portion 147, serving to protect the conductive portion 147, reducing corrosion caused by external water or oxygen, and extending the lifespan of the conductive portion 147. In some examples, the first encapsulation portion 148 is made of insulating material, thereby providing electrical isolation, reducing the risk of short circuits between the conductive portion 147 and other conductive structures, and improving the reliability of the substrate 100.

[0247] In some examples, such as Figures 7A-7D As shown, the first encapsulation portion 148 can not only cover the conductive portion 147, but also cover the second reflective layer 194 located in the area surrounding the conductive portion 147. That is, the first encapsulation portion 148 can overlap with the second reflective layer 194 in the area surrounding the conductive portion 147, thereby improving the encapsulation protection effect of the first encapsulation portion 148 on the conductive portion 147.

[0248] In some examples, such as Figure 7A and Figure 7BAs shown, the first encapsulation portion 148 can cover a large area of ​​the second reflective layer 194 surrounding the conductive portion 147. In other examples, such as Figure 7C and Figure 7D As shown, the first encapsulation portion 148 may also cover only the second reflective layer 194 in a smaller area around the conductive portion 147.

[0249] In some examples, when the material of the first package 148 includes a light-transmitting material, light can pass through the first package 148 and irradiate the surface of the conductive portion 147 away from the substrate 101. Under the reflection of the surface of the conductive portion 147 away from the substrate 101, light is emitted from the substrate 100 via the first package 148.

[0250] In some examples, when the material of the first package portion 148 includes a reflective material, the light irradiated onto the bridging portion 140 can irradiate outside the substrate 100 under the reflection of the first package portion 148.

[0251] That is, when the material of the first encapsulation portion 148 includes a light-transmitting material, light can exit the substrate 100 under the reflection of the conductive portion 147. When the material of the first encapsulation portion 148 includes a reflective material, light can exit the substrate 100 under the reflection of the first encapsulation portion 148.

[0252] In some examples, the material of the first encapsulation portion 148 includes a light-transmitting material and a reflective material, so that light can shine outside the substrate 100 under the reflection of both the conductive portion 147 and the first encapsulation portion 148.

[0253] Understandably, when at least a portion of the surface of the conductive portion 147 away from the substrate 101 can reflect light, and the first encapsulation portion 148 includes a reflective material, even if light passes through the first encapsulation portion 148, it can be reflected by the surface of the conductive portion 147 away from the substrate 101, thereby increasing the brightness of the substrate 100 and reducing the influence of the bridging portion 140 on the brightness of the substrate 100.

[0254] In some examples, when the first encapsulation portion 148 includes a reflective material, the material of the first encapsulation portion 148 may include white ink or white adhesive. For example, the white ink may be at least one of photosensitive white ink and curable white ink. When the first encapsulation portion 148 includes a transparent material, the material of the first encapsulation portion 148 may include transparent adhesive.

[0255] In other examples, the surface of the conductive portion 147 on the side away from the substrate 101 cannot reflect light. In this case, at least a portion of the surface of the first package portion 148 on the side away from the substrate 101 can reflect light.

[0256] That is, when the surface of the conductive portion 147 away from the substrate 101 cannot reflect light, at least a portion of the surface of the first encapsulation portion 148 away from the substrate 101 can be provided for reflecting light. Since the first encapsulation portion 148 covers the conductive portion 147, the light irradiated to the bridging portion 140 can be irradiated outside the substrate 100 under the reflection of the first encapsulation portion 148, reducing the impact of the bridging portion 140 on the brightness of the substrate 100, improving the utilization rate of light incident on the area where the bridging portion 140 is located on the substrate 100, and improving the brightness uniformity of the substrate 100.

[0257] Understandably, the surface of the conductive part 147 away from the substrate 101 cannot reflect light, and the first encapsulation part 148 reflects the light, which simplifies the fabrication process of the substrate 100 and reduces the cost of the substrate 100.

[0258] In some examples, the material of the first encapsulation portion 148 includes a reflective material, such that at least a portion of the surface of the first encapsulation portion 148 away from the substrate 101 can reflect light. For example, the reflective material can be white ink or white adhesive. For example, the white ink can be at least one of photosensitive white ink and curable white ink.

[0259] In some examples, such as Figure 7B and Figure 7C As shown, the conductive part 147 is a chip resistor or conductive adhesive.

[0260] As described above, the conductive part 147 is used for conducting electricity. In some examples, such as... Figure 7C As shown, the conductive part 147 is a surface mount resistor. Understandably, the surface mount resistor includes two leads, one of which is soldered to a third pad 1314 on one sub-part 1311, and the other lead is soldered to a third pad 1314 on another sub-part 1311, so that the surface mount resistor can electrically connect two spaced sub-parts 1311.

[0261] In other examples, the conductive part 147 can also be other conductive devices, such as capacitors. Understandably, by using different conductive devices for the conductive part 147, different control effects can be achieved on the current flowing through it, thus meeting different application requirements.

[0262] In some other examples, the conductive part 147 may also be a metal sheet or a metal wire, such as a copper sheet, aluminum sheet, copper wire or aluminum wire, or the conductive part 147 may also be a conductive tape, etc.

[0263] The following example illustrates the fabrication method of substrate 100, using conductive part 147 as a chip resistor or conductive adhesive.

[0264] As described above, the passivation layer 109 can expose the pads (including the first pad 1312, the second pad 1313, and the third pad 1314). In some examples, the pads exposed by the passivation layer 109 (including the first pad 1312, the second pad 1313, and the third pad 1314) can be subjected to a gold plating process before the formation of the second reflective layer 194. Understandably, the gold plating process uses chemical oxidation-reduction to form a nickel-gold layer on the surface of the pads away from the substrate 101, improving the corrosion resistance of the pads (including the first pad 1312, the second pad 1313, and the third pad 1314) and enhancing the soldering effect.

[0265] In other examples, OSP (Organic Solderability Preservatives) processing can be performed on the surfaces of the signal line groups 130 away from the substrate 101 and the surfaces of the interconnects 112 away from the substrate 101 before forming the passivation layer 109. Understandably, OSP processing forms an organic protective layer on the surfaces of the signal line groups 130 and interconnects 112 away from the substrate 101, improving oxidation of the signal line groups 130 and interconnects 112. Understandably, after OSP processing of the signal line groups 130 and interconnects 112, it is unnecessary to perform gold plating processing on the pads (including the first pad 1312, the second pad 1313, and the third pad 1314).

[0266] As can be seen from the above, after the passivation layer 109 is formed, a patterned second reflective layer 194 can be formed on the side of the passivation layer 109 away from the substrate 101, so that the second reflective layer 194 can expose the first pad 1312, the second pad 1313 and the third pad 1314.

[0267] In some examples, when the conductive part 147 is a surface mount resistor, a soldering process can be used to solder the leads of the surface mount resistor to the third pad 1314. That is, the electronic component 120 is soldered to the second pad 1313, the first driver chip 103 is soldered to the first pad 1312, and the surface mount resistor is soldered to the third pad 1314.

[0268] For example, solder can be pre-applied to the pins of electronic component 120 or applied to the second pad 1313. Similarly, solder can be pre-applied to the pins of the first driver chip 103 or applied to the first pad 1312. Solder can be pre-applied to one end of the surface mount resistor or applied to the third pad 1314. For example, the solder can be solder.

[0269] For example, a die-bonding process can be used to place the electronic component 120 on the side of the second pad 1313 away from the substrate 101, and the first driver chip 103 on the side of the first pad 1312 away from the substrate 101. Alternatively, surface mount technology (SMT) can be used to place the chip resistor on the side of the third pad 1314 away from the substrate 101 using a placement device (e.g., a pick-and-place machine). A reflow soldering process is then used to solder the electronic component 120 to the second pad 1313, the first driver chip 103 to the first pad 1312, and the chip resistor to the third pad 1314.

[0270] In other examples, when the conductive part 147 is made of conductive adhesive, a printing process or a fabrication process can be used to electrically connect the conductive adhesive to the third pad 1314. For example, the conductive adhesive can be silver paste, nano-silver paste, or copper paste, etc.

[0271] In some examples, conductive adhesive can be formed after electronic component 120 is soldered to second pad 1313 and first driver chip 103 is soldered to first pad 1312.

[0272] In some examples, conductive adhesive can be formed using a printing process via pneumatic or solenoid valves. In other examples, conductive adhesive can be formed using a printing process via steps such as prefabricated stencils.

[0273] Understandably, after the conductive adhesive is formed, it needs to be cured at a high temperature. Taking Ag glue (also known as silver glue) as an example, the curing temperature can be around 150℃, and the curing time can be around 1 hour.

[0274] Understandably, the resistance of conductive adhesive varies depending on its length, width, and thickness. The following example uses Ag adhesive (also known as silver adhesive) and Table 1 to illustrate the resistance values ​​of conductive adhesive at different lengths, widths, and thicknesses.

[0275] Table 1

[0276] As shown in Table 1, conductive parts 147 were formed using Ag adhesives with different resistivities and applied by needle coating. The resistance values ​​of the Ag adhesives varied depending on their length, width, and thickness.

[0277] For example, Cu traces formed using electroplating or magnetron sputtering processes are set to a resistivity of 1.75E-08 (1.75 × 10⁻⁸). -8When the length is 1m, the width is 0.31mm, and the thickness is 2.7μm, the resistance of the Cu trace is approximately 21Ω. That is, by using Ag adhesive as the conductive part 147 and controlling the length, width, and thickness of the Ag adhesive, the resistance of the Ag adhesive can be made the same as, or even less than, the resistance of the Cu trace, thereby reducing the voltage drop of the conductive part 147 and improving the reliability of the substrate 100.

[0278] In some examples, after the conductive portion 147 is formed, an electrical test (ET) needs to be performed on the substrate 100. For example, the substrate 100 can be powered on to observe whether the electronic component 120 can emit light. If the substrate 100 fails during the electrical test, the faulty component (such as the electronic component 120, the first driver chip 103, or the conductive portion 147) needs to be reworked (RW).

[0279] Figure 7E This is a structural diagram of a substrate according to some other embodiments.

[0280] As can be seen from the above, if Figure 7E As shown, the second reflective layer 194 has a second solder hole M3, which exposes the second solder pad 1313, and the electronic component 120 is soldered to the second solder pad 1313.

[0281] In some examples, such as Figure 7E As shown, the substrate 100 also includes a plurality of reflective portions 195, one of which is adjacent to the edge of a second solder hole M3. That is, the reflective portion 195 can surround the second solder pad 1313.

[0282] Understandably, the reflective portion 195 serves to reflect light. In some examples, the material of the reflective portion 195 includes white adhesive. In this way, the light emitted by the electronic component 120, after shining on the reflective portion 195, can shine outside the substrate 100 under the reflection of the reflective portion 195, thereby increasing the brightness of the substrate 100 and reducing the power consumption of the substrate 100.

[0283] In some examples, the reflective portion 195 can be formed by coating after the electronic component 120 is soldered to the second pad 1313.

[0284] In some examples, one or more reflective portions 195 are arranged adjacent to the edge of the second solder hole M3, another one or more reflective portions 195 are arranged adjacent to the edge of the first solder hole M2, and yet another one or more reflective portions 195 are arranged adjacent to the edge of the third solder hole M4. That is, the reflective portions 195 can not only surround the second solder pad 1313, but also surround the first solder pad 1312 and the third solder pad 1314, improving the light reflection effect of the reflective portions 195, thereby increasing the brightness of the substrate 100.

[0285] Figure 8A This is a structural diagram of a substrate according to some other embodiments. Figure 8B This is a structural diagram of a conductive part according to some embodiments. Figure 8C This is a structural diagram of the conductive part according to some other embodiments. Figure 8D This is a structural diagram of the conductive part according to some other embodiments.

[0286] In some examples, such as Figure 8A and Figure 8B As shown, the conductive portion 147 includes a main body portion 1471 and two connecting portions 1472. The two connecting portions 1472 are respectively connected to both ends of the main body portion 1471. The maximum distance between the surface of the main body portion 1471 facing the substrate 101 and the substrate 101 is greater than the maximum distance between the surface of either connecting portion 1472 facing the substrate 101 and the substrate 101.

[0287] Understandably, the main body 1471 and the connecting part 1472 can be fixedly connected, or the main body 1471 and the connecting part 1472 can be detachably connected.

[0288] In some examples, such as Figure 8A and Figure 8B As shown, the main body 1471 includes a first sub-main body 1471a and a second sub-main body 1471b. There are two second sub-main body parts 1471b, each connected to one end of the first sub-main body 1471a. A connecting part 1472 is connected to the end of the second sub-main body 1471b furthest from the first sub-main body 1471a. Understandably, the connecting part 1472 is used for soldering to the third pad 1314.

[0289] Understandably, such as Figure 8A As shown, the maximum distance between the surface of the main body 1471 facing the substrate 101 and the substrate 101 is also the maximum distance between the surface of the first sub-main body 1471a facing the substrate 101 and the surface of the substrate 101 on the side closer to the main body 1471.

[0290] In some examples, the extension direction of the first sub-body portion 1471a is parallel or approximately parallel to the substrate 101. That is, the distance between the surface of the first sub-body portion 1471a facing the substrate 101 and the substrate 101 is the same or approximately the same at different positions.

[0291] Understandably, such as Figure 8A As shown, the maximum distance between the surface of the connecting portion 1472 facing the substrate 101 and the substrate 101 is also the maximum distance between the surface of the connecting portion 1472 facing the substrate 101 and the surface of the substrate 101 on the side closer to the connecting portion 1472.

[0292] In some examples, the extension direction of the connector 1472 is parallel or approximately parallel to the substrate 101. That is, the distance between the surface of the connector 1472 facing the substrate 101 and the substrate 101 is the same or approximately the same at different positions.

[0293] In some examples, the extension direction of the first sub-body portion 1471a intersects the extension direction of the second sub-body portion 1471b, so that the conductive portion 147 can be arched or approximately arched, thereby making the maximum distance between the surface of the body portion 1471 facing the substrate 101 and the substrate 101 greater than the maximum distance between the surface of any connecting portion 1472 facing the substrate 101 and the substrate 101.

[0294] Understandably, such as Figure 8A As shown, a signal line 131 is provided between two adjacent third pads 1314. Since the second reflective layer 194 covers the signal line 131, the conductive part 147 needs to cross not only the signal line 131, but also the second reflective layer 194 covering the signal line 131.

[0295] Since the second reflective layer 194 is usually thicker, the maximum distance between the surface of the main body 1471 facing the substrate 101 and the substrate 101 is set to be greater than the maximum distance between the surface of any connecting part 1472 facing the substrate 101 and the substrate 101. This allows the main body 1471 to avoid the second reflective layer 194, reducing the mutual interference between the main body 1471 and the second reflective layer 194, improving the convenience and reliability of soldering between the conductive part 147 and the third pad 1314, thereby improving the reliability of the substrate 100.

[0296] In some examples, such as Figure 8C and Figure 8D As shown, the orthographic projection of the main body 1471 onto the substrate 101 is a first rectangle. The length L1 of the first rectangle ranges from 0.5mm to 25mm, and the width L2 of the first rectangle ranges from 0.2mm to 3mm.

[0297] In some examples, the length L1 of the first rectangle can range from 3mm to 20mm, 5mm to 15mm, or 8mm to 12mm, etc. In other examples, the length L1 of the first rectangle can be 5.8mm, 6.35mm, 12mm, 16mm, or 22mm, etc.

[0298] In some examples, the width L2 of the first rectangle can range from 0.5mm to 2.5mm, 1mm to 2mm, or 1.2mm to 1.8mm, etc. In other examples, the width L2 of the first rectangle can range from 0.85mm, 1.0mm, 2.2mm, or 2.8mm, etc.

[0299] In some examples, the orthographic projection of any connection portion 1472 onto the substrate 101 is a second rectangle, the length L3 of which ranges from 0.2 mm to 3 mm, and the width L4 of which ranges from 0.2 mm to 3 mm.

[0300] In some examples, the length L3 of the second rectangle can range from 0.5mm to 2.5mm, 1mm to 2mm, or 1.2mm to 1.5mm, etc. In other examples, the length L3 of the second rectangle can be 1mm, 1.5mm, 1.8mm, or 2.2mm, etc.

[0301] In some examples, the width L4 of the second rectangle can range from 0.5mm to 2.5mm, 1mm to 2mm, or 1.2mm to 1.5mm, etc. In other examples, the width L4 of the second rectangle can be 1mm, 1.5mm, 1.8mm, or 2.2mm, etc.

[0302] In some examples, the width L4 of the second rectangle may be the same as or different from the width L2 of the first rectangle.

[0303] Understandably, by setting the length L1 and width L2 of the first rectangle, the length L3 and width L4 of the second rectangle to different values, two third pads 1314 with different spacings can be electrically connected through the conductive part 147, thus meeting different usage requirements and improving the applicability of the conductive part 147.

[0304] In some examples, such as Figure 8D As shown, the maximum distance between the surface of the main body 1471 facing the substrate 101 and the surface of the connecting part 1472 facing the substrate 101 is the first distance H1, and the value of the first distance H1 ranges from 0.1 mm to 0.8 mm.

[0305] In some examples, the first distance H1 can range from 0.2mm to 0.6mm, 0.3mm to 0.5mm, or 0.35mm to 0.48mm, etc. In other examples, the first distance H1 can be 0.2mm, 0.30mm, or 0.7mm, etc.

[0306] In some examples, the main body 1471 is away from the surface of the substrate 101, and the maximum distance between it and the surface of the connecting part 1472 facing the substrate 101 is the second distance H2, which ranges from 0.2 mm to 1 mm.

[0307] In some examples, the value of the second distance H2 can be in the range of 0.25mm~0.9mm, 0.3mm~0.8mm, or 0.4mm~0.7mm, etc. In some examples, the value of the second distance H2 can be 0.3mm, 0.50mm, or 0.8mm, etc.

[0308] Understandably, by setting different values ​​for the first distance H1 and the second distance H2, different usage requirements can be met and the reliability of the substrate 100 can be improved.

[0309] Understandably, the sum of the length L1 of the first rectangle and the length L3 of the second rectangle is the length of the orthographic projection of the conductive portion 147 onto the substrate 101. In some examples, the length of the orthographic projection of the conductive portion 147 onto the substrate 101 can be 5 mm, 9.6 mm, or 15 mm, etc.

[0310] Figure 9A for Figure 6G A cross-sectional view along the C2-C2 direction. Figure 9B for Figure 6G Another sectional view along the C2-C2 direction. Figure 9C for Figure 6G Another sectional view along the C2-C2 direction.

[0311] It should be noted that, Figures 9A-9C In different embodiments, Figure 6G A sectional view along the C2-C2 direction. See below for reference. Figures 9A-9C Let's continue with an example of substrate 100.

[0312] In some examples, such as Figures 9A-9C As shown, the substrate 100 also includes a first reflective layer 191. The first reflective layer 191 is located on the side of the plurality of device groups 110, the plurality of signal line groups 130 and the plurality of bridging portions 140 away from the substrate 101.

[0313] Understandably, the first reflective layer 191 serves to reflect light. In some examples, the first reflective layer 191 is a reflective sheet.

[0314] As can be seen from the above, in some examples, such as Figure 9A As shown, the bridging portion 140 includes a conductive portion 147 and a first encapsulation portion 148, with the first encapsulation portion 148 covering the conductive portion 147. At this time, the first reflective layer 191 covers the plurality of bridging portions 140, that is, the first reflective layer 191 can be located on the side of the first encapsulation portion 148 away from the substrate 101.

[0315] In other examples, such as Figure 9B and Figure 9C As shown, when the bridging portion 140 includes only the conductive portion 147 and does not include the first encapsulation portion 148, the first reflective layer 191 covers the plurality of bridging portions 140, that is, the first reflective layer 191 can be located on the side of the conductive portion 147 away from the substrate 101.

[0316] As can be seen from the above, the conductive part 147 can be a conductive material or a resistor, etc. In some examples, such as Figure 9B As shown, when the conductive portion 147 is made of a conductive material, the conductive material is soldered to the third pad 1314, and the first reflective layer 191 is located on the side of the conductive material away from the substrate 101. In some examples, the first reflective layer 191 may be attached to the surface of the conductive material away from the substrate 101. In other examples, there may be a gap between the first reflective layer 191 and the surface of the conductive material away from the substrate 101.

[0317] In other examples, such as Figure 9C As shown, when the conductive part 147 is a resistor, the solder part 1473 of the resistor is soldered to the third solder pad 1314, and the first reflective layer 191 is located on the side of the electrical component away from the substrate 101. In some examples, the first reflective layer 191 may be attached to the surface of the resistor on the side away from the substrate 101. In other examples, there may be a gap between the first reflective layer 191 and the surface of the resistor on the side away from the substrate 101.

[0318] Understandably, the first reflective layer 191 is configured to cover multiple device groups 110, multiple signal line groups 130, and multiple bridging portions 140, so that the first reflective layer 191 can reflect light, thereby increasing the brightness of the substrate 100 and reducing the power consumption of the substrate 100.

[0319] Figure 9D This is a structural diagram of a substrate according to some other embodiments.

[0320] like Figure 9DAs shown, the first reflective layer 191 has multiple first functional regions Q1, and the orthographic projection of the bridging portion 140 on the substrate 101 is located within the range of the orthographic projection of the first functional regions Q1 on the substrate 101. The first reflective layer 191 has multiple first linear slots G1, and any one of the first linear slots G1 penetrates the first reflective layer 191 in a direction perpendicular to the substrate 101. The first functional regions Q1 are surrounded by multiple mutually spaced first linear slots G1.

[0321] Understandably, the orthographic projection of the bridging portion 140 onto the substrate 101 is within the range of the orthographic projection of the first functional region Q1 onto the substrate 101, that is, the bridging portion 140 can be located within the first functional region Q1.

[0322] In some examples, the number of first functional regions Q1 is the same as the number of bridging portions 140, and the orthographic projection of one bridging portion 140 onto the substrate 101 lies within the range of the orthographic projection of one first functional region Q1 onto the substrate 101. In other examples, the number of first functional regions Q1 is less than the number of bridging portions 140, and the orthographic projections of one or more bridging portions 140 onto the substrate 101 lie within the range of the orthographic projection of one first functional region Q1 onto the substrate 101.

[0323] Understandably, the bridging portion 140 is located on the side of the plurality of signal line groups 130 away from the substrate 101, and the first reflective layer 191 covers the bridging portion 140, causing the bridging portion 140 to exert stress on the first reflective layer 191. Therefore, any one of the first linear slots G1 is provided to penetrate the first reflective layer 191 in a direction perpendicular to the substrate 101, so that the first linear slot G1 can absorb the stress of the first reflective layer 191.

[0324] like Figure 9D As shown, a plurality of first linear slots G1 are provided to form a first functional area Q1, and the bridging portion 140 is located within the first functional area Q1, so that the first linear slots G1 can absorb the stress caused by the bridging portion 140 on the first reflective layer 191, reducing the risk of the first reflective layer 191 shrinking under stress, causing electrical components (such as electronic component 120, first driving chip 103, or bridging portion 140, etc.) to fall off, thereby improving the reliability of the substrate 100.

[0325] In some examples, different first functional areas Q1 can be formed by different numbers of first linear slits G1. Understandably, the shapes and areas of the different first functional areas Q1 can be the same or different.

[0326] In some examples, the ratio of the area of ​​the orthographic projection of any bridging portion 140 onto the substrate 101 to the area of ​​the first functional region Q1 where the orthographic projection of the bridging portion 140 onto the substrate 101 is located ranges from 0.5 to 2.

[0327] In some examples, the ratio of the area of ​​the orthographic projection of any bridging portion 140 onto the substrate 101 to the area of ​​the first functional region Q1 where the orthographic projection of the bridging portion 140 onto the substrate 101 is located can be in the range of 0.6~1.8, 0.8~1.5, or 0.9~1.4, etc.

[0328] In some examples, the ratio of the area of ​​the orthographic projection of any bridging portion 140 onto the substrate 101 to the area of ​​the first functional region Q1 where the orthographic projection of the bridging portion 140 onto the substrate 101 is located can be 0.8, 0.9, 1.0, or 1.2, etc.

[0329] Understandably, by setting the ratio of the area of ​​the orthographic projection of any bridging portion 140 on the substrate 101 to the area of ​​the first functional region Q1 where the orthographic projection of the bridging portion 140 on the substrate 101 is located to a value in the range of 0.5 to 2, it is possible to reduce the absolute value of the difference between the area of ​​the orthographic projection of the bridging portion 140 on the substrate 101 and the area of ​​the first functional region Q1 where the bridging portion 140 is located, thereby improving the stress absorption effect of the first linear gap G1 and improving the reliability of the substrate 100.

[0330] In some examples, the length of the first linear slit G1 ranges from 1 mm to 5 mm, and the width of the first linear slit G1 ranges from 50 μm to 300 μm.

[0331] In some examples, the length of the first linear slit G1 can range from 1.5mm to 4.5mm, 2mm to 4mm, or 2.5mm to 3.5mm, etc. In some examples, the length of the first linear slit G1 can be 1.2mm, 2.8mm, 3.4mm, or 4.8mm, etc.

[0332] In some examples, the width of the first linear slit G1 can be in the range of 100μm~250μm, 120μm~220μm, or 150μm~200μm, etc. In some examples, the width of the first linear slit G1 can be 80μm, 120μm, 220μm, or 280μm, etc.

[0333] Understandably, the length and width of the multiple first linear slits G1 can be the same or different.

[0334] Understandably, setting the length and width of the first linear gap G1 to different values ​​can meet different usage requirements and improve the reliability of the substrate 100.

[0335] In some examples, such as Figures 9A-9C As shown, the first reflective layer 191 has a plurality of second linear slits G2, and any one of the second linear slits G2 penetrates the first reflective layer 191 in a direction perpendicular to the substrate 101, such as... Figure 9D As shown, any one of the second linear slots G2 is located in the first functional area Q1. The orthographic projection of the edge of the second linear slot G2 onto the substrate 101 at least partially overlaps with the orthographic projection of the bridging portion 140 onto the substrate 101.

[0336] In some examples, the second linear slit G2 may extend along the first direction X. In other examples, the second linear slit G2 may extend along the second direction Y. In still other examples, the second linear slit G2 may extend along a direction that intersects both the first direction X and the second direction Y.

[0337] As described above, the orthographic projection of the bridging portion 140 onto the substrate 101 is located within the range of the orthographic projection of the first functional region Q1 onto the substrate 101. Therefore, by positioning the second linear slot G2 within the first functional region Q1, the orthographic projection of the edge of the second linear slot G2 onto the substrate 101 can at least partially overlap with the orthographic projection of the bridging portion 140 onto the substrate 101. In other words, the position of the second linear slot G2 corresponds to the position of the bridging portion 140.

[0338] In some examples, the orthographic projection of the edge of the second linear slit G2 onto the substrate 101 is within the range of the orthographic projection of the bridging portion 140 onto the substrate 101.

[0339] Understandably, the second linear gap G2 can absorb the stress caused by the bridging portion 140 on the first reflective layer 191, reduce the risk of the first reflective layer 191 shrinking under stress, causing electrical components (such as electronic component 120, first driving chip 103, or bridging portion 140, etc.) to fall off, and improve the reliability of the substrate 100.

[0340] As described above, at least a portion of the bridging portion 140 on the side away from the substrate 101 can reflect light. In some examples, the area of ​​the bridging portion 140 on the side away from the substrate 101 and exposed by the second linear slit G2 can reflect light to reduce the impact of the bridging portion 140 on the brightness of the substrate 100, thereby improving the utilization rate of light incident on the area where the bridging portion 140 is located on the substrate 100 and improving the brightness uniformity of the substrate 100.

[0341] In other examples, the entire area of ​​the bridging portion 140 on the side away from the substrate 100 can reflect light, improving the reliability of the light reflected by the bridging portion 140.

[0342] In some examples, the ratio of the length of the second linear slit G2 to the length of the longest side of the bridging portion 140 ranges from 0.9 to 1.5.

[0343] Understandably, the ratio of the length of the second linear slit G2 to the length of the longest side of the bridging portion 140 is also the ratio of the length of the second linear slit G2 to the length of the longest side of the bridging portion 140 where the orthographic projection of the second linear slit G2 on the substrate 101 intersects with the orthographic projection of the edge of the second linear slit G2 on the substrate 101.

[0344] As described above, in some examples, the bridging portion 140 includes a conductive portion 147 and a first encapsulation portion 148, and the first encapsulation portion 148 covers the conductive portion 147. In this case, the length of the longest side of the bridging portion 140 is the same as the length of the longest side of the first encapsulation portion 148.

[0345] In some other examples, the bridging portion 140 includes only the conductive portion 147 and does not include the first encapsulation portion 148. In this case, the length of the longest side of the bridging portion 140 is the length of the longest side of the conductive portion 147.

[0346] In some examples, the ratio of the length of the second linear gap G2 to the length of the longest side of the bridging portion 140 can be in the range of 0.95~1.3, 1.0~1.25, or 1.1~1.15, etc. In some examples, the ratio of the length of the second linear gap G2 to the length of the longest side of the bridging portion 140 can be 0.95, 1.0, 1.1, or 1.2, etc.

[0347] Understandably, setting the ratio of the length of the second linear gap G2 to the length of the longest side of the bridging portion 140 to be in the range of 0.9 to 1.5 can reduce the absolute value of the difference between the length of the second linear gap G2 and the length of the longest side of the bridging portion 140, improve the stress absorption effect of the second linear gap G2, and improve the reliability of the substrate 100.

[0348] In some examples, the length of the second linear slit G2 ranges from 1 mm to 35 mm, and the width of the second linear slit G2 ranges from 50 μm to 300 μm.

[0349] In some examples, the length of the second linear slit G2 can range from 5mm to 30mm, 10mm to 25mm, or 15mm to 20mm, etc. In some examples, the length of the second linear slit G2 can be 1.2mm, 8mm, 12mm, 18mm, 22mm, 25mm, or 32mm, etc.

[0350] In some examples, the width of the second linear slit G2 can range from 100μm to 250μm, 120μm to 220μm, or 150μm to 200μm, etc. In other examples, the width of the second linear slit G2 can be 80μm, 120μm, 220μm, or 280μm, etc.

[0351] Understandably, the length of the second linear slit G2 can be the same as or different from the length of the first linear slit G1. The width of the second linear slit G2 can be the same as or different from the width of the first linear slit G1. Multiple second linear slits G2 can have the same length and different widths.

[0352] Understandably, setting the length and width of the second linear slit G2 to different values ​​can meet different usage requirements and improve the reliability of the substrate 100.

[0353] Figure 9E for Figure 9D A sectional view along the D1-D1 direction. Figure 9F for Figure 9D A cross-sectional view along the D2-D2 direction. Figure 9G This is a structural diagram of a substrate according to some other embodiments.

[0354] It should be noted that in some examples, the first reflective layer 191 can cover the non-optical element 122, therefore Figure 9D Non-optical element 122 is not shown. See also other examples. Figure 9G The first reflective layer 191 can also expose the non-optical element 122. See below for reference. Figures 9D to 9G The positional relationship between the optical element 121 and the non-optical element 122 and the first reflective layer 191 is illustrated by example.

[0355] In some examples, such as Figure 9E As shown, the electronic component 120 includes an optical component 121, and the substrate 100 also includes a second encapsulation portion 192, which covers the optical component 121, and the material of the second encapsulation portion 192 is a light-transmitting material.

[0356] In some examples, optical element 121 can be a light-emitting device, such as a Mini LED, for emitting light outwards. In other examples, optical element 121 can also be a photosensitive element, such as a photodiode or phototransistor, for converting received light signals into electrical signals.

[0357] like Figure 9EAs shown, the second encapsulation portion 192 covers the optical element 121, thereby protecting and encapsulating the optical element 121 and extending its service life. Furthermore, the material of the second encapsulation portion 192 is a light-transmitting material, reducing the amount of light blocked by the second encapsulation portion 192 and increasing the intensity of light that can pass through it.

[0358] In this way, when the optical element 121 is a light-emitting device (e.g., a Mini LED), the light emitted by the optical element 121 can pass through the second encapsulation portion 192 and illuminate the outside of the substrate 100. When the optical element 121 is a photosensitive element, external light can pass through the second encapsulation portion 192 and illuminate the optical element 121. That is, the material of the second encapsulation portion 192 includes a light-transmitting material, which can reduce the impact of the second encapsulation portion 192 on the optical element 121 and improve the reliability of the substrate 100.

[0359] In some examples, the material of the second encapsulation part 192 includes transparent adhesive.

[0360] In some examples, the second encapsulation portion 192 may be mushroom-shaped or approximately mushroom-shaped.

[0361] In some examples, such as Figure 9D As shown, the first reflective layer 191 has a first through hole M1, and the orthographic projection of the optical element 121 on the substrate 101 is located in the area enclosed by the orthographic projection of the edge of the first through hole M1 on the substrate 101.

[0362] Understandably, since the optical element 121 needs to emit light outward or receive light from the outside, the orthographic projection of the optical element 121 on the substrate 101 is positioned within the area enclosed by the orthographic projection of the edge of the first through hole M1 on the substrate 101. This allows the optical element 121 to be exposed through the first through hole M1, preventing the first reflective layer 191 from blocking the optical element 121 and improving the optical performance of the substrate 100.

[0363] In some examples, the orthographic projection of the second package portion 192 on the substrate 101 is also located within the area enclosed by the orthographic projection of the edge of the first through hole M1 on the substrate 101. That is, the second package portion 192 can also be exposed through the first through hole M1.

[0364] In some examples, such as Figure 9F As shown, electronic component 120 includes non-optical component 122. Substrate 100 also includes a third encapsulation portion 193, which covers non-optical component 122, and a first reflective layer 191 covers third encapsulation portion 193.

[0365] Understandably, non-optical element 122 is an electronic element that does not need to emit or receive light from the outside. In some examples, non-optical element 122 can be a driver IC (Integrated Circuit) or a sensor, etc.

[0366] like Figure 9F As shown, the third encapsulation part 193 covers the non-optical element 122, thereby protecting and encapsulating the non-optical element 122 and extending its service life.

[0367] In some examples, the material of the third encapsulation portion 193 can be a light-transmitting material, such as transparent silicone. In other examples, the material of the third encapsulation portion 193 can also be a reflective material, such as white silicone. The embodiments of this disclosure do not further limit the material of the third encapsulation portion 193.

[0368] In some examples, such as Figure 9D and Figure 9F As shown, the first reflective layer 191 has a second functional region Q2, and at least a portion of the orthographic projection of the non-optical element 122 onto the substrate 101 is located in the second functional region Q2. The first reflective layer 191 has a plurality of third linear slits G3, any one of which penetrates the first reflective layer 191 along a direction perpendicular to the substrate 101, and any one of the third linear slits G3 is located in the second functional region Q2. The orthographic projection of the edge of the third linear slit G3 onto the substrate 101 overlaps with at least a portion of the orthographic projection of the non-optical element 122 onto the substrate 101.

[0369] Understandably, the orthographic projection of the non-optical element 122 onto the substrate 101 is within the range of the orthographic projection of the second functional region Q2 onto the substrate 101, that is, the non-optical element 122 can be located within the second functional region Q2.

[0370] In some examples, the number of second functional regions Q2 is the same as the number of non-optical elements 122, and the orthographic projection of one non-optical element 122 onto the substrate 101 lies within the range of the orthographic projection of one second functional region Q2 onto the substrate 101. In other examples, the number of second functional regions Q2 is less than the number of non-optical elements 122, and the orthographic projections of one or more non-optical elements 122 onto the substrate 101 lie within the range of the orthographic projection of one second functional region Q2 onto the substrate 101.

[0371] Understandably, the non-optical element 122 is located on the side of the plurality of signal line groups 130 away from the substrate 101, the third package portion 193 covers the non-optical element 122, and the first reflective layer 191 covers the third package portion 193, so that the non-optical element 122 and the third package portion 193 cause stress to the first reflective layer 191.

[0372] Therefore, any third linear slit G3 is provided to penetrate the first reflective layer 191 in a direction perpendicular to the substrate 101. Any third linear slit G3 is located in the second functional area Q2, and the orthographic projection of the edge of the third linear slit G3 on the substrate 101 overlaps at least partially with the orthographic projection of the non-optical element 122 on the substrate 101. This allows the third linear slit G3 to absorb the stress caused to the first reflective layer 191 by the non-optical element 122 and the third packaging part 193, reducing the risk of the first reflective layer 191 shrinking under stress, which could lead to the detachment of electrical components (such as electronic component 120, first driving chip 103, or bridging part 140, etc.), and improving the reliability of the substrate 100.

[0373] In some examples, the orthographic projection of the edge of the third linear slit G3 onto the substrate 101 falls within the range of the orthographic projection of the non-optical element 122 onto the substrate 101.

[0374] In some examples, the number of third linear slits G3 located within the same second functional area Q2 can be one or more. The number of third linear slits G3 can be the same or different in different second functional areas Q2.

[0375] In some examples, such as Figure 9D As shown, at least two third linear slits G3 are located in the same second functional region Q2, and the edges of the at least two third linear slits G3 located in the same second functional region Q2 are arranged in an X-shape on the substrate 101 by orthogonal projection.

[0376] In some examples, there are two third linear slots G3 located in the same second functional area Q2, and the extension directions of the two third linear slots G3 located in the same second functional area Q2 intersect, so that the orthographic projection of the edges of the two third linear slots G3 located in the same second functional area Q2 onto the substrate 101 can be arranged in an X shape.

[0377] In other examples, such as Figure 9DAs shown, the number of the third linear slits G3 located in the same second functional region Q2 can also be three or four. For example, when the number of the third linear slits G3 located in the same second functional region Q2 is three, two of the third linear slits G3 have the same extending direction and are arranged at intervals, and the other third linear slit G3 is located between the two third linear slits G3 arranged at intervals, and its extending direction intersects with the extending directions of the two third linear slits G3 arranged at intervals, so that the orthographic projections of the edges of the three third linear slits G3 located in the same second functional region Q2 on the substrate 101 can be arranged in an X shape.

[0378] For example, when the number of the third linear slits G3 located in the same second functional region Q2 is four, two of the third linear slits G3 have the same extending direction and are arranged at intervals, and the other two third linear slits G3 also have the same extending direction and are arranged at intervals. Moreover, the extending directions of the two third linear slits G3 with the same extending direction intersect with the extending directions of the other two third linear slits G3 with the same extending direction, so that the orthographic projections of the edges of the four third linear slits G3 located in the same second functional region Q2 on the substrate 101 can be arranged in an X shape.

[0379] In some other examples, the number of the third linear slits G3 located in the same second functional region Q2 can also be five, six or more. The embodiments of the present disclosure do not further limit the number of the third linear slits G3 located in the same second functional region Q2.

[0380] It can be understood that arranging the orthographic projections of the edges of at least two third linear slits G3 located in the same second functional region Q2 on the substrate 101 in an X shape can improve the stress absorption effect of the third linear slits G3 on the stress of the first reflective layer 191, reduce the risk of the first reflective layer 191 shrinking under the action of stress and causing electrical components (such as the electronic component 120, the first driving chip 103 or the bridging part 140, etc.) to fall off, and improve the reliability of the substrate 100.

[0381] In some other examples, as Figure 9G shown, the orthographic projections of the edges of the third linear slits G3 located in the same second functional region Q2 on the substrate 101 can also be arranged in a "cross" shape.

[0382] In some other examples, the orthographic projections of the edges of the third linear slits G3 located in the same second functional region Q2 on the substrate 101 can also be arranged in a "rice" shape.

[0383] As can be seen from the above, in some examples, the first reflective layer 191 covers the third encapsulation part 193. In some other examples, as Figure 9GAs shown, the first reflective layer 191 has a second through-hole M5. The second through-hole M5 penetrates the first reflective layer 191 in a direction perpendicular to the substrate 101, and the third package portion 193 and non-optical components 122 can be exposed through the second through-hole M5. This avoids the third package portion 193 and non-optical components 122 causing stress to the first reflective layer 191, reduces the risk of the first reflective layer 191 shrinking under stress, and causing electrical components (such as electronic components 120, the first driving chip 103, or the bridging portion 140, etc.) to fall off, and improves the reliability of the substrate 100.

[0384] In some examples, such as Figure 9D As shown, the two third linear slits G3 are located within the same second functional area Q2. The ratio of the length of the third linear slit G3 to the maximum size of the non-optical element 122 ranges from 0.9 to 2.5.

[0385] Understandably, the ratio of the length of the third linear slit G3 to the maximum size of the non-optical element 122 is also the ratio of the length of the third linear slit G3 to the maximum size of the non-optical element 122 whose orthogonal projection on the substrate 101 intersects with the orthogonal projection of the edge of the third linear slit G3 on the substrate 101.

[0386] For example, when the orthographic projection of the non-optical element 122 onto the substrate 101 is square, rectangular, or other irregular polygonal, the maximum size of the non-optical element 122 is the length of the diagonal of its orthographic projection onto the substrate 101. When the orthographic projection of the non-optical element 122 onto the substrate 101 is circular or approximately circular, the maximum size of the non-optical element 122 is the diameter of its orthographic projection onto the substrate 101.

[0387] In some examples, the lengths of the two third linear slits G3 located within the same second functional area Q2 are the same or approximately the same. In some examples, the ratio of the length of the third linear slit G3 to the maximum size of the non-optical element 122 can also range from 0.95 to 21 to 1.8 or 1.1 to 1.5, etc. For example, the ratio of the length of the third linear slit G3 to the maximum size of the non-optical element 122 can be 0.95, 1.0 to 1.5, or 2.2, etc.

[0388] Understandably, setting the ratio of the length of the third linear slit G3 to the maximum size of the non-optical element 122 to a value in the range of 0.9 to 2.5 can reduce the absolute value of the length difference between the length of the third linear slit G3 and the maximum size of the non-optical element 122, improve the stress absorption effect of the third linear slit G3 on the first reflective layer 191, and improve the reliability of the substrate 100.

[0389] In some examples, the ratio of the length of the third linear slit G3 to the maximum size of the third encapsulation portion 193 ranges from 0.9 to 2.5.

[0390] Understandably, the ratio of the length of the third linear slit G3 to the maximum size of the third package portion 193 is also the ratio of the length of the third linear slit G3 to the maximum size of the third package portion 193 where the orthographic projection of the third linear slit G3 onto the substrate 101 intersects with the orthographic projection of the edge of the third linear slit G3 onto the substrate 101.

[0391] For example, when the orthographic projection of the third package portion 193 onto the substrate 101 is square, rectangular, or other irregular polygonal, the maximum size of the third package portion 193 is the length of the diagonal of its orthographic projection onto the substrate 101. When the orthographic projection of the third package portion 193 onto the substrate 101 is circular or approximately circular, the maximum size of the third package portion 193 is the diameter of its orthographic projection onto the substrate 101.

[0392] In some examples, the lengths of the two third linear slits G3 located within the same second functional area Q2 are the same or approximately the same. In some examples, the ratio of the length of the third linear slit G3 to the maximum size of the third encapsulation portion 193 can also range from 0.95 to 21 to 1.8 or from 1.1 to 1.5. For example, the ratio of the length of the third linear slit G3 to the maximum size of the third encapsulation portion 193 can be 0.95, 1.0 to 1.5, or 2.2, etc.

[0393] Understandably, setting the ratio of the length of the third linear slit G3 to the maximum size of the third encapsulation portion 193 to a value in the range of 0.9 to 2.5 can reduce the absolute value of the length difference between the length of the third linear slit G3 and the maximum size of the third encapsulation portion 193, improve the stress absorption effect of the third linear slit G3 on the first reflective layer 191, and improve the reliability of the substrate 100.

[0394] In some examples, the first reflective layer 191 has a third through-hole (not shown in the figure). The substrate 100 also includes a support structure, one end of which is connected to the second reflective layer 194 through the third through-hole, and the other end extends away from the substrate 101. For example, the extension direction of the support structure is perpendicular or approximately perpendicular to the substrate 101.

[0395] Understandably, the substrate 100 includes an optical film and a condenser lens to improve the light extraction efficiency of the substrate 100. The optical film and the condenser lens are located on the side of the first reflective layer 191 away from the substrate 101, and the support structure serves to support the optical film and the condenser lens.

[0396] In some examples, the support structure can be conical or frustum-shaped to improve the reliability of the support.

[0397] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A substrate having a plurality of edges; the substrate including a device region and at least one bonding region, the bonding region being adjacent to any edge of the substrate relative to the device region; the substrate comprising: Substrate; Multiple device groups are located on one side of the substrate, and the multiple device groups are located in the device region; The plurality of device groups are arranged along a first direction and a second direction, respectively; the first direction and the second direction intersect each other and are parallel to the substrate; each device group includes at least one electronic component; Multiple signal line groups are located on the same side of the substrate as the multiple device groups; each signal line group includes multiple signal lines; the multiple signal lines all extend along the second direction and are spaced apart along the first direction; any one signal line extends from the bonding region to the device region, and any one of the signal lines is electrically connected to a column of the device groups arranged along the second direction; as well as, Multiple bridging portions are located on the same side of the substrate as the multiple device groups, and at least one bridging portion is located in the device region; the bridging portion includes a conductive portion; Wherein, at least two of the signal lines in at least one of the signal line groups are electrically connected through the conductive portion; and / or, at least one signal line in at least one of the signal line groups includes at least two sub-sections spaced apart along the second direction, and two adjacent sub-sections in the same signal line are electrically connected through the conductive portion. At least a portion of any of the bridging portions on the side away from the substrate can reflect light.

2. The substrate according to claim 1, wherein, At least a portion of the conductive portion on the surface away from the substrate can reflect light.

3. The substrate according to claim 2, wherein, The bridging portion further includes a first encapsulation portion that covers the conductive portion; the material of the first encapsulation portion includes at least one of a light-transmitting material and a reflective material.

4. The substrate according to claim 1, wherein, The bridging portion further includes a first encapsulation portion that covers the conductive portion; at least a portion of the surface of the first encapsulation portion away from the substrate can reflect light.

5. The substrate according to claim 1, wherein, The conductive part includes: Main body; Two connecting portions are respectively connected to both ends of the main body portion; the maximum distance between the surface of the main body portion facing the substrate and the substrate is greater than the maximum distance between the surface of either connecting portion facing the substrate and the substrate.

6. The substrate according to claim 5, wherein, The orthographic projection of the main body onto the substrate is a first rectangle, the length of which ranges from 0.5mm to 25mm, and the width of which ranges from 0.2mm to 3mm; and / or, The shape of the orthographic projection of any of the connecting parts on the substrate is a second rectangle, the length of the second rectangle is in the range of 0.2mm to 3mm, and the width of the second rectangle is in the range of 0.2mm to 3mm.

7. The substrate according to claim 6, wherein, The maximum distance between the surface of the main body facing the substrate and the surface of the connecting part facing the substrate is a first distance, and the value of the first distance ranges from 0.1mm to 0.8mm. And / or, The maximum distance between the surface of the main body facing away from the substrate and the surface of the connecting part facing the substrate is the second distance, and the value of the second distance ranges from 0.2mm to 1mm.

8. The substrate according to claim 1, further comprising: The first reflective layer is located on the side of the plurality of device groups, the plurality of signal line groups, and the plurality of bridging portions away from the substrate; The first reflective layer has a plurality of first functional areas; the orthographic projection of the bridging portion on the substrate is located within the range of the orthographic projection of the first functional areas on the substrate; The first reflective layer has a plurality of first linear slits, and any one of the first linear slits penetrates the first reflective layer in a direction perpendicular to the substrate; the first functional area is composed of a plurality of first linear slits arranged at intervals between each other.

9. The substrate according to claim 8, wherein, The ratio of the area of ​​the orthographic projection of any of the bridging portions onto the substrate to the area of ​​the first functional area where the orthographic projection of the bridging portion onto the substrate is located ranges from 0.5 to 2.

10. The substrate according to claim 8, wherein, The length of the first linear slit ranges from 1 mm to 5 mm, and the width of the first linear slit ranges from 50 μm to 300 μm.

11. The substrate according to claim 8, wherein, The first reflective layer has a plurality of second linear slits, any one of which penetrates the first reflective layer in a direction perpendicular to the substrate, and any one of the second linear slits is located in the first functional area; The orthographic projection of the edge of the second linear slit onto the substrate at least partially overlaps with the orthographic projection of the bridging portion onto the substrate.

12. The substrate according to claim 11, wherein, The ratio of the length of the second linear gap to the length of the longest side of the bridging portion ranges from 0.9 to 1.

5.

13. The substrate according to claim 11, wherein, The length of the second linear slit ranges from 1 mm to 35 mm, and the width of the second linear slit ranges from 50 μm to 300 μm.

14. The substrate according to claim 8, wherein, The electronic component includes an optical component, and the substrate further includes a second encapsulation portion that covers the optical component, and the material of the second encapsulation portion is a light-transmitting material; The first reflective layer has a first through hole, and the orthographic projection of the optical element on the substrate is located within the area enclosed by the orthographic projection of the edge of the first through hole on the substrate.

15. The substrate according to claim 8, wherein, The electronic components include non-optical components, and the substrate further includes: A third encapsulation portion covers the non-optical element, and the first reflective layer covers the third encapsulation portion.

16. The substrate according to claim 15, wherein, The first reflective layer has a second functional region, and at least a portion of the orthographic projection of the non-optical element onto the substrate is located in the second functional region; The first reflective layer has a plurality of third linear slits, any one of which penetrates the first reflective layer in a direction perpendicular to the substrate, and any one of the third linear slits is located in the second functional area; The orthographic projection of the edge of the third linear slit onto the substrate overlaps at least partially with the orthographic projection of the non-optical element onto the substrate.

17. The substrate according to claim 16, wherein, At least two of the third linear slots are located in the same second functional area, and the edges of the at least two third linear slots located in the same second functional area are arranged in an X-shape on the substrate.

18. The substrate according to claim 17, wherein, The two third linear slits are located within the same second functional area; The ratio of the length of the third linear slit to the maximum size of the non-optical element ranges from 0.9 to 2.5; and / or, The ratio of the length of the third linear slit to the maximum size of the third encapsulation part ranges from 0.9 to 2.

5.

19. The substrate according to any one of claims 1 to 18, wherein, The conductive part is a chip resistor or conductive adhesive.

20. An electronic device comprising a substrate as claimed in any one of claims 1 to 19.

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