Reset circuit and electronic device

Abstract

The application provides a reset circuit and electronic equipment, and relates to the field of circuits. The reset circuit comprises a first charging circuit, which is used for charging a second charging circuit for N times in succession. Each charging operation comprises that the first charging circuit and a charger are electrically connected and disconnected, and the time length of charging the second charging circuit for N times in succession is less than 1 minute. The second charging circuit is used for outputting a control signal to a reset signal output circuit in the period in which the first charging circuit and the charger are electrically connected and disconnected. The reset signal output circuit is used for outputting a reset signal when the voltage value of the detected control signal exceeds a preset threshold. The reset circuit in the application generates a reset signal in the process in which the charger and the electronic equipment are repeatedly electrically connected, triggers the electronic equipment to perform a reset operation, does not need to depend on a physical button in the electronic equipment, and reduces the cost of the electronic equipment.

Description

[0001] This application is a divisional application. The original application has the application number 202211311478.7 and the original application date is October 25, 2022. The entire contents of the original application are incorporated herein by reference. Technical Field

[0002] This application relates to the field of circuits, and more particularly to a reset circuit and electronic device. Background Technology

[0003] With the development of smart terminals, they are increasingly being used by users. During operation, smart terminals (such as smartwatches and smart bands) may malfunction (e.g., program crashes), causing the terminal to freeze and requiring a reset to restore operation. Currently, there are several ways to reset a smart terminal. One method is to incorporate a watchdog circuit, which outputs a reset signal to reset the terminal. Another method is to have a reset button on the terminal; when the user presses the reset button, it triggers the MCU to perform a reset operation.

[0004] However, watchdog circuits are expensive and require corresponding software configuration, increasing the cost of smart terminals. Another method of resetting a smart terminal relies on a reset button; if the smart terminal does not have a reset button, it cannot perform the reset function. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a reset circuit and an electronic device that generates a reset signal during repeated electrical connections between the charger and the electronic device, triggering the electronic device to perform a reset operation without relying on physical buttons in the electronic device, thus reducing the cost of the electronic device.

[0006] In a first aspect, this application provides a reset circuit disposed in an electronic device. The reset circuit includes: a first charging circuit, a second charging circuit, and a reset signal output circuit. The first charging circuit is used to charge the second charging circuit during N consecutive cycles of electrical connection and disconnection with the charger, where N is an integer greater than 1, and the duration of the N consecutive cycles of electrical connection and disconnection of the first charging circuit with the charger is less than 1 minute. The second charging circuit is used to output a control signal to the reset signal output circuit. The reset signal output circuit is used to output a reset signal when it detects that the voltage value of the control signal exceeds a preset threshold. The reset signal is used to trigger a reset operation of the microprocessor in the electronic device.

[0007] In this way, by repeatedly connecting and disconnecting the charger from the first charging circuit, the first charging circuit can delay charging the second charging circuit, avoiding the problem of triggering a reset operation as soon as the charger is connected to the electronic device. Furthermore, since the duration of the first charging circuit's N consecutive connections and disconnections from the charger is less than one minute, the problem of excessively long charging time for the second charging circuit is avoided, improving the user experience for reset operations. Simultaneously, due to the repeated plugging and unplugging of the charger, the voltage of the second charging circuit gradually increases, and the voltage of the control signal output by the second charging circuit also gradually increases. When the voltage value of the control signal of the second charging circuit exceeds a preset threshold, the reset signal output circuit is triggered to output a reset signal. This reset circuit does not use a watchdog circuit or rely on physical buttons in the electronic device, reducing the cost of the electronic device and increasing the application scenarios of the reset circuit.

[0008] According to a first aspect, the first charging circuit includes: a first capacitor, a discharging component, and a first diode; the second charging circuit includes: a second capacitor and a first resistor; a first terminal of the first capacitor is electrically connected to the anode of the first diode and a first terminal of the discharging component; a second terminal of the discharging component is grounded; the cathode of the first diode is electrically connected to the first terminal of the second capacitor and a first terminal of the first resistor; a first terminal of the second capacitor is electrically connected to the input terminal of a reset signal output circuit; a second terminal of the second capacitor is electrically connected to the second terminal of the first resistor; a second terminal of the first resistor is grounded; the output terminal of the reset signal output circuit is electrically connected to the reset terminal of the microprocessor; wherein the second terminal of the first capacitor and the second terminal of the discharging component are used for electrical connection with the charger.

[0009] In this way, at the instant the first capacitor is connected to the charger, because the voltage across the first capacitor cannot change abruptly, a pulse voltage is generated at the first terminal of the first capacitor. This pulse voltage can charge the second capacitor. When the first capacitor is disconnected from the charger, it releases its charge through the discharge component, reducing the voltage across the first capacitor so that the pulse voltage used to charge the second capacitor is generated the next time the first capacitor is connected to the charger. For example, the discharge component (such as the discharge component including a fourth resistor) can form a discharge circuit with the equivalent resistance (such as the third resistor) in the charging management circuit of the electronic device, or the first capacitor can form a discharge circuit with the discharge component (including the third and fourth resistors). Since the first charging circuit includes a first diode, and the cathode of the first diode is electrically connected to the first terminal of the second capacitor, the second capacitor will not discharge in reverse when the first capacitor is disconnected from the charger. At the same time, the first resistor in the second charging circuit can release the charge in the second capacitor, preventing the charge accumulated by the charger each time it normally charges the electronic device, thereby avoiding the problem of accidental triggering of the reset operation.

[0010] According to the first aspect, the first charging circuit further includes: a second resistor; the first end of the second resistor is electrically connected to the cathode of the first diode, and the second end of the second resistor is electrically connected to the first end of the second capacitor and the first end of the second resistor. Thus, by adding a second resistor to the first charging circuit, the current flowing into the second capacitor can be limited, thereby allowing the charging speed of the first capacitor to the second capacitor to be controlled by the second resistor. The second resistor also isolates the first capacitor from the reset signal output circuit, preventing accidental triggering of the reset signal output circuit during the charging process of the first capacitor to the second capacitor, and improving the ESD (Electro-Static Discharge) protection performance of the reset circuit.

[0011] According to the first aspect, the first charging circuit further includes: a second resistor; a first end of the second resistor is electrically connected to a first end of the first capacitor, and a second end of the second resistor is electrically connected to the anode of the first diode. Thus, by adding a second resistor to the first charging circuit, the current flowing into the second capacitor can be limited, thereby allowing the charging speed of the first capacitor to the second capacitor to be controlled by the second resistor. The second resistor also isolates the first capacitor from the reset signal output circuit, preventing accidental triggering of the reset signal output circuit during the charging process of the first capacitor to the second capacitor, and improving the ESD (Electro-Static Discharge) protection performance of the reset circuit.

[0012] According to the first aspect, the discharge assembly includes a third resistor and a fourth resistor; a first terminal of the fourth resistor is electrically connected to a first terminal of the first capacitor; a second terminal of the fourth resistor is electrically connected to a first terminal of the third resistor; a second terminal of the third resistor is electrically connected to a second terminal of the first capacitor; and a first terminal of the third resistor is grounded. In this way, the first capacitor, the third resistor, and the fourth resistor can form a discharge circuit. The third resistor can increase the discharge speed of the first capacitor, so that when the first capacitor comes into contact with the charger again, the voltage across the first capacitor is lower, allowing for more efficient charging of the second capacitor.

[0013] According to the first aspect, the discharge assembly includes: a third resistor and a second diode; the second terminal of the third resistor is electrically connected to the second terminal of the first capacitor; the first terminal of the third resistor is grounded and electrically connected to the input terminal of the second diode; the output terminal of the second diode is electrically connected to the first terminal of the first capacitor. Thus, the discharge assembly can include the third resistor and the second diode, allowing the first capacitor, the third resistor, and the second diode to form a discharge circuit, reducing the voltage across the first capacitor; it also avoids the problem of a negative voltage appearing in the first capacitor after power is cut off.

[0014] According to a first aspect, the first charging circuit includes: a first capacitor, a discharging component, and a first diode; the second charging circuit includes: a second capacitor and a first resistor; a first terminal of the first capacitor is electrically connected to the input terminal of the first diode and the first terminal of the discharging component; a second terminal of the discharging component is grounded; the output terminal of the first diode is electrically connected to the first terminal of the second capacitor and the first terminal of the first resistor; a first terminal of the second capacitor is electrically connected to the input terminal of the reset signal output circuit; a second terminal of the second capacitor is electrically connected to the second terminal of the first resistor; a second terminal of the first resistor is grounded; the output terminal of the reset signal output circuit is electrically connected to the reset terminal of the microprocessor; wherein, the second terminal of the first capacitor and the second terminal of the discharging component are used for electrical connection with the charger.

[0015] In this way, at the instant the first capacitor is connected to the charger, because the voltage across the first capacitor cannot change abruptly, a pulse voltage is generated at the first terminal of the first capacitor. This pulse voltage can charge the second capacitor. When the first capacitor is disconnected from the charger, it releases its charge through the discharge component, reducing the voltage across the first capacitor so that the pulse voltage used to charge the second capacitor is generated the next time the first capacitor is connected to the charger. The second terminal of the discharge component (e.g., the discharge component includes a fourth resistor) is grounded, which can form a discharge loop with the equivalent resistance (e.g., a third resistor) in the charging management circuit of the electronic device, eliminating the need for additional components and reducing the cost of the reset circuit.

[0016] According to the first aspect, the discharge component includes: a fourth resistor; a first terminal of the fourth resistor electrically connected to a first terminal of a first capacitor; a second terminal of the fourth resistor electrically connected to a first terminal of a third resistor, the third resistor being the equivalent resistance of the charging management circuit in the electronic device; a second terminal of the third resistor electrically connected to a second terminal of the first capacitor; and a first terminal of the third resistor grounded. In this way, the equivalent resistance of the charging management circuit of the electronic device can be used as the third resistor, eliminating the need for additional components in the reset electronics and saving the cost of the reset resistor.

[0017] According to the first aspect, the discharge component includes: a second diode; a second terminal of a first capacitor electrically connected to the second terminal of a third resistor, the third resistor being the equivalent resistance of the charging management circuit in the electronic device; a first terminal of the third resistor grounded and electrically connected to the input terminal of the second diode; and an output terminal of the second diode electrically connected to the first terminal of the first capacitor. In this way, the equivalent resistance of the charging management circuit of the electronic device can be used as the third resistor, eliminating the need for additional components in the reset electronics and saving the cost of the reset resistor.

[0018] According to the first aspect, the reset signal output circuit includes: an N-type metal-oxide-semiconductor (NMOS) transistor; the gate of the NMOS transistor serves as the input terminal of the reset signal output circuit; the drain of the NMOS transistor serves as the output terminal of the reset signal output circuit; and the source of the NMOS transistor is electrically connected to the second terminal of a first resistor. Thus, the reset signal output circuit is implemented using an NMOS transistor, which simplifies the circuit and reduces its cost.

[0019] According to the first aspect, the reset signal output circuit includes: a NOT circuit; the input terminal of the NOT circuit serves as the input terminal of the reset signal output circuit; the output terminal of the NOT circuit serves as the output terminal of the reset signal output circuit. Thus, the reset signal output circuit can employ a NOT circuit, where the input signal and output signal are opposite, triggering the MCU to perform a reset operation.

[0020] According to the first aspect, the reset signal output circuit includes: a comparator; the negative input terminal of the comparator serves as the input terminal of the reset signal output circuit; the positive input terminal of the comparator is electrically connected to a reference voltage, the voltage range of which is 0.5V to 1V; the output terminal of the comparator serves as the output terminal of the reset signal output circuit, wherein the microprocessor's reset terminal is triggered by a low-level signal. Thus, the positive input terminal of the comparator is electrically connected to the reference voltage, and the voltage range of the reference voltage is 0.5V to 1V. That is, when the comparator detects that the voltage at the negative input terminal is less than the voltage at the positive input terminal, it outputs a high-level signal; when the comparator detects that the voltage at the negative input terminal is greater than the voltage at the positive input terminal, it outputs a low-level signal. Since the MCU's reset terminal is triggered by a low-level signal, when the MCU's reset terminal receives a low-level signal, it triggers the MCU to perform a reset operation. Using a comparator as the reset signal output circuit is simple and less prone to false triggering.

[0021] According to the first aspect, the resistance of the fourth resistor is less than the resistance of the first resistor. This means that when the first capacitor charges the second capacitor, the amount of charge consumed by the fourth resistor is greater than the amount consumed by the second capacitor, thus preventing the first capacitor from fully charging the second capacitor on the first attempt.

[0022] According to the first aspect, the duration of the first charging circuit and the charger being electrically connected and disconnected ranges from 1 second to 5 seconds. Thus, if the duration of the first charging circuit and the charger being electrically connected and disconnected exceeds 5 seconds, the reset circuit will take too long to output a reset signal, thus reducing the user experience.

[0023] Secondly, this application provides an electronic device, including: a reset circuit and a microprocessor corresponding to the first aspect and any implementation thereof, wherein the reset signal output terminal of the reset circuit is electrically connected to the reset terminal of the microprocessor.

[0024] According to the second aspect, the electronic device is a smartwatch, smart bracelet, or smart card camera.

[0025] According to the second point, the smartwatch or smart bracelet does not have buttons.

[0026] The second aspect corresponds to the first aspect and any one of its implementations. The technical effects of the second aspect's implementation are similar to those of the first aspect and any one of its implementations, and will not be repeated here. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a schematic diagram illustrating an electronic device;

[0029] Figure 2 This is a schematic diagram of a reset circuit as an example.

[0030] Figure 3 This is a circuit diagram illustrating an exemplary reset circuit;

[0031] Figure 4a This is an exemplary schematic diagram showing the connection between a simulated charger and a smartwatch;

[0032] Figure 4b This is an exemplary schematic diagram showing another type of analog charger connected to a smartwatch;

[0033] Figure 5 This is an exemplary circuit diagram showing a first charging circuit including a second resistor;

[0034] Figure 6 This is an exemplary circuit diagram showing a first charging circuit including a second resistor;

[0035] Figure 7 This is an exemplary circuit diagram that also includes a third resistor in the reset circuit;

[0036] Figure 8 This is an exemplary circuit diagram showing a reset circuit including a comparator;

[0037] Figure 9 This is an exemplary circuit diagram showing a reset circuit including a non-circuit;

[0038] Figure 10 This is an exemplary schematic diagram illustrating the use of an oscilloscope to detect voltage at various locations;

[0039] Figure 11 This is an example showing the waveforms of four detection points in one scenario.

[0040] Figure 12 This is an example showing the waveforms of four detection points in one scenario.

[0041] Figure 13 This is an example showing the waveforms of four detection points in one scenario.

[0042] Figure 14 This is an example showing the waveforms of four detection points in one scenario. Detailed Implementation

[0043] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0044] The electronic device in this application embodiment can be a wearable electronic device, such as a smartwatch or bracelet. Of course, the electronic device can also be other devices, such as a point-and-shoot camera (portable point-and-shoot camera). This application embodiment does not limit the specific form of the electronic device. For ease of explanation, a smartwatch will be used as an example below.

[0045] Figure 1 This is a schematic diagram of an electronic device as an example.

[0046] like Figure 1As shown, the smartwatch 100 may include a motherboard, a display screen, a battery, etc. The motherboard may integrate a microcontroller unit (MCU), internal memory, a charging circuit, etc. Of course, the smartwatch may also include other components, and the motherboard may integrate other circuit structures; this embodiment does not limit this. The charging circuit of the smartwatch includes a power management circuit and a charging management circuit. The power management circuit connects the lithium battery, the charging management circuit, and the microprocessor. The internal memory in the smartwatch can be used to store computer executable program code, which may include instructions. The microprocessor executes various functions and data processing of the phone by running the instructions stored in the internal memory. The microprocessor, internal memory, charging circuit, etc., integrated on the motherboard mentioned above each include one or more chips.

[0047] The charging management circuit is used to receive charging input from the charger. The charger can be a wired charger, and the charging management circuit can receive the charging input from the wired charger via a USB interface.

[0048] The power management circuit receives input from the battery and / or charging management circuit to power microprocessors, internal memory, external memory, displays, and wireless communication modules.

[0049] With the increasing prevalence of smartwatches, a common issue is system crashes due to program malfunctions. A physical button can be incorporated into the smartwatch, allowing the user to press and hold it to send a reset signal to the MCU (Microcontroller Unit), triggering a reset operation. This reset signal can be a signal used to initiate the reset process; for example, a low-level signal triggers a reset operation when received by the MCU's reset pin. However, this reset method relies on a physical button. Figure 1 As shown, Figure 1 The smartwatch in this example does not have physical buttons. Therefore, when the smartwatch malfunctions due to a program crash, a reset signal cannot be generated via a physical button. In one example, since the smartwatch 100 lacks physical buttons, a watchdog circuit can be included. This watchdog chip is electrically connected to the microprocessor in the smartwatch 100. When the smartwatch is operating normally, the MCU periodically sends a feed signal to the input of the watchdog circuit. Upon receiving the feed signal, the watchdog circuit does not output a reset signal. When the MCU freezes, it can no longer send feed signals to the watchdog circuit. Because the watchdog circuit does not receive the feed signal in time, it outputs a reset signal, triggering the MCU to perform a reset operation.

[0050] The high cost of watchdog circuits increases the overall cost of the smartwatch, hindering its widespread adoption. If the smartwatch has physical buttons, a reset signal can be output by the user pressing the button, triggering the MCU to perform a reset operation. However, this method cannot be applied to... Figure 1 The smartwatch shown.

[0051] This application provides a reset circuit whose signal output terminal can be electrically connected to the reset terminal of the MCU in a smartwatch, and whose input terminal is electrically connected to a charger. When the connection between the charger and the reset circuit is repeatedly switched from electrical connection to disconnection, the reset circuit can be triggered to output a reset signal to the MCU's reset terminal, thereby triggering the MCU to perform a reset operation. The reset circuit in this example does not require a watchdog circuit or rely on physical buttons in the electronic device, resulting in low cost and expanding its application scenarios in smartwatches.

[0052] Figure 2 This is a schematic diagram of a reset circuit as an example.

[0053] The smartwatch includes an MCU and a reset circuit. The reset circuit 10 includes a first charging circuit, a second charging circuit 102, and a reset signal output circuit 103. A first terminal of the first charging circuit 102 is connected to a first terminal of the second charging circuit 103. A second terminal of the first charging circuit 102 and a third terminal of the first charging circuit 102 are used for electrical connection to a charger. The second terminal of the first charging circuit 101 can also be connected to the ground of the smartwatch. The second terminal of the second charging circuit 102 is grounded (i.e., electrically connected to the ground of the smartwatch). The first terminal of the second charging circuit 102 is also electrically connected to a first terminal of the reset signal output circuit. The second terminal of the reset signal output circuit 103 is grounded, and the third terminal of the reset signal output circuit 103 is electrically connected to the reset terminal (RESET terminal) of the MCU.

[0054] It should be noted that in this example, grounding refers to the electrical connection of the circuit or component to the ground in the smartwatch.

[0055] The first charging circuit 101 is used to charge the second charging circuit during N consecutive cycles of electrical connection and disconnection with the charger, where N is an integer greater than 1, and the duration of these N consecutive cycles is less than 1 minute. The second charging circuit 102 is used to detect when the voltage reaches a preset threshold within a preset time period, and output a control signal to the reset signal output circuit within that preset time period, which is less than 1 minute. The reset signal output circuit 103 is used to output a reset signal after receiving the control signal, and this reset signal triggers a reset operation in the microprocessor of the electronic device.

[0056] Specifically, when a smartwatch freezes and requires a reset, the user can electrically connect the charger to the second and third terminals of the first charging circuit 101 in the reset circuit, allowing the charger to charge the first charging circuit 101. After a first interval, the user disconnects the charger from the first charging circuit 101. The first interval can be 1 to 10 seconds, such as 1 second, 2 seconds, 5 seconds, 8 seconds, 10 seconds, etc. The user repeats the above steps of connecting the charger to the first charging circuit 101 and disconnecting it after the first interval N times. N is an integer greater than 1, for example, N can be 2, 4, 6, 8, etc.

[0057] The first charging circuit 101 can charge the second charging circuit 102 during N cycles of electrical connection and disconnection from the charger. When the voltage of the second charging circuit 102 reaches a preset threshold, it outputs a control signal to the reset signal output circuit 103. Upon receiving the control signal, the reset signal output circuit 103 outputs a reset signal to the reset terminal of the MCU.

[0058] It should be noted that the second and third terminals of the first charging circuit 101 in the reset circuit can serve as input terminals for the electrical connection between the smartwatch and the charger. Simultaneously, the second and third terminals of the first charging circuit 101 can also serve as input terminals for the charging management circuit in the smartwatch; that is, if... Figure 2 The O1 and O2 terminals are also electrically connected to the input terminals of the charging management circuit.

[0059] In this example, because the charger and the first charging circuit need to be connected and disconnected multiple times, the user's accidental operation that would cause the smartwatch to reset can be avoided. At the same time, this example does not require a watchdog circuit or rely on physical buttons in the smartwatch, which reduces the cost of the smartwatch and increases the application scenarios of the reset circuit.

[0060] Figure 3 This is a circuit diagram illustrating a reset circuit as an example. Figure 3 As shown, the first charging circuit 101 in the reset circuit includes: a first capacitor (such as...) Figure 3 C1), discharge components and first diode (e.g.) Figure 3 The second charging circuit 102 includes: a second capacitor (such as D3 in the circuit). Figure 3 C2) and the first resistor (e.g.) Figure 3 R1 in the example. The reset signal output circuit in this example uses an NMOS transistor (such as R1). Figure 3 Let's take Q1 as an example to illustrate.

[0061] Specifically, the discharge component in the first charging circuit 101 is used to discharge the first capacitor. This discharge component may include one or more resistors, and may also include a resistor and a diode. Optionally, in this example, the discharge component is described using a single resistor as an example, such as... Figure 3 Resistor R4 is shown in the diagram. The first terminal of the first capacitor C1 is electrically connected to the anode of the first diode D3 and the first terminal of resistor R4; the second terminal of resistor R4 is grounded. The cathode of the first diode D3 is electrically connected to the first terminal of the second capacitor C2 and the first terminal of the first resistor R1; the second terminal of the first resistor R1 is grounded; the first terminal of the second capacitor C2 is electrically connected to the gate of NMOS transistor Q1, the drain of NMOS transistor Q1 is electrically connected to the reset terminal of the microprocessor; the source of NMOS transistor Q1 is grounded. The second terminal of the second capacitor C2 is electrically connected to the second terminal of the first resistor R1; wherein, the second terminal of the first capacitor C1 and the second terminal of resistor R4 are used for electrical connection to the charger. In this example, the capacitance values ​​of the first capacitor C1 and the second capacitor C2 can be set according to the actual application. For example, to reduce the charging time of the second capacitor, the capacitance value of the second capacitor is less than the capacitance value of the first capacitor, such as the capacitance value of the first capacitor being 10 microfarads and the capacitance value of the second capacitor being 2.2 microfarads.

[0062] The following is combined with Figure 4a Detailed Explanation Figure 3 The working process of the reset circuit in the middle. Figure 4a This is an example of a schematic diagram showing the connection between an analog charger and a smartwatch.

[0063] like Figure 4a As shown, the battery and resistor R5 are used to simulate a charger. The operation of closing switch S1 is used to simulate the user's action of electrically connecting the charger to the first charging circuit 101, and the operation of opening switch S1 is used to simulate the user's action of disconnecting the charger from the first charging circuit 101. Resistor R3 is used to indicate the equivalent resistance in the charging management circuit of the smartwatch; the second terminal of the third resistor R3 is electrically connected to the second terminal of the first capacitor C1; the first terminal of the third resistor R3 is grounded and electrically connected to the second terminal of resistor R4.

[0064] like Figure 4aAs shown, at time t1, the user electrically connects the charger to the charging input terminal of the smartwatch (i.e., the charger is inserted into the charging port provided in the smartwatch), meaning the charger is electrically connected to the first charging circuit 101 in the reset circuit. At time t1, switch S1 is closed, and the battery charges the first capacitor C1. Since the voltage across the capacitor cannot change abruptly, at the instant switch S1 closes at time t1, the charging voltage is applied to the first terminal of the first capacitor C1, forming a pulse voltage at the first terminal of the first capacitor C1. The pulse voltage formed at the first terminal of the first capacitor C1 charges the second capacitor C2 through the first diode D3. In this example, since the discharge component includes a resistor R4, when the first capacitor C1 charges the second capacitor C2, a portion of the current is diverted to the resistor R4. In this example, when the discharge component includes a resistor R4, the amount of electricity charged to the second capacitor C2 each time can be controlled by the resistor R4, avoiding the problem of fully charging the second capacitor C2 at once. Optionally, the resistance value of resistor R4 is less than the resistance value of the first resistor R1. When the resistance of resistor R4 is less than the resistance of the first capacitor R1, the current flowing to the second capacitor C2 can be further reduced, preventing the second capacitor C2 from being quickly charged. For example, in this example, resistor R4 can be set to 5KΩ, and the first resistor R1 can be greater than resistor R4, such as 10KΩ, 20KΩ, 50KΩ, etc. In this example, the first resistor R1 is set to 5MΩ. As the closing time of switch S1 increases, the voltage across the first capacitor C1 continuously decreases, preventing the first capacitor C1 from continuing to charge the second capacitor C2.

[0065] At time t2, switch S1 is open. Due to the presence of resistor R4 and an equivalent third resistor R3, the first capacitor C1, the third resistor R3, and resistor R4 can form discharge circuit 1: C1—R3—R4—C1. Through the third resistor R3 and resistor R4, the charge in the first capacitor C1 can be released, reducing the voltage between the first and second terminals of the first capacitor C1. At time t2, when switch S1 is open, the second capacitor C2 and the first resistor R1 form discharge circuit 2: C2—R1—C2. Discharge circuit 2 can dissipate the charge on the second capacitor C2, preventing the voltage of the second capacitor from gradually increasing and mistakenly triggering the reset signal output circuit due to prolonged charging by the user. Optionally, a large-value first resistor can be selected to reduce the discharge rate of the second capacitor C2. In this example, the first resistor R1 can be set to a megaohm level value, for example, 5MΩ.

[0066] Meanwhile, the first terminal of the second capacitor C2 is electrically connected to the gate of Q1. Since the charge of the second capacitor C2 is small, its output voltage does not meet the conduction condition of Q1; for example, the initial output voltage of the second capacitor C2 is 0.7V. This does not meet the conduction voltage requirement of the NMOS transistor Q1 (e.g., a conduction voltage of 1.2V), so the NMOS transistor does not conduct. The voltage at the reset terminal of the MCU is high by default.

[0067] Optionally, the turn-on voltage (Vgs, i.e., gate-source voltage) of each NMOS transistor is different. In application, the turn-on voltage of NMOS transistor Q1 can be adjusted by using a voltage divider resistor. Typically, the turn-on condition of an NMOS transistor is a voltage difference of 0.6 to 1.2V between Vgs and Vgs. In this example, a voltage divider resistor is added so that the adjusted turn-on voltage of NMOS transistor Q1 can be 1.2V. Figure 4b A schematic diagram of the reset circuit with added voltage divider resistors is shown. Figure 4b As shown, a new voltage divider resistor R6 is added. The first terminal of the first capacitor C1 is electrically connected to the anode of the first diode D3 and the first terminal of the resistor R4; the second terminal of the resistor R4 is grounded. The cathode of the first diode D3 is electrically connected to the first terminal of the second capacitor C2 and the first terminal of the voltage divider resistor R6; the second terminal of the voltage divider resistor R6 is electrically connected to the gate of the NMOS transistor Q1, and the second terminal of the voltage divider resistor R6 is also electrically connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is grounded, and the second terminal of the second capacitor C2 is grounded. The drain of the NMOS transistor Q1 is electrically connected to the reset terminal of the microprocessor; the source of the NMOS transistor Q1 is grounded. The second terminal of the first capacitor C1 and the second terminal of the resistor R4 are used for electrical connection to the charger. Because of the voltage divider resistor R6, the conduction voltage of the NMOS transistor Q1 can be adjusted; the resistance value of the voltage divider resistor can be the same as the resistance value of the first resistor.

[0068] Optionally, if a voltage divider resistor is provided for the NMOS transistor Q1, the voltage divider resistor can also be used as the discharge resistor for the second capacitor C2, that is, the voltage divider resistor can be used as the first resistor R1.

[0069] In this example, the cathode of the first diode D3 is electrically connected to the first terminal of the second capacitor C2, which also avoids the problem of reverse discharge of the second capacitor C2, preventing it from being charged. The difference between time t1 and time t2 can be in the range of [1, 5]. In this example, the difference between time t1 and time t2 is 1 second. Optionally, as the duration of switch S1 being off increases, the amount of charge stored in the first capacitor C1 decreases, and the voltage across the first capacitor C1 decreases, which is beneficial for the first capacitor C1 to charge the second capacitor C2 in the next cycle.

[0070] At time t3, switch S1 closes again. Since the first capacitor C1 has discharged between times t2 and t3, the voltage between its first and second terminals decreases. At the instant switch S1 closes, the charging voltage is applied again to the first terminal of the first capacitor C1, forming a pulse voltage at that terminal. At time t3, this pulse voltage charges the second capacitor C2 again through the first diode D3. Optionally, the duration between t2 and t3 can be greater than, less than, or equal to the duration between t1 and t2; in this example, no limitation is imposed.

[0071] At time t4, switch S1 is open. Due to the presence of resistor R4 and an equivalent third resistor R3, the first capacitor C1, the third resistor R3, and resistor R4 can form discharge circuit 1: C1—R3—R4—C1. Through resistor R4, the current in the first capacitor C1 can be discharged, thereby reducing the voltage between the first and second terminals of the first capacitor C1. At time t4, when switch S1 is open, the second capacitor C2 and the first resistor R1 form discharge circuit 2: C2—R1—C2.

[0072] In this example, assuming switch S1 is closed and opened four times, the voltage of the second capacitor C2 gradually reaches a preset threshold, which can be the turn-on voltage Vgs of Q1. For example, when switch S1 is closed for the fourth time, the voltage of the second capacitor C2 reaches the turn-on voltage Vgs of NMOS transistor Q1, causing NMOS transistor Q1 to turn on. The drain voltage of the NMOS transistor decreases, meaning the drain of NMOS transistor Q1 outputs a low-level signal. The reset terminal of the MCU receives a low-level reset signal, triggering the MCU to perform a reset operation. In this example, the MCU's reset terminal is triggered by a low-level signal. Because NMOS transistor Q1 is turned on, it continuously consumes the charge in the second capacitor C2, causing the voltage of the second capacitor C2 to continuously decrease. When the voltage input to the gate of NMOS transistor Q1 via the second capacitor C2 is low (i.e., the voltage Vgs is less than the turn-on voltage), the drain voltage of NMOS transistor Q1 changes from low to high again.

[0073] It should be noted that after the fourth closing of switch S1, the electrical connection between switch S1 and the first capacitor C1 can be disconnected after a time interval of t1 to t2. Alternatively, the electrical connection between switch S1 and the first capacitor C1 can remain open.

[0074] The reset circuit in this example is simple. During the continuous connection and disconnection process between the charger and the first charging circuit, the second capacitor is charged. When the voltage of the second capacitor reaches the turn-on voltage of the NMOS transistor, the NMOS transistor Q1 outputs a low level. As the NMOS transistor Q1 turns on, it outputs a reset signal, triggering the MCU to perform a reset operation. The output reset signal of this reset circuit does not depend on physical buttons, and its cost is much lower than that of a watchdog circuit, thus reducing the cost of electronic devices.

[0075] In some embodiments, the first charging circuit 101 may further include a second resistor. The first end of the second resistor is electrically connected to the cathode of the first diode, and the second end of the second resistor is electrically connected to the first end of the second capacitor and the first end of the second resistor. Figure 5 An exemplary circuit diagram is shown, which includes a second resistor in the first charging circuit.

[0076] like Figure 5 As shown, the first charging circuit 101 in the reset circuit includes: a first capacitor (such as...) Figure 5 C1), discharge component, first diode (e.g.) Figure 5 D3 in the middle) and the second resistor (such as D3) Figure 5 The second charging circuit 102 includes: a second capacitor (such as R2 in the circuit). Figure 5 C2) and the first resistor (e.g.) Figure 5 R1 in the example. The reset signal output circuit in this example uses an NMOS transistor (such as R1). Figure 5 Let's take Q1 as an example to illustrate.

[0077] Specifically, the discharge assembly is illustrated using a resistor as an example, such as... Figure 5 Resistor R4 is shown in the diagram. The first terminal of the first capacitor C1 is electrically connected to the anode of the first diode D3 and the first terminal of resistor R4; the second terminal of resistor R4 is grounded. The cathode of the first diode D3 is electrically connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2 and the first terminal of the first resistor R1; the second terminal of the first resistor R1 is grounded; the first terminal of the second capacitor C2 is electrically connected to the gate of the NMOS transistor Q1, the drain of the NMOS transistor Q1 is electrically connected to the reset terminal of the microprocessor; the source of the NMOS transistor Q1 is grounded. The second terminal of the second capacitor C2 is electrically connected to the second terminal of the first resistor R1; wherein, the second terminal of the first capacitor C1 and the second terminal of resistor R4 are used for electrical connection to the charger. Resistor R3 is used to indicate the equivalent resistance in the charging management circuit of the smartwatch. The second terminal of the third resistor R3 is electrically connected to the second terminal of the first capacitor C1; the first terminal of the third resistor R3 is grounded and electrically connected to the second terminal of resistor R4.

[0078] In this example, with Figure 4a Similarly, the battery and resistor R5 are used to simulate the charger, the operation of closing switch S1 is used to simulate the user's action of electrically connecting the charger to the first charging circuit 101, and the operation of opening switch S1 is used to simulate the user's action of disconnecting the charger from the first charging circuit 101.

[0079] At time t1, the user electrically connects the charger to the charging input terminal of the smartwatch, meaning the charger is electrically connected to the first charging circuit 101 in the reset circuit. At time t1, switch S1 closes, and the battery charges the first capacitor C1. At the instant switch S1 closes, a charging voltage is applied to the first terminal of the first capacitor C1, forming a pulse voltage at that terminal. This pulse voltage charges the second capacitor C2 through the first diode D3 and the second resistor R2. In this example, the addition of the second resistor R2 to the first charging circuit 101 increases the resistance of the branch composed of the first diode D3, the second resistor R2, and the first capacitor C1, thereby reducing the current in that branch and controlling the charging speed of the second capacitor C2 by the first capacitor C1. In this example, the second resistor can be set to 120KΩ.

[0080] In addition, since there may be glitches in the pulse voltage generated by the first capacitor C1, which may cause the NMOS transistor Q1 to be falsely triggered, the second resistor R2 can be used to isolate the first capacitor C1 from the NMOS transistor Q1, thus avoiding the problem of the NMOS transistor Q1 being falsely triggered to conduct during the charging process of the first capacitor C1 to the second capacitor C2, and improving the ESD (Electro-Static Discharge) protection performance of the reset circuit.

[0081] In this example, the functions of resistor R4 and the first resistor R1 are the same as... Figure 4a The same function applies; you can refer to it. Figure 4a The relevant descriptions in the text will not be repeated here.

[0082] Figure 5 The process of the reset circuit in the middle opening the switch S1 at time t2 is related to... Figure 4a Similar descriptions can be found in [the relevant text]. Figure 4a The relevant descriptions in [the original text] will not be repeated here. Similarly, Figure 5 The process of the reset circuit generating a reset signal in the middle is as follows: Figure 4a The process of the reset circuit outputting the reset signal is similar and can be referred to... Figure 4a The relevant descriptions in the text will not be repeated here.

[0083] In some embodiments, the first end of the second resistor may also be electrically connected to the first end of the first capacitor, and the second end of the second resistor may be electrically connected to the anode of the first diode. Figure 6 A circuit diagram including a second resistor is shown as an example in the first charging circuit.

[0084] like Figure 6 As shown, the first charging circuit 101 in the reset circuit includes: a first capacitor (such as...) Figure 6 C1), discharge component, first diode (e.g.) Figure 6 D3 in the middle) and the second resistor (such as D3) Figure 6 The second charging circuit 102 includes: a second capacitor (such as R2 in the circuit). Figure 6 C2) and the first resistor (e.g.) Figure 6 R1 in the example. The reset signal output circuit in this example uses an NMOS transistor (such as R1). Figure 6 Let's take Q1 as an example to illustrate.

[0085] Figure 6 The working principle of the reset circuit in Figure 5 The working principle of the reset circuit is the same, which can be found in [reference]. Figure 5 The relevant descriptions in the text will not be repeated here.

[0086] In some embodiments, the discharge assembly includes: a third resistor and a fourth resistor; a first terminal of the fourth resistor is electrically connected to a first terminal of a first capacitor; a second terminal of the fourth resistor is electrically connected to a first terminal of the third resistor; a second terminal of the third resistor is electrically connected to a second terminal of the first capacitor; and a first terminal of the third resistor is grounded. In this example, the discharge assembly includes a third resistor R3 and a fourth resistor R4 for illustration. Figure 7 An exemplary circuit diagram is shown, which also includes a third resistor in the discharge assembly. Figure 7 As shown, the second terminal of the third resistor R3 is electrically connected to the second terminal of the first capacitor C1, and the first terminal of the third resistor R3 is grounded. The first terminal of the first capacitor C1 is electrically connected to the anode of the first diode D3 and the first terminal of the resistor R4; the second terminal of the resistor R4 is grounded. The cathode of the first diode D3 is electrically connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2 and the first terminal of the first resistor R1; the second terminal of the first resistor R1 is grounded; the first terminal of the second capacitor C2 is electrically connected to the gate of the NMOS transistor Q1, the drain of the NMOS transistor Q1 is electrically connected to the reset terminal of the microprocessor; the source of the NMOS transistor Q1 is grounded. The second terminal of the second capacitor C2 is electrically connected to the second terminal of the first resistor R1; wherein, the second terminals of the first capacitor C1 and the second terminals of the resistor R4 are used for electrical connection to the charger.

[0087] In this example, the third resistor R3 can discharge the first capacitor C1 when the charger disconnects from the first capacitor C1, which can further improve the discharge speed of the first capacitor C1 and ensure that the first capacitor C1 can continue to charge the second capacitor C2 when the charger is connected to the first capacitor C1 again.

[0088] At time t1, the user electrically connects the charger to the charging input terminal of the smartwatch, meaning the charger is electrically connected to the first charging circuit 101 in the reset circuit. At time t1, the instant switch S1 closes, a charging voltage is applied to the first terminal of the first capacitor C1, forming a pulse voltage at the first terminal of the first capacitor C1. This pulse voltage charges the second capacitor C2 through the first diode D3 and the second resistor R2. In this example, the resistor R4 can be set to 5KΩ, and the first resistor R1 can be set to 5MΩ. As the duration of switch S1's closure increases, a voltage gradually forms across the first capacitor C1, and the second capacitor C2 is no longer charged.

[0089] In this example, when the charger is charging the first capacitor C1, some current flows through the fourth resistor, which can reduce the charging voltage of the first capacitor and also prevent the first capacitor C1 from quickly charging the second capacitor C2 or accidentally triggering the NMOS transistor Q1 to conduct.

[0090] At time t2, switch S1 is open. Due to the presence of resistor R4 and the third resistor R3, discharge circuit 1 is formed: C1—R3—R4—C1. Resistors R4 and R3 accelerate the discharge of charge from the first capacitor C1, thereby reducing the voltage between the first and second terminals of C1. At time t2, when switch S1 is open, the second capacitor C2 and the first resistor R1 form discharge circuit 2: C2—R1—C2. Discharge circuit 2 can dissipate the charge on the second capacitor C2. Optionally, the resistance of the third resistor R3 can be the same as that of resistor R4, such as 5KΩ.

[0091] Figure 6 The process of the reset circuit generating a reset signal in the middle is as follows: Figure 4a The process of the reset circuit outputting the reset signal is similar and can be referred to... Figure 4a The relevant descriptions in the text will not be repeated here.

[0092] In some embodiments, the discharge component may further include a third resistor R3 and a second diode D4. The anode of the second diode D4 is grounded, and the cathode of the second diode D4 is electrically connected to the first terminal of the first capacitor C1. The second diode D4 can discharge the first capacitor C1 when the charger is disconnected from the first capacitor C1, thus preventing a negative voltage from appearing at the first terminal of the first capacitor C1. The structure of the reset circuit is as follows: Figure 8 As shown.

[0093] The first charging circuit 101 in the reset circuit includes: a first capacitor (such as...) Figure 8 C1), discharge component, first diode (e.g.) Figure 8 D3 in the middle) and the second resistor (such as D3) Figure 8 The second charging circuit 102 includes: a second capacitor (such as R2 in the circuit). Figure 8 C2) and the first resistor (e.g.) Figure 8 R1 in the example. The reset signal output circuit in this example uses a comparator (such as R1). Figure 8 Let's take Q1 as an example to illustrate.

[0094] Specifically, the second terminal of the third resistor R3 is electrically connected to the second terminal of the first capacitor C1, and the first terminal of the third resistor R3 is grounded. The first terminal of the first capacitor C1 is electrically connected to the anode of the first diode D3 and the cathode of the second diode D4; the anode of the second diode D4 is electrically connected to the first terminal of the third resistor R3. The cathode of the first diode D3 is electrically connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2 and the first terminal of the first resistor R1; the second terminal of the first resistor R1 is grounded; the first terminal of the second capacitor C2 is electrically connected to the negative input terminal of the comparator 103. The second terminal of the second capacitor C2 is electrically connected to the second terminal of the first resistor R1. The positive input terminal of the comparator 103 is electrically connected to the reference voltage Vref, and the output terminal of the comparator 103 is electrically connected to the reset terminal of the MCU. This reference voltage can be provided by a device in the smartwatch that meets the voltage value of the reference voltage, and the voltage value range of the reference voltage is 0.5V to 1V. The first and second terminals of the third resistor R3 can be used for electrical connection to the charger.

[0095] The working process of this reset circuit is explained in detail below.

[0096] At time t5, the user electrically connects the charger to the charging input terminal of the smartwatch, meaning the charger is electrically connected to the first charging circuit 101 in the reset circuit. At time t5, switch S1 closes. At the instant switch S1 closes, a charging voltage is applied to the first terminal of the first capacitor C1, forming a pulse voltage at that terminal. This pulse voltage charges the second capacitor C2 through the first diode D3 and the second resistor R2. In this example, because the diode is a unidirectional conductor, when the first capacitor C1 charges the second capacitor C2, all current flows to the second capacitor C2.

[0097] The negative input terminal of comparator 103 is electrically connected to the second terminal of the second resistor R2. The comparator detects the voltage at the negative input terminal and compares it with the reference voltage. If the voltage at the negative input terminal is less than the reference voltage, the output terminal of the comparator outputs a high level.

[0098] At time t6, switch S1 is open. Due to the presence of the second diode D4, discharge circuit 1 is formed: C1 — R3 — D4 — C1. Through the second diode D4 and the third resistor R3, the charge in the first capacitor C1 can be discharged, thereby reducing the voltage between the first and second terminals of the first capacitor C1. At time t6, when switch S1 is open, the second capacitor C2 and the first resistor R1 form discharge circuit 2: C2 — R1 — C2. Discharge circuit 2 can dissipate the charge on the second capacitor C2.

[0099] Meanwhile, the first terminal of the second capacitor C2 is electrically connected to the negative input terminal of comparator 103. The voltage value output by the second capacitor C2 is small. If the comparator detects that the voltage at the negative input terminal is less than the reference voltage, then comparator 103 outputs a high level. In this example, the reference voltage can be 0.7V.

[0100] As the duration of switch S1 being off increases, the third resistor R3 and the second diode D4 consume the stored charge in the first capacitor C1, reducing the voltage across the first capacitor C1, which is beneficial for charging the second capacitor C2 next time.

[0101] At time t7, switch S1 closes again. Since the first capacitor C1 discharged between times t6 and t7, the voltage between its first and second terminals decreases. At the instant switch S1 closes, the charging voltage is applied again to the first terminal of the first capacitor C1, forming a pulse voltage at that terminal. At time t7, this pulse voltage charges the second capacitor C2 again through the first diode D3 and the second resistor R2. Optionally, the time between t6 and t7 can be longer than the time between t5 and t6.

[0102] At time t8, switch S1 is open. Due to the presence of the second diode D4, discharge circuit 1 is formed: C1—R3—D4—C1. Through the second diode D4 and the third resistor R3, the charge in the first capacitor C1 can be discharged, thereby reducing the voltage between the first and second terminals of the first capacitor C1. At time t8, when switch S1 is open, the second capacitor C2 and the first resistor R1 form discharge circuit 2: C2—R1—C2.

[0103] In this example, assuming switch S1 has undergone four operations from closed to open, the voltage of the second capacitor C2 reaches a preset threshold, which can be a value greater than a reference voltage (e.g., a preset threshold of 0.8V). The comparator compares the voltage at its negative input terminal with the reference voltage. If the voltage at the negative input terminal is higher than the reference voltage, the comparator outputs a low-level signal. The MCU's reset terminal receives a low-level reset signal, triggering the MCU to perform a reset operation. In this example, the reset signal at the MCU's reset terminal is a low-level signal. As the charge on the second capacitor C2 decreases, when the comparator detects that the voltage at the negative input terminal is less than the reference voltage, the comparator outputs a high-level signal.

[0104] It should be noted that this comparator can use existing comparator circuits or comparator chips.

[0105] In some embodiments, the reset signal output circuit 103 can also be a NOT circuit, with the input terminal of the NOT circuit electrically connected to the first terminal of the second capacitor, and the output terminal of the NOT circuit 103 electrically connected to the reset terminal of the MCU.

[0106] The first charging circuit 101 in the reset circuit includes: a first capacitor (such as...) Figure 9 C1), discharge component, first diode (e.g.) Figure 9 D3 in the middle) and the second resistor (such as D3) Figure 9 The second charging circuit 102 includes: a second capacitor (such as R2 in the circuit). Figure 9 C2) and the first resistor (e.g.) Figure 9 (R1 in the diagram). The reset signal output circuit 103 can be a NOT circuit, and the NOT circuit 103 can be an inverter.

[0107] Specifically, the second terminal of the third resistor R3 is electrically connected to the second terminal of the first capacitor C1, and the first terminal of the third resistor R3 is grounded. The first terminal of the first capacitor C1 is electrically connected to the anode of the first diode D3 and the cathode of the second diode D4; the anode of the second diode D4 is electrically connected to the first terminal of the third resistor R3. The cathode of the first diode D3 is electrically connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2 and the first terminal of the first resistor R1; the second terminal of the first resistor R1 is grounded; the first terminal of the second capacitor C2 is electrically connected to the input terminal of the NOT circuit 103. The second terminal of the second capacitor C2 is electrically connected to the second terminal of the first resistor R1. The output terminal of the NOT circuit 103 is electrically connected to the reset terminal of the MCU.

[0108] The working process of this reset circuit is explained in detail below.

[0109] At time t5, the user electrically connects the charger to the charging input terminal of the smartwatch, meaning the charger is electrically connected to the first charging circuit 101 in the reset circuit. At time t5, the instant switch S1 closes, a charging voltage is applied to the first terminal of the first capacitor C1, forming a pulse voltage at the first terminal of the first capacitor C1. This pulse voltage charges the second capacitor C2 through the first diode D3 and the second resistor R2. In this example, since the second diode D4 is a unidirectional conducting device, when the first capacitor C1 charges the second capacitor C2, the current flows entirely to the second capacitor.

[0110] The input terminal of the non-circuit 103 is electrically connected to the second terminal of the second resistor R2 and the first terminal of the second capacitor C2. When the voltage obtained by the non-circuit 103 is lower than a preset threshold (e.g., the preset threshold is 0.7V), the non-circuit 103 outputs a high level. In this example, the high level can be 2 to 5V.

[0111] At time t6, switch S1 is open. Due to the presence of the second diode D4, discharge circuit 1 is formed: C1 — R3 — D4 — C1. Through the second diode D4 and the third resistor R3, the charge in the first capacitor C1 can be discharged, thereby reducing the voltage between the first and second terminals of the first capacitor C1. At time t6, when switch S1 is open, the second capacitor C2 and the first resistor R1 form discharge circuit 2: C2 — R1 — C2. Discharge circuit 2 can dissipate the charge on the second capacitor C2.

[0112] Meanwhile, the first terminal of the second capacitor C2 is electrically connected to the input terminal of the non-circuit 103. The second capacitor C2 has a small charge and a small output voltage. For example, if the output voltage is 0.25V, the non-circuit 103 will output a high level.

[0113] As the duration of switch S1 being off increases, the third resistor R3 and the second diode D4 consume the stored charge in the first capacitor C1, reducing the voltage across the first capacitor C1, which is beneficial for charging the second capacitor C2 next time.

[0114] At time t7, switch S1 closes again. Since the first capacitor C1 discharged between times t6 and t7, the voltage between its first and second terminals decreases. At the instant switch S1 closes, the charging voltage is applied again to the first terminal of the first capacitor C1, forming a pulse voltage at that terminal. At time t7, this pulse voltage charges the second capacitor C2 again through the first diode D3 and the second resistor R2. Optionally, the time between t6 and t7 can be longer than the time between t5 and t6.

[0115] At time t8, switch S1 is open. Due to the presence of the second diode D4, discharge circuit 1 is formed: C1—R3—D4—C1. Through the second diode D4 and R3, the charge in the first capacitor C1 can be discharged, thereby reducing the voltage between the first and second terminals of the first capacitor C1. At time t8, when switch S1 is open, the second capacitor C2 and the first resistor R1 form discharge circuit 2: C2—R1—C2.

[0116] In this example, assuming switch S1 has undergone four operations from closed to open, the voltage of the second capacitor C2 exceeds a preset threshold (e.g., 0.7V). The NOT circuit detects that the voltage at the input terminal is 1V, which is greater than the preset threshold. The output terminal of the NOT circuit 103 outputs a low level (the low level signal ranges from 0 to 0.25V), triggering the MCU to perform a reset operation. In this example, the reset signal at the MCU's reset terminal is a low level signal. When the comparator detects that the voltage at the negative input terminal is less than the reference voltage, the comparator outputs a high level signal.

[0117] Figure 10 This is an illustrative diagram showing the use of an oscilloscope to detect voltage at various locations.

[0118] The first charging circuit 101 in the reset circuit includes: a first capacitor (such as...) Figure 10 C1), discharge component, first diode (e.g.) Figure 10 D3 in the middle) and the second resistor (such as D3) Figure 10 The second charging circuit 102 includes: a second capacitor (such as R2 in the circuit). Figure 10 C2) and the first resistor (e.g.) Figure 10 (R1 in the diagram). The reset signal output circuit 103 is illustrated using an NMOS transistor as an example.

[0119] Specifically, the second terminal of the third resistor R3 is electrically connected to the second terminal of the first capacitor C1, and the first terminal of the third resistor R3 is grounded. The first terminal of the first capacitor C1 is electrically connected to the anode of the first diode D3 and the first terminal of the resistor R4; the second terminal of the resistor R4 is grounded. The cathode of the first diode D3 is electrically connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is electrically connected to the first terminal of the second capacitor C2 and the first terminal of the first resistor R1; the second terminal of the first resistor R1 is grounded; the first terminal of the second capacitor C2 is electrically connected to the gate of the NMOS transistor Q1, the drain of the NMOS transistor Q1 is electrically connected to the reset terminal of the microprocessor; the source of the NMOS transistor Q1 is grounded. The second terminal of the second capacitor C2 is electrically connected to the second terminal of the first resistor R1; wherein, the second terminals of the first capacitor C1 and the second terminals of the resistor R4 are used for electrical connection to the charger.

[0120] Due to the potential capacitance in the charging management circuit of a smartwatch, in this example, a third capacitor C3 is used to simulate the potential capacitance in the charging management circuit. The first terminal of the third capacitor C3 is electrically connected to the first terminal of the third resistor R3, and the second terminal of the third capacitor C3 is grounded.

[0121] In this example, the oscilloscope is a four-channel oscilloscope. Channel A is used to measure the signal input to the charger; the detection point of channel A can be connected between the first terminal of the third capacitor C3 and the second terminal of the third resistor R3. Channel B is used to measure the output signal of the first diode D3; the detection point of channel B can be connected to the cathode of the first diode D3. Channel C is used to measure the gate voltage of the NMOS transistor; the detection point of channel C can be connected to the gate of the NMOS transistor Q1. Channel D is used to measure the drain voltage of the NMOS transistor; the detection point of channel D can be connected to the drain of the NMOS transistor Q1. The gate (G) terminal of the oscilloscope is grounded.

[0122] Figures 11-14 The waveforms of four detection points under different scenarios are shown.

[0123] Figure 11 The waveforms at four detection points are shown as an example, assuming that the duration of electrical connection between the charger and the first charging circuit is longer than the duration of disconnection between the charger and the first charging circuit.

[0124] Specifically, such as Figure 11 As shown, the horizontal axis indicates time, with each division representing 1 second; the vertical axis indicates voltage, where the voltage per division (Div) differs for different detection points. In this example, each division (Div) in the waveform of the detection point in channel A represents 5V; each division (Div) in the waveform of the detection point in channel B represents 5V; each division (Div) in the waveform of the detection point in channel C represents 1V; and each division (Div) in the waveform of the detection point in channel D represents 5V. Figure 11 As shown, the charger's initial electrical connection with the first capacitor in the smartwatch lasts for 0.7 seconds. After 0.7 seconds, the user disconnects the charger from the first capacitor, with the disconnection time being less than 0.7 seconds (e.g., 0.05 seconds). From Figure 11 As can be seen, when the charger goes through a process of being electrically connected to and disconnected from the first capacitor, the voltage at the second terminal (i.e., the gate voltage) of the second capacitor C2 increases. After the charger goes through eight repeated processes of being electrically connected to and disconnected from the first capacitor, the gate voltage of the NMOS transistor Q1 continuously increases through this reset circuit, reaching the turn-on voltage of the NMOS transistor Q1 (e.g., 1.2V) at 7.3 seconds. At this point, the drain of the NMOS transistor Q1 outputs a reset signal (e.g., ...). Figure 11(As shown by the thin solid line in the image), thereby triggering the MCU to perform a reset operation.

[0125] Figure 11 If the charger is disconnected from the first capacitor C1 for a short period of time, the first capacitor C1 will not discharge sufficiently, increasing the number of times the charger is plugged in and unplugged.

[0126] Figure 12 The waveforms at four detection points are shown as an example, assuming that the duration of electrical connection between the charger and the first charging circuit is less than the duration of disconnection between the charger and the first charging circuit.

[0127] Specifically, such as Figure 12 As shown, the horizontal axis indicates time, with each division representing 1 second; the vertical axis indicates voltage, where the voltage per division (Div) differs for different detection points. In this example, each division (Div) in the waveform of the detection point in channel A represents 5V; each division (Div) in the waveform of the detection point in channel B represents 5V; each division (Div) in the waveform of the detection point in channel C represents 1V; and each division (Div) in the waveform of the detection point in channel D represents 5V. Figure 12 As shown, the charger's initial electrical connection with the first capacitor in the smartwatch lasts for 0.2 seconds. After 0.2 seconds, the user disconnects the charger from the first capacitor, and the disconnection time is greater than 0.2 seconds (e.g., 0.8 seconds). From Figure 12 As can be seen, when the charger goes through a process of being electrically connected to and disconnected from the first capacitor, the voltage at the second terminal (i.e., the gate voltage) of the second capacitor C2 increases. After the charger goes through four repeated processes of being electrically connected to and disconnected from the first capacitor, the gate voltage of the NMOS transistor Q1 continuously increases through this reset circuit, reaching the turn-on voltage of the NMOS transistor Q1 (e.g., 1.2V) at 4.2 seconds. The drain of the NMOS transistor Q1 then outputs a reset signal (e.g.,...). Figure 12 (As shown by the thin solid line in the image), thereby triggering the MCU to perform a reset operation.

[0128] It should be noted that in this example, after the voltage output by the second capacitor reaches the preset threshold, the charger continues to repeatedly connect and disconnect from the first capacitor, meaning the first capacitor continues to charge the second capacitor. Figure 12 After 4.2 seconds, the drain of the NMOS transistor outputs a low-level signal.

[0129] Figure 13 The waveforms at four detection points are shown as an example, assuming that the duration of electrical connection between the charger and the first charging circuit is equal to the duration of disconnection between the charger and the first charging circuit.

[0130] Specifically, such as Figure 13As shown, the horizontal axis indicates time, with each division representing 1 second; the vertical axis indicates voltage, where the voltage per division (Div) differs for different detection points. In this example, each division (Div) in the waveform of the detection point in channel A represents 5V; each division (Div) in the waveform of the detection point in channel B represents 5V; each division (Div) in the waveform of the detection point in channel C represents 1V; and each division (Div) in the waveform of the detection point in channel D represents 5V. Figure 13 As shown, the charger's second electrical connection with the first capacitor in the smartwatch lasts for 0.5 seconds. After 0.5 seconds, the user disconnects the charger from the first capacitor, with the disconnection time being equal to 0.5 seconds (e.g., 0.5 seconds). From Figure 13 As can be seen, when the charger goes through the second process of being electrically connected to and disconnected from the first capacitor, the voltage at the second terminal (i.e., the gate voltage) of the second capacitor C2 increases. Starting from the second time, the charger undergoes four repeated operations of being electrically connected to and disconnected from the first capacitor. The gate voltage of the NMOS transistor Q1 in the reset circuit continuously increases, reaching the turn-on voltage of NMOS transistor Q1 (e.g., 1.2V) at 5.4 seconds. At this point, the drain of NMOS transistor Q1 outputs a reset signal (e.g.,...). Figure 13 (As shown by the thin solid line in the image), thereby triggering the MCU to perform a reset operation.

[0131] Figure 14 The waveforms at four detection points are shown as an example, where the charger and the first charging circuit are electrically connected m times in 1 second, and m is an integer greater than 2.

[0132] Specifically, such as Figure 14 As shown, the horizontal axis indicates time, with each division representing 1 second; the vertical axis indicates voltage, where the voltage per division (Div) differs for different detection points. In this example, each division (Div) in the waveform of the detection point in channel A represents 5V; each division (Div) in the waveform of the detection point in channel B represents 5V; each division (Div) in the waveform of the detection point in channel C represents 1V; and each division (Div) in the waveform of the detection point in channel D represents 5V. Figure 14 As shown, within one second, the charger connects to the first capacitor in the smartwatch four times, and the drain of the NMOS transistor Q1 outputs a reset signal (such as...). Figure 14 (As shown by the thin solid line in the image), thereby triggering the MCU to perform a reset operation.

[0133] The rapid electrical connection and disconnection between the charger and the first charging circuit, such as the charger connecting and disconnecting the first charging circuit m times per second, where m is an integer greater than 2, makes the output reset signal more stable and has strong anti-interference ability.

[0134] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0135] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0136] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0137] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0138] Any content in the various embodiments of this application, as well as any content in the same embodiment, can be freely combined. Any combination of the above content is within the scope of this application.

[0139] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A reset circuit, characterized in that, The reset circuit, which is installed in an electronic device, includes: a first charging circuit, a second charging circuit, and a reset signal output circuit; The first charging circuit is used to charge the second charging circuit N times consecutively. Each charging operation includes: the first charging circuit and the charger are electrically connected and disconnected, where N is an integer greater than 1, and the duration of the N consecutive charging operations for the second charging circuit is less than 1 minute. The first charging circuit includes: a first capacitor, a discharge component, and a first diode; when the discharge component has three connection terminals, the first terminal of the first capacitor is electrically connected to the anode of the first diode and the first terminal of the discharge component, the second terminal of the discharge component is grounded, and the third terminal of the discharge component is electrically connected to the second terminal of the first capacitor; when the discharge component has two connection terminals, the first terminal of the first capacitor is electrically connected to the anode of the first diode and the first terminal of the discharge component, and the second terminal of the discharge component is grounded; wherein, the cathode of the first diode serves as the output terminal of the first charging circuit, and the second terminal of the first capacitor and the second terminal of the discharge component are used for electrical connection with the charger; The second charging circuit is used to output a control signal to the reset signal output circuit during the period when the first charging circuit and the charger are switched from disconnected to connected. The reset signal output circuit is used to output a reset signal when the voltage value of the control signal exceeds a preset threshold. The reset signal is used to trigger the microprocessor in the electronic device to perform a reset operation. The second charging circuit includes: a second capacitor and a first resistor; the capacitance value of the second capacitor is smaller than the capacitance value of the first capacitor; The cathode of the first diode is electrically connected to the first terminal of the second capacitor and the first terminal of the first resistor; The first terminal of the second capacitor is electrically connected to the input terminal of the reset signal output circuit; The second terminal of the second capacitor is electrically connected to the second terminal of the first resistor; The second terminal of the first resistor is grounded; The output terminal of the reset signal output circuit is electrically connected to the reset terminal of the microprocessor.

2. The reset circuit according to claim 1, characterized in that, When the discharge component includes three connection terminals, the first charging circuit further includes: a second resistor; The first end of the second resistor is electrically connected to the cathode of the first diode, and the second end of the second resistor is electrically connected to the first end of the second capacitor and the first end of the second resistor.

3. The reset circuit according to claim 1, characterized in that, When the discharge component includes three connection terminals, the first charging circuit further includes: a second resistor; The first end of the second resistor is electrically connected to the first end of the first capacitor, and the second end of the second resistor is electrically connected to the anode of the first diode.

4. The reset circuit according to claim 1, characterized in that, When the discharge assembly includes three connection terminals, the discharge assembly includes: a third resistor and a fourth resistor; The first terminal of the fourth resistor is electrically connected to the first terminal of the first capacitor. The second end of the fourth resistor is electrically connected to the first end of the third resistor; The second end of the third resistor is electrically connected to the second end of the first capacitor; The first terminal of the third resistor is grounded. Wherein, the first end of the fourth resistor serves as the first end of the discharge component, the first end of the third resistor serves as the second end of the discharge component, and the second end of the third resistor serves as the third end of the discharge component.

5. The reset circuit according to claim 1, characterized in that, When the discharge assembly includes three connection terminals, the discharge assembly includes: a third resistor and a second diode; The second end of the third resistor is electrically connected to the second end of the first capacitor; The first terminal of the third resistor is grounded and electrically connected to the anode of the second diode; The cathode of the second diode is electrically connected to the first terminal of the first capacitor; Wherein, the cathode of the second diode serves as the first terminal of the discharge component, the first terminal of the third resistor serves as the second terminal of the discharge component, and the second terminal of the third resistor serves as the third terminal of the discharge component.

6. The reset circuit according to claim 1, characterized in that, When the discharge assembly includes two connection terminals, the discharge assembly includes: a fourth resistor; The first terminal of the fourth resistor is electrically connected to the first terminal of the first capacitor. The second end of the fourth resistor is electrically connected to the first end of the third resistor, and the third resistor is the equivalent resistance of the charging management circuit in the electronic device. The first terminal of the third resistor is grounded. The second end of the third resistor is electrically connected to the second end of the first capacitor; Wherein, the first end of the fourth resistor serves as the first end of the discharge component, and the second end of the fourth resistor serves as the second end of the discharge component.

7. The reset circuit according to claim 1, characterized in that, When the discharge assembly includes two connection terminals, the discharge assembly includes: a second diode; The second terminal of the first capacitor is electrically connected to the second terminal of the third resistor, which is the equivalent resistance of the charging management circuit in the electronic device; The first terminal of the third resistor is grounded and electrically connected to the input terminal of the second diode; The output terminal of the second diode is electrically connected to the first terminal of the first capacitor; Wherein, the output terminal of the second diode serves as the first terminal of the discharge component, and the input terminal of the second diode serves as the second terminal of the discharge component.

8. The reset circuit according to any one of claims 1 to 7, characterized in that, The reset signal output circuit includes: an N-type metal-oxide-semiconductor NMOS transistor; The gate of the NMOS transistor serves as the input terminal of the reset signal output circuit. The drain of the NMOS transistor serves as the output terminal of the reset signal output circuit. The source of the NMOS transistor is electrically connected to the second terminal of the first resistor.

9. The reset circuit according to any one of claims 1 to 7, characterized in that, The reset signal output circuit includes: a NOT circuit; The input terminal of the non-circuit is used as the input terminal of the reset signal output circuit; The output terminal of the non-circuit is used as the output terminal of the reset signal output circuit.

10. The reset circuit according to any one of claims 1 to 7, characterized in that, The reset signal output circuit includes: a comparator; The negative input terminal of the comparator serves as the input terminal of the reset signal output circuit; The positive input terminal of the comparator is electrically connected to a reference voltage, the voltage range of which is 0.5V to 1V; The output terminal of the comparator serves as the output terminal of the reset signal output circuit, wherein the reset terminal of the microprocessor is triggered by a low-level signal.

11. The reset circuit according to claim 4 or 6, characterized in that, The resistance value of the fourth resistor is less than the resistance value of the first resistor.

12. The reset circuit according to any one of claims 1 to 7, characterized in that, The duration of the first charging circuit and the charger from electrical connection to disconnection ranges from 1 second to 5 seconds.

13. An electronic device, characterized in that, include: The reset circuit and microprocessor as described in any one of claims 1 to 12, wherein the reset signal output terminal of the reset circuit is electrically connected to the reset terminal of the microprocessor.

14. The electronic device according to claim 13, characterized in that, The electronic device is a smartwatch, smart bracelet, or smart card reader.

15. The electronic device according to claim 14, characterized in that, The smartwatch or smart bracelet does not have any buttons.

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