FPGA-based combinatorial optimization solving method and device

Abstract

The application provides a combination optimization solving method and device based on FPGA, and relates to the technical field of computers.The combination optimization solving method based on FPGA comprises the following steps: performing hardware implementation on a previously set simulation bifurcation algorithm on a field programmable logic gate array (FPGA) to obtain a combination optimization problem solver based on FPGA; and solving a previously set combination optimization problem by using the combination optimization problem solver based on FPGA to obtain a combination optimization solving result.The embodiment of the application utilizes the special advantages of an FPGA chip, simulates a bifurcation algorithm through hardware design, and realizes efficient solving of a combination optimization problem, has wide applicability, and can meet the needs of various different fields.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a combinatorial optimization solution method and apparatus based on FPGA. Background Technology

[0002] Combinatorial optimization problems are a typical class of non-deterministic polynomial (NP) difficult problems, such as the Traveling Salesman Problem (TSP), the knapsack problem, scheduling problems, logistics supply problems, and population intention problems in social sciences. These problems require finding optimal solutions under a given set of constraints, where the optimal solution usually refers to minimizing or maximizing a specific objective function.

[0003] Traditional methods for solving combinatorial optimization problems include: Central Processing Unit (CPU) computing, Graphics Processing Unit (GPU) parallel computing, and some emerging technologies such as quantum computers.

[0004] However, traditional methods for solving combinatorial optimization problems may face challenges in certain situations. CPU computing speed may be limited, while GPUs, although offering parallelism, provide limited performance improvements for some complex problems. Quantum computers are still in the research and development stage and have not yet been widely used. There is an urgent need to find an efficient and scalable solution to meet the current demands for solving combinatorial optimization problems. Summary of the Invention

[0005] This invention provides a combinatorial optimization solution method and apparatus based on FPGA, which can solve the problems that traditional combinatorial optimization problem solving methods may face in some cases.

[0006] This invention provides a combinatorial optimization solution method based on FPGA, comprising:

[0007] The pre-set simulated bifurcation algorithm is implemented in hardware on a field-programmable gate array (FPGA) to obtain an FPGA-based combinatorial optimization problem solver.

[0008] The FPGA-based combinatorial optimization problem solver solves a pre-set combinatorial optimization problem and obtains the combinatorial optimization solution result.

[0009] According to the FPGA-based combinatorial optimization problem-solving method provided by the present invention, the step of solving a pre-set combinatorial optimization problem using the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result includes:

[0010] On the FPGA, the pre-set Hamiltonian function H bSB Taking partial derivatives of N variables in parallel yields 2N partial differential equations; among which, the H... bSB Related to the aforementioned combinatorial optimization problem, N is an integer greater than 0, and N represents the number of spins to be solved in the spin glass state problem;

[0011] The combinatorial optimization problem is solved by solving the 2N partial differential equations, and the combinatorial optimization solution is obtained.

[0012] According to the FPGA-based combinatorial optimization solution method provided by the present invention, the combinatorial optimization problem is solved by solving the 2N partial differential equations to obtain the combinatorial optimization solution result, including:

[0013] The optimal solutions to the 2N partial differential equations are determined using the Euler algorithm or an adiabatic evolution algorithm simulating a nonlinear Hamiltonian system, and are used as the combined optimization solution results.

[0014] According to the FPGA-based combinatorial optimization problem-solving method provided by the present invention, before solving the pre-set combinatorial optimization problem through the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result, the method further includes:

[0015] The system receives the optimization function specified by the user through a pre-configured input / output I / O communication interface.

[0016] The step of solving a pre-set combinatorial optimization problem using the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result includes:

[0017] The optimization function in the combinatorial optimization problem is solved by the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result.

[0018] According to the FPGA-based combinatorial optimization solution method provided by the present invention, after solving the pre-set combinatorial optimization problem through the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result, the method further includes:

[0019] The combined optimization solution result is sent to the user through the IO communication interface.

[0020] The combined optimization solution result includes at least one of the intermediate solution result and the final solution result.

[0021] According to the combinatorial optimization solution method based on FPGA provided by the present invention, the method further includes:

[0022] Using a pre-set data storage module, at least one of the following is stored: problem instance, algorithm parameters, intermediate solution results, and final solution result corresponding to the combinatorial optimization problem.

[0023] The present invention also provides an FPGA-based combinatorial optimization solution device, comprising:

[0024] The processing module is used to implement the pre-set simulated bifurcation algorithm in hardware on a field-programmable gate array (FPGA) to obtain an FPGA-based combinatorial optimization problem solver.

[0025] The solution module is used to solve a pre-set combinatorial optimization problem using the FPGA-based combinatorial optimization problem solver, and obtain the combinatorial optimization solution result.

[0026] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the FPGA-based combinatorial optimization solution method described above.

[0027] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the FPGA-based combinatorial optimization solution method as described above.

[0028] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the FPGA-based combinatorial optimization solution method described above.

[0029] This invention provides a combinatorial optimization solution method and apparatus based on FPGA, which combines simulated bifurcation algorithms with FPGA to solve combinatorial optimization problems. Utilizing the parallel computing capabilities of FPGA, it achieves efficient solution of combinatorial optimization problems and accelerates the decision-making process. Leveraging the high customizability of FPGA, hardware design can be tailored to the specific requirements of the combinatorial optimization problem, optimizing it to its specific characteristics. Utilizing the low latency of FPGA, communication time during data transmission can be shortened, enabling faster and more efficient completion of the program's input and output requirements. For real-time applications, such as traffic light optimization or robot path planning, low latency is crucial as it ensures immediate response and decision-making, and the method of this invention is well-suited to this. Utilizing the low power consumption of FPGA, it is suitable for use on mobile devices requiring long-term operation. In many combinatorial optimization problems, long-term computation is necessary, so low power consumption helps reduce energy consumption and heat generation. Furthermore, FPGA can provide hardware acceleration, typically achieving faster computation speeds compared to pure software implementations. FPGA does not necessarily have to be a single FPGA chip; it can also achieve high scalability through FPGA clusters, enabling the handling of large-scale problems. In summary, this invention utilizes the unique advantages of FPGA chips to simulate bifurcation algorithms through hardware design, thereby achieving efficient solutions to combinatorial optimization problems. It has wide applicability and can meet the needs of various fields. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0031] Figure 1 This is one of the flowcharts illustrating the FPGA-based combinatorial optimization solution method provided by the present invention;

[0032] Figure 2 This is a schematic diagram of the solution system used in the FPGA-based combinatorial optimization solution method provided by the present invention;

[0033] Figure 3 This is the second flowchart of the FPGA-based combinatorial optimization solution method provided by the present invention;

[0034] Figure 4 This is a schematic diagram of the FPGA-based combinatorial optimization solving device provided by the present invention;

[0035] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0036] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0037] To facilitate a clearer understanding of the technical solutions provided in the various embodiments of the present invention, some relevant background knowledge is first introduced as follows:

[0038] (I) Detailed description of the simulated bifurcation (SB) algorithm;

[0039] 1) Basic algorithm information:

[0040] The SB algorithm is a heuristic algorithm for accelerating combinatorial optimization problems, inspired by the field of quantum computing. This algorithm is based on a quantum computer model called the quantum bifurcation machine (QbM), which relies on quantum adiabatic optimization and utilizes nonlinear oscillators that exhibit the bifurcation phenomenon in quantum mechanics. Therefore, the core of the SB algorithm is to simulate the bifurcation phenomenon that occurs during the adiabatic evolution of classical nonlinear Hamiltonian systems.

[0041] Unlike traditional simulated annealing (SA) algorithms, the SB algorithm allows for simultaneous updates of variables. This characteristic enables large-scale parallel processing using modern multi-core processors, such as Field Programmable Gate Arrays (FPGAs) and Graphics Processing Units (GPUs), significantly accelerating the solution of combinatorial optimization problems. A single FPGA-based SB machine (SBM) can find a good approximate solution to the 2000-spin Ising problem in 0.5 milliseconds, approximately 10 times faster than traditional Coherent Ising Machines (CIMs). This result demonstrates that the parallelization capability of an algorithm is a key attribute for accelerating optimization algorithms using modern high-performance computing systems.

[0042] The SB algorithm is not based on gradient methods, but rather relies on the adiabatic evolution of energy-conserving systems, similar to pure adiabatic quantum annealing (QA) and QbM. Due to its unique methodology and efficient performance, the SB algorithm shows great potential in solving modern optimization problems, especially in situations requiring the handling of complex combinatorial optimization problems. Furthermore, research in this field includes other parallelizable algorithms, such as methods that map a given problem to a binary problem and apply parallel SA updates to each set of spins. These new algorithms, though different in name, essentially rely on the same mechanisms, such as momentum annealing (MA), stochastic cellular automata annealing (SCA), and parallel random sampling of restricted Boltzmann machines (RBMs).

[0043] 2) Comparison of other optimization algorithms with the SB algorithm:

[0044] [a]SA;

[0045] 1> Principle: SA is inspired by the annealing process in physics. It explores and eventually stabilizes at the global optimum by gradually reducing the system temperature. In the initial high-temperature stage, the system tends to explore a wide range of state spaces, while as the temperature decreases, it gradually tends to fix at a local optimum.

[0046] 2> Applications: The SA algorithm has applications in various optimization problems, such as the traveling salesman problem and the scheduling problem.

[0047] 3. Performance: SA is particularly suitable for small to medium-sized problems. For large-scale problems, its computation time may become too long, affecting efficiency.

[0048] QA;

[0049] 1> Principle: The QA algorithm is based on the principles of quantum mechanics, especially utilizing quantum superposition and tunneling effects to find the optimal solution. This algorithm changes the Hamiltonian of the quantum system, causing the system to gradually evolve from an initial state to the lowest energy state.

[0050] 2> Applications: QA is mainly used to solve specific optimization problems and usually needs to be implemented on quantum computers.

[0051] 3. Performance: In theory, QA can find the global optimum more quickly, especially when dealing with complex problems. However, its performance is limited by the current development of quantum computing technology.

[0052] [c] Swarm Algorithms;

[0053] 1> Principle: Swarm optimization is inspired by the group behavior in nature (such as flocks of birds and ant colonies). It achieves complex swarm intelligence through the interaction and information sharing between individuals, thereby finding the optimal solution.

[0054] 2> Applications: This type of algorithm is applicable to a wide range of optimization problems, including path planning and resource allocation.

[0055] 3> Performance: Swarm optimization algorithms are not very sensitive to initial parameters and can effectively handle large-scale problems. Although they may sometimes get stuck in local optima, they have poor parallelism.

[0056] [d]SB;

[0057] 1> Principle: The SB algorithm draws inspiration from quantum computing, based on simulating the adiabatic evolution process in nonlinear Hamiltonian systems, especially involving bifurcation phenomena. Unlike traditional gradient-based methods, it solves the problem by simulating the adiabatic evolution of energy-conserving systems.

[0058] 2> Applications: The SB algorithm is particularly suitable for solving complex combinatorial optimization problems, such as large-scale Ising problems.

[0059] 3> Performance: A significant advantage of the SB algorithm is its parallelization capability, especially when using modern multi-core processors such as FPGAs and GPUs, which enables SB to significantly improve computation speed when dealing with large-scale problems.

[0060] The following describes the comprehensive comparison results:

[0061] [1] Applicability: SA and swarm optimization are applicable to a wide range of problem types, QA is applicable to specific problems that quantum computers can effectively process, while SB is particularly applicable to large-scale combinatorial optimization problems. In general, the above-mentioned solution algorithms are used to solve combinatorial optimization problems under certain constraints, and the problem can be modeled as the Hamiltonian function of the optimization system, i.e., H(x).

[0062] [2] Computational resources: SA and swarm algorithms can be implemented on traditional computers, QA requires quantum computing resources, while SB is particularly well-suited for modern multi-core processors such as FPGAs and GPUs.

[0063] [3] Efficiency and speed: QA can theoretically find solutions faster through quantum effects, but it is limited by the maturity of technology and the cost of quantum computer equipment. SA is more efficient for small-scale problems, swarm algorithms are suitable for large-scale problems, and SB shows high efficiency in large-scale problems due to its parallelization capability.

[0064] [4] Robustness: Swarm algorithms are generally superior to SA and QA in terms of robustness due to their distributed and adaptive characteristics. SB algorithms also demonstrate robustness in complex environments, especially in parallel computing environments.

[0065] (II) Combinatorial Optimization Problem:

[0066] In real life, combinatorial optimization problems are widespread in business, science, and engineering. These problems typically involve finding the optimal solution under given constraints to maximize or minimize a certain objective function. For example, the Traveling Salesman Problem requires finding the shortest path connecting a set of cities; the traffic light optimization problem involves adjusting traffic signals to minimize traffic congestion. Solving these problems usually requires significant computational resources and time.

[0067] The FPGA-based combinatorial optimization solution method and apparatus of the present invention are described below with reference to the accompanying drawings.

[0068] Figure 1 This is one of the flowcharts illustrating the FPGA-based combinatorial optimization solution method provided by the present invention, such as... Figure 1 As shown, the method includes steps 101 and 102; wherein:

[0069] Step 101: Implement the pre-set simulated bifurcation algorithm in hardware on a field-programmable gate array (FPGA) to obtain an FPGA-based combinatorial optimization problem solver;

[0070] Step 102: Solve the pre-set combinatorial optimization problem using the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result.

[0071] In related technologies, traditional methods for solving combinatorial optimization problems can generally be summarized into three types: first, using existing software solvers; second, utilizing GPUs to accelerate computation; and third, utilizing specific hardware devices such as Application Specific Integrated Circuits (ASICs).

[0072] 1) Software Solvers: Solving most combinatorial optimization problems relies on computer software, such as linear programmers, depth-first search algorithms (e.g., branch and bound), and approximation algorithms. These methods typically run on general-purpose processors and require significant computation time for complex problems. Common solvers include:

[0073] [a]CPLEX (Mathematical Optimization Software) Solver: A commercial solver for linear programming (LP), integer programming (IP), and mixed integer programming (MIP) problems. It features highly optimized solving algorithms and is widely used in industry and research.

[0074] It should be noted that CPLEX was developed by IBM and is specifically designed to solve various mathematical programming problems, including LP, IP, MIP, and other related optimization problems. The full name of CPLEX can be IBM ILOG CPLEX OptimizationStudio.

[0075] [b]Gurobi Solver: Another commercial solver for LP, IP, and MIP problems, it is a strong competitor to CPLEX in terms of performance.

[0076] [c] Boolean Satisfiability Problem (SAT) Solvers: Used to solve the Boolean satisfiability problem, which is an NP-complete problem. Some popular SAT solvers include MiniSat and Z3.

[0077] [d] Continuous Mixed-Integer Programming (CMIP) solvers: Tools for solving continuous mixed-integer programming problems, which combine the characteristics of LP and IP. Some decision variables are continuous real values, while others must take integer values. CMIP problems have wide applications in industry, operations research, logistics, resource allocation, and many other fields.

[0078] 2) GPU acceleration: In recent years, many studies have attempted to use GPUs to accelerate the solution of combinatorial optimization problems. GPUs have parallel processing capabilities, which can improve the speed of problem solving to a certain extent.

[0079] However, GPUs are typically used for general purposes, and not all combinatorial optimization problems can be parallelized. Some combinatorial optimization problems have memory or information dependencies, making it difficult to effectively decompose them into parallel tasks. In addition, the high price of GPUs is also a factor that restricts their development.

[0080] 3) ASICs and specific hardware: For some highly specialized combinatorial optimization problems, one might consider using ASICs or other specific hardware to provide high performance. However, the development and deployment costs of these solutions are usually high, and they are not suitable for a wide range of problem domains.

[0081] In summary, the relevant technologies mainly have the following drawbacks:

[0082] 1) Computation time: Software solvers running on general-purpose processors typically require a significant amount of computation time to process complex combinatorial optimization problems, which can pose a constraint in real-time applications that require rapid decision-making.

[0083] 2) Energy efficiency: The combination of software and general hardware to optimize problem solvers usually consumes a lot of energy when dealing with complex problems, and is not suitable for low-power applications.

[0084] 3) Hardware resource limitations: General-purpose processors and GPUs may encounter performance bottlenecks when dealing with large-scale problems, making it difficult to achieve high scalability.

[0085] 4) Customization: Existing general-purpose hardware and software solvers often lack a high degree of customization for specific problems, and therefore may not achieve optimal performance.

[0086] To address the aforementioned problems, this invention provides a combinatorial optimization solution method based on FPGA. The main technical concept is to utilize the unique advantages of FPGA chips and simulate a bifurcation algorithm through hardware design to achieve efficient solutions to combinatorial optimization problems.

[0087] Specifically, in this embodiment of the invention, a pre-set simulated bifurcation algorithm is first implemented in hardware on an FPGA to obtain an FPGA-based combinatorial optimization problem solver. Then, the pre-set combinatorial optimization problem is solved by the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result, thereby achieving efficient solution of the combinatorial optimization problem.

[0088] The potential advantages of using FPGAs to solve combinatorial optimization problems are explained below:

[0089] 1> High degree of customization: FPGAs allow designers to customize hardware to meet the needs of specific problems, thereby achieving highly optimized solutions.

[0090] 2> Parallel performance: FPGA has parallel processing capabilities, which can process multiple problem instances simultaneously, improving the solution speed.

[0091] 3> Low latency: FPGAs typically have low latency, making them suitable for both real-time and low-latency applications.

[0092] 4> Energy efficiency: FPGAs can be optimized to address problems and provide low-power solutions.

[0093] 5> Hardware resource limitations: FPGA clusters can be used to handle large-scale problems, breaking through the performance limits of hardware resources.

[0094] 6> Hardware acceleration: FPGA provides hardware acceleration, which is usually faster and more energy-efficient than software implementation.

[0095] In some embodiments, the simulated bifurcation algorithm is combined with an FPGA to solve combinatorial optimization problems. The specific implementation can be divided into two parts: hardware design and software algorithm implementation.

[0096] (I) Hardware Design: When implementing an FPGA-based combinatorial optimization problem solver, the first step is hardware design, which mainly includes the following key aspects:

[0097] 1) FPGA Selection: It is necessary to select an FPGA chip model and specifications suitable for solving the problem. The different characteristics of FPGA chips have been introduced above. Since different FPGA chips have different resource and performance characteristics, it is necessary to select a suitable FPGA based on the complexity of the problem and the requirements of the solution.

[0098] 2) Circuit design: Develop problem-specific circuits to perform forking, merging, and selection operations. This may involve the layout and interconnection of circuit elements such as logic gates, registers, clock controllers, etc.

[0099] 3) Power supply: Ensure a stable power supply to prevent power fluctuations from interfering with system operation.

[0100] (II) Algorithm Implementation: The simulated bifurcation algorithm is implemented on the FPGA, mainly including the following steps:

[0101] 1) FPGA Hardware Description Language Selection: Use a hardware description language to write the hardware design description of the FPGA. Hardware description languages ​​include, for example, Very-High-Speed ​​Integrated Circuit Hardware Description Language (VHDL) or Verilog.

[0102] 2) Initialize parameters: Set the initial parameters of the algorithm, including temperature, cooling rate, etc. These parameters can be adjusted according to the characteristics of the problem.

[0103] 3) Parallel computing: Utilizing the parallel computing capabilities of FPGAs, multiple problem instances or multiple solution steps can be processed simultaneously, which is mainly achieved through parallel hardware design.

[0104] 4) Simulated forking: Perform simulated forking operations on the FPGA, i.e. generate different solutions to the problem instance and evaluate their quality.

[0105] 5) Simulated merging: Merge different solutions to select the best one.

[0106] 6) Result feedback: The optimal solution or near-optimal solution is fed back to the user or other devices, which can be done through the IO communication interface in the IO communication module.

[0107] 7) I / O Communication Interface Implementation: Provides a communication interface between the user and the system, allowing interaction through a graphical user interface (GUI) or a command-line interface (CLI). Users can use the interface to specify problem instances, begin solving, and retrieve results.

[0108] 8) Data storage: Use the data storage module to save problem instances, algorithm parameters, intermediate results, and final solutions. This facilitates problem tracking and result analysis.

[0109] 9) Results Output: Provides a results output interface, allowing users or other devices to read and use the results of the solved combinatorial optimization problem. This can include the optimal solution, the quality index of the solution, and other relevant information.

[0110] It should be noted that the FPGA is the hardware carrier for algorithm implementation. The algorithm implementation process involves mapping and optimizing the FPGA resources (such as lookup tables, registers, and RAM blocks) to ensure efficient use of FPGA resources while avoiding bottlenecks such as excessively high clock frequencies or resource contention.

[0111] In the FPGA-based combinatorial optimization solution method provided in this invention embodiment, the simulated bifurcation algorithm is combined with FPGA to solve combinatorial optimization problems. Utilizing the parallel computing capabilities of FPGA, efficient solutions to combinatorial optimization problems are achieved, accelerating the decision-making process. The high customizability of FPGA allows for hardware design tailored to the specific requirements of a particular combinatorial optimization problem, optimizing it to its specific characteristics. The low latency of FPGA shortens communication time during data transmission, enabling faster and more efficient completion of program inputs and outputs. For real-time applications, such as traffic light optimization or robot path planning, low latency is crucial as it ensures immediate response and decision-making, and the method of this invention is well-suited to this. The low power consumption of FPGA makes it suitable for use on mobile devices requiring long-term operation. In many combinatorial optimization problems, long computation times are necessary, so low power consumption helps reduce energy consumption and heat generation. Furthermore, FPGA can provide hardware acceleration, typically achieving faster computation speeds compared to pure software implementations. An FPGA is not necessarily a standalone chip; it can also achieve high scalability through FPGA clusters, enabling the handling of large-scale problems. In summary, this invention utilizes the unique advantages of FPGA chips to simulate bifurcation algorithms through hardware design, thereby achieving efficient solutions to combinatorial optimization problems. It has wide applicability and can meet the needs of various fields.

[0112] Optionally, the method of solving the pre-set combinatorial optimization problem using the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result may include:

[0113] On the FPGA, the pre-set Hamiltonian function H bSB Taking partial derivatives of N variables in parallel yields 2N partial differential equations; among which, the H... bSB Related to the aforementioned combinatorial optimization problem, N is an integer greater than 0, and N represents the number of spins to be solved in the spin glass state problem;

[0114] The combinatorial optimization problem is solved by solving the 2N partial differential equations, and the combinatorial optimization solution is obtained.

[0115] In some embodiments, considering the generalizability and implementability of the problem, the accelerated SB (ballistic SB, bSB) algorithm can be used as an improvement basis:

[0116]

[0117]

[0118]

[0119]

[0120] This process is based on a set of dynamic equations that simulate how the system evolves to an optimal state over time.

[0121] Where, x S and y S These are the two components of the system state, representing the position and momentum of each spin (analogy). a0 is a system parameter, while a(t) is a time-varying parameter used to control the "adiabatic" evolution of the system. c0 is the coupling constant, j i,j This represents the interaction between spins i and j. The Hamiltonian function H... bSB In, for all x i In other words, through V bSB The result obtained by the calculation formula is |x i The potential energy of the system is V when |≤1, otherwise V bSB =∞. Potential energy term V bSB This includes the interactions between spins and their individual contributions, when |x i When |>1, the potential energy tends to be infinite, which means that the state of the system is restricted to a certain range.

[0122] The above formula illustrates how a system controlled by a variable parameter a(t) evolves within a potential energy landscape. The SB algorithm seeks the optimal state of the system, i.e., the state with the lowest potential energy, through this dynamic evolution process.

[0123] In terms of parallel efficiency, the SB algorithm is very efficient in parallel computing because... and The calculations can be performed independently. The formula in the figure shows that each x... i partial derivatives of nodes and It can compute simultaneously without waiting for results from other nodes. This independence is a key characteristic of parallel computing because it allows algorithms to execute concurrently on multiple processors or processing units, each processing a single x. i and y i And without any synchronization operation.

[0124] On parallel hardware like FPGAs, this means that derivatives can be computed simultaneously for thousands of spin nodes, greatly accelerating the process of finding the optimal solution. FPGAs can perform these computations in parallel using their large number of logic units, which significantly reduces the total computation time required compared to performing them on a serial processor, thus achieving the goal of quickly solving optimization problems.

[0125] However, the aforementioned algorithm is primarily used to solve the Ising problem, and its limitation is that it can only handle binary spin values. This limitation means that the algorithm may not be efficient enough when dealing with broader and more complex optimization problems. To address this issue, this invention generalizes the simulated bifurcation algorithm to handle spin glass state problems, which have a wider state space and require the algorithm to handle independent variables with multiple values. In spin glass state problems, independent variables can take many different values, rather than being limited to the two states in the Ising model.

[0126] Generally, in this embodiment of the invention, a series of binary spins in the Ising problem simulation bifurcation algorithm are extended to multi-valued spins in the spin glass state problem. That is, the above formulas (1) and (2) are extended to take the partial derivatives with respect to each variable. Taking a spin glass state system with 4 spin entanglement (a total of 16 solution states) as an example, that is, taking N equal to 4 as an example, the equations can be extended as follows:

[0127]

[0128] In this embodiment of the invention, 2N partial differential equations can be obtained by taking the partial derivatives of N variables in the Hamiltonian function related to the combinatorial optimization problem in parallel. This transforms the combinatorial optimization problem into the form of partial differential equations. The combinatorial optimization problem is then solved by solving these 2N partial differential equations, yielding the combinatorial optimization solution. Existing simulated bifurcation algorithms are mainly used to solve the Ising problem, but they can only handle binary spin values. This limitation means that the algorithm may not be effective enough when dealing with more extensive and complex optimization problems. The method provided in this invention is generalized, thus enabling it to handle spin glass state problems. These problems have a wider state space and require the algorithm to handle independent variables with multiple values. In spin glass state problems, independent variables can take many different values, rather than being limited to the two states in the Ising model, thus improving the versatility of combinatorial optimization solutions.

[0129] Optionally, the method of solving the combinatorial optimization problem by solving the 2N partial differential equations to obtain the combinatorial optimization solution result may include:

[0130] The optimal solutions to the 2N partial differential equations are determined using the Euler algorithm or an adiabatic evolution algorithm simulating a nonlinear Hamiltonian system, and are used as the combined optimization solution results.

[0131] Specifically, the Euler method (alternating implicit scheme) can be used to solve the aforementioned multivariable partial differential equations (PDEs). This numerical analysis technique allows algorithms to approximate the solution of differential equations, thus enabling the effective simulation of dynamic changes in variables within more complex systems.

[0132] Furthermore, this invention also draws upon some advanced concepts in quantum computing from the SB algorithm, such as QbM and quantum adiabatic optimization. The SB algorithm finds optimal solutions by simulating the adiabatic evolution of a nonlinear Hamiltonian system, a process involving bifurcation of system states. This approach enables the SB algorithm to achieve large-scale parallel processing on modern multi-core processors, significantly improving its efficiency.

[0133] By combining these improvements, the generalized simulated bifurcation algorithm of this invention can not only handle a wider range of problems but also make more efficient use of modern computing resources. These improvements make the algorithm more adaptable to solving complex optimization problems, especially in situations that require handling multivariables and multiple values.

[0134] It should be noted that in physics, the Hamiltonian function H describes the total energy of a system, and it can take different forms depending on the physical model. For the Ising model and the spin glass model, the form of the Hamiltonian function has its own characteristics:

[0135] 1) Hamiltonian function in the Ising model: In the Ising model, the Hamiltonian function describes the energy of a set of spin particle interactions and the influence of an external magnetic field. Its expression is:

[0136] H = -∑ i＜j J ij s i s j -μ∑ i h i s i ;

[0137] Among them, s i J is the value of the i-th spin, usually +1 or -1; ij It is the interaction strength between spin i and spin j; h i is the strength of the external magnetic field acting on spin i; μ is the magnetic moment.

[0138] In this model, the spin can only take two values ​​(+1 or -1), representing two directions.

[0139] 2) Hamiltonian function of the spin glass model: The spin glass model is a more complex model that can be used to describe multi-valued spin systems. In this model, each spin can take multiple different phase values, not just +1 or -1. The Hamiltonian function can be written as:

[0140]

[0141] in, It means that the i-th p A multivalued variable of spin states; J ij It is the interaction strength between spin i and spin j, h i It is the strength of the external magnetic field acting on spin i.

[0142] In the spin glass model, the state of each spin can be determined by its phase (or a generalized multivalued variable). ) represents the interaction that is more complex than a simple two-state system.

[0143] In this embodiment of the invention, optimized solutions to 2N partial differential equations can be obtained by Euler's algorithm or by simulating the adiabatic evolution algorithm in a nonlinear Hamiltonian system. The optimization solution is found by simulating the adiabatic evolution in a nonlinear Hamiltonian system. This process involves the bifurcation phenomenon of the system state, which enables the simulated bifurcation algorithm to achieve large-scale parallel processing on modern multi-core processors, greatly improving the efficiency of the algorithm.

[0144] Optionally, before solving the pre-set combinatorial optimization problem through the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result, the user-specified optimization function to be solved can be received through a pre-set input / output IO communication interface.

[0145] The implementation method of solving a pre-set combinatorial optimization problem using the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result may include:

[0146] The optimization function in the combinatorial optimization problem is solved by the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result.

[0147] Specifically, in this embodiment of the invention, an I / O communication interface is set up between the solving device and the user. The user can specify the optimization function to be solved through the I / O communication interface, so that the solving device can solve the subsequent combinatorial optimization problem based on the specified optimization function. By setting up the I / O communication interface, the user can customize the optimization function of the combinatorial optimization problem to be solved, which fully reflects the customization of the device and realizes the versatility of the solving device, enabling it to play a role in many fields such as UAV swarm scheduling, urban optimization management, and logistics optimization.

[0148] Optionally, after solving the pre-set combinatorial optimization problem using the FPGA-based combinatorial optimization problem solver and obtaining the combinatorial optimization solution result, the combinatorial optimization solution result can be sent to the user through the IO communication interface;

[0149] The combined optimization solution result includes at least one of the intermediate solution result and the final solution result.

[0150] Specifically, the IO communication interface can also transmit the combined optimization solution obtained from the solution to the user side.

[0151] Optionally, a pre-set data storage module can be used to store at least one of the following: problem instance, algorithm parameters, intermediate solution results, and final solution results corresponding to the combinatorial optimization problem.

[0152] Specifically, embodiments of the present invention may include a data storage module for storing at least one of the following: problem instance, algorithm parameters, intermediate solution results, and final solution results corresponding to the combinatorial optimization problem. This data storage module can be read and written by other electronic devices, which is helpful for subsequent problem tracking and result analysis.

[0153] The following example illustrates the FPGA-based combinatorial optimization solution method provided by the embodiments of the present invention.

[0154] This invention presents an FPGA-based combinatorial optimization solution method, aiming to provide an efficient and universal solution applicable to various combinatorial optimization problems. Specifically, it leverages the unique advantages of FPGA chips to simulate bifurcation algorithms through hardware design, achieving efficient solutions to combinatorial optimization problems. This method not only has broad applicability but also user-defined functionality, enabling it to meet the needs of various fields.

[0155] Figure 2 This is a schematic diagram of the solution system used in the FPGA-based combinatorial optimization solution method provided by the present invention, as shown in the figure. Figure 2As shown, the core components of the solution system mainly include: a power supply module, an FPGA core, an I / O communication module, and a data storage module. These modules together constitute an Ising computer, capable of effectively solving combinatorial optimization problems. Specifically:

[0156] 1) Power supply module: The function of the power supply module is to provide a stable and reliable power supply to the system. Power stability is crucial when solving combinatorial optimization problems to ensure that the system is not affected by power fluctuations during operation. The power supply module may include power supply units, batteries or power management systems to meet different power supply needs. The power supply module transmits power to the FPGA core and other parts through cables or lines.

[0157] 2) FPGA Core: The FPGA core is a key component of this invention. It runs the Simulated Bifurcation Algorithm (SB algorithm) as the primary algorithm for solving combinatorial optimization problems. This algorithm is a highly efficient combinatorial optimization problem-solving algorithm, implemented on an FPGA chip through hardware design to improve computational speed and efficiency. Specifically, it includes an FPGA chip, HDL programming, and the hardware design of the SB algorithm. The FPGA core executes the SB algorithm based on the input combinatorial optimization problem and user-defined parameters (e.g., optimization functions), while leveraging the parallel performance of the FPGA to accelerate the solution process.

[0158] By designing the FPGA core hardware, a simulated bifurcation algorithm is integrated in parallel, enabling it to function as a solver.

[0159] 3) I / O Communication Module: The I / O communication module acts as the interface between the user and the system, used for problem specification and result communication. Users can use this module to specify the optimization function to be solved, i.e., the combinatorial optimization problem to be solved, typically via commands, configuration files, or network communication, while simultaneously receiving and returning the solution results. This customizable interface allows the system to handle the solution requirements of different problems. Specifically, the I / O communication module receives user input, transmits the problem to the FPGA core, and then returns the solution results to the user or other devices.

[0160] It is important to note that when deploying the SB algorithm on an FPGA chip, designing an effective I / O communication module is crucial for the solver's versatility. The I / O communication module is responsible for receiving external input, i.e., the model to be solved is in derivative form, and passing it to the SB algorithm on the FPGA. Generally, the I / O communication interface should receive a series of partial differential equations in symbolic form, where the interaction coefficients are stored through symbols or data matrices.

[0161] For example, when solving the spin glass state problem of 4 spin interactions, the specific calculation form of the above equation (3) should be given and input into the IO communication module, and the solver will return the optimal result X.

[0162] 4) Data Storage Module: The data storage module records calculation results and intermediate data, which can be read and written by other electronic devices for further analysis, archiving, and retrieval, and is used for data analysis and tracing the solution process. The data storage module typically includes storage devices (such as hard drives, solid-state drives, cloud storage, etc.) and corresponding data management software. The data storage module receives the results generated by the FPGA core and securely stores them for later access by users or other applications.

[0163] The interaction between these parts is described below:

[0164] 1> Users can use the IO communication module to submit a description and parameters of the combinatorial optimization problem through a specified interface.

[0165] 2> The IO communication module transmits the problem to the FPGA core and initiates the execution of the SB algorithm.

[0166] 3> The FPGA core executes the SB algorithm, using hardware acceleration to solve problems efficiently.

[0167] 4> Once the problem is solved, the FPGA core will transmit the result back to the IO communication module.

[0168] 5> The IO communication module returns the results to the user or other devices, and stores the results in the data storage module.

[0169] 6> The data storage module saves the results for later analysis and retrieval.

[0170] The advantage of this invention lies in combining the high customizability and versatility of FPGAs, making it applicable to various combinatorial optimization problems, including but not limited to optimal allocation problems, traffic light optimization problems, and coloring problems.

[0171] Figure 3 This is the second flowchart of the FPGA-based combinatorial optimization solution method provided by the present invention, as shown below. Figure 3 As shown, the specific steps include:

[0172] 1) Start: The starting point of the process.

[0173] 2) Hardware design: Select FPGA chips, hardware description language programming, circuit design, etc., to make full use of the programmability of FPGA.

[0174] 3) Algorithm implementation: Implement the simulated bifurcation algorithm (SB algorithm) on the FPGA to make full use of the hardware design to improve the calculation speed and efficiency.

[0175] 4) Communication Interface Design: Create a communication interface between the user and the system, allowing users to define their own questions and receive solutions.

[0176] 5) Data storage design: Develop a data storage module to record problem instances, intermediate results, and final solutions for further analysis.

[0177] 6) Power supply design: Ensure the system has a stable power supply, making it suitable for long-duration computing tasks and low-power applications.

[0178] 7) Problem specification: Users specify the combinatorial optimization problem to be solved using the communication interface, which fully reflects the system's customizability.

[0179] 8) Problem Solving: The system executes a simulated bifurcation algorithm, and the hardware acceleration of the FPGA improves the problem solving speed.

[0180] 9) Output: The system feeds back the optimal solution or near-optimal solution to the user or other devices through the communication interface, emphasizing high efficiency and real-time performance.

[0181] 10) Store results: Store the results in the data storage module for further analysis, providing users with detailed information about the problem-solving process.

[0182] 11) End: The end point of the process.

[0183] The embodiments of the present invention include at least the following beneficial effects:

[0184] 1> Efficient Solution: By leveraging the parallel computing capabilities of FPGA, efficient solutions to combinatorial optimization problems are achieved, accelerating the decision-making process.

[0185] 2. High Customization: One of the greatest advantages of FPGAs is their high degree of customization. According to this invention, designers can tailor hardware designs to the specific requirements of a particular combinatorial optimization problem, optimizing it to the problem's specific characteristics. This flexibility means that we can customize an optimal solution for each problem, rather than using a generic algorithm. This is crucial for combinatorial optimization problems across various fields, as the nature and requirements of the problems can vary greatly.

[0186] 3. Parallel Performance: FPGAs possess excellent parallel processing capabilities, enabling them to handle multiple problem instances or multiple solution steps simultaneously. This means that a large number of problems can be processed in a short time, significantly improving solution speed. This is especially important for applications requiring rapid decision-making, such as real-time scheduling and decision support systems.

[0187] 4. Low Latency: FPGAs typically feature low latency, reducing communication time during data transmission and enabling faster and more efficient completion of program I / O. For real-time applications, such as traffic light optimization or robot path planning, low latency is crucial as it ensures immediate response and decision-making.

[0188] 5. Energy Efficiency: FPGAs are typically capable of performing computational tasks with low power consumption, making them highly advantageous for applications requiring long-running operations or mobile devices. Long computation times are necessary in many combinatorial optimization problems, so low power consumption helps reduce energy consumption and heat generation.

[0189] 6. High Applicability: This invention can be more than just a standalone FPGA chip; it can also achieve high scalability through FPGA clusters. This means it can handle large-scale problems, easily tackling everything from optimizing large networks in logistics management to solving complex issues in urban planning.

[0190] 7. Hardware Acceleration: FPGAs provide hardware acceleration, which typically enables faster computation speeds compared to pure software implementations. This is a significant advantage for combinatorial optimization problems requiring high performance, as hardware acceleration minimizes problem-solving time and improves overall system efficiency.

[0191] The combinatorial optimization solving device based on FPGA provided by the present invention is described below. The combinatorial optimization solving device based on FPGA described below and the combinatorial optimization solving method based on FPGA described above can be referred to and correspond to each other.

[0192] Figure 4 This is a schematic diagram of the FPGA-based combinatorial optimization solving device provided by the present invention, as shown below. Figure 4 As shown, the FPGA-based combinatorial optimization solver 400 includes:

[0193] Processing module 400 is used to implement the pre-set simulated bifurcation algorithm in hardware on a field-programmable gate array (FPGA) to obtain an FPGA-based combinatorial optimization problem solver.

[0194] The solution module 401 is used to solve a pre-set combinatorial optimization problem through the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result.

[0195] In the FPGA-based combinatorial optimization problem-solving device provided in this embodiment of the invention, a processing module and a solution module are used to combine a simulated bifurcation algorithm with an FPGA to solve combinatorial optimization problems. The parallel computing capabilities of the FPGA enable efficient solving of combinatorial optimization problems, accelerating the decision-making process. The high customizability of the FPGA allows for hardware design tailored to the specific requirements of a particular combinatorial optimization problem, optimizing it to its specific characteristics. The low latency of the FPGA shortens communication time during data transmission, enabling faster and more efficient completion of the program's input and output. For real-time applications, such as traffic light optimization or robot path planning, low latency is crucial as it ensures immediate response and decision-making, and the method of this invention is well-suited to this. The low power consumption of the FPGA makes it suitable for use on mobile devices requiring long-term operation. In many combinatorial optimization problems, long-term computation is necessary, so low power consumption helps reduce energy consumption and heat generation. Furthermore, the FPGA can provide hardware acceleration, typically achieving faster computation speeds compared to pure software implementations. The FPGA is not necessarily a single chip; it can also achieve high scalability through FPGA clusters, enabling the handling of large-scale problems. In summary, this invention utilizes the unique advantages of FPGA chips to simulate bifurcation algorithms through hardware design, thereby achieving efficient solutions to combinatorial optimization problems. It has wide applicability and can meet the needs of various fields.

[0196] Optionally, the solver module 401 is specifically used for:

[0197] On the FPGA, the pre-set Hamiltonian function H bSB Taking partial derivatives of N variables in parallel yields 2N partial differential equations; among which, the H... bSB Related to the aforementioned combinatorial optimization problem, N is an integer greater than 0, and N represents the number of spins to be solved in the spin glass state problem;

[0198] The combinatorial optimization problem is solved by solving the 2N partial differential equations, and the combinatorial optimization solution is obtained.

[0199] Optionally, the solver module 401 is also specifically used for:

[0200] The optimal solutions to the 2N partial differential equations are determined using the Euler algorithm or an adiabatic evolution algorithm simulating a nonlinear Hamiltonian system, and are used as the combined optimization solution results.

[0201] Optionally, the FPGA-based combinatorial optimization solver 400 further includes:

[0202] The communication module is used to receive the optimization function specified by the user and to solve it through a pre-set input / output IO communication interface.

[0203] The solution module 401 is also specifically used to: solve the optimization function in the combinatorial optimization problem through the FPGA-based combinatorial optimization problem solver, and obtain the combinatorial optimization solution result.

[0204] Optionally, the communication module is also used for:

[0205] The combined optimization solution result is sent to the user through the IO communication interface.

[0206] The combined optimization solution result includes at least one of the intermediate solution result and the final solution result.

[0207] Optionally, the FPGA-based combinatorial optimization solver 400 further includes:

[0208] The storage module is used to: store at least one of the following in the case of the combinatorial optimization problem: problem instance, algorithm parameters, intermediate solution results, and final solution results, using a pre-set data storage module.

[0209] Figure 5 This is a schematic diagram of the structure of the electronic device provided by the present invention, such as... Figure 5 As shown, the electronic device 500 may include a processor 510, a communication interface 520, a memory 530, and a communication bus 540. The processor 510, communication interface 520, and memory 530 communicate with each other via the communication bus 540. The processor 510 can call logic instructions from the memory 530 to execute an FPGA-based combinatorial optimization problem solver. This method includes: implementing a pre-set simulated bifurcation algorithm in hardware on a field-programmable gate array (FPGA) to obtain an FPGA-based combinatorial optimization problem solver.

[0210] The FPGA-based combinatorial optimization problem solver solves a pre-set combinatorial optimization problem and obtains the combinatorial optimization solution result.

[0211] Furthermore, the logical instructions in the aforementioned memory 530 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, essentially, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0212] On the other hand, the present invention also provides a computer program product, the computer program product including a computer program, the computer program being able to be stored on a non-transitory computer-readable storage medium, the computer program being executed by a processor, the computer being able to execute the FPGA-based combinatorial optimization solution method provided by the above methods, the method including: hardware implementation of a pre-set simulated bifurcation algorithm on a field-programmable gate array (FPGA) to obtain an FPGA-based combinatorial optimization problem solver;

[0213] The FPGA-based combinatorial optimization problem solver solves a pre-set combinatorial optimization problem and obtains the combinatorial optimization solution result.

[0214] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the FPGA-based combinatorial optimization solution method provided by the above methods. The method includes: hardware implementation of a pre-set simulated bifurcation algorithm on a field-programmable gate array (FPGA) to obtain an FPGA-based combinatorial optimization problem solver.

[0215] The FPGA-based combinatorial optimization problem solver solves a pre-set combinatorial optimization problem and obtains the combinatorial optimization solution result.

[0216] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0217] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0218] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A combinatorial optimization solution method based on FPGA, characterized in that, include: The pre-set simulated bifurcation algorithm is implemented in hardware on a field-programmable gate array (FPGA) to obtain an FPGA-based combinatorial optimization problem solver. The FPGA-based combinatorial optimization problem solver is used to solve the pre-set Hamiltonian function. Parallel partial derivatives are taken for N variables, resulting in 2N partial differential equations; among which, the Hamiltonian function... Related to a pre-defined combinatorial optimization problem, N is an integer greater than 0, and N represents the number of spins to be solved in the spin glass state problem; The optimal solutions to the 2N partial differential equations are determined using the Euler algorithm or the adiabatic evolution algorithm in a simulated nonlinear Hamiltonian system, and are used as the results of the combined optimization solution.

2. The FPGA-based combinatorial optimization solution method according to claim 1, characterized in that, The FPGA-based combinatorial optimization problem solver solves the pre-set Hamiltonian function. Before obtaining 2N partial differential equations by taking partial derivatives of N variables in parallel, the method further includes: The system receives the optimization function specified by the user through a pre-set input / output I / O communication interface. The optimization function is a function in the pre-set combinatorial optimization problem. The optimization function is solved by the FPGA-based combinatorial optimization problem solver to obtain the combinatorial optimization solution result.

3. The FPGA-based combinatorial optimization solution method according to claim 2, characterized in that, After determining the optimal solutions to the 2N partial differential equations as the result of the combined optimization solution, the method further includes: The combined optimization solution result is sent to the user through the IO communication interface. The combined optimization solution result includes at least one of the intermediate solution result and the final solution result.

4. The FPGA-based combinatorial optimization solution method according to claim 1, characterized in that, The method further includes: Using a pre-set data storage module, at least one of the following is stored: problem instance, algorithm parameters, intermediate solution results, and final solution result corresponding to the combinatorial optimization problem.

5. A combinatorial optimization solution device based on FPGA, characterized in that, include: The processing module is used to implement the pre-set simulated bifurcation algorithm in hardware on a field-programmable gate array (FPGA) to obtain an FPGA-based combinatorial optimization problem solver. The solution module is used to solve a pre-set Hamiltonian function using the FPGA-based combinatorial optimization problem solver. Parallel partial derivatives are taken for N variables, resulting in 2N partial differential equations; among which, the Hamiltonian function... Related to a pre-defined combinatorial optimization problem, N is an integer greater than 0, and N represents the number of spins to be solved in the spin glass state problem; the optimized solutions of the 2N partial differential equations are determined by the Euler algorithm or the adiabatic evolution algorithm in the simulation of nonlinear Hamiltonian systems, and are used as the combinatorial optimization solution results.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the FPGA-based combinatorial optimization solution method as described in any one of claims 1 to 4.

7. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the FPGA-based combinatorial optimization solution method as described in any one of claims 1 to 4.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the FPGA-based combinatorial optimization solution method as described in any one of claims 1 to 4.

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