Cryptographic chip and chip encryption method

Abstract

The application provides an encryption chip and an encryption method thereof. The encryption chip comprises a combined encryption module, which stores a plurality of sets of encryption information. Each set of encryption information corresponds to a process in the formation process of the encryption chip. Each set of encryption information comprises process encryption information and previous process comprehensive encryption information. The previous process comprehensive encryption information is formed based on comprehensive password information obtained in the previous process. In the process, the comprehensive password information of the next process is formed based on the process password information and the comprehensive password information obtained in the previous process. Thus, the encryption anti-theft task of the chip can be refined to each process link in the formation process of the encryption chip to form a final multi-level and multi-dimensional encryption anti-theft system, thereby reducing the risk of illegal theft of the chip.

Description

[Technical Field]

[0001] This invention relates to the field of chip design, and in particular to an encryption chip and a chip encryption method. [Background Technology]

[0002] A chip generally refers to the carrier of an integrated circuit (IC), and is also the result of the IC's design, manufacturing, packaging, and testing. It is typically a self-contained unit ready for immediate use. Integrated circuits emphasize circuit design and layout, while chips emphasize circuit integration, production, and packaging. The physical form of an integrated circuit often exists in the form of a chip. In a narrow sense, an integrated circuit emphasizes the circuit itself; in a broad sense, it can encompass various meanings related to chips. The terms "chip" and "integrated circuit" are often used interchangeably.

[0003] After front-end digital and analog design, integrated circuits enter the back-end automated placement and routing process. Once the layout is complete, it is sent to a wafer foundry for production, followed by packaging and testing. A single project, from market research, project initiation, functional definition, circuit and layout design, can take anywhere from several months to tens of months, requiring dozens or even hundreds of engineers. Tape-out and revisions also incur significant expenses. The leakage or theft of a product developed with such painstaking effort can cause enormous losses to the project's owners.

[0004] GDSII (a database file format that has become the de facto industry standard for data conversion in integrated circuit layouts) files are at risk of leakage and theft during storage and transmission, and MASK (a mask used in photolithography in integrated circuit manufacturing) files are at risk of being leaked and stolen during storage and use; even manufactured chips are at risk of being reverse-engineered.

[0005] Currently, the protection of intellectual property rights for integrated circuits is usually achieved through patent applications for specific methods or functions and through registration of the overall integrated circuit layout design.

[0006] If certain integrated circuits are not patented or do not use specific patents, they cannot obtain patent protection. In some cases, even if specific patented technologies are used, there is still a potential risk that the infringed party may apply to invalidate the patented technology, thus preventing patent protection.

[0007] While integrated circuit layout design registration can protect the overall layout, organizations or entities with the relevant technology can still adjust the layout when they obtain the developer's GDSII file or through reverse engineering. This allows them to achieve a final function similar to the developer's integrated circuit, even if the layout is different. The modified layout can still be registered. If the developer's integrated circuit is indeed infringed, legal proceedings are lengthy and time-consuming, with each side presenting its own arguments.

[0008] In order to reduce and mitigate further losses to the company caused by the leakage or theft of GDSII or MASK, and to prevent the illegal infringement of the owner's rights due to reverse copying of chips, it is particularly necessary to develop an encryption method to mitigate or even avoid the losses of developers caused by the aforementioned situations. [Summary of the Invention]

[0009] One of the objectives of this invention is to provide an encryption chip and a chip encryption method, which can refine the encryption and anti-theft task of the chip to each process step in the formation of the encryption chip, so as to form a final multi-level and multi-dimensional encryption and anti-theft system and reduce the risk of the chip being illegally stolen.

[0010] According to one aspect of the present invention, an encryption chip is provided, comprising: a combined encryption module storing multiple sets of encryption information, each set of encryption information corresponding to a process in the formation of the encryption chip, each set of encryption information including encryption information of the current process and comprehensive encryption information of the previous process, wherein the comprehensive encryption information of the previous process is formed based on the comprehensive cryptographic information obtained in the previous process, and in the current process, the comprehensive cryptographic information of the next process is formed based on the cryptographic information of the current process and the comprehensive cryptographic information obtained in the previous process.

[0011] In one embodiment, the encrypted information of each group of encrypted information in this process includes the password information of this process and the verification information of this process obtained by encrypting the password information of this process using the first encryption algorithm of this process; the comprehensive password information obtained in the previous process is encrypted using the second encryption algorithm of this process to obtain the comprehensive encrypted information of the previous process.

[0012] According to another aspect of the present invention, the present invention provides an encryption method for an encryption chip, the encryption chip comprising: a combined encryption module, which stores multiple sets of encryption information, each set of encryption information corresponding to a process in the formation of the encryption chip, each set of encryption information including encryption information of the current process and comprehensive encryption information of the previous process, the comprehensive encryption information of the previous process being formed based on comprehensive cryptographic information obtained in the previous process, and comprehensive cryptographic information of the next process being formed based on the cryptographic information of the current process and the comprehensive cryptographic information obtained in the previous process in the current process.

[0013] Compared with existing technologies, the combined encryption module in this invention stores multiple sets of encryption information, each set of encryption information corresponding to a process in the formation of the encryption chip. This allows the encryption and anti-theft task of the chip to be refined to each process step in the formation of the encryption chip, so as to form a final multi-level and multi-dimensional encryption and anti-theft system, reducing the risk of the chip being illegally stolen. [Attached Image Description]

[0014] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0015] Figure 1 This is a schematic diagram of the traditional chip design and manufacturing process;

[0016] Figure 2 This is a schematic diagram illustrating the design and manufacturing process of a sample of the encryption chip in this invention.

[0017] Figure 3 A schematic diagram of the mass production process for traditional encryption chips;

[0018] Figure 4 This is a schematic diagram of the mass production process of the encryption chip in this invention;

[0019] Figure 5 This is an example diagram illustrating the writing of a corresponding set of encrypted information into the encryption chip in process N of the encryption chip formation process in this invention;

[0020] Figure 6 This is a structural diagram of a set of encrypted information formed in each process of the encryption chip in this invention, in one example.

Detailed Implementation Methods

[0021] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0022] The term "an embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the invention. The phrase "in one embodiment" appearing in different places throughout this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0023] In this invention, the task of chip encryption and anti-theft is refined into each process of design, production and application. Software and hardware are used to jointly encrypt the chip to form a multi-level and multi-dimensional encryption and anti-theft system. This increases the difficulty and cost of decryption and reduces the risk of the chip being illegally stolen.

[0024] This invention establishes a multi-layered and multi-dimensional encryption and anti-theft system by implementing encryption at various stages of the integrated circuit process. Specifically, during the functional definition stage, the encryption and anti-theft functions of this project are meticulously planned, and encryption rules and detailed implementation guidelines are established. Encryption is implemented during front-end digital and analog design; during placement and routing; during layout design; during wafer testing; during packaging; and in the application software. Each of these stages requires a specific password to enable a particular function or a combination of functions. Different projects use different passwords, and the password for each of these stages must be correct to enable the chip. Furthermore, different versions of the same project may use different passwords.

[0025] The linewidth and integration density of an integrated circuit (IC) determine its design flow. Different companies, or even different projects within the same company, do not have identical design flows. Generally, after market research and project approval, the IC design process from start to finish, before mass production, typically follows this sequence: Figure 1 The process is shown below; the dashed lines in the diagram below represent the "possible" iterations.

[0026] Figure 2 This is a schematic diagram illustrating the design and manufacturing process of a sample of the encryption chip in this invention. Encryption is implemented at each stage of the process.

[0027] Figure 3 A schematic diagram of the mass production process for traditional encryption chips; Figure 4 This is a schematic diagram illustrating the mass production process of the encryption chip in this invention. Compared with existing technologies, this invention implements encryption at each stage of the process.

[0028] Specifically, in combination Figure 2 and Figure 4 As shown, the relevant encryption tasks are implemented step by step in this invention, as detailed below.

[0029] In the functional definition phase, the encryption and anti-theft functions of this project were carefully planned, and encryption rules and detailed rules for the implementation of encryption tasks were formulated.

[0030] Encryption is used during the design of digital behavior so that without the correct key, all or some functions will not work. For example, if a "specific code" is encrypted and embedded using a certain encryption rule, and the correct input of this "specific code" is not received and recognized by the chip during the chip's startup initialization, then a certain function or some functions of the chip will not be enabled.

[0031] Encryption is performed during layout and routing. Without the correct key, some functions will not work. For example, encryption information in the encryption area of ​​this process can be implemented by adding some circuits and logic. This encryption information can be achieved by setting certain specific nodes of the encryption area circuit of this process to a high or low level.

[0032] The simulation module is encrypted during design. Without the correct key, all or some functions will not work. For example, if "specific code" is encrypted and embedded according to a certain encryption rule, and the correct input of this "specific code" is not received and recognized by the chip during the chip's startup initialization, some or all functions of the chip will not be enabled, or the simulation module may still work but its performance will be reduced, and so on.

[0033] Encryption is performed during layout drawing; without the correct key, some functions will not work. For example, setting certain node connections to high or low level can enable one or more functions.

[0034] Mask encryption involves periodically (every so many weeks) replacing one or more masks. Different production dates for the same mask result in different encryption locations, which in turn affect the encryption-related information. This operation requires the initial layout and other unchanging masks to support it. In other words, both the initial front-end and back-end designs must support modifications to one or more masks later. Therefore, without the correct key, some functions will not work.

[0035] Encryption is performed during wafer testing, such as blowing certain fuses. For specific processes that support OTP (One-Time Program) and MTP (Multi-Time Program), there are more encryption methods available. Therefore, without the correct key, some functions will not work.

[0036] Encryption is performed during packaging, such as setting certain solder pads high or low to form specific password information. Therefore, without the correct key, some functions of the chip will not work.

[0037] Application software encryption involves writing all or part of the aforementioned information into a program and encrypting that program. This program needs to be updated regularly (every few weeks), otherwise it will not function correctly. When the encryption bit of the process is involved in processes such as changing the mask, blowing the fuse, operating OTP or MTP, or changing the packaging bonding pad, the application software also needs to be adjusted and updated accordingly.

[0038] The encryption tasks in each of the aforementioned processes are encrypted using a specific encryption method. Furthermore, the personnel involved in different processes are unaware of each other's keys; that is, each key is restricted to a specific group of people, and the overall key is formed by combining all the individual keys. Alternatively, it can be configured so that after encryption in process A, partial or complete decryption is performed in the next process B, or in a subsequent process C, D, or E. This limits the overall key complexity and prevents leaks by insiders.

[0039] Because the encryption task is nested within multiple processes of design, production, and application, and the passwords for each process are difficult to analyze or guess correctly, and because there is also hardware and software co-encryption, the difficulty of decryption is increased, thus playing a role in encryption and theft prevention.

[0040] The method of this invention can prevent unscrupulous individuals from making the chip work correctly even if they obtain the developer's GDSII file or MASK and produce a wafer to package into a chip, or if the chip is reverse-engineered. This increases the difficulty and cost of decryption, thereby preventing or delaying its sale and profit-making.

[0041] In summary, the present invention ultimately yields an encryption chip. The encryption chip includes a combined encryption module. The combined encryption module stores multiple sets of encryption information, each set corresponding to a process in the formation of the encryption chip. Specifically, in some processes during the formation of the encryption chip, a set of encryption information may be stored in the combined encryption module. However, in some processes during the formation of the encryption chip, encryption information may not be stored in the combined encryption module.

[0042] Each set of encrypted information includes encrypted information for this process and comprehensive encrypted information from the preceding process. The comprehensive encrypted information from the preceding process is formed based on the comprehensive cryptographic information obtained in the previous process. In this process, the comprehensive cryptographic information for the next process is formed based on the cryptographic information for this process and the comprehensive cryptographic information obtained in the previous process. Specifically, in one embodiment, the encrypted information for this process in each set of encrypted information includes the cryptographic information for this process and the verification information for this process obtained by encrypting the cryptographic information for this process using the first encryption algorithm of this process. The comprehensive encrypted information from the preceding process is obtained by encrypting the comprehensive cryptographic information obtained in the previous process using the second encryption algorithm of this process. "This process" refers to the process corresponding to this set of encrypted information.

[0043] Figure 6 This is a structural diagram of a set of encrypted information formed in each process of the encryption chip in this invention, presented in an example. Figure 6 As shown, Part 1 contains the comprehensive encryption information of the preceding process, and Parts 2-3 contain the encryption information of this process.

[0044] Specifically, the encryption chip formation process includes multiple processes such as digital behavior design process, placement and routing process, analog module design process, layout drawing process, mask process, wafer testing process and packaging process. In each of the multiple processes in the digital behavior design process, placement and routing process, analog module design process, layout drawing process, mask process, wafer testing process and packaging process, a set of encryption information corresponding to this process is written into the combined encryption module.

[0045] Figure 5 This is an example diagram illustrating the writing of a corresponding set of encrypted information into the encryption chip during process N in the formation of the encryption chip in this invention. For example... Figure 5 As shown, when N=1, that is, when this process is the first process, the comprehensive cryptographic information obtained by the previous process (N-1=0) is a predetermined value, that is, the initial comprehensive cryptographic information is a predetermined value.

[0046] Combination Figure 5 and 6 As shown, this section will introduce the encryption of mask process, wafer testing process, and packaging process as examples.

[0047] First, a set of encrypted information corresponding to the mask process is written into the mask process.

[0048] In this invention, the first encryption algorithm is, for example, summing the corresponding numbers bit by bit in decimal, but it can also be other more complex encryption algorithms; the second encryption algorithm is, for example, summing the corresponding numbers bit by bit in decimal, but it can also be other more complex encryption algorithms. The first encryption algorithm in each process can be the same or different; this paper describes it as an example of the same algorithm. Similarly, the second encryption algorithm in each process can be the same or different; this paper describes it as an example of the same algorithm. For example, the product of the cryptographic information in this process and the comprehensive cryptographic information obtained in the previous process is the comprehensive cryptographic information for the next process.

[0049] Now assume that the pre-process comprehensive encryption information sent from the process preceding the mask process is decimal 20231208. Thus, the pre-process comprehensive encryption information in the mask process is: decimal 2 + 0 + 2 + 3 + 1 + 2 + 0 + 8 = 18, which is represented as 10010 in binary. After padding with zeros at the high bits, the pre-process comprehensive encryption information in the mask process is binary 0001 0010.

[0050] If the password information for this process written in the mask process is 127 in decimal (or other data), its binary representation is 111 1111. After padding the high bits with zeros, the password information for this process will be 0000 00000111 1111 in binary.

[0051] The verification information for this process is decimal 1+2+7=10, which is binary 1010. After padding with zeros at the high bits, the verification information for this process will be binary 0000 1010.

[0052] The comprehensive cryptographic information sent to the next process is 20231208*127=2569363416 in decimal, which is the comprehensive cryptographic information for entering the wafer testing process.

[0053] Then, a set of encrypted information corresponding to the wafer testing process is written into the wafer testing process.

[0054] The pre-process synthesis encryption information for wafer testing is 2+5+6+9+3+6+3+4+1+6=45 in decimal, and its binary representation is 101101. After padding with zeros in the high bits, the pre-process synthesis encryption information will be written as 0010 1101 in binary.

[0055] If the password information for this process written in the wafer testing process is 31 in decimal, its binary representation is 11111. After padding the high bits with zeros, the password information for this process will be written as 0001 1111 in binary.

[0056] The verification information for this process in the wafer testing procedure is 3+1=4 in decimal, which is 100 in binary. After padding the high bits with zeros, the verification information for this process will be written as 0000 0100 in binary.

[0057] The comprehensive cryptographic information for the next process is 20231208*127*31 in decimal = 79650265896. This is the comprehensive cryptographic information for the encapsulation process.

[0058] Then, a set of encrypted information corresponding to the encapsulation process is written into the encapsulation process.

[0059] The pre-process comprehensive encryption information of the encapsulation process is 7+9+6+5+0+2+6+5+8+9+6=63, which is represented in binary as 11 1111. After padding the high bits with zeros, the pre-process comprehensive encryption information will be written as binary 00111111.

[0060] Assuming the password information for this process written during the encapsulation process is 17 in decimal, its binary representation is 10001, after padding the high bits with zeros, the password information for this process will be written as 0001 0001 in binary.

[0061] The verification information in this process of the encapsulation process is 1+7=8 in decimal, which is 1000 in binary. After padding the high bits with zeros, the verification information in this process will be written as 0000 1000 in binary.

[0062] The comprehensive password information for the next step is 20231208*127*31*17 in decimal, which is 1354054520232.

[0063] In one embodiment, devices, circuits, combinational logic, timing logic, or data are set in one or more of the processes such as digital behavior design process, placement and routing process, analog module design process, layout drawing process, mask process, wafer testing process and packaging process, chip application process to perform the encryption task.

[0064] In an optional embodiment, in the digital behavior design process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process, and multiple specific nodes of the added circuits or logic are set to high or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the digital behavior design process in the combined encryption module of the encryption chip.

[0065] In an optional embodiment, during the placement and routing process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process, and multiple specific nodes of the added circuits or logic are set to high or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the placement and routing process in the combined encryption module of the encryption chip.

[0066] In an optional embodiment, during the simulation module design process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process, and multiple specific nodes of the added circuits or logic are set to high or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the simulation module design in the combined encryption module of the encryption chip.

[0067] In an optional embodiment, during the layout drawing process, multiple predetermined nodes in the layout are set to high or low levels based on the encryption information of this process and the comprehensive encryption information of the previous process, so that the encryption chip formed based on the layout records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the layout drawing process in the combined encryption module of the encryption chip.

[0068] In an optional embodiment, in the mask process, by adding a structure based on the encryption information of this process and a structure based on the comprehensive encryption information of the previous process to the formed mask, the encryption chip formed based on the mask records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the mask process in the combined encryption module of the encryption chip.

[0069] Specifically, since the mask is based on the GDSII file, the GDSII file must actually support encryption operations at the mask location. The method can be one or more of the following methods or a combination thereof: 1) adding or deleting multiple vias (VIAs) of the same or different types; 2) connecting a node to power or ground using one or more layers of metal wires; 3) disconnecting the metal wires in some encrypted areas using one or more layers of metal wires.

[0070] In an optional embodiment, during the wafer testing process, a predetermined plurality of fuses in the encryption chip are fused based on the encryption information of this process and the comprehensive encryption information of the previous process, so that the encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the wafer testing process in the combined encryption module of the encryption chip.

[0071] In an optional embodiment, during the packaging process, based on the encryption information of this process and the comprehensive encryption information of the previous process, a predetermined number of solder pads of the encryption chip are set to a high level or a low level, so that the encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the packaging process in the combined encryption module of the encryption chip.

[0072] The application software workflow, following the steps outlined above, includes encryption information for this specific workflow and comprehensive encryption information from previous workflows. The final step of each workflow generates a comprehensive password. Details can be deduced from the preceding workflows and will not be repeated here. The purpose of including this encryption information and comprehensive encryption information from previous workflows in the application software workflow is to verify the compatibility between the current software version and the current chip version. Verifying an outdated software version against a newer chip version will fail the password verification.

[0073] Multiple sets of encrypted information from the encryption chip's combined encryption module are loaded into software (such as test software or application software) running on the encryption chip. After the encryption chip is powered on and initialized, the software verifies each set of encrypted information in the encryption chip's combined encryption module when performing read and write operations on the encryption chip. If the verification passes, the encryption chip can function normally; if any verification fails, the encryption chip cannot function normally. Preferably, after the encryption chip is powered on and initialized, a self-test is first performed on the multiple sets of encrypted information in the combined encryption module. Only after the self-test passes is the software verified.

[0074] In one embodiment, if the verification fails M times consecutively, the encryption chip initiates a self-destruct mechanism. The self-destruct mechanism causes system-level signals (such as clock signal CLK, system reset signal RST, etc.) or circuits (bandgap reference of analog circuits, bias circuits used by analog circuits, etc.) to malfunction by blowing the fuse in the encryption chip. For example, M is a natural number greater than or equal to 3.

[0075] It is evident that the set of encrypted information generated in each process is not only related to the encrypted information input in that process, but also to the encrypted information input in all previous processes. This significantly enhances the encryption level and greatly increases the cost of unauthorized access.

[0076] The present invention also provides an encryption method for an encryption chip. The encryption chip includes: a combined encryption module, which stores multiple sets of encryption information. Each set of encryption information corresponds to a process in the formation of the encryption chip. Each set of encryption information includes encryption information for the current process and comprehensive encryption information for the previous process. The comprehensive encryption information for the previous process is formed based on the comprehensive cryptographic information obtained in the previous process. In the current process, the comprehensive cryptographic information for the next process is formed based on the cryptographic information for the current process and the comprehensive cryptographic information obtained in the previous process.

[0077] Specifically, the encrypted information for each group of encrypted information in this process includes the password information for this process and the verification information for this process obtained by encrypting the password information for this process using the first encryption algorithm of this process; the comprehensive password information obtained in the previous process is encrypted using the second encryption algorithm of this process to obtain the comprehensive encrypted information of the previous process. The comprehensive password information obtained in the previous process of the first process is a predetermined value.

[0078] Specifically, the encryption chip formation process includes multiple processes such as digital behavior design, placement and routing, analog module design, layout drawing, masking, wafer testing, and packaging. In each of these processes, a set of encryption information corresponding to that process is written into the combined encryption module.

[0079] In one embodiment, in the digital behavior design process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process, and multiple specific nodes of the added circuits or logic are set to high level or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the digital behavior design process in the combined encryption module of the encryption chip.

[0080] In one embodiment, during the layout and routing process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process, and multiple specific nodes of the added circuits or logic are set to high or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the layout and routing process in the combined encryption module of the encryption chip.

[0081] In one embodiment, during the simulation module design process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process. Multiple specific nodes of the added circuits or logic are set to high or low levels, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the simulation module design in the combined encryption module of the encryption chip.

[0082] In one embodiment, during the layout drawing process, multiple predetermined nodes in the layout are set to high or low levels based on the encryption information of this process and the comprehensive encryption information of the previous process, so that the encryption chip formed based on the layout records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the layout drawing process in the combined encryption module of the encryption chip.

[0083] In one embodiment, in the mask process, by adding a structure based on the encryption information of this process and a structure based on the comprehensive encryption information of the previous process to the formed mask, the encryption chip formed based on the mask records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the mask process in the combined encryption module of the encryption chip.

[0084] In one embodiment, during the wafer testing process, multiple predetermined fuses in the encryption chip are fused based on the encryption information of this process and the comprehensive encryption information of the previous process, so that the encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the wafer testing process in the combined encryption module of the encryption chip.

[0085] In one embodiment, during the packaging process, based on the encryption information of this process and the comprehensive encryption information of the previous process, a predetermined number of solder pads of the encryption chip are set to a high level or a low level, so that the encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the packaging process in the combined encryption module of the encryption chip.

[0086] In one embodiment, in the application software process, a specific combination of multiple "0" and "1" codes is written based on the encryption information of this process and the comprehensive encryption information of the previous process, so that the application software of the encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby adding a set of encryption information related to the application software process to the combined encryption module in the application software process of the encryption chip.

[0087] Multiple sets of encrypted information from the combined encryption module of the encryption chip are loaded into the software running on the encryption chip. After the encryption chip is powered on and initialized, the software will verify each set of encrypted information in the combined encryption module of the encryption chip when performing read and write operations on the encryption chip. If the verification is successful, the encryption chip can work normally. If any step of the verification fails, the encryption chip cannot work normally.

[0088] It should be noted that any modifications made by those skilled in the art to the specific embodiments of the present invention do not depart from the scope of the claims. Accordingly, the scope of the claims is not limited to the foregoing specific embodiments.

Claims

1. An encryption chip, characterized in that, It includes: The combined encryption module stores multiple sets of encryption information. Each set of encryption information corresponds to a process in the formation of the encryption chip. Each set of encryption information includes encryption information for the current process and comprehensive encryption information from the previous process. The comprehensive encryption information from the previous process is formed based on the comprehensive cryptographic information obtained in the previous process. In the current process, the comprehensive cryptographic information for the next process is formed based on the cryptographic information for the current process and the comprehensive cryptographic information obtained in the previous process. The encrypted information for each group of encrypted information in this process includes the password information for this process and the verification information for this process obtained by encrypting the password information for this process using the first encryption algorithm of this process. The comprehensive cryptographic information obtained in the previous process is encrypted using the second encryption algorithm in this process to obtain the comprehensive encrypted information of the previous process. The comprehensive cryptographic information obtained from the previous process in the first process is a predetermined value. The encryption chip formation process includes multiple processes such as digital behavior design process, placement and routing process, analog module design process, layout drawing process, mask process, wafer testing process and packaging process.

2. The encryption chip according to claim 1, characterized in that, In each of the multiple processes in the digital behavior design process, placement and routing process, analog module design process, layout drawing process, mask process, wafer testing process, and packaging process, a set of encrypted information corresponding to this process is written into the combined encryption module.

3. The encryption chip according to claim 2, characterized in that, In the digital behavior design process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process, and multiple specific nodes of the added circuits or logic are set to high level or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the digital behavior design process in the combined encryption module of the encryption chip. or In the layout and routing process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process, and multiple specific nodes of the added circuits or logic are set to high level or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the layout and routing process in the combined encryption module of the encryption chip. or In the simulation module design process, based on the encryption information of this process and the comprehensive encryption information of the previous process, some circuits or logic are added to the encryption chip, and multiple specific nodes of the added circuits or logic are set to high or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the simulation module design in the combined encryption module of the encryption chip. or In the layout drawing process, based on the encryption information of this process and the comprehensive encryption information of the previous process, multiple predetermined nodes in the layout are set to high level or low level, so that the encryption chip formed based on the layout records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the layout drawing process in the combined encryption module of the encryption chip; or In the mask process, by adding a structure based on the encryption information of this process and a structure based on the comprehensive encryption information of the previous process to the formed mask, the encryption chip formed based on the mask records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the mask process in the combined encryption module of the encryption chip. or In the wafer testing process, based on the encryption information of this process and the comprehensive encryption information of the previous process, multiple predetermined fuses in the encryption chip are blown, so that the encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the wafer testing process in the combined encryption module of the encryption chip; or In the packaging process, based on the encryption information of this process and the comprehensive encryption information of the previous process, a predetermined number of solder pads of the encryption chip are set to a high level or a low level, so that the encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the packaging process in the combined encryption module of the encryption chip.

4. The encryption chip according to claim 1, characterized in that, Multiple sets of encrypted information from the combined encryption module of the encryption chip are loaded into the software running on the encryption chip. After the encryption chip is powered on and initialized, the software will verify each group of encryption information in the encryption chip's combined encryption module when performing read and write operations on the encryption chip. If the verification passes, the encryption chip can work normally; if any step of the verification fails, the encryption chip cannot work normally.

5. The encryption chip according to claim 4, characterized in that, After the encryption chip is powered on and initialized, it first performs a self-test on the multiple sets of encrypted information in the combined encryption module. After the self-test passes, the software performs the verification.

6. The encryption chip according to claim 4, characterized in that, If the verification fails M times consecutively, the encryption chip will activate a self-destruct mechanism. The self-destruct mechanism will cause the system-level signals or circuits to malfunction by blowing the fuse in the encryption chip. M is a natural number greater than or equal to 3.

7. An encryption method for an encryption chip, characterized in that, The encryption chip includes a combined encryption module, which stores multiple sets of encryption information. Each set of encryption information corresponds to a process in the formation of the encryption chip. Each set of encryption information includes encryption information for the current process and comprehensive encryption information from the previous process. The comprehensive encryption information from the previous process is formed based on the comprehensive cryptographic information obtained in the previous process. In the current process, the comprehensive cryptographic information for the next process is formed based on the cryptographic information for the current process and the comprehensive cryptographic information obtained in the previous process. The encrypted information for each group of encrypted information in this process includes the password information for this process and the verification information for this process obtained by encrypting the password information for this process using the first encryption algorithm of this process. The comprehensive cryptographic information obtained in the previous process is encrypted using the second encryption algorithm in this process to obtain the comprehensive encrypted information of the previous process. The comprehensive cryptographic information obtained from the previous process in the first process is a predetermined value. The encryption chip formation process includes multiple processes such as digital behavior design process, placement and routing process, analog module design process, layout drawing process, mask process, wafer testing process and packaging process.

8. The encryption method according to claim 7, characterized in that, In each of the multiple processes in the digital behavior design process, placement and routing process, analog module design process, layout drawing process, mask process, wafer testing process, and packaging process, a set of encrypted information corresponding to this process is written into the combined encryption module.

9. The encryption method according to claim 8, characterized in that, In the digital behavior design process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process, and multiple specific nodes of the added circuits or logic are set to high level or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the digital behavior design process in the combined encryption module of the encryption chip. or In the layout and routing process, some circuits or logic are added to the encryption chip based on the encryption information of this process and the comprehensive encryption information of the previous process, and multiple specific nodes of the added circuits or logic are set to high level or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the layout and routing process in the combined encryption module of the encryption chip. or In the simulation module design process, based on the encryption information of this process and the comprehensive encryption information of the previous process, some circuits or logic are added to the encryption chip, and multiple specific nodes of the added circuits or logic are set to high or low level, so that the final encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the simulation module design in the combined encryption module of the encryption chip. or In the layout drawing process, based on the encryption information of this process and the comprehensive encryption information of the previous process, multiple predetermined nodes in the layout are set to high level or low level, so that the encryption chip formed based on the layout records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the layout drawing process in the combined encryption module of the encryption chip; or In the mask process, by adding a structure based on the encryption information of this process and a structure based on the comprehensive encryption information of the previous process to the formed mask, the encryption chip formed based on the mask records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the mask process in the combined encryption module of the encryption chip. or In the wafer testing process, based on the encryption information of this process and the comprehensive encryption information of the previous process, multiple predetermined fuses in the encryption chip are blown, so that the encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the wafer testing process in the combined encryption module of the encryption chip; or In the packaging process, based on the encryption information of this process and the comprehensive encryption information of the previous process, a predetermined number of solder pads of the encryption chip are set to a high level or a low level, so that the encryption chip records the encryption information of this process and the comprehensive encryption information of the previous process, thereby storing a set of encryption information related to the packaging process in the combined encryption module of the encryption chip.

10. The encryption method according to claim 9, characterized in that, Multiple sets of encrypted information from the combined encryption module of the encryption chip are loaded into the software running on the encryption chip. After the encryption chip is powered on and initialized, the software will verify each group of encryption information in the encryption chip's combined encryption module when performing read and write operations on the encryption chip. If the verification passes, the encryption chip can work normally; if any step of the verification fails, the encryption chip cannot work normally.

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