Memory refresh parameter determination, memory refresh method, apparatus, medium, and device

Abstract

The disclosure provides a memory refresh parameter determination, a memory refresh method, a device, a medium and equipment, and relates to the technical field of semiconductors. The memory refresh parameter determination method determines, for each memory cell in a to-be-tested semiconductor, a time ratio between a data retention duration of the memory cell and a reference data retention duration of a reference memory cell; wherein the reference memory cell refers to a memory cell with the shortest data retention duration in the to-be-tested semiconductor; for each memory cell, a target refresh interval duration of the memory cell is determined according to the reference data refresh interval duration of the reference memory cell and the time ratio; and for each memory cell, a target refresh amount of the memory cell within the target refresh interval duration is determined according to the reference refresh amount of the reference memory cell for memory data within the reference refresh interval duration and the time ratio. The technical problem that the power consumption of a DRAM chip is large in the prior art is solved, and the technical effect of reducing the power consumption of the DRAM chip is achieved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method, apparatus, medium and device for determining memory refresh parameters. Background Technology

[0002] The basic structure of a DRAM (Dynamic Random Access Memory) chip generally includes one transistor and one capacitor. The capacitor is prone to leakage during operation, and the data retention time is inversely proportional to the memory refresh interval. Therefore, in order to ensure data integrity, the capacitor needs to be periodically charged. This charging process is called memory refresh.

[0003] Due to factors such as physical layout and manufacturing processes, the data retention time of different memory cells varies, with differences reaching over 50%. To address this, most current solutions use the memory cell with the shortest data retention time as the baseline for refresh. This results in memory cells with longer data retention times also needing to be refreshed based on the shortest refresh interval. In other words, memory cells with longer data retention times are refreshed more frequently per unit time, significantly increasing the power consumption of the DRAM chip.

[0004] Therefore, DRAM chips currently consume a relatively large amount of power. Summary of the Invention

[0005] This disclosure provides a method, apparatus, medium, and device for determining memory refresh parameters, thereby reducing the power consumption of DRAM chips.

[0006] In a first aspect, one embodiment of this disclosure provides a method for determining memory refresh parameters, including:

[0007] For each memory cell in the semiconductor under test, determine the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell; where the reference memory cell is the memory cell in the semiconductor under test with the shortest data retention time.

[0008] For each memory cell, the target refresh interval duration is determined based on the ratio of the baseline refresh interval duration of the baseline memory cell to the time.

[0009] For each memory cell, the target refresh amount within the target refresh interval is determined based on the ratio of the baseline refresh amount of memory data to the time within the baseline refresh interval of the baseline memory cell.

[0010] In an optional embodiment of this disclosure, before determining the time ratio between the data retention duration of a memory cell and the reference data retention duration of a reference memory cell for each memory cell in the semiconductor under test, the memory refresh parameter determination method further includes:

[0011] Obtain the data retention duration of each memory cell in the semiconductor under test during the data retention test;

[0012] The memory unit corresponding to the minimum value among the data retention times is determined as the baseline memory unit.

[0013] In an optional embodiment of this disclosure, obtaining the data retention time of each memory cell in the semiconductor under test during a data retention test includes:

[0014] Mass production testing is performed on the semiconductor under test to obtain the test results.

[0015] The data retention time of each memory unit is extracted from the test results.

[0016] In an optional embodiment of this disclosure, after determining the time ratio between the data retention duration of a memory cell and the reference data retention duration of a reference memory cell for each memory cell in the semiconductor under test, the memory refresh parameter determination method further includes:

[0017] The time ratio corresponding to each memory unit is stored in a preset storage module in the semiconductor under test.

[0018] In an optional embodiment of this disclosure, the memory refresh parameter determination method further includes:

[0019] The target refresh rate corresponding to each memory unit is stored in a preset storage module in the semiconductor under test.

[0020] In one optional embodiment of this disclosure, the preset storage module is a readable register in the semiconductor under test.

[0021] In an optional embodiment of this disclosure, for each memory cell, the target refresh interval duration of the memory cell is determined based on the ratio of the reference refresh interval duration of the reference memory cell to the time, including:

[0022] For each memory cell, the ratio between the baseline refresh interval duration of the baseline memory cell and the time ratio of the corresponding memory cell is calculated to obtain the target refresh interval duration of the memory cell.

[0023] In an optional embodiment of this disclosure, for each memory cell, the target refresh amount of the memory cell within the target refresh interval is determined based on the ratio of the baseline refresh amount of the memory data within the baseline refresh interval to the time, including:

[0024] Determine the baseline refresh amount of memory data in the baseline memory cell within the baseline refresh interval;

[0025] For each memory unit, the ratio between the baseline refresh rate and the time ratio corresponding to the memory unit is calculated to obtain the target refresh rate of the memory unit within the target refresh interval.

[0026] In one optional embodiment of this disclosure, the baseline refresh amount is the number of refresh units for each data unit in the memory cell within a baseline refresh interval.

[0027] In one optional embodiment of this disclosure, the semiconductor under test is a dynamic random access memory.

[0028] Secondly, one embodiment of this disclosure provides a memory refresh method, including:

[0029] Obtain the target refresh interval duration for each memory cell in the semiconductor under test, and the target refresh amount within the target refresh interval duration; wherein the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method of any of the above items;

[0030] The memory refresh of each memory cell in the semiconductor under test is controlled based on the target refresh interval duration and the target refresh amount.

[0031] Thirdly, one embodiment of this disclosure provides a memory refresh parameter determination apparatus, the apparatus comprising:

[0032] The first determining module is used to determine the time ratio between the data retention time of each memory cell in the semiconductor under test and the reference data retention time of the reference memory cell; wherein, the reference memory cell refers to the memory cell in the semiconductor under test with the shortest data retention time.

[0033] The second determining module is used to determine the target refresh interval duration of each memory unit based on the ratio of the baseline refresh interval duration of the baseline memory unit to the time for each memory unit.

[0034] The third determining module is used to determine the target refresh amount of each memory unit within the target refresh interval based on the ratio of the baseline refresh amount of memory data to the time within the baseline refresh interval of the baseline memory unit.

[0035] Fourthly, one embodiment of this disclosure provides a memory refresh apparatus, the apparatus comprising:

[0036] The acquisition module is used to acquire the target refresh interval duration for each memory cell in the semiconductor under test, and the target refresh amount within the target refresh interval duration; wherein, the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method of any of the above.

[0037] The control module is used to control the memory refresh of each memory cell in the semiconductor under test based on the target refresh interval duration and the target refresh amount.

[0038] Fifthly, one embodiment of this disclosure provides a computer-readable storage medium having a computer program stored thereon that, when executed by a processor, implements the method described above.

[0039] In a sixth aspect, one embodiment of this disclosure provides an electronic device, including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-described method by executing the executable instructions.

[0040] The technical solution disclosed herein has the following beneficial effects:

[0041] The aforementioned method for determining memory refresh parameters, for each memory cell in the semiconductor under test, determines the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell. Firstly, based on the reference refresh interval time of the reference memory cell and the time ratio, the target refresh interval time of each memory cell is determined, thereby avoiding the use of the longest refresh interval time among all memory cells in the traditional method. The overall refresh interval time is shorter, and the memory refresh efficiency is higher. Furthermore, each memory cell has a target refresh interval time adapted to the corresponding data retention time to ensure normal data refresh.

[0042] Secondly, the embodiments of this disclosure determine the target refresh amount of the memory cell within the target refresh interval based on the ratio of the baseline refresh amount of the memory cell to the time within the baseline refresh interval, thereby avoiding the uniform use of the maximum refresh amount in the traditional method. The refresh amount is reduced, further reducing the power consumption of memory refresh.

[0043] Therefore, the embodiments of this disclosure improve the efficiency of memory refresh while greatly reducing the power consumption of memory refresh, thereby solving the technical problem of high power consumption of current DRAM chips and achieving the technical effect of reducing the power consumption of DRAM chips.

[0044] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0045] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0046] Figure 1(a) shows a schematic diagram of the structure of a DRAM chip in this exemplary embodiment;

[0047] Figure 1(b) shows a schematic diagram of the structure of a memory cell in a DRAM chip according to this exemplary embodiment;

[0048] Figure 2 This diagram illustrates a method for determining memory refresh parameters in this exemplary embodiment.

[0049] Figure 3 This diagram illustrates the relationship between data retention time and time ratio in a memory refresh parameter determination method according to this exemplary embodiment.

[0050] Figure 4 This diagram illustrates a method for determining memory refresh parameters in this exemplary embodiment.

[0051] Figure 5 This diagram illustrates a method for determining memory refresh parameters in this exemplary embodiment.

[0052] Figure 6 This diagram illustrates a method for determining memory refresh parameters in this exemplary embodiment.

[0053] Figure 7 This diagram illustrates a flowchart of a memory refresh method in this exemplary embodiment;

[0054] Figure 8 This diagram illustrates the structure of a memory refresh parameter determination device according to this exemplary embodiment.

[0055] Figure 9 This diagram illustrates the structure of a memory refresh device in this exemplary embodiment.

[0056] Figure 10 A schematic diagram of the structure of an electronic device in this exemplary embodiment is shown. Detailed Implementation

[0057] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this disclosure more comprehensive and complete, and to fully convey the concept of exemplary embodiments to those skilled in the art. The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced with one or more specific details omitted, or other methods, components, apparatus, steps, etc., can be employed. In other instances, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of this disclosure.

[0058] Furthermore, the accompanying drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0059] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0060] In related technologies, the basic structure of a DRAM (Dynamic Random Access Memory) chip generally includes one transistor and one capacitor. Capacitors are prone to leakage during operation; therefore, to ensure data integrity, the capacitor needs to be periodically charged. This charging process is called memory refresh. Referring to Figures 1(a) and 1(b), the memory array of the current DRAM chip 10 consists of multiple Bank Groups / Banks (memory cell combinations / memory cells). For example, in Figure 1(a), each memory cell 110 is arranged in a certain order within a DRAM chip. Each memory cell 110 contains multiple data cells, such as the 7×7 data cells in Figure 1(b) (this is just an example and does not represent the limitations on the number and arrangement of paired data cells). The CPU (central processing unit, memory processor) needs to refresh each memory cell 110 every tRFCpb (refresh interval), and each memory cell undergoes memory refresh at the same refresh interval. Due to factors such as physical layout and manufacturing processes, the refresh intervals of different memory cells are not only the same, but can differ by more than 50%. To address this issue, most current DRAM chips refresh based on the shortest refresh interval among all memory cells. This results in memory cells with longer refresh intervals also needing to be refreshed based on the shortest interval. In other words, memory cells with longer refresh intervals are refreshed more times per unit time, significantly increasing the power consumption of the DRAM chip. Therefore, current DRAM chips have relatively high power consumption.

[0061] In view of the above problems, this disclosure provides a method for determining memory refresh parameters to reduce the power consumption of DRAM chips. The following is a brief introduction to the application environment of the memory refresh parameter determination method provided in this disclosure:

[0062] The memory refresh parameter determination method provided in this disclosure is applied to a control device. The control device can be the CPU inside the DRAM chip, or it can be other control devices, control equipment, or control chips independent of the DRAM chip. This disclosure does not impose specific limitations and can be set arbitrarily according to the actual situation.

[0063] The following example illustrates how the memory refresh parameter determination method is applied to the control device described above to determine the memory refresh parameters of the memory cells in the semiconductor under test. The semiconductor under test can be any semiconductor requiring memory refresh, such as a DRAM chip; this embodiment does not impose specific limitations. Please refer to... Figure 2The memory refresh parameter determination method provided in this embodiment includes the following steps 201-203:

[0064] Step 201: For each memory cell in the semiconductor under test, determine the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell.

[0065] Data retention time refers to the duration for which a capacitor in a memory cell can maintain its current without leakage. Each memory cell corresponds to a specific data retention time, such as 10 seconds, 20 seconds, or 30 seconds. The reference memory cell is the memory cell in the semiconductor under test with the shortest data retention time. For example, please refer to [link to example]. Figure 3 , Figure 3 This is a graph representing the data retention time of each memory cell in a batch of DDR 4 SDRAM (Double Data Rate Fourth Synchronous Dynamic Random Access Memory). The horizontal axis represents the cell numbers (BANK0-BANK7), and the vertical axis represents the data retention time of each memory cell. Figure 3 As can be seen from the table, BANK3 has the shortest data retention time, which is 30 seconds. Therefore, BANK3 is determined as the baseline memory unit, and the corresponding baseline data retention time is 30 seconds. Then, the ratio between the data retention time of each memory unit and 30 seconds is calculated to obtain the time ratio corresponding to each memory unit, as shown in Table (1) below:

[0066] Table (1)

[0067]

[0068] Step 202: For each memory cell, determine the target refresh interval duration of the memory cell based on the ratio of the baseline refresh interval duration of the baseline memory cell to the time.

[0069] The refresh interval duration refers to the time interval between two memory refreshes of a memory cell. Correspondingly, the baseline refresh interval duration is the time interval between two memory refreshes of a baseline memory cell. The target refresh interval duration for each memory cell can be obtained by calculating the ratio, product, or weighted product of the baseline refresh interval duration with each time ratio.

[0070] Continuing with the above example, for instance, the baseline refresh interval of the baseline memory cell BANK3 is 90 nanoseconds, and the target refresh intervals corresponding to BANK0-BANK7 are shown in Table (2) below:

[0071] Table (2)

[0072]

[0073] As can be seen from Table (2) above, the target refresh interval of the memory cell is negatively correlated with the data retention time. The shorter the data retention time, the longer the target refresh interval. Conversely, the longer the data retention time, the shorter the target refresh interval. Moreover, the target refresh intervals of different memory cells are not the same. The refresh interval of each memory cell is shorter than the longest refresh interval used in the traditional method (e.g., 90 nanoseconds for BANK3 in the example above), which improves the refresh efficiency.

[0074] Step 203: For each memory cell, determine the target refresh amount of the memory cell within the target refresh interval based on the ratio of the baseline refresh amount of the memory data to the time within the baseline refresh interval of the baseline memory cell.

[0075] In this embodiment, the refresh amount refers to the number of times memory data is refreshed by a memory unit within one refresh interval. It can be characterized by specific data sizes, such as 3MB or 5MB, or by data units, such as 1 row or 2 rows. This embodiment does not impose any specific limitation. Correspondingly, the baseline refresh amount is the number of times memory data is refreshed by a baseline memory unit within one refresh interval. The target refresh amount for each memory unit can be obtained by calculating the ratio, product, or weighted product of the baseline refresh amount and each time ratio.

[0076] Continuing with the above example, for instance, the baseline refresh rate of the baseline memory unit BANK3 is 4.0 rows, and the target refresh rates corresponding to BANK0-BANK7 are shown in the following table (3):

[0077] Table (3)

[0078]

[0079] As can be seen from Table (3) above, the target refresh amount of the memory cell is negatively correlated with the data retention time. The shorter the data retention time, the larger the target refresh amount. Conversely, the longer the data retention time, the smaller the target refresh amount. Moreover, the target refresh amounts of different memory cells are not the same. Compared with the traditional method of uniformly using the maximum refresh amount (e.g., the refresh amount 4 of BANK3 in the example above), the refresh interval of each memory cell is reduced, which further reduces the power consumption of memory refresh.

[0080] The memory refresh parameter determination method provided in this disclosure determines the time ratio between the data retention time of each memory cell in the semiconductor under test and the reference data retention time of the reference memory cell. Firstly, the target refresh interval time of each memory cell is determined based on the reference refresh interval time of the reference memory cell and the time ratio, thereby avoiding the use of the longest refresh interval time among all memory cells in the traditional method. The overall refresh interval time is shorter and the memory refresh efficiency is higher. Moreover, each memory cell has a target refresh interval time adapted to the corresponding data retention time to ensure normal data refresh.

[0081] Secondly, in this embodiment of the present disclosure, the target refresh amount of the memory cell within the target refresh interval is determined based on the ratio of the baseline refresh amount of the memory data to the time within the baseline refresh interval of the baseline memory cell. This avoids the use of the maximum refresh amount uniformly in the traditional method (e.g., the refresh amount 4 of BANK3 in the example above). The refresh amount is reduced, which further reduces the power consumption of memory refresh.

[0082] Therefore, the embodiments of this disclosure improve the efficiency of memory refresh while greatly reducing the power consumption of memory refresh, thereby solving the technical problem of high power consumption of current DRAM chips and achieving the technical effect of reducing the power consumption of DRAM chips.

[0083] Please see Figure 4 In an optional embodiment of this disclosure, before step 201, which determines the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell for each memory cell in the semiconductor under test, the memory refresh parameter determination method further includes the following steps 401-402:

[0084] Step 401: Obtain the data retention time of each memory cell in the semiconductor under test during the data retention test.

[0085] Data retention testing refers to testing the data retention duration of each memory cell in the semiconductor under test. For example, by continuously testing the data written to the memory cell, the starting time is the time when the data is written or the test is started, and the ending time is the time when the first set of data is lost or when a set number of data is lost. The duration between the starting time and the ending time is the data retention duration, which is used to characterize the data retention capability of the memory cell.

[0086] Step 402: Determine the memory unit corresponding to the minimum value among the data retention times as the base memory unit.

[0087] Continuing with the example above, for example... Figure 3As can be seen, BANK3 has the shortest data retention time, which is 30 seconds. Therefore, if BANK3 is determined as the baseline memory unit, the corresponding baseline data retention time is 30 seconds.

[0088] The data retention duration in this embodiment is obtained based on data retention testing, rather than empirical fitting. The obtained baseline memory cell is based on actual production, and the target refresh interval duration and target refresh amount of each memory cell determined based on the baseline memory cell are more reliable.

[0089] Please see Figure 5 In an optional embodiment of this disclosure, step 401, obtaining the data retention time of each memory cell in the semiconductor under test during the data retention test, includes the following steps 501-502:

[0090] Step 501: Perform mass production testing on the semiconductor under test to obtain the test results.

[0091] Automatic Test Equipment (ATE) is used to test the integrity of integrated circuit functions. Test content includes, but is not limited to: data retention time of memory cells, whether there are open circuits or short circuits in chip pins, logic functions, device DC current and voltage parameters, quality of AC output signals and signal timing parameters, and the function and performance of embedded flash memory.

[0092] Step 502: Extract the data retention time of each memory unit from the test results.

[0093] This disclosed embodiment does not require separate data retention testing. Data retention testing can be added during mass production testing and tested synchronously with other projects. After the test is completed, the required data retention duration can be extracted from the test results, saving testing time and testing costs.

[0094] In an optional embodiment of this disclosure, after step 201, which determines the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell for each memory cell in the semiconductor under test, the memory refresh parameter determination method further includes the following step A:

[0095] Step A: Store the time ratio corresponding to each memory unit in the preset storage module of the semiconductor under test.

[0096] The preset storage module can be the storage module in the semiconductor under test, and can be selected or set according to the actual situation, without any limitation. The time ratio corresponding to each memory unit is stored in the preset storage module to facilitate the control device to read it, thereby improving the convenience and efficiency of determining the memory refresh parameters.

[0097] In an optional embodiment of this disclosure, the memory refresh parameter determination method further includes the following step B:

[0098] Step B: Store the target refresh rate corresponding to each memory unit in the preset storage module of the semiconductor under test.

[0099] Similar to step A above, the preset storage module can be the storage module in the semiconductor under test, and can be selected or set according to the actual situation, without any limitation here. The target refresh value corresponding to each memory unit is stored in the preset storage module to facilitate reading by the control device, thereby improving the convenience and efficiency of determining the memory refresh parameters.

[0100] In an optional embodiment of this disclosure, the aforementioned baseline refresh amount is the number of refresh units for each data unit in the memory cell within a baseline refresh interval. A data unit refers to the storage format of memory data within a memory cell. For example, it can be one, two, or three rows as a data unit, or 10KB, 20KB, or 30KB as a data unit, or 10, 20, or 30 characters as a data unit. Measuring the refresh amount using data units requires less computation than real-time calculation of memory data, saving computational resources and further improving the efficiency of determining memory refresh parameters.

[0101] In one optional embodiment of this disclosure, the semiconductor under test is a dynamic random access memory (DRAM). That is, the semiconductor under test is a DRAM chip. By determining the target refresh interval duration for each memory cell during memory refresh in the DRAM chip, and the target refresh amount within the target refresh interval duration, based on the memory refresh parameter determination method provided in this disclosure, the efficiency of DRAM chip memory refresh and the power consumption of memory refresh can be greatly improved.

[0102] In one optional embodiment of this disclosure, the aforementioned preset storage module is a readable register in the semiconductor under test.

[0103] A readable register refers to a readable mode register (e.g., MR register) in a semiconductor under test, such as a DRAM chip. This readable mode register can be accessed by control devices, such as the CPU of the DRAM chip, to easily obtain the time ratio of each memory cell, the target refresh interval, and the target refresh amount, thereby improving the efficiency and convenience of memory refresh and the overall performance of the DRAM chip.

[0104] In an optional embodiment of this disclosure, step 202, determining the target refresh interval duration of each memory cell based on the ratio of the reference refresh interval duration to the time of the reference memory cell, includes the following step C:

[0105] Step C: For each memory cell, calculate the ratio between the baseline refresh interval duration of the baseline memory cell and the time ratio of the corresponding memory cell to obtain the target refresh interval duration of the memory cell.

[0106] That is, the target refresh interval of the memory cell can be calculated using the following formula (1) in this embodiment:

[0107] tRF i =tRF0 / (RT) i / RT0) (1)

[0108] In formula (1), tRF i tRF0 represents the target refresh interval duration for the i-th memory unit, tRF0 represents the baseline refresh interval duration for the baseline memory unit, and RT represents the baseline refresh interval duration for the i-th memory unit. i RT represents the duration of data retention in the i-th memory unit, and RT0 represents the duration of data retention in the reference memory unit. i / RT0) represents the time ratio of the i-th memory unit.

[0109] This embodiment directly calculates the target refresh interval of the memory unit by comparing the ratio between the baseline refresh interval of the baseline memory unit and the time ratio of the corresponding memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of memory refresh parameter determination in this embodiment.

[0110] Please see Figure 6 In an optional embodiment of this disclosure, step 203, determining the target refresh amount of the memory cell within the target refresh interval for each memory cell based on the ratio of the baseline refresh amount of the memory data within the baseline refresh interval to the time, includes the following steps 601-602:

[0111] Step 601: Determine the baseline refresh amount of memory data in the baseline memory cell within the baseline refresh interval.

[0112] For example, the baseline refresh amount of the baseline memory cell within the baseline refresh interval is 4.

[0113] Step 602: For each memory cell, calculate the ratio between the baseline refresh rate and the time ratio corresponding to the memory cell to obtain the target refresh rate of the memory cell within the target refresh interval.

[0114] That is, the target refresh amount of the memory unit can be calculated using the following formula (2) in this embodiment:

[0115] R i =R0 / (RT) i / RT0) (2)

[0116] In formula (2), R i R0 represents the target refresh rate of the i-th memory unit, R0 represents the baseline refresh rate of the baseline memory unit, and RT represents the baseline refresh rate of the baseline memory unit. i RT represents the duration of data retention in the i-th memory unit, and RT0 represents the duration of data retention in the reference memory unit. i / RT0) represents the time ratio of the i-th memory unit.

[0117] This embodiment directly calculates the target refresh amount of the memory unit within the target refresh interval by calculating the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit. The calculation method is simple and more efficient, which can further improve the efficiency of determining the memory refresh parameters in this embodiment.

[0118] Please see Figure 7 This disclosure provides a memory refresh method in one embodiment, including the following steps 701-702:

[0119] Step 701: Obtain the target refresh interval duration for each memory cell in the semiconductor under test, and the target refresh amount within the target refresh interval duration.

[0120] Among them, the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method of any of the above items;

[0121] The beneficial effects of this memory refresh parameter determination method have been described in detail in the above embodiments and will not be repeated here.

[0122] Step 702: Based on the target refresh interval duration and target refresh amount, control the corresponding memory cells in the semiconductor under test to perform memory refresh.

[0123] This embodiment of the present disclosure, based on the aforementioned memory refresh parameter determination method, first determines the target refresh interval duration and the target refresh amount within the target refresh interval duration for each memory cell in the semiconductor under test. Then, based on the target refresh interval duration and the target refresh amount, it controls the corresponding memory cells in the semiconductor under test to perform memory refresh. Firstly, it avoids the use of the longest refresh interval duration among all memory cells in the traditional approach, resulting in a shorter overall refresh interval duration and higher memory refresh efficiency. Furthermore, each memory cell has a target refresh interval duration adapted to its corresponding data retention time, ensuring normal data refresh. Secondly, it avoids the use of the maximum refresh amount (e.g., refresh amount 4 for BANK3 in the above example) in the traditional approach, reducing the refresh amount and further lowering the power consumption of memory refresh. Therefore, this embodiment of the present disclosure significantly reduces the power consumption of memory refresh while improving memory refresh efficiency, thereby solving the technical problem of high power consumption in current DRAM chips and achieving the technical effect of reducing the power consumption of DRAM chips.

[0124] Please see Figure 8 In order to implement the above-mentioned memory refresh parameter determination method, one embodiment of this disclosure provides a memory refresh parameter determination device 800. Figure 8 A schematic architecture diagram of a memory refresh parameter determination device 800 is shown. The device includes a first determination module 810, a second determination module 820, and a third determination module 830, wherein:

[0125] The first determining module 810 is used to determine, for each memory cell in the semiconductor under test, the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell; wherein, the reference memory cell refers to the memory cell in the semiconductor under test with the shortest data retention time.

[0126] The second determining module 820 is used to determine the target refresh interval duration of each memory unit based on the ratio of the reference refresh interval duration of the reference memory unit to the time for each memory unit.

[0127] The third determining module 830 is used to determine, for each memory unit, the target refresh amount of the memory unit within the target refresh interval based on the ratio of the baseline refresh amount of the memory data to the time within the baseline refresh interval of the baseline memory unit.

[0128] In an optional embodiment, the first determining module 810 is further configured to obtain the data retention duration of each memory cell in the semiconductor under test during the data retention test; and determine the memory cell corresponding to the minimum value among the data retention durations as the reference memory cell.

[0129] In an optional embodiment, the first determining module 810 is specifically used to perform mass production testing on the semiconductor under test to obtain the test results of the semiconductor under test; and to extract the data retention time of each memory cell from the test results.

[0130] In an optional embodiment, the first determining module 810 is further configured to store the time ratio corresponding to each memory unit in a preset storage module in the semiconductor under test.

[0131] In an optional embodiment, the third determining module 830 is further configured to store the target refresh amount corresponding to each memory unit in a preset storage module in the semiconductor under test.

[0132] In an optional embodiment, the preset storage module is a readable register in the semiconductor under test.

[0133] In an optional embodiment, the second determining module 820 is specifically used to calculate, for each memory unit, the ratio between the baseline refresh interval duration of the baseline memory unit and the time ratio corresponding to the memory unit, to obtain the target refresh interval duration of the memory unit.

[0134] In an optional embodiment, the third determining module 830 is specifically used to determine the baseline refresh amount of memory data of the baseline memory unit within the baseline refresh interval duration; and for each memory unit, calculate the ratio between the baseline refresh amount and the time ratio corresponding to the memory unit to obtain the target refresh amount of the memory unit within the target refresh interval duration.

[0135] In an optional embodiment, the baseline refresh rate is the number of refresh units for each data unit in the memory cell within the baseline refresh interval.

[0136] In an optional embodiment, the semiconductor under test is a dynamic random access memory (DRAM).

[0137] Please see Figure 9 In order to implement the above memory refresh method, one embodiment of this disclosure provides a memory refresh device 900. Figure 9 A schematic architecture diagram of a memory refresh device 900 is shown. The memory refresh device 900 includes: an acquisition module 910 and a control module 920, wherein:

[0138] The acquisition module 910 is used to acquire the target refresh interval duration of each memory cell in the semiconductor under test, and the target refresh amount within the target refresh interval duration; wherein, the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method of any of the above.

[0139] The control module 920 is used to control the memory refresh of each memory cell in the semiconductor under test based on the target refresh interval duration and the target refresh amount.

[0140] Exemplary embodiments of this disclosure also provide a computer-readable storage medium that can be implemented as a program product including program code, which, when run on an electronic device, causes the electronic device to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of this disclosure. In one embodiment, the program product can be implemented as a portable compact disc read-only memory (CD-ROM) including program code and can run on an electronic device, such as a personal computer. However, the program product of this disclosure is not limited thereto. In this document, the readable storage medium can be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0141] The program product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0142] Computer-readable signal media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable signal medium may also be any readable medium other than a readable storage medium, capable of sending, propagating, or transmitting programs for use by or in conjunction with an instruction execution system, apparatus, or device.

[0143] The program code contained on the readable medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0144] Program code for performing the operations of this disclosure can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider). In embodiments of this disclosure, when the program code stored in the computer-readable storage medium is executed, it can implement any step of the memory refresh parameter determination method or the memory refresh method described above.

[0145] Please see Figure 10 Exemplary embodiments of this disclosure also provide an electronic device 1000, which can be a backend server of an information platform. References are provided below. Figure 10 This electronic device 1000 will be described. It should be understood that... Figure 10 The electronic device 1000 shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments disclosed herein.

[0146] like Figure 10 As shown, the electronic device 1000 is presented in the form of a general-purpose computing device. The components of the electronic device 1000 may include, but are not limited to: at least one processing unit 1010, at least one storage unit 1020, and a bus 1030 connecting different system components (including storage unit 1020 and processing unit 1010).

[0147] The storage unit stores program code, which can be executed by the processing unit 1010 to perform the steps described in the "Exemplary Methods" section of this specification according to various exemplary embodiments of the present invention. For example, the processing unit 1010 can perform, as follows: Figure 2 The methods and steps shown are as follows.

[0148] Storage unit 1020 may include volatile storage units, such as random access memory (RAM) 1021 and / or cache memory 1022, and may further include read-only memory (ROM) 1023.

[0149] Storage unit 1020 may also include a program / utility 1024 having a set (at least one) program module 1025, such program module 1025 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0150] Bus 1030 may include a data bus, an address bus, and a control bus.

[0151] Electronic device 1000 can also communicate with one or more external devices 2000 (e.g., keyboards, pointing devices, Bluetooth devices, etc.) via input / output (I / O) interface 1040. Electronic device 1000 can also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) via network adapter 1050. As shown, network adapter 1050 communicates with other modules of electronic device 1000 via bus 1030. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 1000, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0152] In this embodiment of the disclosure, when the program code stored in the electronic device is executed, it can implement any step of the memory refresh parameter determination method or the memory refresh method described above.

[0153] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to exemplary embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0154] Those skilled in the art will understand that various aspects of this disclosure can be implemented as systems, methods, or program products. Therefore, various aspects of this disclosure can be embodied in entirely hardware implementations, entirely software implementations (including firmware, microcode, etc.), or implementations combining hardware and software aspects, collectively referred to herein as “circuit,” “module,” or “system.” Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and embodiments are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0155] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A method for determining memory refresh parameters, characterized in that, include: For each memory cell in the semiconductor under test, determine the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell; wherein, the reference memory cell refers to the memory cell in the semiconductor under test with the shortest data retention time; For each memory cell, the target refresh interval duration of the memory cell is determined based on the ratio of the baseline refresh interval duration of the baseline memory cell to the time. For each memory cell, the target refresh amount of the memory cell within the target refresh interval is determined based on the ratio of the baseline refresh amount of the memory data in the baseline refresh interval to the time.

2. The method for determining memory refresh parameters according to claim 1, characterized in that, Before determining the time ratio between the data retention time of each memory cell in the semiconductor under test and the reference data retention time of a reference memory cell, the method further includes: Obtain the data retention duration of each memory cell in the semiconductor under test during the data retention test; The memory unit corresponding to the minimum value among the data retention times is determined as the reference memory unit.

3. The method for determining memory refresh parameters according to claim 2, characterized in that, The step of obtaining the data retention duration of each memory cell in the semiconductor under test during the data retention test includes: Mass production testing is performed on the semiconductor under test to obtain the test results of the semiconductor under test; The data retention time of each memory unit is extracted from the test results.

4. The method for determining memory refresh parameters according to claim 1, characterized in that, After determining the time ratio between the data retention time of each memory cell in the semiconductor under test and the reference data retention time of a reference memory cell, the method further includes: The time ratio corresponding to each memory unit is stored in a preset storage module in the semiconductor under test.

5. The method for determining memory refresh parameters according to claim 1, characterized in that, The method further includes: The target refresh rate corresponding to each memory unit is stored in a preset storage module in the semiconductor under test.

6. The method for determining memory refresh parameters according to claim 4 or 5, characterized in that, The preset storage module is a readable register in the semiconductor under test.

7. The method for determining memory refresh parameters according to claim 1, characterized in that, The step of determining the target refresh interval duration for each memory unit based on the ratio of the baseline refresh interval duration of the baseline memory unit to the time includes: For each memory cell, the ratio between the baseline refresh interval duration of the baseline memory cell and the time ratio corresponding to the memory cell is calculated to obtain the target refresh interval duration of the memory cell.

8. The method for determining memory refresh parameters according to claim 1, characterized in that, The step of determining the target refresh amount of each memory unit within the target refresh interval based on the ratio of the baseline refresh amount of memory data in the baseline refresh interval to the time for each memory unit includes: Determine the baseline refresh amount of memory data in the baseline memory unit within the baseline refresh interval; For each memory cell, the ratio between the baseline refresh amount and the time ratio corresponding to the memory cell is calculated to obtain the target refresh amount of the memory cell within the target refresh interval.

9. The method for determining memory refresh parameters according to claim 1, characterized in that, The baseline refresh rate is the number of refresh units for each data unit in the memory unit within the baseline refresh interval.

10. The method for determining memory refresh parameters according to claim 1, characterized in that, The semiconductor under test is a dynamic random access memory.

11. A memory refresh method, characterized in that, include: The target refresh interval duration and the target refresh amount within the target refresh interval duration are obtained for each memory cell in the semiconductor under test; wherein the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method as described in any one of claims 1-10. Based on the target refresh interval duration and the target refresh amount, the corresponding memory cells in the semiconductor under test are controlled to perform memory refresh.

12. A memory refresh parameter determination device, characterized in that, The device includes: The first determining module is used to determine, for each memory cell in the semiconductor under test, the time ratio between the data retention time of the memory cell and the reference data retention time of the reference memory cell; wherein, the reference memory cell refers to the memory cell in the semiconductor under test with the shortest data retention time; The second determining module is used to determine the target refresh interval duration of each memory unit based on the ratio of the reference refresh interval duration of the reference memory unit to the time for each memory unit. The third determining module is used to determine, for each memory unit, the target refresh amount of the memory unit within the target refresh interval based on the ratio of the baseline refresh amount of the memory data of the baseline memory unit within the baseline refresh interval to the time.

13. A memory refresh device, characterized in that, The device includes: An acquisition module is used to acquire the target refresh interval duration and the target refresh amount within the target refresh interval duration for each memory cell in the semiconductor under test; wherein the target refresh interval duration and the target refresh amount are determined according to the memory refresh parameter determination method as described in any one of claims 1-10; The control module is used to control each memory cell in the semiconductor under test to perform memory refresh based on the target refresh interval duration and the target refresh amount.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the method described in any one of claims 1 to 11.

15. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the method of any one of claims 1 to 11 by executing the executable instructions.

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