Clock generation circuit and memory

Abstract

The application provides a clock generation circuit and a memory, comprising: a sampling module which samples consecutive chip select signals based on a sampling clock to obtain odd data and even data; a detection module which is configured to output an indication signal in a first state when it is detected that adjacent chip select signals satisfy a predetermined condition, and output an indication signal in a second state otherwise; wherein the predetermined condition comprises that data bits of a previous chip select signal are all in a first level state, and a first data bit of a next chip select signal is in a second level state; and a generation module which is configured to generate an output clock when the indication signal is in the first state. The scheme can ensure accurate and reliable sampling while generating an output clock in a timely manner.

Description

Technical Field

[0001] This application relates to memory technology, and more particularly to a clock generation circuit and a memory. Background Technology

[0002] With the development of memory technology, memory has been widely used in many fields. For example, Dynamic Random Access Memory (DRAM) is widely used.

[0003] In practical applications, signal testing is usually required to ensure the normal operation of the memory. For example, chip select (CS) signal pin timing margin is improved by performing CS training.

[0004] Considering the characteristics of memory, especially when memory speeds are high, a frequency-divided sampling clock with a period sufficient to meet sampling requirements is used to sample the chip select signal, obtaining the complete chip select signal calculation result, and then outputting the result according to the output clock. Therefore, how to generate an output clock suitable for chip select testing in a timely manner becomes a problem that needs to be solved. Summary of the Invention

[0005] Embodiments of this application provide a clock generation circuit and a memory.

[0006] According to some embodiments, a first aspect of this application provides a clock generation circuit, comprising: a sampling module, configured to sample consecutive chip select signals based on a sampling clock, wherein the holding duration of each data bit of the chip select signal is equal to the period of the system clock, the sampling clock includes an odd clock and an even clock with opposite phases, the period of the odd clock and the even clock being equal to twice the period of the system clock, and the data sampled based on the odd clock is denoted as odd data, and the data sampled based on the even clock is denoted as even data; a detection module, connected to the sampling module, configured to output a first state indication signal when adjacent chip select signals are detected to meet predetermined conditions, otherwise output a second state indication signal; wherein the predetermined conditions include that all data bits of the preceding chip select signal are in a first level state, and the first data bit of the following chip select signal is in a second level state; and a generation module, connected to the detection module, configured to generate an output clock when the indication signal is in the first state; wherein the period of the output clock is the length of a single chip select signal, and the rising edge of the output clock is aligned with the rising edge of the sampling clock of the following chip select signal whose first data bit is in a low level state.

[0007] In some embodiments, each chip select signal includes four data bits.

[0008] In some embodiments, the detection module includes: a first delay unit, a second delay unit, a first arithmetic unit, and a second arithmetic unit; the first delay unit, connected to the sampling module, is used to sequentially delay and output odd data at predetermined time intervals to obtain first delayed odd data, second delayed odd data, third delayed odd data, fourth delayed odd data, and fifth delayed odd data; the second delay unit, connected to the sampling module, is used to sequentially delay and output even data at predetermined time intervals to obtain first delayed even data, second delayed even data, third delayed even data, fourth delayed even data, and fifth delayed even data; the input terminal of the first arithmetic unit is connected to the first delay unit and the second delay unit, and the first arithmetic unit is used to receive the first delayed odd data, second delayed even data, third delayed odd data, fourth delayed even data, and fifth delayed odd data, and detect whether a predetermined condition is met; the output terminal of the first arithmetic unit is connected to the generation module; the input terminal of the second arithmetic unit is connected to the first delay unit and the second delay unit, and the second arithmetic unit is used to receive the first delayed even data, second delayed odd data, third delayed even data, fourth delayed odd data, and fifth delayed even data, and detect whether a predetermined condition is met; the output terminal of the second arithmetic unit is connected to the generation module.

[0009] In some embodiments, the first arithmetic unit includes: a first NOT gate, a first NAND gate, a second NAND gate, and a first NOR gate; the input of the first NOT gate receives first delayed odd data, and the output of the first NOT gate is connected to the first input of the first NAND gate; the second input of the first NAND gate receives second delayed even data, the third input of the first NAND gate receives third delayed odd data, and the output of the first NAND gate is connected to the first input of the first NOR gate; the first input of the second NAND gate receives fourth delayed even data, the second input of the second NAND gate receives fifth delayed odd data, and the output of the second NAND gate is connected to the second input of the first NOR gate; the output of the first NOR gate is connected to the generator modulus. The block is connected; the second arithmetic unit includes: a second NOT gate, a third NAND gate, a fourth NAND gate, and a second NOR gate; the input of the second NOT gate receives first delayed even data, and the output of the second NOT gate is connected to the first input of the third NAND gate; the second input of the third NAND gate receives second delayed odd data, the third input of the third NAND gate receives third delayed even data, and the output of the third NAND gate is connected to the first input of the second NOR gate; the first input of the fourth NAND gate receives fourth delayed odd data, the second input of the fourth NAND gate receives fifth delayed even data, and the output of the fourth NAND gate is connected to the second input of the second NOR gate; the output of the second NOR gate is connected to the generation module.

[0010] In some embodiments, the first delay unit includes: a plurality of first delay sub-units connected in series; the input terminal of the first first delay sub-unit is connected to the sampling module for receiving first delayed odd data generated based on odd data; the input terminal of each first delay sub-unit is connected to the output terminal of the previous first delay sub-unit, and each first delay sub-unit is used to output the received data after a time interval; the second delay unit includes: a plurality of second delay sub-units connected in series; the input terminal of the first second delay sub-unit is connected to the sampling module for receiving first delayed even data generated based on even data; the input terminal of each second delay sub-unit is connected to the output terminal of the previous second delay sub-unit, and each second delay sub-unit is used to output the received data after a time interval.

[0011] In some embodiments, the output clock includes a first output clock and a second output clock with opposite phases; at the same time, the first output clock or the second output clock is valid; wherein the validity of either output clock indicates that the sampling clock corresponding to that output clock first samples the next chip select signal where the first data bit is in a low-level state.

[0012] In some embodiments, the generation module includes: a selection unit, a first generation unit, and a second generation unit; the selection unit is connected to the first arithmetic unit and the second arithmetic unit; the selection unit is configured to output a valid first enable signal to the first generation unit in response to the first arithmetic unit first outputting an indication signal of a first state; and to output a valid second enable signal to the second generation unit in response to the second arithmetic unit first outputting an indication signal of a first state; the enable terminal of the first generation unit is connected to the selection unit, the first generation unit receives an odd clock, and the first generation unit is configured to divide the odd clock in response to the first enable signal being valid, and output a first output clock; the enable terminal of the second generation unit is connected to the selection unit, the second generation unit receives an even clock, and the second generation unit is configured to divide the even clock in response to the second enable signal being valid, and output a second output clock.

[0013] In some embodiments, the first generation unit includes a first flip-flop and a third delay unit; the input terminal of the first flip-flop is connected to the inverted output terminal of the first flip-flop, the clock terminal of the first flip-flop receives an odd clock, the reset terminal of the first flip-flop is the enable terminal of the first generation unit, and the output terminal of the first flip-flop is connected to the input terminal of the third delay unit; the third delay unit is used to delay the signal output by the first flip-flop to obtain a first output clock; the second generation unit includes a second flip-flop and a fourth delay unit; the input terminal of the second flip-flop is connected to the inverted output terminal of the second flip-flop, the clock terminal of the second flip-flop receives an even clock, the reset terminal of the second flip-flop is the enable terminal of the second generation unit, and the output terminal of the second flip-flop is connected to the input terminal of the fourth delay unit; the fourth delay unit is used to delay the signal output by the second flip-flop to obtain a second output clock.

[0014] In some embodiments, the first generation unit further includes a fifth delay unit; the input terminal of the fifth delay unit is connected to the output terminal of the first flip-flop, and the fifth delay unit is used to invert and delay the signal output by the first flip-flop to obtain an inverted signal of the first output clock; the second generation unit further includes a sixth delay unit; the input terminal of the sixth delay unit is connected to the output terminal of the second flip-flop, and the sixth delay unit is used to invert and delay the signal output by the second flip-flop to obtain an inverted signal of the second output clock.

[0015] In some embodiments, the selection unit includes: a first transmission unit, a second transmission unit, and a control unit; the input terminal of the first transmission unit receives a first high-level signal, the control terminal of the first transmission unit receives an indication signal output by a first arithmetic unit, and the output terminal of the first transmission unit is connected to the enable terminal of a first generation unit and the control unit; the first transmission unit is used to transmit the first high-level signal to the control unit when the indication signal output by the first arithmetic unit is in a first state; the input terminal of the second transmission unit receives a second high-level signal, the control terminal of the second transmission unit receives an indication signal output by a second arithmetic unit, and the output terminal of the second transmission unit is connected to the enable terminal of a second generation unit and the control unit; the second transmission unit is used to transmit the second high-level signal to the control unit when the indication signal output by the second arithmetic unit is in the first state; the control unit is connected to the enable terminal of the first transmission unit and the enable terminal of the second transmission unit, and is used to enable the first transmission unit and reset the second transmission unit when receiving the signal output by the first transmission unit; and to enable the second transmission unit and reset the first transmission unit when receiving the signal output by the second transmission unit.

[0016] In some embodiments, the control unit includes: a third NOR gate and a fourth NOR gate; the input of the third NOR gate is connected to the output of the second transmission unit, and the output of the third NOR gate is connected to the enable terminal of the first transmission unit; the input of the fourth NOR gate is connected to the output of the first transmission unit, and the output of the fourth NOR gate is connected to the enable terminal of the second transmission unit.

[0017] In some embodiments, the control unit further includes: a first reset unit; the first reset unit includes: a seventh NOT gate and an OR gate; the input of the seventh NOT gate receives a test mode signal, and the output of the seventh NOT gate is connected to the first input of the OR gate; the second input of the OR gate receives a reset signal, and the output of the OR gate is connected to the other input of the third NOR gate and the other input of the fourth NOR gate.

[0018] In some embodiments, the generation module further includes: a second reset unit; the second reset unit includes: an eighth NOT gate, a ninth NOT gate, a fifth NOR gate, and a sixth NOR gate; the input terminal of the eighth NOT gate is connected to the output terminal of the first transmission unit, and the output terminal of the eighth NOT gate is connected to the first input terminal of the fifth NOR gate; the second input terminal of the fifth NOR gate is connected to the first input terminal of the sixth NOR gate, and the output terminal of the fifth NOR gate is connected to the enable terminal of the first generation unit; the input terminal of the ninth NOT gate is connected to the output terminal of the second transmission unit, and the output terminal of the ninth NOT gate is connected to the second input terminal of the sixth NOR gate; the first input terminal of the sixth NOR gate receives a reset signal, and the output terminal of the sixth NOR gate is connected to the enable terminal of the second generation unit.

[0019] According to some embodiments, a second aspect of this application provides a memory, including: a clock generation circuit and a chip test circuit as described above; wherein the clock generation circuit and the chip test circuit are connected to provide an output clock for the chip test circuit, and the chip test circuit is used to perform chip select signal testing on the memory.

[0020] In the clock generation circuit and memory provided in this application embodiment, the sampling module samples consecutive chip select signals based on odd and even clocks to obtain odd and even data. The detection module detects whether adjacent chip select signals meet predetermined conditions based on the odd and even data. When adjacent chip select signals meet the predetermined conditions, the generation module starts generating an output clock. Through this scheme, predetermined conditions that characterize the start of chip select testing can be set according to actual testing. This enables the acquisition and detection of each data bit in the chip select signal based on odd and even clocks with a clock period twice the system clock period, and timely generation of the output clock. This ensures accurate and reliable sampling while generating the output clock promptly. This output clock, combined with the accurate output of the chip select test results, achieves accurate and reliable chip select testing. Attached Figure Description

[0021] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of the embodiments of this application.

[0022] Figure 1 This is an example diagram of the architecture of a memory according to an embodiment of this application;

[0023] Figure 2 This is a structural example diagram of a storage cell shown in one embodiment of this application;

[0024] Figure 3 The storage topology is shown in the example.

[0025] Figure 4 A structural example diagram of a clock generation circuit provided in one embodiment;

[0026] Figure 5 and Figure 6 This is a timing example diagram for sampling;

[0027] Figure 7 This is a structural example diagram of a detection module provided in one embodiment;

[0028] Figure 8 and Figure 9 A time-series example diagram of a data sequence;

[0029] Figure 10 Structural example diagrams of the first and second arithmetic units provided in one embodiment;

[0030] Figure 11 and Figure 12 Example structural diagrams of the first and second delay units are provided for illustration;

[0031] Figures 13-16 The diagram below shows an example of the structure of the generated module.

[0032] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0033] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0034] The terms "comprising" and "having" in this application are used to indicate an open-ended inclusion, meaning that additional elements / components / etc. may exist besides those listed. The terms "first" and "second," etc., are used only as markings or distinctions and are not intended to limit the order or quantity of the objects. Furthermore, the different elements and areas in the accompanying drawings are only schematic and are therefore not limited to the dimensions or distances shown in the drawings.

[0035] The technical solution will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0036] Figure 1 This is an example diagram of the memory architecture shown in one embodiment of this application, such as... Figure 1 As shown, taking DRAM as an example, it includes data input / output buffers, row decoders, column decoders, sense amplifiers, and a memory array. The memory array mainly consists of word lines, bit lines, and memory cells. Word lines in the memory array extend along the row direction, and bit lines extend along the column direction. The intersection of word lines and bit lines is the memory cell of the memory array.

[0037] Each storage unit is used to store one bit of data. For example... Figure 2 As shown, Figure 2 This is a structural example diagram of a memory cell according to an embodiment of this application. The memory cell mainly consists of a transistor M and a capacitor C. The capacitor is used to store data, and the transistor is used to turn off or on depending on the word line state.

[0038] Access to a memory cell can be achieved by controlling rows and columns. Taking a read scenario as an example: when data needs to be read from a memory cell, the word line of the row containing that memory cell is selected using a row decoder. Correspondingly, transistor M in the diagram turns on, and the state of capacitor C can be detected by sensing and amplifying the bit line signal. For example, if the data stored in the memory cell is 1, then after transistor M turns on, 1 will be read from the bit line of the memory cell, and vice versa. Furthermore, taking a write scenario as an example: when data needs to be written to a memory cell, such as writing 1, the word line of the row containing that memory cell is selected using a row decoder. The corresponding transistor M in the diagram turns on, and by setting the logic level of the bit line to 1, capacitor C is charged, thus writing 1 to the memory cell. Conversely, to write 0, the logic level of the bit line is set to 0, causing capacitor C to discharge, thus writing 0 to the memory cell.

[0039] In practical applications, multiple memory chips are typically used to increase storage capacity. For example, Figure 3This diagram illustrates a storage topology. It should be noted that this is merely an example; various chip topologies exist in related technologies, including but not limited to dual-T architectures and Fly-By topologies, and no limitation is imposed here. Referring to the example, when accessing a memory cell is required, the memory chip containing that cell must first be selected, i.e., chip selection. For instance, when the chip select signal for a memory chip is latched high, all commands are ignored, meaning the memory chip is not selected; conversely, if it is low, the memory chip is selected and commands can be executed. Then, the corresponding memory cell is selected from the selected chips based on address information, thereby enabling access to that memory cell, such as data access. It is evident that the chip select signal affects whether the desired memory cell can be successfully addressed. Therefore, relevant standards specify requirements for chip select signal testing. As an example, during the test, a sample signal is sent to the memory. The memory performs calculations based on the sampled chip select signal to obtain the calculation result. If the calculation result is consistent with the standard result, it means that the memory can receive the chip select signal normally, and the CS test passes; otherwise, it means that the memory cannot receive the chip select signal correctly.

[0040] Taking Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) as an example, the DDR5 standard specifies a Chip Select Test Mode (CSTM) to provide an independent mode for CS testing. Once in CSTM mode, the DRAM samples the received CS signal on the rising edge of the clock. Specifically, CSTM mode can be entered and exited using Multi-Purpose Commands (MPC).

[0041] In practical applications, because DDR5's speed and frequency are significantly higher than DDR4, higher requirements are placed on the reliability of CS testing. In some embodiments, odd and even clocks with a clock period twice the system clock period are used to sample and process the chip select signal, and the result of the operation is output in response to the output clock. Here, the output clock is used to capture and output the result of the operation based on the complete chip select signal to realize chip select signal testing. Therefore, it is necessary to ensure that an accurate output clock is provided in a timely manner when chip select testing begins.

[0042] Some aspects of the embodiments of this application relate to the above considerations. The following describes the solutions with reference to some embodiments of this application.

[0043] Example 1

[0044] Figure 4A structural example diagram of a clock generation circuit provided in one embodiment is shown below. Figure 4 As shown, the clock generation circuit includes:

[0045] The sampling module 11 is used to sample the continuous chip select signal based on the sampling clock. The holding time of each data bit of the chip select signal is equal to the period of the system clock. The sampling clock includes odd clock and even clock with opposite phases. The period of the odd clock and even clock is equal to twice the period of the system clock. The data sampled based on the odd clock is called odd data, and the data sampled based on the even clock is called even data.

[0046] The detection module 12, connected to the sampling module 11, is used to output a first state indication signal when it detects that adjacent chip select signals meet predetermined conditions, and otherwise output a second state indication signal; wherein, the predetermined conditions include that the data bits of the preceding chip select signal are all in the first level state, and the first data bit of the following chip select signal is in the second level state.

[0047] The generation module 13, connected to the detection module, is used to generate an output clock when the indicator signal is in the first state; wherein, the period of the output clock is the length of a single chip select signal, and the rising edge of the output clock is aligned with the rising edge of the sampling clock of the next chip select signal that first samples the first data bit as low.

[0048] In practical applications, the chip test circuit provided in this embodiment can be used in various memories. For example, it can be applied to, but is not limited to, Double Data Rate Synchronous Dynamic Random Access Memory (DDR). Each chip select signal includes at least one data bit. In one example, considering a memory scenario, each chip select signal includes four data bits.

[0049] Taking DDR5 as an example, let's illustrate with a practical scenario: When CS testing is required, CSTM mode can be activated. Considering the high speed of DDR5, to ensure sampling reliability, some embodiments use odd and even clocks with opposite phases and periods twice the system clock period for sampling. The corresponding sampled signals are called odd data and even data, respectively, thus providing a sufficient sampling window for the chip select signal, avoiding sampling errors and failures, and ensuring the accuracy of CS testing. As an example, the chip select signal can be sampled at the rising edge of the odd and even clocks. It should be noted that "odd data" and "even data" here are only names for the data acquired in response to the odd and even clocks, and do not limit the specific content of the actual sampled data or its parity attribute in the chip select signal. Subsequently, chip select test calculations are performed based on the odd data to obtain the calculation results. The output clock controls when the computation result is output. This is because odd and even data cannot always form a complete chip select signal. Instead, a complete chip select signal is formed only within a specific time period, such as after the last data bit of the chip select signal is sampled and before the sampling of the new chip select signal begins. The output clock controls the output of the computation result within this specific time period, ignoring the computation results obtained in other time periods to ensure the accuracy of the test results.

[0050] Therefore, the timely generation of the output clock affects the accuracy of the test results. In this embodiment, a predetermined condition that characterizes the start of the chip select test is set to ensure the timely provision of the output clock. The predetermined condition here is set on the chip select signal; that is, when the data of the chip select signal meets the predetermined condition, it indicates that the chip select test has started. This predetermined condition can be set in advance, and the chip select signal is provided based on this predetermined condition in subsequent applications, so as to identify whether the test has started. In practical applications, relevant standards specify relevant content regarding chip select signal testing. For example, after receiving an instruction to enter CSTM mode, before the sample signal of the input chip select signal is received, the chip select signal is controlled to maintain a high level for a period of time before the actual chip select test begins, that is, the sample signal of the input chip select signal is used to perform calculations and output the calculation results. Therefore, in one example, the predetermined condition may include all data bits of the previous chip select signal being 1 and the first data bit of the next chip select signal being 0. In this way, no adjustment to other signals is required to accurately identify when the chip select test starts.

[0051] Combination Figure 5 and Figure 6 Example: Figure 5 and Figure 6This is a timing example diagram for sampling. CS is the chip select signal, CLK is the system clock, CLK_E is the even clock, and CLK_O is the odd clock. Odd data obtained from sampling based on the odd clock is denoted as ODD, and even data obtained from sampling based on the even clock is denoted as EVEN. Furthermore, the diagram illustrates two scenarios: one where the chip select test is initiated first in response to an odd clock, and the other where the chip select test is initiated first in response to an even clock.

[0052] In one example Figure 7 A structural example diagram of a detection module provided in one embodiment is shown below. Figure 7 As shown, the detection module 12 includes: a first delay unit 21, a second delay unit 22, a first arithmetic unit 23, and a second arithmetic unit 24;

[0053] The first delay unit 21 is connected to the sampling module 11 and is used to output the odd data ODD sequentially with a predetermined time interval to obtain the first delayed odd data ODD1, the second delayed odd data ODD2, the third delayed odd data ODD3, the fourth delayed odd data ODD4 and the fifth delayed odd data ODD5.

[0054] The second delay unit 22 is connected to the sampling module 11 and is used to output the even data EVEN sequentially according to the time interval to obtain the first delayed even data EVEN1, the second delayed even data EVEN2, the third delayed even data EVEN3, the fourth delayed even data EVEN4 and the fifth delayed even data EVEN5.

[0055] The input terminal of the first arithmetic unit 23 is connected to the first delay unit 21 and the second delay unit 22. The first arithmetic unit 23 is used to receive the first delayed odd data ODD1, the second delayed even data EVEN2, the third delayed odd data ODD3, the fourth delayed even data EVEN4 and the fifth delayed odd data ODD5, and to detect whether the predetermined conditions are met. The output terminal of the first arithmetic unit 23 is connected to the generation module 13.

[0056] The input terminal of the second operation unit 24 is connected to the first delay unit 21 and the second delay unit 22. The second operation unit 24 is used to receive the first delayed even data EVEN1, the second delayed odd data ODD2, the third delayed even data EVEN3, the fourth delayed odd data ODD4 and the fifth delayed even data EVEN5, and to detect whether the predetermined conditions are met. The output terminal of the second operation unit 23 is connected to the generation module 13.

[0057] In one example, the time interval is one system clock cycle. Combined Figure 8 and Figure 9 Example: Figure 8 and Figure 9This is a timing example diagram of the data sequence. The data sequence is generated by the first and second delay units based on the sampled odd and even data. For example, the data sequence includes ODD1 to ODD5 output by the first delay unit and EVEN1 to EVEN5 output by the second delay unit. Specifically, since this embodiment uses odd and even clocks to sample the chip select signal, before performing the chip select test, it is necessary to integrate the previous chip select signal (four data bits) and the first data bit of the subsequent chip select signal based on the sampled odd and even data. When these five data bits satisfy 11110, i.e., the predetermined condition is met, it indicates that the chip select test begins. Specifically, the chip select signal with the first data bit being 0 is the first sample signal. In this example, the first and second arithmetic units correspond to the two cases mentioned above, combined with... Figure 8 In the example, the first arithmetic unit detects that the current five data bits meet the predetermined conditions in response to the odd clock of the sampling module. That is, the received fifth delayed odd data ODD5, fourth delayed even data EVEN4, third delayed odd data ODD3, and second delayed even data EVEN2 are a chip select signal, and each data bit is 1. The first data bit D0 of the next chip select signal is 0.

[0058] Specifically, the first and second arithmetic units, based on the received signals, perform calculations to detect whether predetermined conditions are met. In some examples, Figure 10 Structural example diagrams of the first and second arithmetic units provided in one embodiment, such as... Figure 10 As shown, the first arithmetic unit includes 23: a first NOT gate 231, a first NAND gate 232, a second NAND gate 233, and a first NOR gate 234;

[0059] The input of the first NOT gate 231 receives the first delayed odd data ODD1, and the output of the first NOT gate 231 is connected to the first input of the first NAND gate 232; the second input of the first NAND gate 232 receives the second delayed even data EVEN2, the third input of the first NAND gate 232 receives the third delayed odd data ODD3, and the output of the first NAND gate 232 is connected to the first input of the first NOR gate 234; the first input of the second NAND gate 233 receives the fourth delayed even data EVEN4, the second input of the second NAND gate 233 receives the fifth delayed odd data ODD5, and the output of the second NAND gate 233 is connected to the second input of the first NOR gate 234; the output of the first NOR gate 234 is connected to the generation module 13.

[0060] The second arithmetic unit 24 includes: a second NOT gate 241, a third NAND gate 242, a fourth NAND gate 243, and a second NOR gate 244; the input of the second NOT gate 241 receives the first delayed even data EVEN1, and the output of the second NOT gate 241 is connected to the first input of the third NAND gate 242; the second input of the third NAND gate 242 receives the second delayed odd data ODD2, the third input of the third NAND gate 242 receives the third delayed even data EVEN3, and the output of the third NAND gate 242 is connected to the first input of the second NOR gate 244; the first input of the fourth NAND gate 243 receives the fourth delayed odd data ODD4, the second input of the fourth NAND gate 243 receives the fifth delayed even data EVEN5, and the output of the fourth NAND gate 243 is connected to the second input of the second NOR gate 244; the output of the second NOR gate 244 is connected to the generation module 13.

[0061] In practical applications, the operation result output by the operation module indicates whether a predetermined condition is met. Taking the first operation unit as an example, assume that ODD5, EVEN4, ODD3, and EVEN2 are all 1, and ODD1 is 0. Then, ODD1 outputs 1 through the first NOT gate, and ODD3 and EVEN2, which sum to 1, are input to the first NAND gate for a NAND operation. The first NAND gate outputs 0 to the first NOR gate. At this time, ODD5 and EVEN4, which are 1, are input to the second NAND gate for a NAND operation. The second NAND gate outputs 0 to the first NOR gate. Correspondingly, both inputs to the first NOR gate are 0, and the first NOR gate outputs 1, indicating that the predetermined condition is met, i.e., five consecutive data bits are 11110.

[0062] In this example, the first and second arithmetic units are implemented using conventional devices such as NOT gates, NAND gates, and NOR gates, thereby ensuring timely and accurate generation of the output clock while effectively simplifying the circuit structure and reducing costs.

[0063] Specifically, in order to detect whether five consecutive data bits meet the predetermined conditions based on the sampled odd and even data, the operation module first delays the odd and even data to obtain multiple data sequences, and then uses these multiple data sequences to combine into five consecutive data bits for operation.

[0064] As an example, Figure 11 Structural example diagrams of the first delay unit and the second delay unit provided in one embodiment, such as... Figure 11As shown, the first delay unit 21 includes: a plurality of first delay sub-units 211 connected in series; the input terminal of the first first delay sub-unit 211 is connected to the sampling module 11 for receiving first delayed odd data ODD1 generated based on odd data ODD; the input terminal of each first delay sub-unit 211 is connected to the output terminal of the previous first delay sub-unit 211, and each first delay sub-unit 211 is used to output the received data after a time interval; the second delay unit 22 includes: a plurality of second delay sub-units 221 connected in series; the input terminal of the first second delay sub-unit 221 is connected to the sampling module 11 for receiving first delayed even data EVEN1 generated based on even data EVEN; the input terminal of each second delay sub-unit 221 is connected to the output terminal of the previous second delay sub-unit 221, and each second delay sub-unit 221 is used to output the received data after a time interval.

[0065] The number of first and second delay sub-units can be determined based on the number of consecutive data bits specified in the predetermined conditions. For example, the number of both first and second delay sub-units is four. Specifically, the input of the first delay sub-unit outputs first delayed odd data ODD1, generated based on odd data ODD, and the output of each first delay sub-unit outputs ODD2, ODD3, ODD4, and ODD5, respectively. Similarly, the input of the first second delay sub-unit outputs first delayed even data EVEN1, generated based on even data EVEN, and the output of each second delay sub-unit outputs EVEN2, EVEN3, EVEN4, and EVEN5, respectively.

[0066] As an example, the time interval between adjacent delayed odd data is one system clock cycle, and the time interval between adjacent delayed even data is also one system clock cycle. Specifically, the odd and even clocks are out of phase and their periods are twice the system clock cycle, so the corresponding delayed odd and even data (e.g., between ODD1 and EVEN1, or between ODD2 and EVEN2) also differ by one system clock cycle. Combining the aforementioned example, the data sequences generated by the above delay units can form five consecutive data bits for detecting whether a predetermined condition is met, thereby achieving timely generation of the output clock.

[0067] In one example Figure 12 Structural example diagrams of the first delay unit and the second delay unit provided in one embodiment, such as... Figure 12As shown, each first delay sub-unit 211 includes a first flip-flop 31 and a third NOT gate 32. The input terminal of the first flip-flop 31 serves as the input terminal of the first delay sub-unit 211, and the output terminal of the first flip-flop 31 is connected to the input terminal of the third NOT gate 32. The output terminal of the third NOT gate 32 serves as the output terminal of the first delay sub-unit 211. The clock terminal of the odd-numbered first flip-flop 31 is connected to the inverted signal CLK_OB of the odd clock, and the clock terminal of the even-numbered first flip-flop 31 is connected to the odd clock CLK_O. Each second delay sub-unit 221 includes a second flip-flop 33 and a fourth NOT gate 34. The input terminal of the second flip-flop 33 serves as the input terminal of the second delay sub-unit 221, and the inverted output terminal of the second flip-flop 33 is connected to the input terminal of the fourth NOT gate 34. The output terminal of the fourth NOT gate 34 serves as the output terminal of the second delay sub-unit 221. The clock terminal of the odd-numbered second flip-flop 33 is connected to the inverted signal CLK_EB of the even clock, and the clock terminal of the even-numbered second flip-flop 33 is connected to the even clock CLK_E.

[0068] In this example, a delay sub-unit is constructed using flip-flops and NOT gates to generate a data sequence with a certain time interval, thereby enabling accurate subsequent detection of whether a predetermined condition has been met. Furthermore, the use of conventional components simplifies the circuit structure and reduces costs. Additionally, the combination of flip-flop output inversion and NOT gate inversion processing serves as a driving mechanism, improving the accuracy of the generated signal.

[0069] In light of the foregoing and considering the two scenarios, to achieve the output clock under different conditions, in one example, the output clock includes a first output clock CLK_2_O and a second output clock CLK_2_E with opposite phases. Furthermore, at any given time, either the first output clock CLK_2_O or the second output clock CLK_2_E is valid; the validity of either output clock indicates that the sampling clock corresponding to that output clock is the first to sample the next chip select signal where the first data bit is low.

[0070] Specifically, the first output clock CLK_2_O corresponds to the odd clock CLK_O, and the second output clock CLK_2_E corresponds to the even clock CLK_E. Each rising edge of the output clock corresponds to the rising edge of the corresponding sampling clock. As an example, a single chip select signal includes four data bits; correspondingly, the period of the output clock is the same as the length of a single chip select signal, which is four system clock cycles, or twice the sampling clock. In one example, the corresponding output clock can be generated based on the sampling clock using a frequency divider circuit DIV.

[0071] As an example, Figure 13 Here is a structural example diagram of a generation module provided in one embodiment, such as... Figure 13As shown, the generation module 13 includes: a selection unit 131, a first generation unit 132, and a second generation unit 133;

[0072] Selection unit 131 is connected to first arithmetic unit 23 and second arithmetic unit 24; selection unit 131 is used to output a valid first enable signal CS_O to first generation unit 132 in response to the first arithmetic unit 23 first outputting an indication signal of a first state; and to output a valid second enable signal CS_E to second generation unit 133 in response to the second arithmetic unit 24 first outputting an indication signal of a first state.

[0073] The enable terminal of the first generation unit 132 is connected to the selection unit 131. The first generation unit 132 receives the odd clock CLK_O. The first generation unit 132 is used to divide the odd clock CLK_O in response to the first enable signal CS_O being valid, and output the first output clock CLK_2_O.

[0074] The enable terminal of the second generation unit 133 is connected to the selection unit 131. The second generation unit 133 receives the even clock CLK_E. In response to the second enable signal CS_E being valid, the second generation unit 133 divides the even clock CLK_E and outputs the second output clock CLK_2_E.

[0075] The first state can be set according to actual conditions. For example, if the first state is high, then when the signal output by a certain arithmetic unit is 1, it indicates that the five consecutive data bits received currently meet the predetermined conditions. Accordingly, the selection unit will output a valid enable signal to the generation unit corresponding to the arithmetic unit that first received the first state, so that the generation unit outputs the corresponding output clock based on the received sampling clock. At the same time, the selection unit will reset the generation unit corresponding to another arithmetic unit, so that only one valid output clock is provided at any given time, thereby avoiding signal conflicts when the operation results obtained in response to odd clocks and even clocks are output during subsequent chip select testing.

[0076] In one example Figure 14 Here is a structural example diagram of a generation module provided in one embodiment, such as... Figure 14 As shown, the selection unit 131 includes: a first transmission unit 41, a second transmission unit 42, and a control unit 43;

[0077] The input terminal of the first transmission unit 41 receives a first high-level signal, the control terminal of the first transmission unit 41 receives an indication signal output by the first arithmetic unit 23, and the output terminal of the first transmission unit 41 is connected to the enable terminal of the first generation unit 132 and the control unit 43; the first transmission unit 41 is used to transmit the first high-level signal to the control unit 43 when the indication signal output by the first arithmetic unit 23 is in the first state.

[0078] The input terminal of the second transmission unit 42 receives a second high-level signal, the control terminal of the second transmission unit 42 receives an indication signal output by the second arithmetic unit 24, and the output terminal of the second transmission unit 42 is connected to the enable terminal of the second generation unit 133 and the control unit 43; the second transmission unit 42 is used to transmit the second high-level signal to the control unit 43 when the indication signal output by the second arithmetic unit 24 is in the first state.

[0079] The control unit 43 is connected to the enable terminal of the first transmission unit 41 and the enable terminal of the second transmission unit 42, and is used to enable the first transmission unit 41 and reset the second transmission unit 42 when a signal output by the first transmission unit 41 is received; and to enable the second transmission unit 42 and reset the first transmission unit 41 when a signal output by the second transmission unit 42 is received.

[0080] Specifically, the selection unit is used to enable the corresponding generation unit and reset the generation unit corresponding to the other operation unit when either the first operation unit or the second operation unit detects that a predetermined condition is met, i.e., the operation unit outputs an indication signal of a first state. Taking the first operation unit outputting the indication signal of the first state as an example, the first transmission unit transmits a first high-level signal to the control unit. Upon receiving this signal, the control unit enables the first transmission unit and resets the second transmission unit. After passing through the enabled first transmission unit, the first high-level signal is transmitted to the enable terminal of the first generation unit to enable the first generation unit to operate and output a first output clock. The implementation of the first high-level signal and the second high-level signal is not limited; they can be the same or different. In practice, they can be set according to the enable level of the generation unit. As an example, both the first high-level signal and the second high-level signal are power supply signals VDD. It should be noted that in this example, the first high-level signal output by the first transmission unit is used as the enable signal CS_O of the first generation unit, and the second high-level signal output by the second transmission unit is used as the enable signal CS_E of the second generation unit. In practical applications, the situation is not limited to the example. For example, the high-level signal output by the transmission unit can be further logically operated or processed to obtain the enable signal of the generation unit. The specific content of the enable signal is not limited here.

[0081] In one example Figure 15 Here is a structural example diagram of a generation module provided in one embodiment, such as... Figure 15 As shown, the control unit 43 includes: a third NOR gate 431 and a fourth NOR gate 432; the input terminal of the third NOR gate 431 is connected to the output terminal of the second transmission unit 42, and the output terminal of the third NOR gate 431 is connected to the enable terminal of the first transmission unit 41; the input terminal of the fourth NOR gate 432 is connected to the output terminal of the first transmission unit 41, and the output terminal of the fourth NOR gate 432 is connected to the enable terminal of the second transmission unit 42.

[0082] Referring to the diagram, taking the example where the first arithmetic unit outputs a first-state indicator signal first, the first transmission unit outputs a high-level signal to the input of the fourth NOR gate. The fourth NOR gate then outputs a low-level signal to the enable terminal of the second transmission unit, resetting the second transmission unit. Similarly, taking the example where the second arithmetic unit outputs a first-state indicator signal first, the second transmission unit outputs a high-level signal to the input of the third NOR gate. The third NOR gate then outputs a low-level signal to the enable terminal of the first transmission unit, resetting the first transmission unit. In this example, using two NOR gates to control the enabling or resetting of the transmission unit based on the output indicator signal from the arithmetic unit further simplifies the circuit structure.

[0083] Considering the scenarios requiring reset in practical applications, in one example, such as Figure 15 As shown, the control unit 43 further includes: a first reset unit 433; the first reset unit 433 includes: a seventh NOT gate and an OR gate; the input of the seventh NOT gate receives the test mode signal CSTM_ENT, and the output of the seventh NOT gate is connected to the first input of the OR gate; the second input of the OR gate receives the reset signal VPU RST, and the output of the OR gate is connected to the other input of the third NOR gate 431 and the other input of the fourth NOR gate 432.

[0084] The first reset unit performs a reset function. Specifically, when the reset signal VPU RST is 1, both the third and fourth NOR gates output 0, resetting both the first and second transmission units. It should be noted that although it is called the first reset unit, it does not limit other functions besides reset. For example, in practical applications, considering that DDR5 specifies a dedicated Chip Select Test Mode (CSTM), the first reset unit can also be configured to control entering or exiting this mode for better suitability for memory scenarios. Referring to the illustration, when entering CSTM mode, the test mode signal CSTM_ENT is active, for example, 1. After passing through the seventh NOT gate, it outputs 0 to the OR gate. Assuming no reset is performed at this time, the reset signal VPU RST is 0, so the OR gate outputs 0, and the first and second transmission units are not reset. The two transmission units can then operate normally according to the aforementioned principle. When exiting CSTM mode, the test mode signal CSTM_ENT is inactive, for example, 0. The signal passes through the seventh NOT gate and outputs 1 to the OR gate. Regardless of whether the reset signal VPU RST is 1 or 0 at this time, the OR gate outputs 1, and the third and fourth NOR gates both output 0. The first and second transmission units are reset and do not operate. This example demonstrates how to effectively and promptly reset and control the control unit.

[0085] Specifically, under the control of the control unit, either the first transmission unit or the second transmission unit is selected to transmit the level signal to the corresponding generation unit, so that the generation unit can output the corresponding output clock. In one example, such as Figure 15 As shown, the first transmission unit 41 includes a third flip-flop 411; the input of the third flip-flop 411 receives a first high-level signal VDD, the clock terminal of the third flip-flop 411 receives an indication signal output by the first arithmetic unit 23, and the output terminal of the third flip-flop 411 is connected to the enable terminals of the control unit 43 and the first generation unit 132; the second transmission unit 42 includes a fourth flip-flop 421; the input of the fourth flip-flop 421 receives a second high-level signal VDD, the clock terminal of the fourth flip-flop 421 receives an indication signal output by the second arithmetic unit 24, and the output terminal of the fourth flip-flop 421 is connected to the enable terminals of the control unit 43 and the second generation unit 133.

[0086] In this example, a trigger is used to transmit a high-level signal from the first or second transmission unit to the corresponding generation unit under the control of the control unit, thereby enabling the generation unit and resetting another generation unit. This not only achieves timely and accurate generation of the output clock, but also further simplifies the circuit structure.

[0087] In this embodiment, two generation units are provided for the two aforementioned scenarios to offer output clocks under different conditions. In one example, Figure 16Here is a structural example diagram of a generation module provided in one embodiment, such as... Figure 16 As shown, the first generation unit 132 includes a first flip-flop 51 and a third delay unit 52; the input terminal of the first flip-flop 51 is connected to the inverted output terminal of the first flip-flop 51, the clock terminal of the first flip-flop 51 receives an odd clock CLK_0, the reset terminal of the first flip-flop 51 is the enable terminal of the first generation unit 132, and the output terminal of the first flip-flop 51 is connected to the input terminal of the third delay unit 52; the third delay unit 52 is used to delay the signal output by the first flip-flop 51 to obtain the first output clock CLK_2_0;

[0088] The second generation unit 133 includes a second flip-flop 53 and a fourth delay unit 54; the input terminal of the second flip-flop 53 is connected to the inverted output terminal of the second flip-flop 53, the clock terminal of the second flip-flop 53 receives an even clock CLK_E, the reset terminal of the second flip-flop 53 is the enable terminal of the second generation unit 133, and the output terminal of the second flip-flop 53 is connected to the input terminal of the fourth delay unit 54; the fourth delay unit 54 is used to delay the signal output by the second flip-flop 53 to obtain a second output clock CLK_2_E.

[0089] Specifically, when the first and second generation units are enabled, they output an output clock with a period twice the period of the received sampling clock, based on the received sampling clock. Furthermore, the first or second generation unit is enabled when the first or second arithmetic unit detects that a predetermined condition is met. Therefore, the rising edge of the output clock is aligned with the rising edge of the sampling clock at which the chip select signal was first sampled, i.e., the starting point of the chip select test. To improve signal quality, multi-stage inverting drives are added to the generated output clock. In one example, both the third delay unit 52 and the fourth delay unit 54 include multiple cascaded fifth NOT gates, where the number of fifth NOT gates is even.

[0090] In one example, the first generation unit 132 further includes a fifth delay unit 55; the input of the fifth delay unit 55 is connected to the output of the first flip-flop 51, and the fifth delay unit 55 is used to invert and delay the signal output by the first flip-flop 51 to obtain the inverted signal CLK_2_OB of the first output clock CLK_2_O; the second generation unit 133 further includes a sixth delay unit 56; the input of the sixth delay unit 56 is connected to the output of the second flip-flop 53, and the sixth delay unit 56 is used to invert and delay the signal output by the second flip-flop 53 to obtain the inverted signal CLK_2_EB of the second output clock CLK_2_E. In this example, by generating the inverted signal of the output clock, the richness of the output clock signal is improved. As an example, both the fifth delay unit 55 and the sixth delay unit 56 include multiple sixth NOT gates connected in series, wherein the number of the multiple sixth NOT gates is odd. In this example, the inversion and delay processing is implemented using conventional NOT gates, further simplifying the circuit structure.

[0091] Also considering the reset functions of the first generation unit and the second generation unit, in one example, the generation module 13 further includes: a second reset unit 134; the second reset unit 134 includes: an eighth NOT gate 61, a ninth NOT gate 62, a fifth NOR gate 63 and a sixth NOR gate 64;

[0092] The input terminal of the eighth NOT gate 61 is connected to the output terminal of the first transmission unit 41, and the output terminal of the eighth NOT gate 61 is connected to the first input terminal of the fifth NOR gate 63; the second input terminal of the fifth NOR gate 63 is connected to the first input terminal of the sixth NOR gate 64, and the output terminal of the fifth NOR gate 63 is connected to the enable terminal of the first generation unit 132.

[0093] The input terminal of the ninth NOT gate 62 is connected to the output terminal of the second transmission unit 42, and the output terminal of the ninth NOT gate 62 is connected to the second input terminal of the sixth NOR gate 64; the first input terminal of the sixth NOR gate 64 receives the reset signal VPU RST, and the output terminal of the sixth NOR gate 64 is connected to the enable terminal of the second generation unit 133.

[0094] In this example, a second reset unit is set for the first generation unit and the second generation unit to realize the reset function of the generation unit, improve the reliability of circuit operation, and simplify the circuit structure.

[0095] In the clock generation circuit provided in this embodiment, the sampling module samples consecutive chip select signals based on odd and even clocks to obtain odd and even data. The detection module detects whether adjacent chip select signals meet predetermined conditions based on the odd and even data. When adjacent chip select signals meet the predetermined conditions, the generation module starts generating the output clock. Through this scheme, predetermined conditions that characterize the start of chip select testing can be set according to actual testing. This enables the acquisition and detection of each data bit in the chip select signal based on odd and even clocks with a clock period twice the system clock period, and timely generation of the output clock. This ensures accurate and reliable sampling while timely generation and provision of the output clock, which can be used to coordinate with the accurate output of chip select test results, achieving accurate and reliable chip select testing.

[0096] Example 2

[0097] Embodiment 2 of this application provides a memory, which includes: a chip testing circuit and a clock generation circuit as described above; wherein...

[0098] The clock generation circuit is connected to the chip test circuit to provide the output clock for the chip test circuit, which is used to test the chip select signal of the memory.

[0099] As an example, when CS testing is required, the chip test circuit and clock generation circuit can be activated to enter CSTM mode. After a certain period of time, a sample signal of the chip select signal is input. When the clock generation circuit detects the sample signal, it starts generating the output clock. Simultaneously, the chip test circuit samples using odd and even clocks to obtain odd and even data. The odd and even clocks have opposite phases and their periods are twice the system clock period, thus providing a sufficient sampling window for the chip select signal, avoiding sampling errors and failures, and ensuring the accuracy of the CS test. Based on the sampled odd and even data, a complete chip select signal is integrated for chip select test calculations. The calculation result is output when the rising edge of the output clock provided by the clock generation circuit arrives. The output calculation result is compared with the standard result to determine whether the chip select signal reception is normal.

[0100] In the memory provided in this embodiment, the chip test circuit performs sampling and comparison operations based on odd and even clocks to obtain the operation results, and outputs the operation results in response to the output clock provided by the clock generation circuit. Specifically, the sampling module of the clock generation circuit samples based on odd and even clocks to obtain odd and even data, and the detection module detects whether adjacent chip select signals meet predetermined conditions based on the odd and even data. When adjacent chip select signals are detected to meet the predetermined conditions, the generation module starts generating the output clock. Through the above scheme, predetermined conditions that can characterize the start of chip select testing can be set according to actual testing. This enables the acquisition and detection of each data bit in the chip select signal based on odd and even clocks with a clock period twice the system clock period, and timely generation of the output clock. Thus, while ensuring accurate and reliable sampling, the output clock can be generated and provided in a timely manner. This output clock can be used to cooperate with the accurate output of chip select test results, achieving accurate and reliable chip select testing.

[0101] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0102] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A clock generation circuit, characterized in that, include: A sampling module is used to sample continuous chip select signals based on a sampling clock. The holding time of each data bit of the chip select signal is equal to the period of the system clock. The sampling clock includes an odd clock and an even clock with opposite phases. The period of the odd clock and the even clock is equal to twice the period of the system clock. Data sampled based on the odd clock is denoted as odd data, and data sampled based on the even clock is denoted as even data. A detection module, connected to the sampling module, is used to output a first state indication signal when it detects that adjacent chip select signals meet predetermined conditions, and otherwise output a second state indication signal; wherein, the predetermined conditions include that all data bits of the preceding chip select signal are in the first level state, and the first data bit of the following chip select signal is in the second level state. A generation module, connected to the detection module, is used to generate an output clock when the indication signal is in a first state; wherein the period of the output clock is the length of a single chip select signal, and the rising edge of the output clock is aligned with the rising edge of the sampling clock of the next chip select signal that first samples the first data bit as low.

2. The clock generation circuit according to claim 1, characterized in that, Each chip select signal consists of four data bits.

3. The clock generation circuit according to claim 2, characterized in that, The detection module includes: a first delay unit, a second delay unit, a first arithmetic unit, and a second arithmetic unit; The first delay unit, connected to the sampling module, is used to sequentially delay the odd data according to a predetermined time interval to obtain the first delayed odd data, the second delayed odd data, the third delayed odd data, the fourth delayed odd data, and the fifth delayed odd data. The second delay unit, connected to the sampling module, is used to sequentially delay the even data according to the time interval to output the first delayed even data, the second delayed even data, the third delayed even data, the fourth delayed even data, and the fifth delayed even data. The input terminal of the first arithmetic unit is connected to the first delay unit and the second delay unit. The first arithmetic unit is used to receive the first delayed odd data, the second delayed even data, the third delayed odd data, the fourth delayed even data, and the fifth delayed odd data, and to detect whether the predetermined condition is met. The output terminal of the first arithmetic unit is connected to the generation module. The input terminal of the second arithmetic unit is connected to the first delay unit and the second delay unit. The second arithmetic unit is used to receive the first delay even data, the second delay odd data, the third delay even data, the fourth delay odd data and the fifth delay even data, and to detect whether the predetermined condition is met. The output terminal of the second arithmetic unit is connected to the generation module.

4. The clock generation circuit according to claim 3, characterized in that, The first arithmetic unit includes: a first NOT gate, a first NAND gate, a second NAND gate, and a first NOR gate; the input of the first NOT gate receives the first delayed odd data, and the output of the first NOT gate is connected to the first input of the first NAND gate; the second input of the first NAND gate receives the second delayed even data, the third input of the first NAND gate receives the third delayed odd data, and the output of the first NAND gate is connected to the first input of the first NOR gate; the first input of the second NAND gate receives the fourth delayed even data, the second input of the second NAND gate receives the fifth delayed odd data, and the output of the second NAND gate is connected to the second input of the first NOR gate; the output of the first NOR gate is connected to the generation module. The second arithmetic unit includes: a second NOT gate, a third NAND gate, a fourth NAND gate, and a second NOR gate; the input of the second NOT gate receives the first delayed even data, and the output of the second NOT gate is connected to the first input of the third NAND gate; the second input of the third NAND gate receives the second delayed odd data, the third input of the third NAND gate receives the third delayed even data, and the output of the third NAND gate is connected to the first input of the second NOR gate; the first input of the fourth NAND gate receives the fourth delayed odd data, the second input of the fourth NAND gate receives the fifth delayed even data, and the output of the fourth NAND gate is connected to the second input of the second NOR gate; the output of the second NOR gate is connected to the generation module.

5. The clock generation circuit according to claim 3, characterized in that, The first delay unit includes: a plurality of first delay sub-units connected in series; the input terminal of the first first delay sub-unit is connected to the sampling module for receiving the first delayed odd data generated based on the odd data; the input terminal of each first delay sub-unit is connected to the output terminal of the previous first delay sub-unit, and each first delay sub-unit is used to output the received data after the time interval. The second delay unit includes: a plurality of second delay sub-units connected in series; the input terminal of the first second delay sub-unit is connected to the sampling module for receiving the first delayed even data generated based on the even data; the input terminal of each second delay sub-unit is connected to the output terminal of the previous second delay sub-unit, and each second delay sub-unit is used to output the received data after the time interval.

6. The clock generation circuit according to any one of claims 3-5, characterized in that, The output clock includes a first output clock and a second output clock with opposite phases; At the same time, either the first output clock or the second output clock is valid; The validity of any one of the output clocks indicates that the sampling clock corresponding to that output clock first samples the next chip select signal when the first data bit is in a low-level state.

7. The clock generation circuit according to claim 6, characterized in that, The generation module includes: a selection unit, a first generation unit, and a second generation unit; The selection unit is connected to the first arithmetic unit and the second arithmetic unit; the selection unit is configured to output a valid first enable signal to the first generation unit in response to the first arithmetic unit first outputting an indication signal of a first state; and to output a valid second enable signal to the second generation unit in response to the second arithmetic unit first outputting an indication signal of a first state. The enable terminal of the first generation unit is connected to the selection unit. The first generation unit receives the odd clock. In response to the first enable signal being valid, the first generation unit divides the odd clock and outputs the first output clock. The enable terminal of the second generation unit is connected to the selection unit. The second generation unit receives the even clock and, in response to the second enable signal being valid, divides the even clock and outputs the second output clock.

8. The clock generation circuit according to claim 7, characterized in that, The first generation unit includes a first flip-flop and a third delay unit; the input terminal of the first flip-flop is connected to the inverted output terminal of the first flip-flop, the clock terminal of the first flip-flop receives the odd clock, the reset terminal of the first flip-flop is the enable terminal of the first generation unit, and the output terminal of the first flip-flop is connected to the input terminal of the third delay unit; the third delay unit is used to delay the signal output by the first flip-flop to obtain the first output clock. The second generation unit includes a second flip-flop and a fourth delay unit; the input terminal of the second flip-flop is connected to the inverted output terminal of the second flip-flop, the clock terminal of the second flip-flop receives the even clock, the reset terminal of the second flip-flop is the enable terminal of the second generation unit, and the output terminal of the second flip-flop is connected to the input terminal of the fourth delay unit; the fourth delay unit is used to delay the signal output by the second flip-flop to obtain the second output clock.

9. The clock generation circuit according to claim 8, characterized in that, The first generation unit further includes a fifth delay unit; the input terminal of the fifth delay unit is connected to the output terminal of the first flip-flop, and the fifth delay unit is used to invert and delay the signal output by the first flip-flop to obtain the inverted signal of the first output clock; The second generation unit further includes a sixth delay unit; the input terminal of the sixth delay unit is connected to the output terminal of the second flip-flop, and the sixth delay unit is used to invert and delay the signal output by the second flip-flop to obtain the inverted signal of the second output clock.

10. The clock generation circuit according to any one of claims 7-9, characterized in that, The selection unit includes: a first transmission unit, a second transmission unit, and a control unit; the input terminal of the first transmission unit receives a first high-level signal, the control terminal of the first transmission unit receives an indication signal output by the first arithmetic unit, and the output terminal of the first transmission unit is connected to the enable terminal of the first generation unit and the control unit; the first transmission unit is used to transmit the first high-level signal to the control unit when the indication signal output by the first arithmetic unit is in a first state. The input terminal of the second transmission unit receives a second high-level signal, the control terminal of the second transmission unit receives an indication signal output by the second arithmetic unit, and the output terminal of the second transmission unit is connected to the enable terminal of the second generation unit and the control unit; the second transmission unit is used to transmit the second high-level signal to the control unit when the indication signal output by the second arithmetic unit is in a first state. The control unit is connected to the enable terminal of the first transmission unit and the enable terminal of the second transmission unit, and is used to enable the first transmission unit and reset the second transmission unit when a signal output by the first transmission unit is received; and to enable the second transmission unit and reset the first transmission unit when a signal output by the second transmission unit is received.

11. The clock generation circuit according to claim 10, characterized in that, The control unit includes: a third NOR gate and a fourth NOR gate; The input terminal of the third NOR gate is connected to the output terminal of the second transmission unit, and the output terminal of the third NOR gate is connected to the enable terminal of the first transmission unit. The input terminal of the fourth NOR gate is connected to the output terminal of the first transmission unit, and the output terminal of the fourth NOR gate is connected to the enable terminal of the second transmission unit.

12. The clock generation circuit according to claim 11, characterized in that, The control unit further includes: a first reset unit; The first reset unit includes: a seventh NOT gate and an OR gate; the input terminal of the seventh NOT gate receives a test mode signal, and the output terminal of the seventh NOT gate is connected to the first input terminal of the OR gate; the second input terminal of the OR gate receives a reset signal, and the output terminal of the OR gate is connected to the other input terminal of the third NOR gate and the other input terminal of the fourth NOR gate.

13. The clock generation circuit according to claim 10, characterized in that, The generation module further includes: a second reset unit; the second reset unit includes: an eighth NOT gate, a ninth NOT gate, a fifth NOR gate and a sixth NOR gate; The input terminal of the eighth NOT gate is connected to the output terminal of the first transmission unit, and the output terminal of the eighth NOT gate is connected to the first input terminal of the fifth NOR gate; the second input terminal of the fifth NOR gate is connected to the first input terminal of the sixth NOR gate, and the output terminal of the fifth NOR gate is connected to the enable terminal of the first generation unit. The input terminal of the ninth NOT gate is connected to the output terminal of the second transmission unit, and the output terminal of the ninth NOT gate is connected to the second input terminal of the sixth NOR gate; the first input terminal of the sixth NOR gate receives a reset signal, and the output terminal of the sixth NOR gate is connected to the enable terminal of the second generation unit.

14. A memory, characterized in that, include: The clock generation circuit and chip test circuit as described in any one of claims 1-13; wherein, The clock generation circuit is connected to the chip test circuit and is used to provide an output clock for the chip test circuit. The chip test circuit is used to perform chip select signal testing on the memory.

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