Lower electrode mechanism and semiconductor process apparatus

Abstract

The application provides a lower electrode mechanism and a semiconductor process equipment, which comprises a chuck, a partition distribution plate and a plurality of pulse generation modules, a plurality of electrode pieces are arranged in a medium layer of the chuck and are insulated and spaced from each other; the partition distribution plate is arranged below the medium layer, the pulse generation modules are arranged below the partition distribution plate and are used for generating pulse voltage signals; a distribution circuit is arranged on the partition distribution plate and is arranged to conduct a direct current adsorption voltage signal provided by an electrostatic adsorption power supply to each electrode piece, conduct the pulse voltage signal output by each pulse generation module to at least one electrode piece, and isolate the direct current adsorption voltage signal from the pulse voltage signal. The lower electrode mechanism and the semiconductor process equipment provided by the application can reduce the equivalent parasitic capacitance between the electrode pieces and the chamber structure, so that the heat loss of the pulse generation modules can be reduced.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more specifically, to a lower electrode mechanism and semiconductor process equipment. Background Technology

[0002] With the development of semiconductor manufacturing processes, the etching performance requirements for higher aspect ratios (HAR) are becoming increasingly stringent in the etching process of 3D NAND manufacturing, particularly in advanced memory fabrication. To optimize the aspect ratio parameter in the etching process, a narrower ion energy distribution (IED) is necessary, for example, by obtaining... Figure 1 The diagram shows a more ideal ion energy distribution, which allows for a smaller ion angle distribution and makes it easier to improve the performance of high aspect ratio etching processes.

[0003] Figure 1 This is a schematic diagram of the structure of existing semiconductor process equipment. (Example:) Figure 1 As shown, the semiconductor process equipment includes a process chamber, an upper electrode power supply, a switching mode power supply, an electrostatic chuck power supply, and a controller. An upper electrode is located at the top of the process chamber and is electrically connected to the upper electrode power supply. The upper electrode power supply applies excitation power to the upper electrode to excite the process gas in the process chamber to form plasma. A support structure is located at the bottom of the process chamber, and an electrostatic chuck is housed within this support structure to support the substrate. This electrostatic chuck is electrically connected to the electrostatic chuck power supply via the switching mode power supply. The controller controls the operation of the switching mode power supply and the electrostatic chuck power supply to apply pulsed bias and DC adsorption bias to the electrostatic chuck. The DC adsorption bias is used to adsorb the substrate during the semiconductor processing. The pulsed bias can form a pulsed negative bias on the upper surface of the substrate to accelerate positive ions in the plasma, causing them to collide with the substrate and enhance the etching process.

[0004] However, in the aforementioned semiconductor process equipment, the equivalent parasitic capacitance between the electrostatic chuck and the chamber structure is relatively large, resulting in high losses (heat losses) of the switching devices in the switching mode power supply. This leads to low pulse bias loading efficiency and a large load on the switching mode power supply, thus shortening its service life. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes a lower electrode mechanism and semiconductor process equipment, which can reduce the equivalent parasitic capacitance between the electrode sheet and the cavity structure, thereby reducing the heat loss of the pulse generation module, improving the pulse bias loading efficiency, and reducing the load burden of the pulse generation module, thereby extending the service life of the pulse generation module.

[0006] To achieve the purpose of this invention, a lower electrode mechanism is provided, which is applied to semiconductor process equipment, including a chuck, a partitioning board and multiple pulse generation modules, wherein the chuck includes a dielectric layer for carrying a wafer, and multiple electrode sheets spaced apart from each other and insulated are disposed in the dielectric layer;

[0007] The partition allocation board is disposed below the dielectric layer, and the pulse generation module is disposed below the partition allocation board for generating pulse voltage signals;

[0008] The partition distribution board is provided with a distribution circuit, which has multiple first connection terminals, multiple second connection terminals, and a third connection terminal. The multiple first connection terminals are electrically connected to multiple electrode plates in a one-to-one correspondence; the multiple second connection terminals are electrically connected to the output terminals of multiple pulse generation modules in a one-to-one correspondence; and the third connection terminal is used to electrically connect to the electrostatic adsorption power supply.

[0009] The distribution circuit is configured to transmit the DC adsorption voltage signal provided by the electrostatic adsorption power supply to each of the electrode plates, transmit the pulse voltage signal output by each pulse generation module to at least one of the electrode plates, and isolate the DC adsorption voltage signal from the pulse voltage signal.

[0010] Optionally, the distribution circuit includes multiple isolation resistors and multiple coupling capacitors, wherein each of the first connection terminals and the third connection terminal is connected to an isolation resistor for isolating the DC adsorption voltage signal from the pulse voltage signal;

[0011] Each of the second connection terminals is connected to at least one of the first connection terminals by a coupling capacitor, for coupling and conducting the pulse voltage signal output by each of the pulse generation modules to at least one of the electrode plates.

[0012] Optionally, the plurality of electrode sheets are divided into multiple electrode sheet groups according to multiple different partitions on the bearing surface of the dielectric layer;

[0013] The number of the second connection terminals is the same as the number of the electrode groups, and they correspond one-to-one; each of the second connection terminals and each of the first connection terminals in the corresponding electrode group is connected to a coupling capacitor.

[0014] Optionally, the plurality of electrode sheets are evenly distributed on two circles with different radii;

[0015] Each electrode sheet located on the smaller radius of the circumference and at least one adjacent electrode sheet located on the larger radius of the circumference together form an electrode sheet group.

[0016] Optionally, the orthographic projections of the plurality of electrode sheets located on the circumference with a smaller radius on the bearing surface of the dielectric layer are all sectors with the same area, and the plurality of sector-shaped electrode sheets form a circle;

[0017] The orthographic projections of the multiple electrode sheets located on the circumference with a larger radius on the bearing surface of the dielectric layer are all fan-shaped rings with the same area, and the multiple fan-shaped electrode sheets form a circular ring.

[0018] Optionally, the projected areas of each of the electrode groups on the bearing surface of the dielectric layer are the same; and / or, the projected areas of each of the electrode sheets on the bearing surface of the dielectric layer are the same.

[0019] Optionally, the partition allocation board is further provided with a plurality of first connection plugs, which are electrically connected to a plurality of first connection terminals in a one-to-one correspondence; the dielectric layer is provided with a plurality of plugs, which are plugged into a plurality of first connection plugs in a one-to-one correspondence.

[0020] Optionally, the partition allocation board is further provided with multiple connection sockets, each of which is electrically connected to a multiple second connection terminals in a one-to-one correspondence; each pulse generation module is provided with multiple second connection plugs, each of which is plugged into a multiple connection socket in a one-to-one correspondence.

[0021] Optionally, the partition distribution board is also provided with a DC voltage feed interface, which is electrically connected to the third connection terminal and is used to electrically connect to the wiring terminal of the electrostatic adsorption power supply.

[0022] Optionally, the chuck further includes an interface disk and a support plate, wherein the interface disk is located below the medium layer and is annular, and an annular boss is provided on the inner peripheral wall of the interface disk;

[0023] The support plate is disposed on the annular protrusion, the partition distribution plate is disposed on the support plate, and the inner peripheral wall of the interface disk, the upper surface of the support plate and the lower surface of the medium layer form a first cavity for accommodating the partition distribution plate.

[0024] Optionally, the lower electrode mechanism further includes a lower electrode cavity, which is disposed below the interface disk and connected to the interface disk. The interior of the lower electrode cavity and the interior of the interface disk are connected to form a second cavity; a plurality of pulse generation modules are disposed in the second cavity.

[0025] Optionally, the pulse generation module includes a first circuit board and a conversion unit integrated on the first circuit board, wherein the first circuit board is vertically arranged;

[0026] The conversion unit is used to convert the DC voltage signal provided by the DC power supply module into a pulse voltage signal.

[0027] Optionally, there are two first circuit boards, which are arranged opposite to each other and the two first circuit boards face opposite directions; each of the two first circuit boards is provided with the conversion unit, and the two conversion units are connected in parallel.

[0028] Optionally, the pulse generation module further includes a second circuit board and a damping unit integrated on the second circuit board, wherein the second circuit board is vertically disposed above the two first circuit boards; the input terminal of the damping unit is electrically connected to the output terminals of the two conversion units, and the output terminal of the damping unit is electrically connected to the second connection terminal, and the damping unit is used to suppress the waveform oscillation of the pulse voltage signal.

[0029] Optionally, the pulse generation module further includes a cooling element and two cooling pipes, wherein the two first circuit boards and the second circuit board are fixedly connected to the cooling element, and a portion of the cooling element is located between two opposing surfaces of the two first circuit boards, at least partially in contact with them; the other portion of the cooling element is at least partially in contact with the surface of the second circuit board.

[0030] The cooling component is provided with a cooling channel, the inlet and outlet of which are respectively connected to two cooling pipes to introduce a cooling medium into the cooling channel to cool the two first circuit boards and the second circuit board.

[0031] As another technical solution, the present invention also provides a lower electrode mechanism applied to semiconductor process equipment, including a chuck and multiple pulse generation modules, wherein...

[0032] The pulse generation module is located below the chuck and is used to generate pulse voltage signals;

[0033] The chuck includes a dielectric layer for carrying the wafer, and a plurality of spaced and insulated electrode plates are disposed in the dielectric layer; the pulse generation module is coupled to each of the electrode plates to conduct the pulse voltage signal to at least one of the electrode plates;

[0034] The multiple electrode sheets are divided into multiple electrode sheet groups according to multiple different partitions on the bearing surface of the dielectric layer. The number of electrode sheet groups is the same as the number of pulse generation modules, and they correspond one-to-one.

[0035] Optionally, the projected areas of each of the electrode groups on the bearing surface of the dielectric layer are the same; and / or, the projected areas of each of the electrode sheets on the bearing surface of the dielectric layer are the same.

[0036] Optionally, the plurality of electrode sheets are evenly distributed on two circles with different radii;

[0037] Each electrode sheet located on the smaller radius of the circumference and at least one adjacent electrode sheet located on the larger radius of the circumference together form an electrode sheet group.

[0038] Optionally, the orthographic projections of the plurality of electrode sheets located on the circumference with a smaller radius on the bearing surface of the dielectric layer are all sectors with the same area, and the plurality of sector-shaped electrode sheets form a circle;

[0039] The orthographic projections of the multiple electrode sheets located on the circumference with a larger radius on the bearing surface of the dielectric layer are all fan-shaped rings with the same area, and the multiple fan-shaped electrode sheets form a circular ring.

[0040] As another technical solution, the present invention also provides a lower electrode mechanism applied to semiconductor process equipment, including a chuck and multiple pulse generation modules, wherein...

[0041] The chuck includes a dielectric layer for carrying the wafer, wherein a plurality of electrode plates are disposed therein, spaced apart from and insulated from each other;

[0042] The pulse generation module is located below the chuck and includes two opposing first circuit boards, both vertically arranged, each equipped with a conversion unit connected in parallel. The conversion unit converts the DC voltage signal provided by the DC power supply module into a pulse voltage signal and transmits the pulse voltage signal to at least one of the electrode plates.

[0043] Optionally, the two first circuit boards have their surfaces facing opposite directions.

[0044] Optionally, the conversion unit includes two switching transistors, which are disposed on the surface of the first circuit board facing the other first circuit board.

[0045] Optionally, the two conversion units output pulse bias signals with different phases to achieve frequency multiplication.

[0046] As another technical solution, the present invention also provides a semiconductor process apparatus, including a process chamber and a lower electrode mechanism disposed in the process chamber, wherein the lower electrode mechanism adopts any of the lower electrode mechanisms provided by the present invention.

[0047] Optionally, the process chamber is provided with an inner liner and a grounding ring, wherein the inner liner is arranged around the dielectric layer;

[0048] The grounding ring is located below the liner and surrounds the interface disk. One end of the grounding ring is electrically connected to the liner, and the other end of the grounding ring is electrically connected to the grounding terminals of the plurality of pulse generation modules.

[0049] Optionally, the lower electrode mechanism is the lower electrode mechanism as described in claim 11;

[0050] The grounding ring is electrically connected to the lower electrode cavity; the lower electrode cavity is electrically connected to the grounding terminals of multiple pulse generation modules through four grounding leads.

[0051] Optionally, the lower electrode cavity includes a main cavity and multiple cantilever arms. The multiple cantilever arms surround the main cavity, one end of each cantilever arm is connected to the main cavity, and the other end of each cantilever arm is connected to the side wall of the process chamber. The cantilever arms are provided with lead-out channels for leading out the wires of the pulse generation module for electrical connection with the DC power supply module, and the wires of the partition distribution plate for electrical connection with the electrostatic adsorption power supply, to the outside of the process chamber.

[0052] The present invention has the following beneficial effects:

[0053] This invention provides a lower electrode mechanism, which comprises multiple spaced and insulated electrode plates arranged in the dielectric layer of a chuck, and multiple pulse generation modules. Each pulse generation module generates a pulse voltage signal and loads the pulse voltage signal onto at least one electrode plate through a partitioning distribution plate. Since the area of ​​at least one electrode plate corresponding to each pulse generation module is necessarily smaller than the total area of ​​all electrode plates, that is, compared to the prior art where one pulse generation module corresponds to one electrode with the same total area, in this application, one pulse generation module corresponds to a portion of the electrode plates with a smaller total area. Under the premise that other parameters remain unchanged, if the area of ​​the electrode plates is reduced, the capacitance is reduced, thereby reducing the heat loss of each pulse generation module due to capacitance, and thus improving the loading efficiency of the pulse voltage. At the same time, under the premise of ensuring that the voltage rise rate on all electrode plates is the same, the current provided by each pulse generation module to at least one electrode plate is smaller than the current provided to all electrode plates (or to one electrode with the same total area), thereby reducing the load burden on the pulse generation module and extending its service life.

[0054] This invention also provides a lower electrode mechanism, which, by placing multiple pulse generation modules below the chuck, minimizes the distance between the pulse generation modules and the dielectric layer, and shortens the voltage feed path length between the output terminal of the pulse generation module and the electrode plate, thereby reducing stray inductance in the pulse feed circuit. Furthermore, by dividing the multiple electrode plates into multiple electrode plate groups according to different partitions on the bearing surface of the dielectric layer, and making each electrode plate group correspond one-to-one with a pulse generation module, the pulse voltage signal output by each pulse generation module is transmitted to a corresponding electrode plate group. Since the area of ​​at least one electrode plate in the electrode plate group corresponding to each pulse generation module is small (necessarily smaller than the total area of ​​all electrode plates), the equivalent parasitic capacitance can be effectively reduced, thereby reducing heat loss caused by capacitance in each pulse generation module, thus improving the pulse voltage loading efficiency and extending the service life of the pulse generation module.

[0055] This invention also provides a lower electrode mechanism, which, by placing multiple pulse generation modules below the chuck, minimizes the distance between the pulse generation modules and the dielectric layer, and shortens the voltage feed path length between the output terminal of the pulse generation modules and the electrode plates, thereby reducing stray inductance in the pulse feed circuit. Furthermore, the pulse voltage signal output by the conversion unit of each pulse generation module is conducted to at least one electrode plate. Since the area of ​​the electrode plate corresponding to each pulse generation module is small (necessarily smaller than the total area of ​​all electrode plates), the equivalent parasitic capacitance can be effectively reduced, thereby reducing heat loss caused by capacitance in each pulse generation module, thus improving the pulse voltage loading efficiency and extending the service life of the pulse generation modules. Additionally, by using two conversion units in parallel, the output current can be increased, thereby improving the load-carrying capacity of the pulse generation modules.

[0056] The semiconductor process equipment provided by the present invention, by adopting the lower electrode mechanism provided by the present invention, can reduce the equivalent parasitic capacitance between the electrode sheet and the cavity structure, thereby reducing the heat loss of the pulse generation module, improving the pulse bias loading efficiency, and reducing the load burden of the pulse generation module, thereby extending the service life of the pulse generation module. Attached Figure Description

[0057] Figure 1 A schematic diagram of the lower electrode mechanism provided in an embodiment of the present invention;

[0058] Figure 2 This is a distribution diagram of the multiple electrode sheets used in an embodiment of the present invention;

[0059] Figure 3 This is a schematic diagram of the allocation circuit on the partition allocation board used in an embodiment of the present invention;

[0060] Figure 4 This is a structural diagram of the partition allocation board used in an embodiment of the present invention;

[0061] Figure 5A A cross-sectional perspective view of the lower electrode mechanism provided in an embodiment of the present invention;

[0062] Figure 5B This is a bottom view of the pulse generation module installed on the interface disk in an embodiment of the present invention;

[0063] Figure 5C This is a top view of the lower electrode cavity used in an embodiment of the present invention;

[0064] Figure 6A This is a structural diagram of the pulse generation module used in an embodiment of the present invention;

[0065] Figure 6B This is an exploded view of the pulse generation module used in an embodiment of the present invention;

[0066] Figure 6C This is a structural diagram of the cooling component used in an embodiment of the present invention;

[0067] Figure 7 Another schematic diagram of the lower electrode mechanism provided in an embodiment of the present invention;

[0068] Figure 8 This is a structural diagram of a semiconductor process equipment provided in an embodiment of the present invention. Detailed Implementation

[0069] To enable those skilled in the art to better understand the technical solution of the present invention, the lower electrode mechanism and semiconductor process equipment provided by the present invention will be described in detail below with reference to the accompanying drawings.

[0070] Please see Figure 1 This invention provides a lower electrode mechanism applied to semiconductor process equipment, comprising a chuck, a partitioning plate 2, and multiple pulse generation modules 3. The chuck includes a dielectric layer 11 for supporting a wafer S, the dielectric layer 11 being made of an insulating material, such as a ceramic layer. Multiple electrode pieces 12, spaced apart and insulated from each other, are disposed within the dielectric layer 11. Each electrode piece 12 serves as both an electrostatic adsorption electrode and a pulse bias electrode. Optionally, the multiple electrode pieces 12 can be embedded within the dielectric layer 11, and the electrode pieces 12 are insulated from each other through the dielectric layer 11. However, this invention is not limited to this; in practical applications, the multiple electrode pieces 12 can also be disposed at the bottom of the dielectric layer 11.

[0071] In some optional embodiments, the orthographic projections of multiple electrode sheets 12 onto the bearing surface of the dielectric layer 11 are combined to form a predetermined pattern adapted to the shape of the wafer S. For example, as... Figure 2As shown, if the wafer S has a circular shape, then the preset pattern is circular. Optionally, the outline size of the circle is appropriately larger than the outline size of the wafer. By combining the orthographic projections of multiple electrode sheets 12 onto the bearing surface of the dielectric layer 11 into a preset pattern that conforms to the shape of the wafer S, the ion energy across the entire wafer surface can be controlled to improve the uniformity of ion energy. In practical applications, the number, shape, and layout of the multiple electrode sheets 12 can be set according to different requirements.

[0072] In some optional embodiments, the array formed by the orthographic projections of the plurality of electrode sheets 12 onto the bearing surface of the dielectric layer 11 includes a parallel array, a sector array, a rectangular array, or a ring array, etc. Optionally, the orthographic projection shape of the plurality of electrode sheets 12 constituting the above array onto the bearing surface includes one or more combinations of squares, rectangles, rings, sectors, and irregular quadrilaterals.

[0073] To achieve electrostatic adsorption and pulsed bias for each electrode sheet 12, this embodiment of the invention utilizes a partitioned distribution plate 2 positioned below the dielectric layer 11 to feed in both DC adsorption voltage and pulsed voltage signals. This plate also isolates the DC adsorption voltage and pulsed voltage signals, effectively blocking DC and allowing AC signals. A pulse generation module 3 is positioned below the partitioned distribution plate 2 and is used to generate pulsed voltage signals. Optionally, the pulse generation module 3 is electrically connected to a DC power supply module 5, which provides a high-voltage DC signal (greater than 100V). This DC power supply module 5 can be located outside the process chamber and includes a DC power source. The pulse generation module 3 generates pulsed voltage signals from the DC voltage signal provided by the DC power supply module 5. In practical applications, the lower electrode mechanism may optionally include a control module (not shown in the figure), which sends control signals to the pulse generation module 3 to adjust parameters such as the pulse frequency, pulse width, and voltage of the pulsed voltage signal, thereby obtaining the desired ion energy distribution. The control module can also be located outside the process chamber.

[0074] Specifically, please refer to the following: Figure 1 and Figure 3The aforementioned partitioning board 2 is equipped with a distribution circuit, which has multiple first connection terminals 21, multiple second connection terminals 22, and a third connection terminal 23. The multiple first connection terminals 21 are electrically connected to multiple electrode plates 12 in a one-to-one correspondence; the multiple second connection terminals 22 are electrically connected to the output terminals of multiple pulse generation modules 3 in a one-to-one correspondence; and the third connection terminal 23 is used to electrically connect to the electrostatic adsorption power supply 6. The distribution circuit is configured to transmit the DC adsorption voltage signal provided by the electrostatic adsorption power supply 6 to each electrode plate 12, transmit the pulse voltage signal output by each pulse generation module 3 to at least one electrode plate 12, and isolate the DC adsorption voltage signal from the pulse voltage signal. Optionally, the aforementioned partitioning board 2 is a circuit board with the aforementioned distribution circuit.

[0075] By providing multiple spaced and insulated electrode sheets 12 in the dielectric layer 11, since the area of ​​at least one electrode sheet 12 corresponding to each pulse generation module 3 is necessarily smaller than the total area of ​​all electrode sheets 12, that is, compared to the prior art where one pulse generation module corresponds to one electrode with the same total area, in this application, one pulse generation module 3 corresponds to a portion of the electrode sheets 12 with a smaller total area. According to the calculation formula of the equivalent parasitic capacitance between the electrode sheet 12 and the chamber structure:

[0076]

[0077] It can be seen that, assuming the dielectric constant ε remains constant and the distance d remains constant (the position of dielectric layer 11 will not change), if the area S of the electrode sheet decreases, the equivalent parasitic capacitance C will decrease. Furthermore, since the capacitor itself does not consume energy, and the energy used to charge this capacitor will ultimately be dissipated as heat to the switching devices in the pulse generation module, according to the capacitor energy storage calculation formula:

[0078]

[0079] Assuming the voltage V used to fully charge the capacitor remains constant, a decrease in the equivalent parasitic capacitance C reduces the heat loss W caused by the capacitor in each pulse generation module 3. Therefore, by employing multiple pulse generation modules 3, and utilizing each pulse generation module 3 to independently provide a pulse voltage signal to at least one electrode plate 12, the area of ​​the at least one electrode plate 12 corresponding to each pulse generation module 3 is relatively small, effectively reducing the equivalent parasitic capacitance. This reduces heat loss caused by the capacitor in each pulse generation module 3, thereby improving the pulse voltage loading efficiency and extending the service life of the pulse generation module 3.

[0080] Meanwhile, the following formula for calculating the current through a capacitor is used:

[0081]

[0082] It can be seen that, while ensuring the voltage rise rate on all electrode plates 12 (i.e., Under the same conditions, compared to providing current to all electrode sheets (or to an electrode with the same total area in the prior art), the embodiments of the present invention utilize each pulse generation module 3 to independently provide a pulse voltage signal to at least one electrode sheet 12, which can reduce the equivalent parasitic capacitance C, thereby reducing the current I provided by each pulse generation module 3 to at least one electrode sheet 12, and further reducing the load burden of each pulse generation module 3 and extending the service life of the pulse generation module 3.

[0083] by Figure 2 Taking the 12 electrode pads shown as an example, multiple electrode pads 12 are evenly distributed on two circles with different radii (i.e., inner and outer circles). There are four electrode pads 12 located on the smaller circle (i.e., the inner circle) and eight electrode pads located on the larger circle (i.e., the outer circle). Each electrode pad 12 located on the smaller circle and its two adjacent electrode pads 12 located on the larger circle form an electrode pad group, forming a total of four electrode pad groups (12a, 12b, 12c, 12d). Each electrode pad group contains three electrode pads 12. The number of second connection terminals 22 on the partitioning board 2 is the same as the number of electrode pad groups and corresponds one-to-one. Correspondingly, there are four pulse generation modules 3. The four pulse generation modules 3 provide pulse voltage signals to the four electrode pad groups (12a, 12b, 12c, 12d) through the four second connection terminals 22. The pulse voltage signal output by each pulse generation module 3 is conducted to the three electrode pads 12 in the corresponding electrode pad group.

[0084] In this configuration, the sum of the areas of the three electrode plates 12 in each electrode plate group is approximately one-quarter of the total area of ​​the twelve electrode plates 12. Based on the aforementioned formula for calculating equivalent parasitic capacitance, the equivalent parasitic capacitance corresponding to each electrode plate group is also approximately one-quarter of the equivalent parasitic capacitance corresponding to the twelve electrode plates. Furthermore, the current supplied by each pulse generation module 3 to the three electrode plates 12 in its corresponding electrode plate group is also approximately one-quarter of the current corresponding to the twelve electrode plates 12. Therefore, this reduces heat loss due to capacitance in each pulse generation module 3 and decreases the load on each pulse generation module 3, thereby extending the service life of the pulse generation module 3.

[0085] In a specific embodiment, such as Figure 2As shown, the orthographic projections of multiple electrode sheets 12 located on the inner circle with a smaller radius onto the bearing surface of the dielectric layer 11 are all sector shapes with the same area, and the multiple sector-shaped electrode sheets 12 form a circle; the orthographic projections of multiple electrode sheets 12 located on the outer circle with a larger radius onto the bearing surface of the dielectric layer 11 are all annular fan shapes with the same area, and the multiple annular fan-shaped electrode sheets 12 form a ring. Thus, the orthographic projections of multiple electrode sheets 12 onto the bearing surface of the dielectric layer 11 combine to form a preset pattern that conforms to the shape of the wafer S, thereby enabling control of the ion energy on the entire wafer surface to improve the uniformity of ion energy.

[0086] In some optional embodiments, the projected areas of each electrode group on the bearing surface of the dielectric layer 11 are the same; and / or, the projected areas of each electrode 12 on the bearing surface of the dielectric layer 11 are the same. This allows the pulse generation module 3 to provide approximately the same current to the corresponding electrode group or electrode 12, thereby further improving the uniformity of ion energy.

[0087] In some optional embodiments, the distribution circuit performs DC blocking and AC passing functions and couples the pulse voltage signal to the electrode plate 12. The structure of the distribution circuit can vary, for example, as shown below. Figure 3 As shown, the above distribution circuit includes multiple isolation resistors 24 and multiple coupling capacitors 25. An isolation resistor 24 is connected between each first connection terminal 21 and the third connection terminal 23 to isolate the DC adsorption voltage signal from the pulse voltage signal, thus achieving DC blocking and AC passing. A coupling capacitor 25 is connected between each second connection terminal 22 and at least one first connection terminal 21 to couple and conduct the pulse voltage signal output by each pulse generation module 3 to at least one electrode plate 12. It should be noted that... Figure 3 The diagram only illustrates the connection relationships between the various connection terminals and components (including isolation resistor 24 and coupling capacitor 25) on the distribution circuit and does not represent the actual wiring of the various connection terminals and components on the partition distribution board 2. In practical applications, the wiring design of the distribution circuit needs to avoid the through holes, depending on the specific constraints of the corresponding mechanical structure in the lower electrode mechanism. For example, the partition distribution board 2 needs to be provided with multiple through holes for multiple pins to pass through.

[0088] In some optional embodiments, the plurality of electrode sheets 12 are divided into multiple electrode sheet groups according to multiple different partitions on the bearing surface of the dielectric layer 11, for example... Figure 2 The four electrode groups shown are (12a, 12b, 12c, 12d); the number of second connection terminals 22 is the same as the number of electrode groups, and they correspond one-to-one, for example... Figure 3The four second connection terminals 22 are shown; each second connection terminal 22 is connected to a coupling capacitor 24 between itself and each first connection terminal 21 in the corresponding electrode group. Figure 3 Taking the 12 electrode plates shown as an example, the distribution circuit is equipped with 12 isolation resistors 24 and 12 coupling capacitors 25. One end of each isolation resistor 24 is electrically connected to each of the first connection terminals 21, and the other end of each isolation resistor 24 is electrically connected to the third connection terminal 23. One end of each coupling capacitor 25 is electrically connected to each of the first connection terminals 21, and the other end of each coupling capacitor 25 is electrically connected to the second connection terminal 22 corresponding to the electrode plate group. Thus, the partition distribution board 2 can divide the pulse bias signals provided by the four pulse generation modules 3 into 12 pulse bias signals, which are coupled and conducted to the 12 electrode plates in a one-to-one correspondence.

[0089] By dividing the electrode sheets into multiple different partitions on the bearing surface, the ion energy across the entire wafer surface can be controlled to improve the uniformity of ion energy. In practical applications, the electrode sheets can be divided in any way according to different requirements, and the embodiments of the present invention do not have any particular limitations in this regard. For example, multiple electrode sheets 12 are uniformly distributed on two circumferences with different radii; each electrode sheet 12 located on the smaller radius circumference and at least one adjacent electrode sheet 12 located on the larger radius circumference form an electrode sheet group, for example, as shown below. Figure 2 As shown, each of the four electrode plates 12 located in the inner ring forms an electrode plate group with the two adjacent electrode plates 12 located in the outer ring. This reduces the equivalent parasitic capacitance of each electrode plate group to one-quarter of the equivalent parasitic capacitance of the twelve electrode plates.

[0090] In some alternative embodiments, such as Figure 4 As shown, the partition distribution plate 2 is also provided with a plurality of first connecting plugs 261, which are electrically connected to a plurality of first connecting ends 21 in a one-to-one correspondence; the dielectric layer 11 is provided with a plurality of plugs (not shown in the figure), which are plugged into a plurality of first connecting plugs 261 in a one-to-one correspondence. Thus, a one-to-one electrical connection can be achieved between a plurality of first connecting ends 21 and a plurality of electrode plates 12. Optionally, the aforementioned plugs are connecting posts disposed at the bottom of the dielectric layer 11, one end of which is electrically connected to an electrode plate, and the other end extends from the bottom of the dielectric layer 11 and plugs into the corresponding first connecting plug 261.

[0091] In some alternative embodiments, such as Figure 4 As shown, the partition distribution board 2 is also equipped with multiple connection sockets 262, which are electrically connected to multiple second connection terminals 22 in a one-to-one correspondence; for example Figure 6AAs shown, each pulse generation module 3 is equipped with multiple second connection plugs 37, which are plugged into multiple connection sockets 262 in a one-to-one correspondence. This allows multiple second connection terminals 22 to be electrically connected to the output terminals of multiple pulse generation modules 3 in a one-to-one correspondence. Of course, in practical applications, the second connection plugs can also be provided on the partition distribution board 2, while the connection sockets are provided on the pulse generation modules 3; this also achieves electrical connection between the second connection terminals 22 and the output terminals of the pulse generation modules 3.

[0092] In some alternative embodiments, such as Figure 4 As shown, the partition distribution board 2 is also provided with a DC voltage feed interface 263, which is electrically connected to the third connection terminal 23, and the DC voltage feed interface 263 is used to electrically connect to the wiring terminal of the electrostatic adsorption power supply 6.

[0093] In some alternative embodiments, such as Figures 5A to 5C As shown, the chuck also includes an interface disk 9 and a support plate 7. The interface disk 9 is located below the dielectric layer 11 and is annular in shape. An annular boss 91 is provided on the inner peripheral wall of the interface disk 9. The support plate 7 is disposed on the annular boss 91, which can support and limit the support plate 7. The partition distribution plate 2 is disposed on the support plate 7. The inner peripheral wall of the interface disk 9, the upper surface of the support plate 7, and the lower surface of the dielectric layer 11 form a first cavity for accommodating the partition distribution plate 2. This first cavity can reserve space for the partition distribution plate 2 and its first connecting plug 261 to the plug-in at the bottom of the dielectric layer 11. It should be noted that in practical applications, the function of the partition distribution plate 2 can be expanded. For example, pulse voltage and current acquisition circuits can be set on the partition distribution plate 2. In addition, the chuck may also include a cooling disk (not shown in the figure), which is disposed at the bottom of the dielectric layer 11 and is used to control the temperature of the dielectric layer 11. The cooling plate can be equipped with cooling water channels, and the temperature of the medium layer 11 can be controlled by circulating cooling water into the cooling water channels.

[0094] In some alternative embodiments, such as Figure 5A and Figure 5C As shown, the lower electrode mechanism also includes a lower electrode cavity 10, which is disposed below and connected to the interface disk 9. The interior of the lower electrode cavity 10 and the interior of the interface disk 9 are connected to form a second cavity 10c. Multiple pulse generation modules 3 are disposed in the second cavity 10c, for example, fixed to the bottom of the annular protrusion 91 of the interface disk 9. The second cavity 10c is an atmospheric environment, while the process area above the dielectric layer 11 is a vacuum environment, i.e., the plasma generation area during the process.

[0095] By distributing multiple pulse generation modules 3 within the second cavity 10c, the distance between the pulse generation modules 3 and the dielectric layer 11 can be minimized, as can the voltage feed path length between the output terminal of the pulse generation modules 3 and the electrode plate 12, thereby reducing stray inductance in the pulse feed circuit. The method of distributing the multiple pulse generation modules 3 is as follows: Figure 5B As shown, however, the embodiments of the present invention are not limited thereto. In practical applications, multiple pulse generation modules 3 can be distributed according to the mechanical structure in the second cavity 10c.

[0096] In some alternative embodiments, such as Figure 6A , Figure 6B and Figure 7 As shown, the pulse generation module 3 includes a first circuit board 31 and a conversion unit 311 integrated on the first circuit board 31. The first circuit board 31 is vertically arranged. The conversion unit 311 is used to convert the DC voltage signal provided by the DC power supply module 5 into a pulse voltage signal. By vertically arranging the first circuit board 31, the relative area between the pulse generation module 3 and the chuck (i.e., the cooling plate) can be reduced, thereby reducing the equivalent capacitance formed by the two, and further reducing the capacitive coupling between the chuck and the pulse generation module 3. This reduces the interference of strong pulse signals on the electrode plate 12 on weak signals such as drive signals or sampling signals on the pulse generation module 3.

[0097] In some alternative embodiments, such as Figure 6A , Figure 6B and Figure 7 As shown, there are two first circuit boards 31, arranged opposite each other, with their surfaces facing opposite directions. Each of the two first circuit boards 31 has a conversion unit 311, and the two conversion units 311 are connected in parallel. By using two parallel conversion units 311, the output current can be increased, thereby improving the load-carrying capacity of the pulse generation module 3. Simultaneously, frequency multiplication can be achieved by controlling the output of pulse bias signals of different phases from the two conversion units 311. By having the surfaces of the two first circuit boards 31 face opposite directions, it is easier to connect the outputs of the two conversion units 311 together in parallel. For example, electronic components (e.g., switching transistors) that need to be connected in parallel on the two conversion units 311 can be placed on the opposite surfaces of the two first circuit boards 31, thus avoiding the tangling of parallel wires. The aforementioned first circuit board 31 is, for example, a double-sided printed circuit board (i.e., different electronic components are integrated on the two surfaces of the circuit board). Of course, in practical applications, only one first circuit board 13 and one conversion unit 311 can be provided.

[0098] In some alternative embodiments, the aforementioned conversion unit 311 is, for example, a half-bridge structure composed of switching transistors such as MOSFETs, such as... Figure 7 As shown, the lower electrode mechanism also includes a low-voltage pulse signal generation module 4 and a control module (not shown in the figure). The low-voltage pulse signal generation module 4 is electrically connected to each conversion unit 311 in the plurality of pulse generation modules 3, and is used to provide a DC pulse voltage (low voltage, e.g., 24V) to the conversion unit 311. Under the control of the control module, it controls the operation of the conversion unit 311 (e.g., a switching transistor). Optionally, the low-voltage pulse signal generation module 4 can be disposed in the second cavity 10c inside the lower electrode cavity 10, or it can be disposed outside the process chamber.

[0099] The aforementioned conversion unit 311 includes, for example, two switching transistors. Upon receiving a control signal from the control module, these transistors can alternately switch on and off according to a specified period and pulse width, thereby achieving rapid charging and discharging of the load (i.e., the chuck and chamber plasma load), and thus loading a pulse voltage signal. The switching transistors can be high-speed switching devices, such as gallium nitride transistors (GaN transistors). Using two switching transistors to achieve rapid charging and discharging of the load to form a pulse voltage signal is a well-known technique in the art and will not be elaborated further here. Of course, in practical applications, other circuits or devices that can convert DC voltage signals into pulse voltage signals can also be used, and the present invention does not impose any particular limitations on this.

[0100] In some alternative embodiments, such as Figure 7 As shown, the pulse generation module 3 also includes an isolation drive unit 312, which can be integrated on the first circuit board 31. The input terminal of the isolation drive unit 312 is electrically connected to the output terminal of the control module (not shown in the figure), and the output terminal of the isolation drive unit 312 is electrically connected to the input terminal of the conversion unit 311. It is used to isolate and amplify the control signal output by the control module to the conversion unit 311 to prevent the noise generated by the switching transistor of the driving stage from affecting the control module of the preceding stage.

[0101] In some alternative embodiments, such as Figure 6A , Figure 6B and Figure 7As shown, the pulse generation module 3 also includes a second circuit board 32 and a damping unit 321 integrated on the second circuit board 32. The second circuit board 32 is vertically disposed above the two first circuit boards 31. The input terminal of the damping unit 321 is electrically connected to the output terminals of the two conversion units 311, and the output terminal of the damping unit 321 is electrically connected to the second connection terminal 22. The damping unit 321 is used to suppress waveform oscillation of the pulse voltage signal. The damping unit 321 is, for example, a resistor. Similar to the first circuit board 31, by vertically disposing the second circuit board 32 above the two first circuit boards 31, the relative area of ​​the pulse generation module 3 and the chuck (i.e., the cooling plate) can be reduced, thereby reducing the equivalent capacitance formed by the two components and further reducing the capacitive coupling between the chuck and the pulse generation module 3.

[0102] In some alternative embodiments, such as Figure 6A and Figure 6B As shown, the pulse generation module 3 also includes a cooling element 33 and two cooling pipes 34, wherein two first circuit boards 31 and a second circuit board 32 are fixedly connected to the cooling element 33, and a portion of the cooling element 33 (i.e., Figures 6A to 6C The first portion 33a) shown is located between the two opposing surfaces of the two first circuit boards 31, and is at least partially attached to them. Optionally, the switching transistors on the two first circuit boards 31 can be disposed on the side closer to the cooling element 33, which is the main heat-generating device, and preferably can be attached to the cooling element 33. The driving electronic components on the two first circuit boards 31 that do not require heat dissipation can be disposed on the side away from the cooling element 33. In addition, by making the surfaces of the two first circuit boards 31 face opposite directions, the surfaces of the two first circuit boards 31 with the switching transistors can be attached to the cooling element 33, so that the cooling element 33 located in the middle can simultaneously cool the switching transistors on the two first circuit boards 31.

[0103] Another part of the cooling component 33 (i.e., Figures 6A to 6C The second portion 33b) shown is at least partially attached to the surface of the second circuit board 32 to cool the resistive element in the damping unit 312. A cooling channel (not shown) is provided in the cooling member 33, the inlet and outlet of which are connected to two cooling pipes 34 to introduce a cooling medium (e.g., cooling water) to cool the two first circuit boards 31 and the second circuit board 32. By introducing a cooling medium into the cooling channel in the cooling member 33, heat-generating devices (e.g., the resistive element in the switching unit 311 and the damping unit 312) on the two first circuit boards 31 and the second circuit board 32 can be cooled, improving heat dissipation capacity.

[0104] In a specific embodiment, such as Figures 6A to 6CAs shown, the cooling component 33 is, for example, a heat-conducting component such as a copper block. Furthermore, the pulse generation module 3 also includes a module fixing component 35, a plug fixing component 36, and a pulse feed connection bar 38, wherein, as... Figure 6C As shown, four first threaded holes 331 are respectively provided on both sides of the first part 33a of the cooling component 33 for mounting two first circuit boards 31 by screws engaging with the first threaded holes 331; two second threaded holes 332 are provided on one side of the second part 33b of the cooling component 33 for mounting the second circuit board 32 by screws engaging with the second threaded holes 332; two third threaded holes 333 are provided on the top surface of the second part 33b of the cooling component 33 for mounting the plug fixing member 36 by screws engaging with the third threaded holes 333; the plug fixing member 36 is used to fix the second connecting plug 37. The module fixing member 35 is fixedly connected to the second part 33b of the cooling component 33 and fixedly connected to the interface plate 9 by screws. One end of the pulse feed connection bar 38 is electrically connected to the second connecting plug 37, and the other end is electrically connected to the output end of the damping unit 321 on the second circuit board 32.

[0105] In some optional embodiments, while ensuring cooling capacity, the cooling pipe 34 for outflow corresponding to the cooling element 33 of one pulse generation module 3 can be connected in series with the cooling pipe 34 for inflow corresponding to the cooling element 33 of another pulse generation module 3. By connecting them in series in this way, the cooling channels in the cooling elements 33 of multiple pulse generation modules 3 can be connected in series to form a continuous cooling channel. Moreover, this continuous channel has only one total inlet and one total outlet, which are used to connect to the outflow end and return end of the external cooling circulation system, respectively. This makes it easier to connect to the external cooling circulation system and simplifies the connection pipeline.

[0106] The lower electrode mechanism provided by this invention comprises multiple spaced and insulated electrode plates arranged in the dielectric layer of a chuck, and multiple pulse generation modules. Each pulse generation module generates a pulse voltage signal and loads the pulse voltage signal onto at least one electrode plate through a partitioning distribution plate. Since the area of ​​at least one electrode plate corresponding to each pulse generation module is necessarily smaller than the total area of ​​all electrode plates, that is, compared to the prior art where one pulse generation module corresponds to one electrode with the same total area, in this application, one pulse generation module corresponds to a portion of the electrode plates with a smaller total area. Under the premise that other parameters remain unchanged, if the area of ​​the electrode plates is reduced, the capacitance is reduced, thereby reducing the heat loss of each pulse generation module due to capacitance, and thus improving the loading efficiency of the pulse voltage. At the same time, under the premise of ensuring that the voltage rise rate on all electrode plates is the same, the current supplied by each pulse generation module to at least one electrode plate is smaller than the current supplied to all electrode plates (or to one electrode with the same total area), thereby reducing the load burden of the pulse generation module and extending its service life.

[0107] As another technical solution, please refer to Figure 1 This invention also provides a lower electrode mechanism for semiconductor process equipment, including a chuck and multiple pulse generation modules 3. The pulse generation modules 3 are disposed below the chuck and are used to generate pulse voltage signals. The chuck includes a dielectric layer 11 for supporting wafers. Multiple electrode plates 12 are disposed in the dielectric layer 11 and are spaced apart from each other and insulated from each other. Each electrode plate 12 serves as both an electrostatic adsorption electrode and a pulse bias electrode. Optionally, the multiple electrode plates 12 can be embedded in the dielectric layer 11, and the electrode plates 12 are insulated from each other through the dielectric layer 11. However, this invention is not limited to this. In practical applications, the multiple electrode plates 12 can also be disposed at the bottom of the dielectric layer 11.

[0108] The pulse generation module 3 is coupled to each electrode sheet 12 to transmit the pulse voltage signal to at least one electrode sheet 12. The multiple electrode sheets 12 are divided into multiple electrode sheet groups according to different partitions on the bearing surface of the dielectric layer 11. The number of these electrode sheet groups is the same as the number of pulse generation modules 3, and they correspond one-to-one. For example... Figure 2 The four electrode groups (12a, 12b, 12c, 12d) are shown; the number of second connection terminals 22 is the same as the number of electrode groups, and they correspond one-to-one.

[0109] By dividing the electrode sheets into multiple different partitions on the bearing surface, the ion energy across the entire wafer surface can be controlled to improve the uniformity of ion energy. In practical applications, the electrode sheets can be divided in any way according to different requirements, and the embodiments of the present invention do not have any particular limitations in this regard. For example, multiple electrode sheets 12 are uniformly distributed on two circumferences with different radii; each electrode sheet 12 located on the smaller radius circumference and at least one adjacent electrode sheet 12 located on the larger radius circumference form an electrode sheet group, for example, as shown below. Figure 2 As shown, each of the four electrode plates 12 located in the inner ring forms an electrode plate group with the two adjacent electrode plates 12 located in the outer ring. This reduces the equivalent parasitic capacitance of each electrode plate group to one-quarter of the equivalent parasitic capacitance of the twelve electrode plates.

[0110] In some optional embodiments, the projected areas of each electrode group on the bearing surface of the dielectric layer 11 are the same; and / or, the projected areas of each electrode 12 on the bearing surface of the dielectric layer 11 are the same. This allows the pulse generation module 3 to provide approximately the same current to the corresponding electrode group or electrode 12, thereby further improving the uniformity of ion energy.

[0111] In some optional embodiments, a plurality of electrode sheets 12 are uniformly distributed on two circumferences of different radii; each electrode sheet located on the smaller radius circumference and at least one adjacent electrode sheet located on the larger radius circumference form an electrode sheet group. Figure 2 Taking the 12 electrode pads shown as an example, multiple electrode pads 12 are evenly distributed on two circles with different radii (i.e., inner and outer circles). There are four electrode pads 12 located on the smaller circle (i.e., the inner circle) and eight electrode pads located on the larger circle (i.e., the outer circle). Each electrode pad 12 located on the smaller circle and its two adjacent electrode pads 12 located on the larger circle form an electrode pad group, forming a total of four electrode pad groups (12a, 12b, 12c, 12d). Each electrode pad group contains three electrode pads 12. The number of second connection terminals 22 on the partitioning board 2 is the same as the number of electrode pad groups and corresponds one-to-one. Correspondingly, there are four pulse generation modules 3. The four pulse generation modules 3 provide pulse voltage signals to the four electrode pad groups (12a, 12b, 12c, 12d) through the four second connection terminals 22. The pulse voltage signal output by each pulse generation module 3 is conducted to the three electrode pads 12 in the corresponding electrode pad group.

[0112] In this configuration, the sum of the areas of the three electrode plates 12 in each electrode plate group is approximately one-quarter of the total area of ​​the twelve electrode plates 12. Based on the aforementioned formula for calculating equivalent parasitic capacitance, the equivalent parasitic capacitance corresponding to each electrode plate group is also approximately one-quarter of the equivalent parasitic capacitance corresponding to the twelve electrode plates. Furthermore, the current supplied by each pulse generation module 3 to the three electrode plates 12 in its corresponding electrode plate group is also approximately one-quarter of the current corresponding to the twelve electrode plates 12. Therefore, this reduces heat loss due to capacitance in each pulse generation module 3 and decreases the load on each pulse generation module 3, thereby extending the service life of the pulse generation module 3.

[0113] In a specific embodiment, such as Figure 2 As shown, the orthographic projections of multiple electrode sheets 12 located on the inner circle with a smaller radius onto the bearing surface of the dielectric layer 11 are all sector shapes with the same area, and the multiple sector-shaped electrode sheets 12 form a circle; the orthographic projections of multiple electrode sheets 12 located on the outer circle with a larger radius onto the bearing surface of the dielectric layer 11 are all annular fan shapes with the same area, and the multiple annular fan-shaped electrode sheets 12 form a ring. Thus, the orthographic projections of multiple electrode sheets 12 onto the bearing surface of the dielectric layer 11 combine to form a preset pattern that conforms to the shape of the wafer S, thereby enabling control of the ion energy on the entire wafer surface to improve the uniformity of ion energy.

[0114] In summary, the lower electrode mechanism provided in this embodiment of the invention, by placing multiple pulse generation modules below the chuck, can minimize the distance between the pulse generation modules and the dielectric layer, and shorten the voltage feed path length between the output terminal of the pulse generation module and the electrode plate, thereby reducing stray inductance in the pulse feed circuit. Furthermore, by dividing the multiple electrode plates into multiple electrode plate groups according to different partitions on the bearing surface of the dielectric layer, and making each electrode plate group correspond one-to-one with a pulse generation module, the pulse voltage signal output by each pulse generation module is transmitted to a corresponding electrode plate group. Since the area of ​​at least one electrode plate in the electrode plate group corresponding to each pulse generation module is small (necessarily smaller than the total area of ​​all electrode plates), the equivalent parasitic capacitance can be effectively reduced, thereby reducing heat loss caused by capacitance in each pulse generation module, thus improving the pulse voltage loading efficiency and extending the service life of the pulse generation module.

[0115] As another technical solution, please refer to Figure 1This invention also provides a lower electrode mechanism applied to semiconductor process equipment, including a chuck and multiple pulse generation modules 3. The chuck includes a dielectric layer 11 for supporting wafers. Multiple electrode pieces 12, spaced apart and insulated from each other, are disposed within the dielectric layer 11. Each electrode piece 12 serves as both an electrostatic adsorption electrode and a pulse bias electrode. Optionally, the multiple electrode pieces 12 can be embedded within the dielectric layer 11, and the electrode pieces 12 can be insulated from each other through the dielectric layer 11. However, this invention is not limited to this; in practical applications, the multiple electrode pieces 12 can also be disposed at the bottom of the dielectric layer 11.

[0116] Pulse generation module 3 is located below the chuck, such as Figure 6A , Figure 6B and Figure 7 As shown, the pulse generation module 3 includes two first circuit boards 31 arranged opposite each other. Both first circuit boards 31 are vertically arranged, and each of the two first circuit boards 31 is provided with a conversion unit 311, and the two conversion units 311 are connected in parallel. The conversion unit 311 is used to convert the DC voltage signal provided by the DC power supply module 5 into a pulse voltage signal, and to conduct the pulse voltage signal to at least one electrode plate 12.

[0117] By vertically arranging the first circuit board 31, the relative area between the pulse generation module 3 and the chuck (i.e., the cooling plate) can be reduced, thereby reducing the equivalent capacitance formed by the two, which in turn reduces the capacitive coupling between the chuck and the pulse generation module 3, and reduces the interference of strong pulse signals on the electrode plate 12 on weak signals such as drive signals or sampling signals on the pulse generation module 3.

[0118] By using two parallel conversion units 311, the output current can be increased, thereby improving the load-carrying capacity of the pulse generation module 3.

[0119] In some alternative embodiments, the two conversion units 311 output pulse bias signals with different phases to achieve frequency multiplication.

[0120] In some alternative embodiments, the two first circuit boards 31 have opposite orientations. By having the two first circuit boards 31 have opposite orientations, it is easier to connect the outputs of the two conversion units 311 in parallel. For example, the electronic components (e.g., switching transistors) that need to be connected in parallel on the two conversion units 311 can be placed on the opposite sides of the two first circuit boards 31, thereby avoiding the tangling of parallel wires. The aforementioned first circuit board 31 is, for example, a double-sided printed circuit board (i.e., different electronic components are integrated on the two sides of the circuit board).

[0121] The aforementioned conversion unit 311 includes, for example, two switching transistors. Upon receiving a control signal from the control module, these transistors can alternately switch on and off according to a specified period and pulse width, thereby achieving rapid charging and discharging of the load (i.e., the chuck and chamber plasma load), and thus loading a pulse voltage signal. The switching transistors can be high-speed switching devices, such as gallium nitride transistors (GaN transistors). Using two switching transistors to achieve rapid charging and discharging of the load to form a pulse voltage signal is a well-known technique in the art and will not be elaborated further here. Of course, in practical applications, other circuits or devices that can convert DC voltage signals into pulse voltage signals can also be used, and the present invention does not impose any particular limitations on this.

[0122] In some alternative embodiments, the two switching transistors of the switching unit 311 are disposed on the surface of the first circuit board 31 facing the other first circuit board. That is, the electronic components (e.g., switching transistors) that need to be connected in parallel on the two switching units 311 can be disposed on the surfaces of the two first circuit boards 31 that are opposite to each other, thereby avoiding the tangling of parallel wires.

[0123] In some alternative embodiments, such as Figure 6A and Figure 6B As shown, the pulse generation module 3 also includes a cooling element 33 and two cooling pipes 34, wherein two first circuit boards 31 and a second circuit board 32 are fixedly connected to the cooling element 33, and a portion of the cooling element 33 (i.e., Figures 6A to 6C The first portion 33a) shown is located between the two opposing surfaces of the two first circuit boards 31, and is at least partially attached to them. Optionally, the switching transistors on the two first circuit boards 31 can be disposed on the side closer to the cooling element 33, which is the main heat-generating device, and preferably can be attached to the cooling element 33. The driving electronic components on the two first circuit boards 31 that do not require heat dissipation can be disposed on the side away from the cooling element 33. In addition, by making the surfaces of the two first circuit boards 31 face opposite directions, the surfaces of the two first circuit boards 31 with the switching transistors can be attached to the cooling element 33, so that the cooling element 33 located in the middle can simultaneously cool the switching transistors on the two first circuit boards 31.

[0124] As another technical solution, embodiments of the present invention also provide a semiconductor process apparatus, including a process chamber and a lower electrode mechanism disposed in the process chamber, wherein the lower electrode mechanism adopts the lower electrode mechanism described above in embodiments of the present invention.

[0125] Specifically, please refer to Figure 8The semiconductor process equipment 100 includes, for example, a process chamber 101, an upper electrode device, an inlet gas device 105, and a vacuum device 108. The inlet gas device 105 is used to introduce process gas into the process chamber 101, and the vacuum device 108 is used to expel the gas from the process chamber 101. The upper electrode device is disposed at the top of the process chamber 101 and is used to excite the process gas to form plasma. Specifically, a dielectric window 103 is disposed at the top of the process chamber 101. The upper electrode device includes, for example, a radio frequency coil 104 disposed above the dielectric window 103. The radio frequency coil 104 is electrically connected to the upper electrode power supply 106 through a matching converter 107.

[0126] In some alternative embodiments, combined with Figure 8 and Figure 5A As shown, the process chamber 101 is equipped with an inner liner 102 and a grounding ring 8. The inner liner 102 surrounds the dielectric layer 11. The grounding ring 8 is located below the inner liner 102 and surrounds the interface disk 9. One end of the grounding ring 8 is electrically connected to the inner liner 102, and the other end is electrically connected to the grounding terminals of multiple pulse generation modules 3. Thus, the loop constituting the pulse current path is as follows: pulse generation module 3, partition distribution plate 2, electrode plate 12, wafer S, plasma, inner liner 102, grounding ring 8, and pulse generation module 3, ultimately grounded through the grounding terminal of the pulse generation module 3. This loop has low impedance and a short path, thereby reducing loop inductance and pulse waveform oscillation on the electrode plate 12. There are various ways to electrically connect the other end of the grounding ring 8 to the grounding terminals of the multiple pulse generation modules 3, for example... Figure 5C As shown, the grounding ring 8 is electrically connected to the lower electrode cavity 10; the lower electrode cavity 10 is electrically connected to the grounding terminals of multiple pulse generation modules 3 through four grounding leads 39.

[0127] In some alternative embodiments, such as Figure 5A As shown, the lower electrode cavity 10 includes a main cavity 10a and multiple cantilever 10b. Figure 5A (Only two are shown) Multiple cantilever arms 10b surround the main cavity 10a. One end of each cantilever arm 10b is connected to the main cavity 10a, and the other end of each cantilever arm 10b is connected to the side wall of the process chamber 101. Outlet channels are provided in the cantilever arms 10b for leading out the wires of the pulse generation module 3 for electrical connection with the DC power supply module 5, and the wires of the partition distribution plate 2 for electrical connection with the electrostatic adsorption power supply 6 to the outside of the process chamber 101.

[0128] The semiconductor process equipment provided in this embodiment of the invention, by employing the lower electrode mechanism described above, can reduce the equivalent parasitic capacitance between the electrode sheet and the cavity structure, thereby reducing the heat loss of the pulse generation module, improving the pulse bias loading efficiency, and reducing the load burden on the pulse generation module, thus extending the service life of the pulse generation module.

[0129] It is understood that the above embodiments are merely exemplary implementations used to illustrate the principles of the present invention, and the present invention is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A lower electrode mechanism, applied in semiconductor process equipment, characterized in that, It includes a chuck, a partitioning board, and multiple pulse generation modules. The chuck includes a dielectric layer for carrying the wafer, and multiple electrode plates spaced apart from and insulated from each other are disposed in the dielectric layer. The partition allocation board is disposed below the dielectric layer, and the pulse generation module is disposed below the partition allocation board for generating pulse voltage signals; The partition distribution board is provided with a distribution circuit, which has multiple first connection terminals, multiple second connection terminals, and a third connection terminal. The multiple first connection terminals are electrically connected to multiple electrode plates in a one-to-one correspondence; the multiple second connection terminals are electrically connected to the output terminals of multiple pulse generation modules in a one-to-one correspondence; and the third connection terminal is used to electrically connect to the electrostatic adsorption power supply. The distribution circuit is configured to transmit the DC adsorption voltage signal provided by the electrostatic adsorption power supply to each of the electrode plates, transmit the pulse voltage signal output by each pulse generation module to at least one of the electrode plates, and isolate the DC adsorption voltage signal from the pulse voltage signal.

2. The lower electrode mechanism according to claim 1, characterized in that, The distribution circuit includes multiple isolation resistors and multiple coupling capacitors, wherein each of the first connection terminals and the third connection terminal is connected to an isolation resistor for isolating the DC adsorption voltage signal from the pulse voltage signal; Each of the second connection terminals is connected to at least one of the first connection terminals by a coupling capacitor, for coupling and conducting the pulse voltage signal output by each of the pulse generation modules to at least one of the electrode plates.

3. The lower electrode mechanism according to claim 2, characterized in that, The plurality of electrode sheets are divided into multiple electrode sheet groups according to multiple different partitions on the bearing surface of the dielectric layer; The number of the second connection terminals is the same as the number of the electrode groups, and they correspond one-to-one; each of the second connection terminals and each of the first connection terminals in the corresponding electrode group is connected to a coupling capacitor.

4. The lower electrode mechanism according to claim 3, characterized in that, The plurality of electrode sheets are evenly distributed on two circles with different radii; Each electrode sheet located on the smaller radius of the circumference and at least one adjacent electrode sheet located on the larger radius of the circumference together form an electrode sheet group.

5. The lower electrode mechanism according to claim 4, characterized in that, The orthographic projections of the multiple electrode sheets located on the circumference with a smaller radius on the bearing surface of the dielectric layer are all sectors with the same area, and the multiple sector-shaped electrode sheets form a circle; The orthographic projections of the multiple electrode sheets located on the circumference with a larger radius on the bearing surface of the dielectric layer are all fan-shaped rings with the same area, and the multiple fan-shaped electrode sheets form a circular ring.

6. The lower electrode mechanism according to claim 3, characterized in that, Each of the electrode pads has the same projected area on the bearing surface of the dielectric layer; and / or, each of the electrode pads has the same projected area on the bearing surface of the dielectric layer.

7. The lower electrode mechanism according to claim 1, characterized in that, The partition allocation board is also provided with a plurality of first connection plugs, which are electrically connected to a plurality of first connection terminals in a one-to-one correspondence; the dielectric layer is provided with a plurality of plugs, which are plugged into a plurality of first connection plugs in a one-to-one correspondence.

8. The lower electrode mechanism according to claim 1, characterized in that, The partition allocation board is also provided with multiple connection sockets, each of which is electrically connected to a multiple second connection terminals in a corresponding manner; each pulse generation module is provided with multiple second connection plugs, each of which is plugged into a multiple connection socket in a corresponding manner.

9. The lower electrode mechanism according to claim 1, characterized in that, The partition distribution board is also provided with a DC voltage feed interface, which is electrically connected to the third connection terminal and is used to electrically connect to the wiring terminal of the electrostatic adsorption power supply.

10. The lower electrode mechanism according to claim 1, characterized in that, The chuck also includes an interface disk and a support plate, wherein the interface disk is located below the medium layer and is annular, and an annular boss is provided on the inner peripheral wall of the interface disk; The support plate is disposed on the annular protrusion, the partition distribution plate is disposed on the support plate, and the inner peripheral wall of the interface disk, the upper surface of the support plate and the lower surface of the medium layer form a first cavity for accommodating the partition distribution plate.

11. The lower electrode mechanism according to claim 10, characterized in that, The lower electrode mechanism further includes a lower electrode cavity, which is disposed below the interface disk and connected to the interface disk. The interior of the lower electrode cavity and the interior of the interface disk are connected to form a second cavity. Multiple pulse generation modules are disposed in the second cavity.

12. The lower electrode mechanism according to any one of claims 1-11, characterized in that, The pulse generation module includes a first circuit board and a conversion unit integrated on the first circuit board, wherein the first circuit board is vertically arranged. The conversion unit is used to convert the DC voltage signal provided by the DC power supply module into a pulse voltage signal.

13. The lower electrode mechanism according to claim 12, characterized in that, There are two first circuit boards, which are arranged opposite each other and the two first circuit boards face opposite directions; each of the two first circuit boards is provided with the conversion unit, and the two conversion units are connected in parallel.

14. The lower electrode mechanism according to claim 13, characterized in that, The pulse generation module further includes a second circuit board and a damping unit integrated on the second circuit board, wherein the second circuit board is vertically disposed above the two first circuit boards; the input terminal of the damping unit is electrically connected to the output terminals of the two conversion units, and the output terminal of the damping unit is electrically connected to the second connection terminal; the damping unit is used to suppress the waveform oscillation of the pulse voltage signal.

15. The lower electrode mechanism according to claim 14, characterized in that, The pulse generation module further includes a cooling element and two cooling pipes, wherein the two first circuit boards and the second circuit board are fixedly connected to the cooling element, and a portion of the cooling element is located between two opposing surfaces of the two first circuit boards, at least partially in contact with them; the other portion of the cooling element is at least partially in contact with the surface of the second circuit board. The cooling component is provided with a cooling channel, the inlet and outlet of which are respectively connected to two cooling pipes to introduce a cooling medium into the cooling channel to cool the two first circuit boards and the second circuit board.

16. A lower electrode mechanism, applied in semiconductor process equipment, characterized in that, Includes a chuck and multiple pulse generation modules, among which, The pulse generation module is located below the chuck and is used to generate pulse voltage signals; The chuck includes a dielectric layer for carrying the wafer, and a plurality of spaced and insulated electrode plates are disposed in the dielectric layer. Each electrode plate serves as both an electrostatic adsorption electrode and a pulse bias electrode. The pulse generation module is coupled to each of the electrode plates to conduct the pulse voltage signal to at least one of the electrode plates. The multiple electrode sheets are divided into multiple electrode sheet groups according to multiple different partitions on the bearing surface of the dielectric layer. The number of electrode sheet groups is the same as the number of pulse generation modules, and they correspond one-to-one.

17. The lower electrode mechanism according to claim 16, characterized in that, Each of the electrode pads has the same projected area on the bearing surface of the dielectric layer; and / or, each of the electrode pads has the same projected area on the bearing surface of the dielectric layer.

18. The lower electrode mechanism according to claim 16, characterized in that, The plurality of electrode sheets are evenly distributed on two circles with different radii; Each electrode sheet located on the smaller radius of the circumference and at least one adjacent electrode sheet located on the larger radius of the circumference together form an electrode sheet group.

19. The lower electrode mechanism according to claim 18, characterized in that, The orthographic projections of the multiple electrode sheets located on the circumference with a smaller radius on the bearing surface of the dielectric layer are all sectors with the same area, and the multiple sector-shaped electrode sheets form a circle; The orthographic projections of the multiple electrode sheets located on the circumference with a larger radius on the bearing surface of the dielectric layer are all fan-shaped rings with the same area, and the multiple fan-shaped electrode sheets form a circular ring.

20. A lower electrode mechanism, applied in semiconductor process equipment, characterized in that, It includes a chuck, a partition allocation board, and multiple pulse generation modules, among which, The chuck includes a dielectric layer for carrying the wafer, wherein a plurality of electrode plates are disposed therein, spaced apart from and insulated from each other; The pulse generation module is located below the chuck and includes two opposing first circuit boards, both of which are vertically arranged and each has a conversion unit connected in parallel. The conversion unit is used to convert the DC voltage signal provided by the DC power supply module into a pulse voltage signal and transmit the pulse voltage signal to at least one of the electrode plates. The partitioning board is disposed between the chuck and the pulse generation module, and is configured to transmit the DC adsorption voltage signal provided by the electrostatic adsorption power supply to each of the electrode plates, transmit the pulse voltage signal output by each of the pulse generation modules to at least one of the electrode plates, and isolate the DC adsorption voltage signal from the pulse voltage signal.

21. The lower electrode mechanism according to claim 20, characterized in that, The two first circuit boards face opposite directions.

22. The lower electrode mechanism according to claim 21, characterized in that, The conversion unit includes two switching transistors, which are disposed on the surface of the first circuit board facing the other first circuit board.

23. The lower electrode mechanism according to claim 20, characterized in that, The two conversion units output pulse bias signals with different phases to achieve frequency multiplication.

24. A semiconductor process apparatus, comprising a process chamber and a lower electrode mechanism disposed within the process chamber, characterized in that, The lower electrode mechanism is the lower electrode mechanism described in any one of claims 1-23.

25. The semiconductor process equipment according to claim 24, characterized in that, The process chamber is provided with an inner liner and a grounding ring, wherein the inner liner is arranged around the dielectric layer; The chuck further includes an interface disk, wherein the interface disk is located below the dielectric layer and is in a ring shape; The grounding ring is located below the liner and surrounds the interface disk. One end of the grounding ring is electrically connected to the liner, and the other end of the grounding ring is electrically connected to the grounding terminals of the plurality of pulse generation modules.

26. The semiconductor process equipment according to claim 25, characterized in that, The lower electrode mechanism is the lower electrode mechanism as described in claim 11; The grounding ring is electrically connected to the lower electrode cavity; the lower electrode cavity is electrically connected to the grounding terminals of multiple pulse generation modules through four grounding leads.

27. The semiconductor process equipment according to claim 26, characterized in that, The lower electrode cavity includes a main cavity and multiple cantilever arms. The multiple cantilever arms surround the main cavity. One end of each cantilever arm is connected to the main cavity, and the other end of each cantilever arm is connected to the side wall of the process chamber. The cantilever arms are provided with lead-out channels for the wires of the pulse generation module for electrical connection with the DC power supply module, and the wires of the partition distribution plate located below the dielectric layer and above the pulse generation module for electrical connection with the electrostatic adsorption power supply, to be led out to the outside of the process chamber.

Images