A method of double patterning, semiconductor device and electronic equipment

Abstract

The application discloses a double patterning method, a semiconductor device and electronic equipment, and relates to the technical field of semiconductors, so as to simplify the steps of the existing LELE process, save the time of tape-out and the process cost. The double patterning method comprises the following steps: forming a pattern transfer layer on a substrate; forming a hard mask layer with aluminum as the material on the pattern transfer layer; forming a first mask material layer comprising a first anti-reflection coating soluble in a developing solution on the hard mask layer; forming a first pattern on the hard mask layer by performing exposure and developing treatment on the first mask material layer; performing a patterning treatment on a second mask material layer formed on the pattern transfer layer to form a second pattern on the second mask material layer; and combining the first pattern and the second pattern to perform etching treatment on the pattern transfer layer to form a target pattern on the pattern transfer layer.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a dual patterning method, semiconductor device, and electronic device. Background Technology

[0002] In semiconductor device manufacturing, double patterning, also known as double exposure or two-time exposure, works by dividing the data of the same pattern layer into two separate images or two separate photomasks.

[0003] With the development of integrated circuit manufacturing technology, photolithography technology faces enormous challenges, and the requirements for layout design are becoming more stringent. For example, to ensure the quality of pattern transfer, design rules tend to arrange lines of the same layer in one direction. Nevertheless, when the pitch of lines arranged in the same direction approaches 80nm, it reaches the limit of a single exposure in a 193nm immersion lithography machine; if the pitch is less than 80nm, dual or multiple patterning techniques must be adopted before more advanced lithography machines can be used for mass production.

[0004] Currently, the two most common dual patterning technologies in the industry are Self-Aligned Double Patterning (SADP) and Litho-Eich-Litho-Etch (LELE) dual patterning.

[0005] However, in the traditional LELE process, thin films of materials such as silicon oxide and silicon nitride are often used as hard mask layers, which need to be opened by etching, resulting in a complicated double patterning process and increased process costs. Summary of the Invention

[0006] The purpose of this invention is to provide a dual patterning method, semiconductor device, and electronic device to simplify the steps of the existing LELE process and save tape-out time and process costs.

[0007] To achieve the above objectives, the present invention provides the following technical solution:

[0008] In a first aspect, the present invention provides a dual-graphics method, comprising:

[0009] A pattern transfer layer is formed on the substrate;

[0010] A hard mask layer made of aluminum is formed on the pattern transfer layer;

[0011] A first mask material layer comprising a first antireflective coating soluble in developer is formed on a hard mask layer;

[0012] A first pattern is formed on a hard mask layer by exposing and developing the first mask material layer.

[0013] The second mask material layer formed on the pattern transfer layer is patterned to form a second pattern on the second mask material layer;

[0014] By combining the first and second graphics, the graphics transfer layer is etched to form the target graphics.

[0015] Compared to existing technologies, the dual patterning method provided by this invention utilizes the solubility of aluminum in the developer solution and selects an anti-reflective coating with developer solubility as the first anti-emissivity coating. This allows the first anti-emissivity coating and the hard mask layer to be dissolved by the developer after the first exposure, thus saving the etching step after the first exposure. Simultaneously, the selection of an insoluble anti-reflective coating as the second anti-emissivity coating protects the hard mask layer from being dissolved by the second developer solution during the second development process. Based on this, the dual patterning method provided by this invention simplifies the steps of the existing LELE process, thereby saving wafer fabrication time and process costs to a certain extent.

[0016] Optionally, the thickness of the hard mask layer ranges from 10 nm to 30 nm.

[0017] Optionally, forming a first mask material layer comprising a first antireflective coating soluble in developer on the hard mask layer includes:

[0018] A developer-soluble first anti-reflective coating is formed on the hard mask layer;

[0019] A first photoresist layer is formed on the surface of the first anti-reflective coating.

[0020] Optionally, the first mask material layer is exposed and developed to form a first pattern on the hard mask layer, including: using the first photoresist layer as the first mask, the first anti-reflective coating is exposed and developed to form a first pattern on the hard mask layer.

[0021] Optionally, the second mask material layer formed on the pattern transfer layer is patterned to form a second pattern on the second mask material layer, including:

[0022] A second anti-reflective coating and a second photoresist layer are sequentially formed on the pattern transfer layer;

[0023] The second photoresist layer is exposed and developed to form the second mask.

[0024] Based on the second mask, the second anti-reflective coating is etched to form a second pattern on the second anti-reflective coating.

[0025] Optionally, the second anti-reflective coating may be made of a different material than the first anti-reflective coating.

[0026] Optionally, the second anti-reflective coating is an insoluble anti-reflective coating.

[0027] Optionally, the material of the pattern transfer layer includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.

[0028] In a second aspect, the present invention also provides a semiconductor device comprising at least one patterned structure, the patterned structure being fabricated using a dual patterning method described in the first aspect or any possible implementation thereof.

[0029] Compared with the prior art, the beneficial effects of the semiconductor device provided by the present invention are the same as those of the dual patterning method described in the above technical solution, and will not be repeated here.

[0030] Thirdly, the present invention also provides an electronic device comprising the semiconductor device described in the second aspect.

[0031] Compared with the prior art, the beneficial effects of the electronic device provided by the present invention are the same as those of the dual-graphics method described in the above technical solutions, and will not be repeated here. Attached Figure Description

[0032] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0033] Figures 1(a) to 1(e) Existing technology features dual graphical process flow diagrams;

[0034] Figure 2 A flowchart of a dual-graphical method provided in an embodiment of the present invention;

[0035] Figure 3 This is a flowchart of another dual-graphical method provided in an embodiment of the present invention;

[0036] Figures 4-9 This is a dual-graphical process flow diagram provided by an embodiment of the present invention.

[0037] Figure label:

[0038] 1-Base layer, 2-Graphics transfer layer

[0039] 3-Hard mask layer, 4-First mask material layer,

[0040] 41 - First anti-reflective coating; 42 - First photoresist layer;

[0041] 5-Second mask material layer, 51-Second anti-reflective coating,

[0042] 52 - Second photoresist layer, 01' - Hard mask layer

[0043] 02' - First mask, 03' - Second mask. Detailed Implementation

[0044] To facilitate a clear description of the technical solutions in the embodiments of the present invention, the terms "first" and "second" are used to distinguish identical or similar items with essentially the same function and effect. For example, the first threshold and the second threshold are merely used to distinguish different thresholds and do not limit their order. Those skilled in the art will understand that the terms "first" and "second" do not limit the quantity or execution order, and that the terms "first" and "second" are not necessarily different.

[0045] It should be noted that in this invention, the terms "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in this invention should not be construed as being more preferred or advantageous than other embodiments or designs. Specifically, the use of terms such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0046] In this invention, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a combination of a and b, a combination of a and c, a combination of b and c, or a, b, and c, where a, b, and c can be single or multiple.

[0047] The existing LELE dual patterning process requires splitting the pattern into two layers according to a certain algorithm and making separate masks for each layer, so that each layer of pattern can be within the limitations of photolithography capabilities. Figures 1(a) to 1(e)The existing LELE process flow is illustrated in Figure 1(a). First, a first exposure is performed using a first mask. Then, as shown in Figure 1(b), the hard mask layer 01' is etched based on the first mask 02'. Next, as shown in Figure 1(c), a second exposure is performed using a second mask 03'. Finally, as shown in Figure 1(d), the photoresist formed during the second exposure and the hard mask layer 01' formed during the first etching are used as a barrier layer for the second etching. Finally, as shown in Figure 1(e), the patterns of the first mask 02' and the second mask 03' are simultaneously transferred to the target wafer. In the existing LELE process, the hard mask layer 01' is a thin film made of materials such as silicon oxide or silicon nitride, which requires etching to open, resulting in a cumbersome double patterning process and increased process costs.

[0048] In view of this, such as Figure 2 As shown, an embodiment of the present invention provides a dual-graphics method, including:

[0049] Step 101: Form a pattern transfer layer 2 on the substrate 1.

[0050] In this application, the specific structure of substrate 1 can be set according to the actual application scenario, and is not specifically limited here. Specifically, substrate 1 can be a silicon substrate, indium phosphide (InP) substrate, gallium arsenide (GaAs) substrate, germanium substrate, germanium silicon substrate, germanium substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, etc., where no structure is formed on it, or it can be a substrate 1 with some structure formed on it. For example, the aforementioned substrate 1 can be a common silicon substrate.

[0051] After forming the substrate 1, a pattern transfer layer 2 is formed on the surface of the substrate 1. The material of the pattern transfer layer 2 includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride. For example, the pattern transfer layer 2 can be silicon oxide.

[0052] Step 102: Form a hard mask layer 3 made of aluminum on the pattern transfer layer 2.

[0053] In this application, the thickness of the hard mask layer 3 ranges from 10 nm to 30 nm. For example, the thickness of the hard mask layer 3 can be 10 nm, 11 nm, 15 nm, 20 nm, 25 nm, 29 nm, or 30 nm; this embodiment of the invention does not specifically limit this. It is understood that when the thickness of the hard mask layer 3 is less than 10 nm, although the hard mask layer 3 can be dissolved by the developer more quickly, it cannot act as a barrier layer for pattern transfer, that is, the first pattern cannot be formed on the hard mask layer 3. When the thickness of the hard mask layer 3 is greater than 30 nm, it prolongs the time for the developer to dissolve the hard mask layer 3, thereby greatly increasing the development time. Therefore, selecting a hard mask layer 3 of appropriate thickness not only ensures that the hard mask layer 3 is dissolved by the developer during subsequent development processes, but also enables the hard mask layer 3 to act as a barrier layer for pattern transfer.

[0054] Step 103: Form a first mask material layer 4 on the hard mask layer 3, including a first anti-reflective coating 41 soluble in developer.

[0055] In this application, the first mask material layer 4 includes a first anti-reflective coating 41 and a first photoresist layer 42. The first anti-reflective coating 41 is soluble in developer and can be dissolved by developer during the development process, thereby eliminating the need for etching the first anti-reflective coating 41.

[0056] Step 104: A first pattern is formed on the hard mask layer 3 by exposing and developing the first mask material layer 4.

[0057] It should be understood that, based on the property that aluminum can be dissolved by the developer, when the material of the hard mask layer 3 is aluminum, the hard mask layer 3 can be directly dissolved by the developer during the first exposure and development process, without the need for etching the hard mask layer 3, and the first pattern can be formed on the hard mask layer 3.

[0058] Step 105: The second mask material layer 5 formed on the pattern transfer layer 2 is patterned to form a second pattern on the second mask material layer 5.

[0059] In this application, the second mask material layer 5 includes a second photoresist layer 52 and a second anti-reflective coating 51. After forming the first pattern on the hard mask layer 3, the second anti-reflective coating 51 and the second photoresist layer 52 need to be formed sequentially on the pattern transfer layer 2. The second photoresist layer 52 is used as a mask to etch the second anti-reflective coating 51, ultimately forming the second pattern on the second anti-reflective coating 51. In practice, the second anti-reflective coating 51 is an insoluble anti-reflective coating. During the formation of the second pattern, the second anti-reflective coating 51 will not be dissolved by the developer, thus protecting the hard mask layer 3 from being dissolved by the second development and preventing any impact on the hard mask layer 3.

[0060] Step 106: Combine the first and second graphics to perform etching on the graphic transfer layer 2 to form the target graphic.

[0061] In this application, a first pattern is formed on a hard mask layer 3, and a second pattern is formed on a second mask material layer 5. Based on the formed first and second patterns, the pattern transfer layer 2 is etched to form a target pattern on the pattern transfer layer 2, so that the target pattern can be etched onto the target wafer.

[0062] In summary, the dual patterning method provided by this invention utilizes the solubility of aluminum in the developer and employs an anti-reflective coating that is soluble in the developer as the first anti-emissivity coating. This allows the first anti-emissivity coating and the hard mask layer 3 to be dissolved by the developer after the first exposure, thus saving the etching step after the first exposure. Simultaneously, the use of an insoluble anti-reflective coating as the second anti-emissivity coating protects the hard mask layer 3 from being dissolved by the second developer during the second development process. Therefore, the dual patterning method provided by this invention simplifies the steps of the existing LELE process, thereby saving wafer fabrication time and process costs to a certain extent.

[0063] Figure 3 Another dual-graphics approach is illustrated, including:

[0064] Step 201: As Figure 4 As shown, a pattern transfer layer 2 is formed on substrate 1. The specific structure of substrate 1 can be referred to the previous text and will not be repeated here. The material of pattern transfer layer 2 includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride. For example, pattern transfer layer 2 can be silicon oxide.

[0065] Step 202: Form a hard mask layer 3 made of aluminum on the pattern transfer layer 2.

[0066] In this application, the thickness of the hard mask layer 3 ranges from 10 nm to 30 nm. For example, the thickness of the hard mask layer 3 can be 10 nm, 11 nm, 15 nm, 20 nm, 25 nm, 29 nm, or 30 nm; this embodiment of the invention does not specifically limit this. It is understood that when the thickness of the hard mask layer 3 is less than 10 nm, although the hard mask layer 3 can be dissolved by the developer more quickly, it cannot act as a barrier layer for pattern transfer, that is, the first pattern cannot be formed on the hard mask layer 3. When the thickness of the hard mask layer 3 is greater than 30 nm, it prolongs the time for the developer to dissolve the hard mask layer 3, thereby greatly increasing the development time. Therefore, selecting a hard mask layer 3 of appropriate thickness not only ensures that the hard mask layer 3 is dissolved by the developer during subsequent development processes, but also enables the hard mask layer 3 to act as a barrier layer for pattern transfer.

[0067] Step 203: As Figure 4 As shown, a first antireflective coating 41 soluble in developer is formed on the hard mask layer 3.

[0068] In this application, the first anti-reflective coating 41 is developer-soluble and can be dissolved by the developer during the development process, thereby eliminating the need for etching the first anti-reflective coating 41.

[0069] Step 204: As Figure 4 As shown, a first photoresist layer 42 is formed on the surface of the first anti-reflective coating 41.

[0070] In practice, the first photoresist layer 42 can be formed on the surface of the first antireflective coating 41 by spin coating.

[0071] Step 205: As Figure 5 As shown, the first photoresist layer 42 is used as the first mask to expose and develop the first anti-reflective coating 41, forming the first pattern on the hard mask layer 3.

[0072] It should be understood that, based on the property that aluminum can be dissolved by the developer, when the material of the hard mask layer 3 is aluminum, the hard mask layer 3 can be directly dissolved by the developer during the first exposure and development process, without the need for etching the hard mask layer 3, and the first pattern can be formed on the hard mask layer 3.

[0073] Step 206: The second mask material layer 5 formed on the pattern transfer layer 2 is patterned to form a second pattern on the second mask material layer 5.

[0074] Specifically, step 206 includes the following sub-steps:

[0075] Sub-step A1: such as Figure 6 As shown, a second anti-reflective coating 51 and a second photoresist layer 52 are sequentially formed on the pattern transfer layer 2.

[0076] In this application, the second anti-reflective coating 51 is made of a different material than the first anti-reflective coating 41. Specifically, the second anti-reflective coating 51 is an insoluble anti-reflective coating. Therefore, because it is an insoluble anti-reflective coating, it will not be dissolved by the developer during the formation of the second pattern, thus protecting the hard mask layer 3 from being dissolved by the second development and preventing any impact on the hard mask layer 3.

[0077] Sub-step A2: such as Figure 7 As shown, the second photoresist layer 52 is exposed and developed to form the second mask.

[0078] Sub-step A3: such as Figure 8 As shown, based on the second mask, the second anti-reflective coating 51 is etched to form a second pattern on the second anti-reflective coating 51.

[0079] Step 207: As Figure 9 As shown, the first and second graphics are combined to perform etching on the graphics transfer layer 2, forming the target graphic on the graphics transfer layer 2.

[0080] In this application, a first pattern is formed on a hard mask layer 3, and a second pattern is formed on a second mask material layer 5. Based on the formed first and second patterns, the pattern transfer layer 2 is etched to form a target pattern on the pattern transfer layer 2, so that the target pattern can be etched onto the target wafer.

[0081] This invention also provides a semiconductor device, which includes at least one patterned structure, the patterned structure being fabricated using the dual patterning method provided in the above embodiments.

[0082] Compared with the prior art, the beneficial effects of the semiconductor device provided by the embodiments of the present invention are the same as the beneficial effects of the dual patterning method described in the above embodiments, and will not be repeated here.

[0083] This invention also provides an electronic device, which includes the semiconductor device described in the above embodiments.

[0084] Compared with the prior art, the beneficial effects of the electronic device provided by the embodiments of the present invention are the same as the beneficial effects of the dual graphical method described in the above embodiments, and will not be repeated here.

[0085] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0086] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A dual-graphics method, characterized in that, include: A pattern transfer layer is formed on the substrate; A hard mask layer made of aluminum is formed on the pattern transfer layer; A first mask material layer comprising a first antireflective coating soluble in developer is formed on the hard mask layer; A first pattern is formed on the hard mask layer by exposing and developing the first mask material layer. The second mask material layer formed on the pattern transfer layer is patterned to form a second pattern on the second mask material layer; By combining the first pattern and the second pattern, the pattern transfer layer is etched to form the target pattern on the pattern transfer layer; The step of patterning the second mask material layer formed on the pattern transfer layer to form a second pattern on the second mask material layer includes: A second anti-reflective coating and a second photoresist layer are sequentially formed on the pattern transfer layer; the second anti-reflective coating is an insoluble anti-reflective coating; The second photoresist layer is exposed and developed to form a second mask. Based on the second mask, the second anti-reflective coating is etched to form a second pattern on the second anti-reflective coating.

2. The dual-graphics method according to claim 1, characterized in that, The thickness of the hard mask layer ranges from 10 nm to 30 nm.

3. The dual-graphics method according to claim 1, characterized in that, The first mask material layer, which forms a first antireflective coating that is soluble in developer, on the hard mask layer includes: A first antireflective coating soluble in developer is formed on the hard mask layer; A first photoresist layer is formed on the surface of the first anti-reflective coating.

4. The dual-graphics method according to claim 3, characterized in that, The step of exposing and developing the first mask material layer to form a first pattern on the hard mask layer includes: Using the first photoresist layer as a first mask, the first anti-reflective coating is exposed and developed to form a first pattern on the hard mask layer.

5. The dual-graphics method according to claim 1, characterized in that, The second anti-reflective coating is made of a different material than the first anti-reflective coating.

6. The dual-graphics method according to claim 1, characterized in that, The material of the pattern transfer layer includes any one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, tantalum nitride, or titanium nitride.

7. A semiconductor device, characterized in that, The semiconductor device includes at least one patterned structure, which is formed using the dual patterning method according to any one of claims 1 to 6.

8. An electronic device, characterized in that, The electronic device includes the semiconductor device as described in claim 7.

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