A high-reliability packaging interconnection method for power modules based on thermal stress regulation

Abstract

The application provides a high-reliability packaging interconnection method for a power module based on thermal stress regulation, which realizes thermal stress distribution regulation by changing three factors of porosity, pore distribution and pore size of a sintered nano-silver interconnection layer, so as to improve the reliability of the packaging interconnection of the power module. When the porosity of the first layer of the sintered nano-silver is 6% to 20%, the porosity of the second layer is 9% to 30%, the porosity of the third layer is 3% to 10%, and the pore size is 1 to 3 microns, the maximum thermal stress and thermal strain of the interconnection layer are significantly reduced and far away from the interconnection interface. The application can effectively slow down the failure risk of the sintered nano-silver interconnection interface peeling and improve the packaging reliability.

Description

Technical Field

[0001] This invention relates to the field of power electronic device packaging and interconnection, and more particularly to a high-reliability packaging and interconnection method for power modules based on thermal stress regulation. Background Technology

[0002] With the increasing number of electric vehicles on the road, market demands for their power performance and range are also rising. The frequent start-stop cycles and complex, variable operating conditions of vehicles lead to complex vibration loads, requiring electric vehicles to possess the triple attributes of high power, high efficiency, and reliable safety. Therefore, to ensure the safe and reliable operation of electric vehicles, it is necessary to develop power modules capable of high-temperature applications, handling extreme conditions such as high power and high current while also considering lifespan, reliability, and cost requirements. In the power module packaging structure, the most important aspect is the connection between the chip and the substrate, and between the substrate and the base plate. As a key channel for ensuring interface heat dissipation, the high-temperature reliable operation and heat dissipation capacity of the connection layer are particularly important. Based on considerations of the thermal, electrical, and mechanical properties of the power module connection interface and its packaging process, low-temperature sintering interconnect technology, represented by micro / nano silver solder paste, has been widely developed. Sintered nano silver solder paste has excellent electrical and thermal conductivity and possesses the same melting point as pure silver (960℃), greatly improving the reliability of power electronic devices.

[0003] Power electronic devices generate significant heat loss during operation, often leading to a rise in the temperature around the chip. At high temperatures, the mismatch in the coefficients of thermal expansion (CTE) of different materials causes inconsistent thermal deformation dimensions between the interconnect layer and the substrate, resulting in high thermal stress and subsequent thermal strain, leading to warping and cracking. Warping and cracking not only affect the internal mechanical stress of the module but also compromise the module's external connections, causing interconnect layer failure and reducing the power module's lifespan. Therefore, reducing the maximum thermal stress and thermal strain values ​​of the sintered silver package interconnect layer and controlling the distribution of thermal stress and strain are crucial for improving the reliability of power modules. Summary of the Invention

[0004] To achieve the above objectives, the present invention provides a power module packaging interconnection method based on thermal stress distribution regulation. By changing three factors—porosity, pore distribution, and pore size—of the sintered silver nanolayer interconnect layer, thermal stress distribution is regulated, thereby improving the reliability of the power module packaging interconnection. The method is simple and has high practical application value.

[0005] A power module packaging interconnection method based on thermal stress distribution regulation includes the following steps:

[0006] (1) Place the chip and substrate in anhydrous ethanol and ultrasonically clean for 1-5 minutes to remove surface dirt. Then use a vacuum drying oven to dry at 60°C for 15 minutes to allow the anhydrous ethanol on the substrate surface to fully evaporate.

[0007] (2) The sintered silver is sintered in three layers: the layer closest to the substrate is the first layer, and the layer closest to the chip is the third layer; the porosity of the second layer is controlled to be greater than that of the first layer, and the porosity of the first layer is greater than that of the third layer.

[0008] (3) Coat the first layer of nano silver solder paste on the cleaned substrate surface with a thickness of 30-50 μm. Then place the substrate coated with solder paste on a heating table and pre-dry it at 80-120℃ for 10-20 min to obtain the first layer of sintered silver.

[0009] (4) A second layer of nano silver solder paste with a thickness of 30-50 μm is coated on the surface of the pre-dried solder paste. Then the substrate coated with solder paste is placed on a heating table for secondary drying. It is pre-dried at 100-150℃ for 10-20 min to obtain the second layer of sintered silver.

[0010] (5) Coat the cleaned chip with nano silver solder paste with a thickness of 30-50 μm, then place the chip coated with solder paste on a heating stage and pre-dry at 80-120℃ for 10-20 min to obtain the third layer of sintered silver.

[0011] (6) Place the chip coated with solder paste on the substrate coated with double layer of solder paste, so that the solder paste coating surfaces are attached to form a sandwich structure;

[0012] (7) Place the sample from step 6 in a sintering furnace, heat it to 250-300°C, hold it for 10-30 minutes, apply pressure of 5-10 MPa, and allow it to cool naturally to room temperature after sintering to obtain an interconnected interface with a porosity gradient distribution.

[0013] (8) After sintering, the nano silver solder paste shrinks, with a total thickness of 60-100 μm and a thickness of 20-40 μm per layer; the pore size of the sintered silver is 1-3 μm; the porosity of the first layer of the sintered silver is 6%-20%, the porosity of the second layer is 9%-30%, and the porosity of the third layer is 3%-10%.

[0014] Compared with existing technologies, the present invention has the following advantages and beneficial effects:

[0015] This invention, based on the influence of porosity on the physical properties of sintered silver such as Young's modulus, regulates the location of maximum thermal stress and thermal strain, thereby making the failure location far away from the connection interface between sintered silver and the chip or substrate, and reducing the value of maximum thermal stress and thermal strain, thus improving the service life of the chip or substrate and the reliability of interconnection. Attached Figure Description

[0016] Figure 1 This is a simplified model diagram corresponding to the present invention;

[0017] Figure 2 This is the equivalent thermal stress cloud diagram of the sample;

[0018] Figure 3 This is the equivalent thermal strain contour map of the sample.

[0019] Figure 1 In the middle: 1-substrate, 2-sintered silver first layer, 3-sintered silver second layer, 4-sintered silver third layer, 5-chip;

[0020] Figure 2 In the middle: the red arrows indicate the maximum thermal stress. The left figure is the equivalent thermal stress cloud diagram in Example 1, and the right figure is a magnified view of a part.

[0021] Figure 3 In the middle: the red arrows indicate the maximum thermal strain. The left figure is the equivalent thermal strain cloud map of Example 1, and the right figure is a partial magnified view. Detailed Implementation

[0022] The present invention will now be described in more detail with reference to the accompanying drawings and specific embodiments.

[0023] This invention improves the reliability of power module packaging interconnects by controlling the thermal stress distribution by altering three factors: porosity, pore distribution, and pore size of the sintered nano-silver interconnect layer. Figure 1 This is a simplified model diagram corresponding to the present invention. When the porosity of the second layer of sintered silver is greater than that of the first layer, and the porosity of the first layer is greater than that of the third layer, the reliability of the power module can be effectively improved.

[0024] Example 1

[0025] (1) Place the chip and substrate in anhydrous ethanol and ultrasonically clean for 1-5 minutes to remove surface dirt. Then use a vacuum drying oven to dry at 60°C for 15 minutes to allow the anhydrous ethanol on the substrate surface to fully evaporate.

[0026] (2) Sinter silver in three layers, with the layer closest to the substrate being the first layer and the layer closest to the chip being the third layer; control the porosity of the second layer of sintered silver to be greater than that of the first layer, and the porosity of the first layer to be greater than that of the third layer.

[0027] (3) A first layer of nano silver solder paste with a thickness of 40 μm was coated on the upper surface of the cleaned substrate. Then the substrate coated with solder paste was placed on a heating table and pre-dried at 100°C for 15 min to obtain the first layer of sintered silver.

[0028] (4) A second layer of nano silver solder paste with a thickness of 50 μm is coated on the surface of the pre-dried solder paste. Then the substrate coated with solder paste is placed on a heating table for secondary drying. It is pre-dried at 150°C for 10 min to obtain the second layer of sintered silver.

[0029] (5) Coat the cleaned chip with nano silver solder paste with a thickness of 40 μm, then place the chip coated with solder paste on a heating stage and pre-dry at 100°C for 15 min to obtain the third layer of sintered silver.

[0030] (6) Place the chip coated with solder paste on the substrate coated with double layer of solder paste, so that the solder paste coating surfaces are attached to form a sandwich structure;

[0031] (7) Place the sample from step 6 in a sintering furnace, heat it to 280°C, hold it for 20 minutes, apply a pressure of 8 MPa, and allow it to cool naturally to room temperature after sintering to obtain an interconnected interface with a porosity gradient distribution.

[0032] (8) The total thickness of the sintered nano silver solder paste is about 90 μm, and the thickness of each layer is about 28 μm, 35 μm and 28 μm respectively; the pore size of the sintered silver is about 2.5 μm; the porosity of the first layer of sintered silver is 12%, the porosity of the second layer is 18%, and the porosity of the third layer is 7%.

[0033] (9) Figure 2 and Figure 3 These are the equivalent thermal stress cloud map and equivalent thermal strain cloud map of the sample, respectively. It can be seen that the maximum thermal stress and thermal strain are concentrated in the interconnect layer, and the reliability of the power module is significantly improved.

[0034] Example 2

[0035] (1) Place the chip and substrate in anhydrous ethanol and ultrasonically clean for 1-5 minutes to remove surface dirt. Then use a vacuum drying oven to dry at 60°C for 15 minutes to allow the anhydrous ethanol on the substrate surface to fully evaporate.

[0036] (2) Sinter silver in three layers, with the layer closest to the substrate being the first layer and the layer closest to the chip being the third layer; control the porosity of the second layer of sintered silver to be greater than that of the first layer, and the porosity of the first layer to be greater than that of the third layer.

[0037] (3) A first layer of nano silver solder paste with a thickness of 30 μm was coated on the upper surface of the cleaned substrate. Then the substrate coated with solder paste was placed on a heating table and pre-dried at 80°C for 10 min to obtain the first layer of sintered silver.

[0038] (4) A second layer of nano silver solder paste with a thickness of 30 μm is coated on the surface of the pre-dried solder paste. Then the substrate coated with solder paste is placed on a heating table for secondary drying. It is pre-dried at 120°C for 15 min to obtain the second layer of sintered silver.

[0039] (5) Coat the cleaned chip with nano silver solder paste with a thickness of 30 μm, then place the chip coated with solder paste on a heating stage and pre-dry at 80°C for 10 min to obtain the third layer of sintered silver.

[0040] (6) Place the chip coated with solder paste on the substrate coated with double layer of solder paste, so that the solder paste coating surfaces are attached to form a sandwich structure;

[0041] (7) Place the sample from step 6 in a sintering furnace, heat it to 300°C, hold it for 15 minutes, apply a pressure of 5 MPa, and allow it to cool naturally to room temperature after sintering to obtain an interconnected interface with a porosity gradient distribution.

[0042] (8) The total thickness of the sintered nano silver solder paste is 60 μm, and the thickness of each layer is about 22 μm; the pore size of the sintered silver is about 1.5 μm; the porosity of the first layer of sintered silver is 10%, the porosity of the second layer is 15%, and the porosity of the third layer is 6%.

[0043] (9) Shear strength test showed that the fracture surface was concentrated in the interconnect layer rather than the interconnect interface, indicating that the maximum thermal stress and thermal strain were concentrated in the interconnect layer, and the reliability of the power module was significantly improved.

[0044] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A high-reliability packaging and interconnection method for power modules based on thermal stress regulation, characterized by mainly... Includes the following steps: Step 1: Place the chip and substrate in anhydrous ethanol and ultrasonically clean for 1-2 minutes to remove surface dirt. Then use a vacuum drying oven to dry at 60°C for 15 minutes to allow the anhydrous ethanol on the substrate surface to fully evaporate. Step 2: Apply a first layer of nano silver solder paste to the cleaned substrate surface, with a thickness of 30-50 μm. Then place the substrate coated with solder paste on a heating table and pre-dry at 80-120℃ for 10-20 min to promote the evaporation of low-temperature solvents in the solder paste. After pre-drying, remove the substrate and allow it to cool naturally to room temperature. Step 3: Apply a second layer of nano silver solder paste to the pre-dried solder paste surface, with a thickness of 30-50 μm. Then place the substrate coated with solder paste on a heating table for secondary drying at 100-150℃ for 10-20 min to promote the evaporation of organic solvents in the solder paste. After the secondary drying is completed, remove the substrate and allow it to cool naturally to room temperature. Step 4: Coat the cleaned chip with nano silver solder paste to a thickness of 30-50 μm. Then place the chip coated with solder paste on a heating stage and pre-dry at 80-120℃ for 10-20 min to promote the evaporation of low-temperature solvents in the solder paste. After pre-drying, a third layer of nano silver solder paste is obtained. Remove the substrate and allow it to cool naturally to room temperature. Step 5: Place the chip coated with solder paste onto the substrate coated with double layers of solder paste, so that the solder paste coating surfaces are in contact to form a sandwich structure; wherein, the side closer to the substrate is the first layer, the middle is the second layer, and the side closer to the chip is the third layer. Step 6: Place the sample from Step 5 in a sintering furnace, heat it to 250-300℃, hold it for 10-20 minutes, apply a pressure of 5-10 MPa, and allow it to cool naturally to room temperature after sintering to obtain an interconnected interface with a porosity gradient distribution; wherein, the porosity of the second layer is greater than that of the first layer and the third layer.

2. The high-reliability packaging and interconnection method for power modules based on thermal stress regulation according to claim 1, characterized in that, By changing the coating thickness and sintering conditions of the solder paste, the porosity of the sintered nano-silver solder paste can be controlled, thereby achieving the regulation of the thermal stress distribution of the interconnect layer, reducing the maximum thermal stress and thermal strain at the interconnect interface, and keeping stress concentration away from the interconnect interface.

3. The high-reliability packaging and interconnection method for power modules based on thermal stress regulation according to claim 1, characterized in that, The total thickness of the sintered nano silver solder paste is 60–100 μm, and the thickness of each layer is 20–40 μm.

4. The high-reliability packaging and interconnection method for power modules based on thermal stress regulation according to claim 1, characterized in that, The pore size of sintered silver is 1–3 μm.

5. The high-reliability packaging and interconnection method for power modules based on thermal stress regulation according to claim 1, characterized in that, The porosity of the first layer of sintered silver is 6%–20%, the porosity of the second layer is 9%–30%, and the porosity of the third layer is 3%–10%.

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