Light emitting diode with improved light efficiency, method of manufacturing the same, and display panel

Abstract

The present disclosure provides a light emitting diode with improved light efficiency, a preparation method thereof and a display panel, and belongs to the technical field of optoelectronic manufacturing. The light emitting diode comprises an epitaxial layer, the epitaxial layer comprises a first semiconductor layer, a multi-quantum well layer and a second semiconductor layer which are sequentially stacked, the second semiconductor layer has a groove exposing the first semiconductor layer, and the groove wall exposing the multi-quantum well layer comprises at least one step, each of the steps comprises a first wall surface, a step surface and a second wall surface which are sequentially connected in the direction from the second semiconductor layer to the first semiconductor layer, and the first wall surface and the second wall surface of adjacent steps are the same wall surface. The present disclosure can improve the problem of forming non-radiative recombination centers on the side surface of the epitaxial layer after etching the groove, and improve the light emitting effect of the light emitting diode.

Description

Technical Field

[0001] This disclosure relates to the field of optoelectronic manufacturing technology, and in particular to a light-emitting diode with improved luminous efficiency, a method for its fabrication, and a display panel. Background Technology

[0002] Light-emitting diodes (LEDs) are highly influential new products in the optoelectronics industry. They are characterized by their small size, long lifespan, rich and colorful colors, and low energy consumption. They are widely used in lighting, displays, signal lights, backlights, toys, and other fields.

[0003] In related technologies, a light-emitting diode typically includes a substrate, a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially. A groove exposing the first semiconductor layer is typically formed on the surface of the second semiconductor layer using plasma etching, so that electrodes can be electrically connected to the first semiconductor layer through the groove.

[0004] However, during the plasma etching process, plasma implantation can affect the side surface of the epitaxial layer, forming non-radiative recombination centers within a certain distance on the side surface, which leads to a decrease in the luminous efficiency of the light-emitting diode. Summary of the Invention

[0005] This disclosure provides a light-emitting diode (LED) with improved luminous efficiency, its fabrication method, and a display panel. It addresses the problem of non-radiative recombination centers forming on the side surface of the epitaxial layer after etching grooves, thereby enhancing the LED's luminous efficacy. The technical solution is as follows:

[0006] This disclosure provides a light-emitting diode (LED) comprising an epitaxial layer, the epitaxial layer comprising a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially, the second semiconductor layer having a groove exposing the first semiconductor layer, the groove exposing the groove wall of the multiple quantum well layer comprising at least one step, each step comprising a first wall surface, a step surface, and a second wall surface sequentially connected in the direction from the second semiconductor layer to the first semiconductor layer, the first wall surface and the second wall surface of adjacent steps being the same wall surface.

[0007] In another implementation of this disclosure, the angle between the first wall surface and the step surface is greater than or equal to 90 degrees, and the angle between the second wall surface and the step surface is greater than or equal to 90 degrees.

[0008] In another implementation of the present disclosure, at least one of the stepped surfaces is located in the region where the sidewall of the multi-quantum-well layer is located.

[0009] In another implementation of the embodiments of this disclosure, the width of the step surface is 0.5 μm to 3 μm.

[0010] In another implementation of the present disclosure, the length of the first wall is 1 μm to 2 μm, and the length of the second wall is 0.6 μm to 1 μm.

[0011] This disclosure provides a display panel, which includes a light-emitting functional layer and a driving backplane. The light-emitting functional layer is located on the driving backplane and is electrically connected to the driving backplane. The light-emitting functional layer includes a plurality of light-emitting diodes as described above.

[0012] This disclosure provides a method for fabricating a light-emitting diode (LED). The method includes: providing a substrate; forming an epitaxial layer on the substrate, wherein the epitaxial layer consists of a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer stacked sequentially; etching the second semiconductor layer to form a groove exposing the first semiconductor layer, wherein the groove wall exposing the multiple quantum well layer includes at least one step, and each step includes a first wall surface, a step surface, and a second wall surface that are sequentially connected in the direction from the second semiconductor layer to the first semiconductor layer.

[0013] In another implementation of the present disclosure, etching the second semiconductor layer to form a groove exposing the first semiconductor layer includes: performing a first etching on the surface of the second semiconductor layer to form a first groove that at least exposes the multiple quantum well layer; and performing a second etching on the bottom of the first groove to form a second groove that exposes the first semiconductor layer.

[0014] In another implementation of the present disclosure, the depth of the first tank is 1 μm to 2 μm, the distance between the tank wall of the first tank and the tank wall of the second tank is 0.5 μm to 3 μm, and the depth of the second tank is 0.6 μm to 1 μm.

[0015] In another implementation of the present disclosure, when the first etching is performed on the surface of the second semiconductor layer, the power of the etching equipment is controlled to be 300W to 600W and the lower power to be 100W to 300W; when the second etching is performed on the bottom of the first tank, the power of the etching equipment is controlled to be 200W to 300W and the lower power to be 50W to 150W.

[0016] The beneficial effects of the technical solutions provided in this disclosure include at least the following:

[0017] The second semiconductor layer of the light-emitting diode provided in this embodiment has a groove exposing the first semiconductor layer. The groove wall exposing the multi-quantum well layer includes at least one step, and each step includes a first wall surface, a step surface, and a second wall surface connected in sequence. When fabricating the groove, at least two etching processes are required to ensure that the groove wall has at least one step. This way, even if damage is caused to the side surface of the epitaxial layer during the first etching of the groove, forming a non-radiative recombination center, the damaged area formed by the first etching is removed by the second etching, reducing non-radiative recombination and improving the luminous efficiency of the light-emitting diode. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided by related technologies;

[0020] Figure 2 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure;

[0021] Figure 3 This is a schematic diagram of the groove wall of a groove provided in an embodiment of this disclosure;

[0022] Figure 4 This is a schematic diagram of the groove wall of a groove provided in an embodiment of this disclosure;

[0023] Figure 5 This is a flowchart of a method for fabricating a light-emitting diode provided in an embodiment of this disclosure.

[0024] The markings in the diagram are explained as follows:

[0025] 20. Epitaxial layer; 21. First semiconductor layer; 22. Multiple quantum well layer; 23. Second semiconductor layer;

[0026] 30. Groove; 301. First wall surface; 302. Stepped surface; 303. Second wall surface;

[0027] 41. Transparent conductive layer; 42. Passivation layer;

[0028] 50. Electrode. Detailed Implementation

[0029] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in further detail below with reference to the accompanying drawings.

[0030] Unless otherwise defined, the technical or scientific terms used herein shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” “third,” and similar terms used in this patent application specification and claims do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an” or “a” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “comprising” or “including” and similar terms mean that the elements or objects preceding “comprising” or “including” encompass the elements or objects listed following “comprising” or “including” and their equivalents, and do not exclude other elements or objects. The terms “connected” or “linked” and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” “right,” “top,” and “bottom,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0031] Figure 1 This is a schematic diagram of the structure of a light-emitting diode provided by related technologies. For example... Figure 1 As shown, in the related technology, the light-emitting diode includes an epitaxial layer 20, a transparent conductive layer 41, a passivation layer 42 and an electrode 50 stacked in sequence. The epitaxial layer 20 includes a first semiconductor layer 21, a multiple quantum well layer 22 and a second semiconductor layer 23 stacked in sequence.

[0032] like Figure 1 As shown, the surface of the second semiconductor layer 23 has a groove 30 exposing the first semiconductor layer 21. The transparent conductive layer 41 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21, and the passivation layer 42 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21, the surface of the transparent conductive layer 41, and in the groove 30. The passivation layer 42 has through holes that expose the bottom of the transparent conductive layer 41 and the groove 30, respectively. The electrode 50 is connected to the transparent conductive layer 41 and the first semiconductor layer 21 through the through holes, respectively.

[0033] In related technologies, when fabricating this type of light-emitting diode, plasma etching of the second semiconductor layer 23 is typically used to form a groove 30. Since plasma implantation affects the side surfaces of the epitaxial layer 20, forming non-radiative recombination centers on the side surfaces of the epitaxial layer 20, it leads to a decrease in luminous efficiency.

[0034] Therefore, this disclosure provides a light-emitting diode. Figure 2 This is a schematic diagram of the structure of a light-emitting diode provided in an embodiment of this disclosure. Figure 2As shown, the light-emitting diode includes an epitaxial layer 20, which includes a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23 stacked sequentially. The second semiconductor layer 23 has a groove 30 exposing the first semiconductor layer 21.

[0035] like Figure 2 As shown, the groove 30 exposes the groove wall of the multi-quantum well layer 22, which includes at least one step. Each step includes a first wall surface 301, a step surface 302, and a second wall surface 303 connected sequentially in the direction from the second semiconductor layer 23 to the first semiconductor layer 21. The first wall surface and the second wall surface of adjacent steps are the same wall surface.

[0036] The second semiconductor layer 23 of the light-emitting diode provided in this embodiment has a groove 30 exposing the first semiconductor layer 21. The groove 30 exposes the wall of the multi-quantum well layer 22, which includes at least one step, and each step includes a first wall surface 301, a step surface 302, and a second wall surface 303 connected in sequence. When fabricating the groove 30, at least two etching processes are required to make the groove wall of the groove 30 have at least one step.

[0037] In this embodiment, the depth of the second etching is shallower than that of the first etching, and the upper and lower power of the etching equipment during the second etching are both lower than those during the first etching. Therefore, the second etching can remove the damage formed on the side surface of the epitaxial layer by the first etching, while also producing less damage. Thus, even if the first etching of the groove 30 causes damage on the side surface of the epitaxial layer 20 and forms a non-radiative recombination center, the damaged area formed by the first etching can be removed by the second etching, reducing non-radiative recombination and improving the luminous efficiency of the light-emitting diode.

[0038] Optionally, such as Figure 2 As shown, the trench wall includes a step, which is connected sequentially to a first wall surface 301, a step surface 302, and a second wall surface 303 in the direction from the second semiconductor layer 23 to the first semiconductor layer 21.

[0039] In the above implementation, a step is provided on the groove wall of the groove 30 so that the groove wall is formed by three connected surfaces, and every two surfaces together form a bent structure. Thus, when making the groove 30, a first groove body composed of a first wall surface 301 and a step surface 302 is first etched to form a first groove body. Then, the step surface 302 is etched to form a second groove body composed of a second wall surface 303 and the surface of the first semiconductor layer 21 on the step surface 302. Finally, the groove 30 formed by the combination of the first groove body and the second groove body is obtained, and the groove wall of the groove 30 formed by the first wall surface 301, the step surface 302 and the second wall surface 303 is stepped.

[0040] Even if damage is caused on the side of the epitaxial layer 20 during the etching of the first groove, and nonradiative recombination centers are formed, the damaged area formed by the first etching can be removed by etching the second groove, reducing nonradiative recombination and improving the luminous efficiency of the light-emitting diode.

[0041] In one implementation, the angle between the first wall surface 301 and the step surface 302 is greater than or equal to 90 degrees, and the angle between the second wall surface 303 and the step surface 302 is greater than or equal to 90 degrees.

[0042] For example, such as Figure 2 As shown, the first wall surface 301 and the step surface 302 have a 90-degree angle, and the second wall surface 303 and the step surface 302 also have a 90-degree angle. At this time, the step surface 302 is parallel to the surface of the first semiconductor layer 21.

[0043] For example, such as Figure 3 As shown, the angle between the first wall surface 301 and the step surface 302 is an obtuse angle, and the angle between the second wall surface 303 and the step surface 302 is also an obtuse angle. At this time, the step surface 302 is parallel to the surface of the first semiconductor layer 21, or the step surface 302 has an angle with the surface of the first semiconductor layer 21.

[0044] In the above implementation, the included angle between the first wall surface 301 and the step surface 302 is controlled to be relatively large. This allows the film layer subsequently formed on the first wall surface 301 and the step surface 302 to transition more smoothly from the junction of the first wall surface 301 and the step surface 302 to the step surface 302, reducing the difficulty of preparing the subsequent film layer.

[0045] By controlling the included angle between the second wall surface 303 and the step surface 302 to be relatively large, the film layer subsequently formed on the second wall surface 303 and the step surface 302 can transition more smoothly from the junction of the second wall surface 303 and the step surface 302 to the second wall surface 303, reducing the difficulty of preparing the subsequent film layer.

[0046] In another implementation, such as Figure 4 As shown, the angle between the first wall surface 301 and the step surface 302 is an acute angle, and the angle between the second wall surface 303 and the step surface 302 is also an acute angle. At this time, the step surface 302 is parallel to the surface of the first semiconductor layer 21.

[0047] In the above implementation, the included angle between the first wall surface 301 and the step surface 302 is controlled to be small, so that the surfaces of the first wall surface 301 and the second semiconductor layer 23 away from the first semiconductor layer 21 form chamfers. Similarly, the included angle between the second wall surface 303 and the step surface 302 is controlled to be small, so that the second wall surface 303 and the step surface 302 form chamfers. This way, the film layer subsequently formed on the groove wall of the groove 30 can be overlapped on the chamfers, preventing the film layer from easily detaching and improving the reliability of the light-emitting diode.

[0048] In some implementations, such as Figure 3 , 4 As shown, at least one stepped surface 302 is located in the region where the sidewall of the multi-quantum well layer 22 is located.

[0049] Plasma implantation affects the sides of the epitaxial layer 20, creating nonradiative recombination centers. Since the multiple quantum well layer 22 is the light-emitting layer of the LED, placing the step surface 302 in the region where the sidewalls of the multiple quantum well layer 22 are located allows for the removal of the damaged areas formed by the first etching on the sidewalls of the multiple quantum well layer 22 through a second etching process. This reduces nonradiative recombination and improves the luminous efficiency of the LED.

[0050] In some other implementations, the stepped surface may be located in the region where the sidewall of the first semiconductor layer is located, or the stepped surface may be located in the region where the sidewall of the second semiconductor layer is located.

[0051] Compared to placing the stepped surface on the sidewall region of the multi-quantum-well layer, placing it on the sidewall region of the semiconductor layer removes the damaged area formed on the sidewall of the semiconductor layer through secondary etching, while the multi-quantum-well layer is the light-emitting layer of the epitaxial layer. Therefore, placing the stepped surface on the sidewall of the semiconductor layer is slightly less effective in reducing non-radiative coincidence than placing it on the sidewall of the multi-quantum-well layer.

[0052] Optionally, such as Figure 2 As shown, the width L1 of the step surface 302 is 0.5μm to 3μm.

[0053] The width of the step surface refers to the dimension of the groove wall on a cross section perpendicular to both the step surface and the first wall surface.

[0054] By controlling the width of the step surface 302 within the above range, it is possible to avoid setting the width of the step surface 302 too large, which would etch away too much of the quantum well layer 22 and affect the light emission effect of the light-emitting diode.

[0055] For example, the width of the step surface 302 is 2 μm.

[0056] Optionally, such as Figure 2As shown, the length L2 of the first wall 301 is 1 μm to 2 μm, and the length L3 of the second wall 303 is 0.6 μm to 1 μm.

[0057] The lengths of the first and second walls refer to the dimensions of the groove wall on a cross-section perpendicular to both the step surface and the first wall.

[0058] By controlling the length of the first wall 301 within the above range, it can be ensured that the step surface 302 is located close to the sidewall of the multi-quantum well layer 22. This allows the damaged area formed on the sidewall of the multi-quantum well layer 22 by the first etching to be removed by the second etching, reducing non-radiative recombination and improving the luminous efficiency of the light-emitting diode.

[0059] By controlling the length of the first wall 301 within the above range, it can be ensured that the multi-quantum well layer 22 is etched through during the second etching to expose the first semiconductor layer 21, while also avoiding etching through the first semiconductor layer 21.

[0060] For example, the length of the first wall 301 is 1 μm and the length of the second wall 303 is 0.8 μm.

[0061] Optionally, such as Figure 2 As shown, the light-emitting diode includes an epitaxial layer 20, a transparent conductive layer 41, a passivation layer 42, and an electrode 50 stacked sequentially. The surface of the second semiconductor layer 23 has a groove 30 exposing the first semiconductor layer 21. The transparent conductive layer 41 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21, and the passivation layer 42 is located on the surface of the second semiconductor layer 23 away from the first semiconductor layer 21, the surface of the transparent conductive layer 41, and within the groove 30. The passivation layer 42 has through holes that expose the bottom of the transparent conductive layer 41 and the groove 30, respectively. The electrode 50 is connected to the transparent conductive layer 41 and the first semiconductor layer 21 through the through holes, respectively.

[0062] In this embodiment of the present disclosure, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0063] For example, the first semiconductor layer 21 is an n-type layer and the second semiconductor layer 23 is a p-type layer.

[0064] The following example, using blue light epitaxial layer 20 as an example, illustrates the structure of each layer. In the blue light epitaxial structure, the p-type layer includes a p-type GaN layer.

[0065] The multi-quantum-well layer 22 may include alternating InGaN quantum-well layers and GaN quantum-barrier layers. The third light-emitting layer may include alternating layers of 3 to 8 periods of InGaN quantum-well layers and GaN quantum-barrier layers.

[0066] Among them, the n-type layer includes the n-type GaN layer.

[0067] Optionally, the thickness of the epitaxial layer 20 is 2 μm to 10 μm.

[0068] For example, the thickness of the epitaxial layer 20 is 6 μm.

[0069] The transparent conductive layer 41 is a film layer used to connect with the electrode 50. By using the transparent conductive layer 41, the current injected by the electrode 50 can be laterally expanded, allowing the current to be injected into various regions of the epitaxial layer 20, thereby improving the luminous efficiency.

[0070] For example, the transparent conductive layer 41 can be an indium tin oxide (ITO) layer. Indium tin oxide layers have good transmittance and low resistivity. Using an indium tin oxide layer as the transparent conductive layer 41 allows more light to be transmitted from the transparent conductive layer 41, thus ensuring the light emission effect. At the same time, due to its low resistivity, it also facilitates carrier conduction and improves injection efficiency.

[0071] For example, the transparent conductive layer 41 can be an indium zinc oxide (IZO) layer. Indium zinc oxide layers have good transmittance and low resistivity. Using an indium zinc oxide layer as the transparent conductive layer 41 allows more light to be transmitted through the transparent conductive layer 41, thus ensuring good light emission. Simultaneously, due to its low resistivity, it also facilitates carrier conduction, improving injection efficiency.

[0072] As an example, the thickness of the transparent conductive layer 41 can be from 1,000 angstroms to 5,000 angstroms. For example, the thickness of the transparent conductive layer 41 is 2,000 angstroms.

[0073] Optionally, the passivation layer 42 includes at least one of a silicon oxide layer, a silicon nitride layer, and a titanium oxide layer.

[0074] For example, the passivation layer 42 may be a silicon oxide layer.

[0075] The thickness of the silicon oxide layer can be 5000 angstroms.

[0076] Optionally, the electrodes of the light-emitting diode include a p-electrode and an n-electrode, wherein the p-electrode is used to connect to the p-type layer and the n-electrode is used to connect to the n-type layer.

[0077] This disclosure provides a display panel including a light-emitting functional layer and a driving backplane. The light-emitting functional layer is located on the driving backplane and is electrically connected to the driving backplane. The light-emitting functional layer includes a plurality of light-emitting diodes as described above.

[0078] Optionally, the driving backplane can be a TFT (Thin Film Transistor) substrate. The driving backplane includes multiple driving circuits arranged in an array. Each driving circuit on the driving backplane includes at least two TFTs for controlling the light emission of the connected light-emitting layer.

[0079] For example, the driving circuit includes an active layer, a gate insulating layer, a gate layer, an interlayer dielectric layer, and a source / drain layer sequentially stacked on a substrate. The light-emitting layer is connected to the source / drain layer of the corresponding driving circuit.

[0080] The TFTs driving the backplane can be made of various materials such as polycrystalline silicon and metal oxides, and this embodiment does not impose any restrictions.

[0081] The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0082] Figure 5 This is a flowchart illustrating a method for fabricating a light-emitting diode (LED) according to an embodiment of this disclosure. Figure 5 As shown, the preparation method includes:

[0083] Step S11: Provide a substrate.

[0084] Step S12: Form an epitaxial layer 20 on the substrate.

[0085] The epitaxial layer 20 consists of a first semiconductor layer 21, a multi-quantum well layer 22, and a second semiconductor layer 23, which are stacked sequentially.

[0086] Step S13: Etch the second semiconductor layer 23 to form a groove 30 that exposes the first semiconductor layer 21.

[0087] The groove 30 exposes the groove wall of the multi-quantum well layer 22, which includes at least one step. Each step includes a first wall surface, a step surface, and a second wall surface that are sequentially connected in the direction from the second semiconductor layer to the first semiconductor layer.

[0088] The second semiconductor layer 23 of the light-emitting diode prepared by the method provided in this embodiment has a groove 30 exposing the first semiconductor layer 21. The groove 30 exposes the wall of the multi-quantum well layer 22, which includes at least one step. Each step includes a first wall surface 301, a step surface 302, and a second wall surface 303 connected in sequence. When fabricating the groove 30, at least two etching processes are required to ensure that the groove wall of the groove 30 has at least one step. This way, even if damage is caused to the side surface of the epitaxial layer 20 during the first etching of the groove 30, forming a non-radiative recombination center, the damaged area formed by the first etching is removed by the second etching, reducing non-radiative recombination and improving the luminous efficiency of the light-emitting diode.

[0089] In related technologies, the etching rate is usually reduced to minimize etching damage, but this method makes it difficult to control the morphology of the groove 30.

[0090] In this embodiment, the groove 30 is formed through two etching processes. During the first etching, the upper and lower power of the etching equipment are higher, resulting in a faster etching rate. Therefore, the first etching has a significant impact on the morphology. During the second etching, the upper and lower power of the etching equipment are lower, resulting in a slower etching rate. Therefore, the second etching has almost no impact on the morphology. Thus, this two-etching method, while using a relatively high etching rate in the first etching, effectively controls the morphology of the groove 30 after etching, ensuring that the morphology of the groove 30 meets the design requirements.

[0091] In step S11, the substrate can be a GaAs substrate, a silicon substrate, or a silicon carbide substrate. The substrate can be a flat substrate or a patterned substrate.

[0092] Step S12 may include: sequentially forming a first semiconductor layer 21, a multiple quantum well layer 22, and a second semiconductor layer 23 on a substrate using MOCVD technology.

[0093] Among them, one of the first semiconductor layer 21 and the second semiconductor layer 23 is an n-type layer, and the other of the first semiconductor layer 21 and the second semiconductor layer 23 is a p-type layer.

[0094] For example, the epitaxial layer 20 includes an n-type GaN layer, a multiple quantum well layer 22 and a p-type GaN layer stacked sequentially.

[0095] Optionally, the thickness of the n-type GaN layer can be from 0.5 μm to 3 μm.

[0096] The growth temperature of the n-type GaN layer can be from 1000℃ to 1100℃, and the growth pressure of the n-type GaN layer can be from 100 torr to 300 torr.

[0097] Optionally, the multi-quantum-well layer 22 includes alternating InGaN quantum well layers and GaN quantum barrier layers. Specifically, the multi-quantum-well layer 22 may include 3 to 8 alternating stacked InGaN quantum well layers and GaN quantum barrier layers.

[0098] When growing the multi-quantum-well layer 22, the MOCVD reaction chamber pressure was controlled at 200 torr. When growing the InGaN quantum well layer, the reaction chamber temperature was 760℃ to 780℃. When growing the GaN quantum barrier layer, the reaction chamber temperature was 860℃ to 890℃.

[0099] As an example, in an embodiment of this disclosure, the multi-quantum-well layer 22 includes five alternating periods of InGaN quantum-well layers and GaN quantum-barrier layers.

[0100] Optionally, the thickness of the multiple quantum well layer 22 can be from 150 nm to 200 nm.

[0101] Optionally, the thickness of the p-type GaN layer can be from 0.5 μm to 3 μm.

[0102] When growing p-type GaN layers, the growth pressure of p-type GaN layers can be from 200 Torr to 600 Torr, and the growth temperature of p-type GaN layers can be from 800℃ to 1000℃.

[0103] Step S13 may include the following steps:

[0104] The first step is to perform a first etching on the surface of the second semiconductor layer 23 to form a first trench that exposes at least the multi-quantum well layer 22.

[0105] Specifically, it may include: forming a mask on the surface of the second semiconductor layer 23 using photolithography, and then forming a first groove on the surface of the second semiconductor layer 23 using plasma etching.

[0106] During the etching process, the power of the etching equipment is controlled at 300W to 600W, and the lower power is controlled at 100W to 300W.

[0107] For example, when etching the first groove, the groove depth of the first groove is controlled to be 1 μm to 2 μm so that the first groove 30 exposes at least the multi-quantum well layer 22.

[0108] The second step is to perform a second etching on the bottom of the first tank to form a second tank that exposes the first semiconductor layer 21.

[0109] Specifically, this may include: forming a mask at the bottom of the first tank using photolithography, and then forming a second tank at the bottom of the first tank using plasma etching.

[0110] During the etching process, the power of the etching equipment is controlled at 200W to 300W, and the lower power is controlled at 50W to 150W.

[0111] For example, when etching the second trench, the distance between the trench wall of the first trench and the trench wall of the second trench is controlled to be 0.5 μm to 3 μm. At the same time, the trench depth of the second trench is controlled to be 0.6 μm to 1 μm to ensure that the first semiconductor layer 21 can be exposed in the second trench.

[0112] The above two steps involve two etching processes, and the second etching produces a smaller pattern than the first, thus forming a stepped groove 30.

[0113] The preparation method may further include the following steps after step S13:

[0114] The first step is to form a transparent conductive layer 41 on the surface of the second semiconductor layer 23 that is away from the first semiconductor layer 21.

[0115] For example, the transparent conductive layer 41 may be an indium tin oxide layer or an indium zinc oxide layer.

[0116] As an example, the thickness of the transparent conductive layer 41 can be from 1,000 angstroms to 5,000 angstroms. For example, the thickness of the transparent conductive layer 41 is 2,000 angstroms.

[0117] The second step is to form a passivation layer 42 on the surface of the transparent conductive layer 41 away from the substrate and in the groove 30.

[0118] Optionally, the passivation layer 42 includes at least one of a silicon oxide layer, a silicon nitride layer, and a titanium oxide layer.

[0119] For example, the passivation layer 42 may be a silicon oxide layer. The thickness of the silicon oxide layer may be 5000 angstroms.

[0120] The third step is to etch the passivation layer 42 to form through holes on the surface of the passivation layer 42 that expose the transparent conductive layer 41 and the groove 30, respectively.

[0121] Etching can be achieved through dry etching, or by combining photolithography with wet etching, such as etching with a mixed solution of H3PO4 / H2SO4, or by using laser front scribing.

[0122] The fourth step is to form an electrode 50 on the surface of the passivation layer 42 away from the substrate, and connect the electrode 50 to the transparent conductive layer 41 and the first semiconductor layer 21 in the groove 30 through through holes.

[0123] Specifically, this can include fabricating p-electrodes and n-electrodes using photolithography and evaporation methods.

[0124] The n-electrode is located in the groove 30 and is connected to the n-type layer through a through hole, while the p-electrode is connected to the transparent conductive layer 41 through a through hole.

[0125] Finally, the substrate was peeled off from the epitaxial layer 20 using laser lift-off, followed by stealth dicing, which effectively reduces brightness loss. The resulting light-emitting diode was then tested.

[0126] The above is not intended to limit this disclosure in any way. Although this disclosure has been disclosed above through embodiments, it is not intended to limit this disclosure. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this disclosure. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this disclosure without departing from the content of the technical solution of this disclosure shall still fall within the scope of the technical solution of this disclosure.

Claims

1. A light-emitting diode, characterized in that, The light-emitting diode includes an epitaxial layer (20), which includes a first semiconductor layer (21), a multi-quantum well layer (22), and a second semiconductor layer (23) stacked sequentially. The second semiconductor layer (23) has a groove (30) exposing the first semiconductor layer (21). The groove (30) exposing the groove wall of the multi-quantum well layer (22) includes at least one step. Each step includes a first wall surface (301), a step surface (302), and a second wall surface (303) connected sequentially in the direction from the second semiconductor layer (23) to the first semiconductor layer (21). The first wall surface (301) and the second wall surface (303) of adjacent steps are the same wall surface. At least one step surface (302) is located in the area where the sidewall of the multi-quantum well layer (22) is located.

2. The light-emitting diode according to claim 1, characterized in that, The angle between the first wall surface (301) and the step surface (302) is greater than or equal to 90 degrees, and the angle between the second wall surface (303) and the step surface (302) is greater than or equal to 90 degrees.

3. The light-emitting diode according to claim 1 or 2, characterized in that, The width (L1) of the stepped surface (302) is 0.5 μm to 3 μm.

4. The light-emitting diode according to claim 1 or 2, characterized in that, The length (L2) of the first wall (301) is 1 μm to 2 μm, and the length (L3) of the second wall (303) is 0.6 μm to 1 μm.

5. A display panel, characterized in that, The display panel includes a light-emitting functional layer and a driving backplane. The light-emitting functional layer is located on the driving backplane and is electrically connected to the driving backplane. The light-emitting functional layer includes a plurality of light-emitting diodes as described in any one of claims 1 to 4.

6. A method for fabricating a light-emitting diode, characterized in that, The preparation method includes: Provide a substrate; An epitaxial layer is formed on the substrate, wherein a first semiconductor layer, a multiple quantum well layer, and a second semiconductor layer are sequentially stacked on the epitaxial layer. The second semiconductor layer is etched to form a groove that exposes the first semiconductor layer. The groove that exposes the wall of the multi-quantum well layer includes at least one step. Each step includes a first wall surface, a step surface, and a second wall surface that are sequentially connected in the direction from the second semiconductor layer to the first semiconductor layer. At least one step surface is located in the region where the sidewall of the multi-quantum well layer is located.

7. The preparation method according to claim 6, characterized in that, Etching the second semiconductor layer to form a groove exposing the first semiconductor layer includes: A first etching is performed on the surface of the second semiconductor layer to form a first trench that exposes at least the multiple quantum well layer; A second etching is performed on the bottom of the first trench to form a second trench that exposes the first semiconductor layer.

8. The preparation method according to claim 7, characterized in that, The depth of the first tank is 1 μm to 2 μm, the distance between the tank wall of the first tank and the tank wall of the second tank is 0.5 μm to 3 μm, and the depth of the second tank is 0.6 μm to 1 μm.

9. The preparation method according to claim 7, characterized in that, During the first etching of the surface of the second semiconductor layer, the power of the etching equipment is controlled to be 300W to 600W, and the lower power is controlled to be 100W to 300W. During the second etching at the bottom of the first tank, the power of the etching equipment is controlled at 200W to 300W, and the lower power at 50W to 150W.

Images