A scalable power iteration algorithm based beamforming vector calculation circuit

Abstract

The application discloses a scalable beamforming vector calculation circuit based on power iteration algorithm. The beamforming vector calculation circuit comprises a matrix RAM, a controller and an operation unit. The matrix RAM is used for storing channel covariance matrix information, and according to the conjugate symmetry characteristic of the matrix, the overhead is reduced by nearly half. The controller is used for controlling the flow of data according to the size of the matrix, so as to realize the scalability of calculation. The operation unit is used for realizing the power iteration algorithm, and comprises matrix vector block multiplication, overflow detection and shift operations. The application can be applied to four sizes of channel covariance matrixes of 128*128, 256*256, 512*512 and 1024*1024, and can be applied to a large-scale millimeter wave MIMO communication system.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, specifically, it relates to a scalable beamforming vector calculation circuit based on a power iteration algorithm. Background Technology

[0002] In massive millimeter-wave multi-input multi-output (MIMO) communication systems, which are widely used in contemporary fifth-generation (5G) and future sixth-generation (6G) mobile communications, beamforming technology can concentrate the radiation or reception gain of the signal in the specific direction of the user, thereby achieving enhanced signal strength and coverage at the target location and improving system performance.

[0003] Beamforming can be implemented using different methods, mainly categorized into digital beamforming, analog beamforming, and hybrid beamforming. A key difference between these three types lies in the number of radio frequency (RF) chains. The RF chain is a crucial component connecting the antenna and the digital signal processor, including amplifiers, mixers, filters, and digital-to-analog / analog-to-digital converters. In digital beamforming systems, each antenna requires its own RF chain, while in massive MIMO systems, the number of antennas can reach hundreds or thousands, resulting in high RF chain overhead. Current research often focuses on analog beamforming, which requires only one RF chain, and hybrid beamforming, where the number of RF chains is less than the number of antennas.

[0004] Furthermore, millimeter-wave MIMO channels are sparse, meaning that only the direct-to-spot (LOS) path and a few first-order reflection paths have sufficient energy for transmission, while other reflection paths have too little energy for signal transmission. Therefore, when using millimeter-wave MIMO channels, only a small amount of data is transmitted simultaneously.

[0005] Given the limitations of the number of radio frequency chains and the sparsity of millimeter-wave channels, we consider a communication system that transmits only one data stream at a time. Y.-P. Lin's article, "Hybrid MIMO-OFDM Beamforming for Wideband mmWaveChannels Without Instantaneous Feedback," in IEEE Transactions on Signal Processing, vol. 66, no. 19, pp. 5142-5151, Oct. 1, 2018, proposes an optimal beamforming vector suitable for this communication system: the principal eigenvector of the channel covariance matrix (the eigenvector corresponding to the eigenvalue with the largest amplitude). Traditional hardware methods for calculating eigenvectors include QR decomposition and the Jacobi method, but these methods calculate all eigenvectors of the matrix at once, resulting in hardware waste. Summary of the Invention

[0006] To address the shortcomings of the existing technologies, the present invention aims to provide a scalable beamforming vector calculation circuit based on a power-law iterative algorithm. The present invention considers a communication system that transmits only one data stream at a time, and the beamforming method only requires the principal eigenvector. Therefore, the present invention employs a power-law iterative algorithm that only calculates the principal eigenvector to reduce hardware overhead. The present invention is applicable to channel covariance matrices of four sizes: 128×128, 256×256, 512×512, and 1024×1024, meeting the performance requirements of current large-scale millimeter-wave MIMO communication systems in terms of delay, energy consumption, and accuracy.

[0007] The technical solution of the present invention is described in detail below.

[0008] This invention provides a scalable beamforming vector calculation circuit based on a power-law iteration algorithm, comprising a matrix random access memory (RAM), a controller, and a computation unit; wherein:

[0009] The matrix RAM is used to store information about the diagonal of the channel covariance matrix and the 2×2 matrix blocks above it; the matrix RAM has four blocks, which respectively store the positions of the four elements in the upper left, upper right, lower left and lower right of each matrix block;

[0010] The controller is used to control the flow of data according to the size of the matrix to achieve scalability of the computation. The controller includes an s counter for storing the number of columns of the currently processed matrix block, an r counter for storing the number of rows of the currently processed matrix block, and an address control bit generator. The address control bit generator generates a RAM read address and a control bit cb for determining whether the matrix to be read is stored in RAM, so that after the matrix block is read out, its data can be subjected to conjugate symmetric transformation.

[0011] The arithmetic unit implements a power-law iterative algorithm that includes block multiplication of matrix and vector, overflow detection, and shift operations. Assuming the channel covariance matrix is ​​Σ, the power-law iterative algorithm first randomly initializes the vector v. 0 In the k-th iteration, matrix-vector multiplication is used.

[0012]

[0013] and shift

[0014]

[0015] It consists of two steps, where β k It is the number of shift bits set to prevent overflow. Given a product vector, after several iterations, the resulting vector v is... k Approximate the principal eigenvectors of Σ;

[0016] Matrix-vector multiplication is performed by multiplying a block matrix by a block vector. Assuming the matrix size is N×N, it is divided into n×n 2×2 matrix blocks, where n = N / 2. Correspondingly, the vectors are divided into n 2×1 vector blocks. For the matrix block at position (r, s), the completed block matrix-vector multiplication operation is...

[0017]

[0018] Where Σ x,y It is the element at position (x,y) of Σ, v x It is v k The xth element, yes The xth element The sum of the s-th part, i.e.

[0019]

[0020] In this invention, the address control bit generator reads the RAM read address addr of the matrix block at position (r,s). r,s From the recursive formula

[0021] addr r,0 =r (5)

[0022] and

[0023]

[0024] produce;

[0025] The formula for generating the control bit cb is:

[0026]

[0027] If the control bit is 1, then based on the conjugate symmetry property of the channel covariance matrix, the upper right and lower left elements of the read matrix block are interchanged, and the conjugate of each element is taken as the element of the read matrix block.

[0028] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0029] This invention utilizes a power-law iteration algorithm to perform block multiplication iterative calculations on the channel covariance matrix and vectors. This directly yields the principal eigenvectors of the channel covariance matrix, rather than all eigenvectors, enabling beamforming and significantly reducing hardware overhead. Furthermore, leveraging the conjugate symmetry of the channel covariance matrix, this invention stores only about half of the matrix data in RAM, greatly reducing RAM area. Additionally, this invention improves the normalization operation in each iteration of the traditional power-law iteration algorithm by replacing it with a hardware-friendly shift operation, significantly reducing hardware complexity. Attached Figure Description

[0030] Figure 1 This is a diagram showing the relationship between RAM addresses and matrix block positions in the hardware of this invention.

[0031] Figure 2 This is a hardware overall structure diagram of the present invention.

[0032] Figure 3 This is a structural diagram of the hardware of the present invention for generating RAM read addresses and control bits.

[0033] Figure 4 This is a structural diagram of the block matrix-vector multiplication operation implemented in the hardware of this invention.

[0034] Figure 5 This is a structural diagram of the hardware of the present invention for calculating the real part (or imaginary part) of the sum of the products of two pairs of complex numbers.

[0035] Figure 6 This is a structural diagram of the overflow detection module in the hardware of this invention.

[0036] Figure 7 This is a structural diagram of the hardware of the present invention, which determines the number of shift bits based on the vector protection bit data. Detailed Implementation

[0037] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0038] This invention proposes a scalable beamforming vector calculation circuit based on a power-law iteration algorithm. The hardware implementation circuit includes a matrix random access memory (RAM), a controller, and an arithmetic unit. The matrix RAM stores channel covariance matrix information. The controller controls data flow according to the matrix size, achieving scalability of the computation. The arithmetic unit implements the power-law iteration algorithm, including matrix-vector block multiplication, overflow detection, and shifting operations.

[0039] Assume the channel covariance matrix is ​​Σ. In the power iteration algorithm used in this invention, the initial vector v is first randomly selected. 0 In the k-th iteration, matrix-vector multiplication is used.

[0040]

[0041] and shift

[0042]

[0043] It consists of two steps, where β k This is the number of shift bits set to prevent overflow. After several iterations, v k This will approximate the principal eigenvectors of Σ.

[0044] This invention employs a method of multiplying block matrices and block vectors to perform matrix-vector multiplication. Assuming the matrix size is N×N, it can be divided into n×n 2×2 matrix blocks, where n = N / 2. Correspondingly, the vector can be divided into n 2×1 vector blocks. For the matrix block at position (r, s), the completed block matrix-vector multiplication operation is:

[0045]

[0046] Where Σ x,y It is the element at position (x,y) of Σ, v x It is v k The xth element, yes The xth element The sum of the s-th part, i.e.

[0047]

[0048] To reduce RAM area, the RAM of this invention only stores the matrix blocks along the diagonal and above it, such as... Figure 1The gray matrix blocks are shown below. This invention uses four RAMs to store the positions of the top-left, top-right, bottom-left, and bottom-right elements in each matrix block. During matrix-vector multiplication, the four RAMs share the same read address, and the corresponding matrix blocks are read in the following order: Figure 1 As indicated by the dashed arrow in the diagram. Reading the white matrix block is actually reading its relation to... Figure 1 The matrix consists of gray matrix blocks that are symmetric along its main diagonal, and white matrix blocks are constructed by converting the data into conjugate symmetric blocks.

[0049] Read the RAM read address addr of the matrix block at position (r,s). r,s It can be derived from the recursive formula

[0050] addr r,0 =r (5)

[0051] and

[0052]

[0053] produce.

[0054] Furthermore, the circuit of this invention also generates a control bit cb to determine whether the matrix to be read is stored in RAM, so that after the matrix block is read out, its data can be subjected to a conjugate symmetric transformation. The formula for generating the control bit is as follows:

[0055]

[0056] Since matrix-vector multiplication operations can cause overflow, this invention addresses the issue of product vectors. Set p = log2N+1 guard bits. The data structure of this vector is: b p+q b p-1+q …b 1+q |b q b q-1 …b1, where the bits to the left of the vertical line are p-bit protection bits and the bits to the right of the vertical line are q-bit data bits.

[0057] To prevent overflow, the entire vector should be shifted to the right. For each element in the array, all guard bits of all elements are removed, hence the shift number β k with vector The guard bit data b of all elements in p+q b p-1+q …b 1+q The maximum value is related to the value, as shown in Table 1. Since the shift operation can be directly performed by the shift register, this operation is used in this invention instead of the normalization operation that requires a large number of multiplication and division operations in the traditional power iteration algorithm, in order to reduce hardware complexity.

[0058] Table 1: Protection bit data b p+q b p-1+q …b 1+q With shift number β k Relationship

[0059] 1xx…xx p+1 01x…xx p 001…xx p-1 … … 000…1x 2 000…01 1 000…00 0

[0060] like Figure 2 As shown, a scalable beamforming vector calculation circuit based on a power-law iteration algorithm is presented. The hardware implementation circuit of this invention includes a matrix RAM, a controller, and a computation unit.

[0061] The matrix RAM consists of four RAM blocks, namely RAM0, RAM1, RAM2 and RAM3, which store the positions of the four elements in the upper left, upper right, lower left and lower right of each matrix block, respectively.

[0062] The controller consists of modules such as an s-counter, an r-counter, and an address control bit generator, which are used to control the flow of data according to the size of the matrix to achieve scalability of computation. The s-counter and r-counter store the number of columns and rows of the currently processed matrix block, respectively, i.e., s and r in formulas (5) and (6).

[0063] The arithmetic unit consists of modules such as a vector register, a 2×2 multiplier, an accumulator, a first-in-first-out (FIFO) buffer, overflow detection, and shift update. It is used to implement the power iteration algorithm, including matrix-vector block multiplication, overflow detection, and shift operations.

[0064] In the exponentiation operation, the circuit of this invention performs the following operations:

[0065] The address control bit generator generates the RAM read address and control bits according to formulas (5) and (6), and its structure is as follows: Figure 3 As shown. If the control bit is 1, it indicates that the matrix block being read is... Figure 1 The white matrix block in the code needs to be read by swapping the top-right and bottom-left elements of the read matrix block based on the conjugate symmetry of the channel covariance matrix, and then taking the conjugate of each element as the element of the read matrix block. Additionally, the corresponding vector block in the vector register is read using the s-counter.

[0066] For a single-layer block matrix-vector multiplication operation, matrix blocks are read sequentially from left to right. The matrix blocks and vector blocks are multiplied in a 2×2 multiplier, and the resulting partial multiplication and product vector are accumulated in an accumulator to obtain the product vector result for this layer, i.e., the operations in formulas (3) and (4). The hardware structure for completing a single-layer block matrix-vector multiplication operation is as follows: Figure 4 As shown, the multiply-accumulate module is as follows: Figure 5As shown, the system consists of four pipelined real multipliers, two subtractors (or adders), and one adder. It can calculate the real (or imaginary) part of the sum of the product of complex numbers a and b and the product of complex numbers c and d. In the diagram, the superscript R represents the real part of the complex number, and the superscript I represents the imaginary part. The accumulator accumulates and serially outputs four data streams: the real and imaginary parts of the first element and the real and imaginary parts of the second element of the 2×1 product vector block in this layer.

[0067] After the block matrix-vector multiplication operation of one layer is completed, the data of the next layer is read and the operation is performed until the multiplication operation of all layers is completed. The four output results of the accumulator, that is, the real part and imaginary part of the two elements of the corresponding product vector block, are stored in FIFO.

[0068] During each block matrix-vector multiplication operation completed at each layer, the protection bits of the real and imaginary parts of the two elements of the product vector are input into the overflow detection module. The structure of this module is as follows: Figure 6 As shown. Four data streams are input serially n times. During each input, the four β values ​​in the overflow detection module... k The generator produces the corresponding shift bits according to Table 1. The structure of the generator is as follows: Figure 7 As shown, this is achieved through the cascading of multiplexers. The four shifted bits are used to find the maximum value among three maximum value generators, and then compared with... Figure 6 Compared to the number of shift bits stored in the register shown, if the difference is... Figure 6 The value in the register shown is large, meaning it is stored in the register. Thus, after n serial inputs, the resulting shift bit is the shift bit corresponding to the element with the largest guard bit in the product vector, ensuring that no data overflow occurs after the shift.

[0069] The number of bits to be shifted is input into the shift update module. The real and imaginary parts of the elements of the product vector stored in the FIFO are serially input into the shift update module, all of which are shifted right by the same number of bits and stored back into the vector register.

[0070] The above operation completes one iteration. By repeating the above operation multiple times, the vector output by the shift update module will approximate the principal eigenvector of the channel covariance matrix stored in the matrix RAM.

[0071] The above embodiments are merely preferred embodiments of the present invention. It should be noted that, for those skilled in the art, various improvements can be made based on the technical concept of the present invention, and these improvements also fall within the protection scope of the present invention.

Claims

1. A scalable beamforming vector calculation circuit based on a power-law iteration algorithm, characterized in that, It includes a matrix random access memory (RAM), a controller, and an arithmetic unit; wherein: The matrix RAM is used to store information about the diagonal of the channel covariance matrix and the 2×2 matrix blocks above it; the matrix RAM has four blocks, which respectively store the positions of the four elements in the upper left, upper right, lower left and lower right of each matrix block; The controller is used to control the flow of data according to the matrix size, thereby achieving scalability of computation. The controller includes an S-counter for storing the column number of the currently processed matrix block, an R-counter for storing the row number of the currently processed matrix block, and an address control bit generator. The address control bit generator generates the RAM read address and controls whether the matrix to be read is stored in RAM. This is to facilitate the conjugate symmetric transformation of the data after the matrix block is read out; The arithmetic unit implements a power-law iterative algorithm that includes block multiplication of matrix and vectors, overflow detection, and shift operations; assuming the channel covariance matrix is... In the power iteration algorithm, the initial vector is first randomly selected. , No. In the next iteration, matrix-vector multiplication is used. （1） and shift （2） It consists of two steps, in which It is the number of shift bits set to prevent overflow. Given a product vector, the result vector obtained after several iterations is... Approaching The main eigenvectors; Matrix-vector multiplication is performed by multiplying a block matrix by a block vector; assuming the size of the matrix is... Divide it into There are 2×2 matrix blocks, where Accordingly, vectors are divided into A 2×1 vector block; for The block matrix-vector multiplication operation performed on the matrix block at the given position is: （3） in yes exist Elements at position, yes The One element, yes The element The The sum of the parts, i.e. （4）。 2. The scalable beamforming vector calculation circuit based on the power iteration algorithm according to claim 1, characterized in that, Address control bit generator reads RAM read address of the matrix block at the specified location From the recursive formula （5） and （6） produce; control bit The generating formula is （7） If the control bit is 1, then based on the conjugate symmetry property of the channel covariance matrix, the upper right and lower left elements of the read matrix block are interchanged, and the conjugate of each element is taken as the element of the read matrix block.

3. The scalable beamforming vector calculation circuit based on the power iteration algorithm according to claim 1, characterized in that, The arithmetic unit includes a vector register, a 2×2 multiplier, an accumulator, a first-in-first-out (FIFO) buffer, an overflow detection module, and a shift update module. The steps for implementing the exponentiation algorithm in the arithmetic unit are as follows: For a block matrix-vector multiplication operation at a given layer, matrix blocks are read sequentially from left to right. The matrix block and vector block are multiplied in a 2×2 multiplier. The resulting partial multiplication and the product vector are accumulated in an accumulator to obtain the product vector result for this layer. The accumulator accumulates and serially outputs four data streams, which are the real and imaginary parts of the first and second elements of the 2×1 product vector block at this layer. After the block matrix-vector multiplication operation at one layer is completed, the data of the next layer is read and the operation is performed until the multiplication operation at all layers is completed. The four output results of the accumulator, i.e., the real and imaginary parts of the two elements of the corresponding product vector block, are stored in a FIFO. During each block matrix-vector multiplication operation completed at each layer, the protection bits for the real and imaginary parts of the two elements of the product vector are input to the overflow detection module. Each time this is input, the four protection bits in the overflow detection module... The generator produces the corresponding number of shift bits. The resulting 4 shift bits The maximum value is found using three maximum value generators and compared with the number of shift bits stored in the register. If the maximum value is larger than the value in the register, it is stored there. After the serial input, the number of shift bits obtained is the number of shift bits corresponding to the element with the largest guard bit in the product vector, which ensures that no data overflow will occur after the shift. Afterwards, the shifted bits are input into the shift update module. The real and imaginary parts of the elements of the product vector stored in the FIFO are serially input into the shift update module, all shifted right by the same number of bits, and stored back into the vector register. The above operation completes one iteration; by repeating the above operation multiple times, the vector output by the shift update module approximates the principal eigenvector of the channel covariance matrix stored in the matrix RAM.

4. The scalable beamforming vector calculation circuit based on the power iteration algorithm according to claim 3, characterized in that, The multiply-add module in a 2×2 multiplier consists of four pipelined real number multipliers, two subtractors or adders, and one adder.

5. The scalable beamforming vector calculation circuit based on the power iteration algorithm according to claim 3, characterized in that, The generator is implemented by cascading multiplexers.

6. The scalable beamforming vector calculation circuit based on the power iteration algorithm according to claim 3, characterized in that, For product vectors ,set up Bit protection bits, the data structure of this vector is as follows: The one to the left of the vertical line is The protection bit is to the right of the vertical line. Bit data bits; Protect bit data With shift number of bits The relationship between them is as follows: the data is 000…00, The value is 0; the data is 000…01. The value is 1; the data is 000…1x. The first number is 2, and so on, with the data being 001…xx. for -1; the data is 01x…xx. for The data is 1xx…xx. for +1.

7. The scalable beamforming vector calculation circuit based on the power iteration algorithm according to claim 1, characterized in that, It is applicable to four channel covariance matrix sizes: 128×128, 256×256, 512×512, and 1024×1024.

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