Channel estimation accelerator and inference method of channel estimation model

Abstract

The application provides a channel estimation accelerator, which comprises a total controller, an on-chip cache and a calculation engine, wherein the total controller is used for generating the corresponding address of the on-chip cache and the configuration of the calculation operation in the calculation engine based on a channel estimation instruction; the on-chip cache is used for caching the pilot signal, the weight of all network layers in the channel estimation model and the input and output data of each network layer in the channel estimation model and the intermediate result generated by the irregular connection between the network layers based on the corresponding address thereof; the calculation engine comprises a least square calculation module and a processing module, and the channel estimation result is obtained based on the pilot signal by using the least square calculation module and the processing module. The accelerator designed in the application can efficiently realize the inference of the channel estimation model corresponding to the instruction and the memory access operation of the data by using different channel estimation instructions, and meanwhile, the hardware execution efficiency of the channel estimation model is improved and the inference delay is reduced.

Description

Technical Field

[0001] This invention relates to the field of wireless communication, specifically to a hardware accelerator for a channel estimation model based on machine learning in the field of wireless communication, and more specifically to a channel estimation accelerator and a reasoning method for the channel estimation model. Background Technology

[0002] In wireless communication environments, signals transmitted by the transmitter are distorted by fading and noise, necessitating channel estimation by the receiver. Channel estimation aids subsequent operations such as equalization, demodulation, and decoding, and its accuracy directly impacts the performance of the communication system. Meanwhile, Artificial Intelligence (AI) has demonstrated outstanding performance in many fields, such as computer vision, natural language processing, and gaming. In wireless communication, AI has also received widespread attention, with researchers applying Deep Learning (DL) to problems like channel estimation, signal detection, channel decoding, and modulation pattern recognition, hoping to achieve better performance and latency compared to traditional methods.

[0003] In terms of channel estimation, researchers have combined deep learning to obtain the following channel estimation models: (1) FC-DNN, which is a channel estimation model that combines deep neural network (DNN) for channel estimation and signal detection. It adopts data-driven, offline training and online deployment to realize channel estimation. Related simulation experiments show that the channel estimation model can effectively cope with signal distortion and interference; (2) ComNet, which adopts the idea of ​​model-driven, introduces professional knowledge in the field of communication in the structural design of deep neural network, and uses DNN to assist the original modules in OFDM receiver. It uses the result of least squares (LS) as the initial data of the network, which enhances the performance and interpretability of the channel estimation model and significantly reduces the complexity of the channel estimation model. However, the use of offline data for training leads to a mismatch between the training data and the actual data, resulting in a performance degradation of the two channel estimation models when deployed online. To address this issue, researchers have proposed a new channel estimation model called SwitchNet. This model is a channel estimation model that configures multiple training models in different channel environments by selecting relevant parameters through online learning. It can achieve compatibility with multiple channel environments, thereby solving the problem of performance degradation caused by the mismatch between training data and actual data.

[0004] Meanwhile, inspired by research in image denoising and super-resolution in machine vision, new channel estimation models continue to emerge. For example, ChannelNet treats the LS channel estimation matrix at the pilot as a noisy, low-resolution image, and the complete channel estimation matrix as a noise-free, high-resolution image. It completes the channel estimation task by directly cascading an image super-resolution neural network model and an image denoising neural network model, achieving good performance. However, there are certain differences between channel estimation and image processing problems. Neural network models in machine vision are not designed specifically for channel estimation tasks, and directly applying neural network models from the corresponding field to channel estimation does not yield optimal performance. Therefore, related research has improved ChannelNet to address the characteristics of wireless channels. For example, ReEsNet introduces residual learning and compresses the model size on the basis of ChannelNet; ICINet introduces a preprocessing network on the basis of ChannelNet to deal with inter-channel interference (ICI); Interpolation-ResNet introduces bilinear interpolation on the basis of ChannelNet to be compatible with multiple pilot modes; RRDBNet introduces dense connections on the basis of ChannelNet to increase the capacity of the channel estimation model and improve the training efficiency of the model; and channel estimation models such as AttRNet, HA02, and Channelformer introduce attention mechanisms on the basis of ChannelNet to enhance the adaptive ability of the channel estimation model.

[0005] Although researchers have proposed various channel estimation models, most of these models are still at the algorithm design level, lacking corresponding accelerator designs. This makes it difficult to deploy and test these channel estimation models in real-world environments. Furthermore, while many mature deep learning accelerators exist, they are mostly geared towards fields such as machine vision or natural language processing, and cannot directly support or are inefficient for dedicated channel estimation models with communication expertise modules or complex connection structures. Summary of the Invention

[0006] Therefore, the purpose of this invention is to overcome the shortcomings of the prior art and provide a channel estimation accelerator and a reasoning method for a channel estimation model.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] According to a first aspect of the present invention, a channel estimation accelerator is provided, the channel estimation accelerator being used to obtain channel estimation results based on pilot signals, channel estimation instructions, and a channel estimation model, characterized in that the channel estimation accelerator comprises: a central controller, an on-chip cache, and a computing engine, wherein the central controller is used to generate an address corresponding to the on-chip cache based on the channel estimation instructions and to configure computing operations in the computing engine, wherein the computing operations include: least squares operation, convolution operation, matrix element-wise addition operation, transpose convolution operation, and attention operation; the on-chip cache is used to cache the pilot signals, the weights of all network layers in the channel estimation model, and each network layer in the channel estimation model based on its corresponding address. The computation engine includes a least squares calculation module and a processing module. The least squares calculation module performs least squares operations on the pilot signals cached in the on-chip buffer to obtain the channel estimation matrix at the pilot. The processing module performs convolution, element-wise addition, transpose convolution, and attention operations on the channel estimation matrix at the pilot based on the weights of all network layers in the channel estimation model to obtain the input and output data of each network layer in the channel estimation model and the intermediate results generated by the irregular connections between network layers, and feeds them back to the on-chip buffer. The output data of the last network layer in the channel estimation model is the channel estimation result.

[0009] In some embodiments of the present invention, the overall controller includes: an instruction cache module for caching the channel estimation instruction; and a finite state machine module for generating the address corresponding to the on-chip cache and configuring the computational operations in the computing engine based on the channel estimation instruction cached by the instruction cache module.

[0010] In some embodiments of the present invention, the on-chip cache includes: a data cache module for caching pilot signals, input and output data of each network layer in the channel estimation model, and intermediate results generated by irregular connections between network layers; and a weight cache module for caching the weights of all network layers in the channel estimation model.

[0011] In some embodiments of the present invention, the data caching module includes: a data caching unit for caching pilot signals and input / output data of each network layer in the channel estimation model; and an intermediate result caching unit for caching intermediate results generated by irregular connections between network layers in the channel estimation model.

[0012] In some embodiments of the present invention, the data caching unit includes: a first data sub-caching unit and a second data sub-caching unit, used to cache the input and output data of the corresponding network layer in the channel estimation model, respectively. The first data sub-caching unit is also used to cache pilot signals. The first data sub-caching unit and the second data sub-caching unit are configured to cache the input or output data of the corresponding network layer in the channel estimation model in the following manner: when performing a corresponding operation on the input data of a network layer in the channel estimation model to obtain the output data of that network layer, one data sub-caching unit is used to cache the output data of that network layer as the input data of the next network layer, and the other data sub-caching unit is used to cache the output data of the next network layer.

[0013] In some embodiments of the present invention, the intermediate results generated by irregular connections between network layers include: intermediate results generated by irregular connections between multiple fixed structures composed of network layers of a preset number in the channel estimation model, and intermediate results generated by irregular connections between network layers in the fixed structure composed of network layers of a preset number. The intermediate result caching unit includes: a first intermediate result sub-caching unit for caching intermediate results generated by irregular connections between network layers in the fixed structure composed of network layers of a preset number in the channel estimation model; and a second intermediate result sub-caching unit for caching intermediate results generated by irregular connections between multiple fixed structures composed of network layers of a preset number in the channel estimation model.

[0014] In some embodiments of the present invention, the computation operation further includes a bilinear interpolation operation, and the computation engine further includes a bilinear interpolation computation module; wherein, the processing module is configured to perform convolution operation, matrix element-wise addition operation, and attention operation on the channel estimation matrix at the pilot based on the weights of all network layers in the channel estimation model and give the result to the bilinear interpolation computation module, and to perform a preset number of convolution operations on the result obtained by the bilinear interpolation computation module to obtain the input and output data of each network layer in the channel estimation model and the intermediate results generated by the irregular connections between each network layer and feed them back to the on-chip buffer; the bilinear interpolation computation module is used to perform bilinear interpolation operation on the received data and give the result to the processing module.

[0015] In some embodiments of the present invention, the processing module includes: a plurality of convolution execution units, a plurality of matrix element-wise addition execution units, a plurality of attention execution units, and a transposed convolution execution unit connected in series according to a preset serial structure, wherein each execution unit is used to perform a corresponding operation.

[0016] In some embodiments of the present invention, the processing module is configured to: select the corresponding execution unit to perform the corresponding operation based on the channel estimation instruction.

[0017] According to a second aspect of the present invention, a reasoning method for a channel estimation model is provided, the method comprising: acquiring a pilot signal, a channel estimation command, and a channel estimation model; and obtaining a channel estimation result based on the pilot channel, the channel estimation command, and the channel estimation model using the accelerator described in the above embodiments.

[0018] According to a third aspect of the present invention, an electronic device is provided, comprising: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the electronic device to perform the steps of the method described in the second aspect.

[0019] Compared with the prior art, the advantages of the present invention are as follows:

[0020] The channel estimation accelerator proposed in the above embodiments of the present invention can efficiently realize the inference of the channel estimation model and the memory access operation of the data corresponding to the instruction through different channel estimation instruction configurations, while improving the hardware execution efficiency of the channel estimation model and reducing inference latency. Attached Figure Description

[0021] The embodiments of the present invention will be further described below with reference to the accompanying drawings, wherein:

[0022] Figure 1 This is a schematic diagram of the execution logic framework of the channel estimation accelerator according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of an existing technology accelerator framework;

[0024] Figure 3 This is a schematic diagram of a channel estimation accelerator structure according to an embodiment of the present invention;

[0025] Figure 4 This is a schematic diagram of the execution logic framework of the ReEsNet data flow layer under the accelerator according to an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention is further described in detail below through specific embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0027] As mentioned in the background section, researchers have proposed various channel estimation models, but most of these models are still at the algorithm design level and lack corresponding accelerator designs, making it difficult to deploy and test these channel estimation models in real-world environments. Furthermore, although many mature deep learning accelerators exist, they are mostly geared towards fields such as machine vision or natural language processing, and cannot directly support or are inefficient for dedicated channel estimation models with communication expertise modules or complex connection structures.

[0028] While conducting research on wireless communication channel estimation, the inventors discovered that although existing research indicates that deep learning-based channel estimation models possess advantages such as robustness and high performance, effectively improving the quality of channel estimation without using prior channel information, the methods employed in current wireless communication devices still predominate. This is because deep learning-based channel estimation models are generally complex in structure, computationally intensive, and lack corresponding acceleration hardware, making it difficult to deploy and apply existing channel estimation models in current mobile devices.

[0029] To address this issue, the inventors, through research on existing channel estimation models and hardware accelerators, discovered that designing dedicated hardware accelerators for these models can solve the problem of their complexity and high computational cost, making them difficult to deploy on current mobile devices. Several new deep learning-based channel estimation models have introduced specific algorithmic structures. For example, ReEsNet uses residual learning to improve learning efficiency and avoid the vanishing gradient problem; Interpolation-ResNet uses bilinear interpolation to be compatible with multiple pilot modes; RRDBNet uses dense connections to increase network capacity and improve training efficiency; and AttRNet uses an attention mechanism to enhance the network's adaptability. The inventors, by summarizing the uniformity of the basic operators and connection structures in these deep learning-based channel estimation models and adding corresponding configuration instructions (i.e., channel estimation instructions), have obtained a... Figure 1 The diagram illustrates the execution logic framework of a unified hardware accelerator supporting multiple channel estimation models. This framework can be configured with corresponding channel estimation instructions to be compatible with various channel estimation models, and also supports further algorithm updates and extensions. Building upon this framework, to further support the efficient execution of the hardware accelerator logic framework, the inventors designed a novel dedicated hardware accelerator for channel estimation. This accelerator can efficiently implement channel estimation model inference and memory access operations during the inference process by configuring corresponding channel estimation instructions.

[0030] Before describing the embodiments of the present invention in detail, some of the terms used therein are explained as follows:

[0031] The channel estimation instruction can uniquely characterize the structure of each network layer in the channel estimation model. It contains all the hyperparameters of each network layer in the channel estimation model. For example, for a convolutional layer, these hyperparameters will include the size of the convolutional kernel, the size of the feature map, the size of the padding stride, and the types of activation functions to be fused, etc.

[0032] Pilot signals are specific signals used for synchronization and frequency calibration. They are typically transmitted periodically by the transmitter and used by the receiver to identify and track the transmission characteristics of the signal to ensure correct data reception and demodulation. Pilot signals play a crucial role in wireless communication systems, helping to solve problems such as multipath propagation, frequency offset, and clock drift, thereby improving the performance and reliability of the communication system.

[0033] The present invention will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0034] To better understand how the accelerator designed in this invention can be applied to the operation of channel estimation models in the field of wireless communication, we will first introduce the accelerator structures designed for fields such as machine vision or natural language processing in the prior art. Figure 2 As shown, this is a prior art accelerator structure, which includes a main controller, on-chip cache, and a computing engine, wherein the computing engine includes a processing module. As can be seen from the above structure, prior art accelerators do not have modules corresponding to communication domain expertise, causing them to be unable to support the operation of dedicated channel estimation models with communication expertise modules or complex connection structures.

[0035] Therefore, according to one embodiment of the present invention, such as Figure 3As shown, this invention proposes a channel estimation accelerator. The channel estimation accelerator is used to obtain channel estimation results based on pilot signals, channel estimation instructions, and a channel estimation model. The channel estimation accelerator includes a central controller, an on-chip cache, and a computing engine. The central controller is used to generate the address corresponding to the on-chip cache based on the channel estimation instructions and configure the computational operations in the computing engine. The computational operations include least squares operations, convolution operations, element-wise matrix addition operations, transpose convolution operations, and attention operations. The on-chip cache is used to cache the pilot signals, the weights of all network layers in the channel estimation model, and the input / output of each network layer in the channel estimation model based on its corresponding address. The computation engine includes a least squares calculation module and a processing module. The least squares calculation module performs least squares operations on the pilot signals cached in the on-chip buffer to obtain the channel estimation matrix at the pilot. The processing module performs convolution, element-wise addition, transpose convolution, and attention operations on the channel estimation matrix at the pilot based on the weights of all network layers in the channel estimation model to obtain the input and output data of each network layer in the channel estimation model and the intermediate results generated by the irregular connections between network layers, and feeds them back to the on-chip buffer. The output data of the last network layer in the channel estimation model is the channel estimation result.

[0036] As can be seen from the above embodiments, the present invention processes the pilot signal by designing a corresponding least squares calculation module equipped with communication expert knowledge in the accelerator, thereby forming a channel estimation accelerator that can support the operation of a dedicated channel estimation model with communication expert knowledge modules or complex connection structures.

[0037] To understand in more detail the execution process of the pilot signal in the channel estimation accelerator designed in this invention, the composition structure of the main controller, on-chip cache, and computing engine is described in detail below.

[0038] (1) Main controller

[0039] According to one embodiment of the present invention, still referring to Figure 3 ,from Figure 3 As can be seen from the diagram, the overall controller includes: an instruction cache module for caching the channel estimation instructions; and a finite state machine module for generating the address corresponding to the on-chip cache and configuring the computational operations in the computing engine based on the channel estimation instructions cached by the instruction cache module. The finite state machine can synchronize its state with the main processor to ensure that the accelerator is in the correct state when executing a specific computational task.

[0040] (2) On-chip cache

[0041] The inventors discovered through research that the on-chip cache of accelerators in the existing technology cannot solve the problem of data access and mapping during the operation of channel estimation models with complex structures.

[0042] Therefore, according to one embodiment of the present invention, reference is still made to... Figure 3 ,from Figure 3 As can be seen from the diagram, the on-chip cache includes: a data cache module, used to cache pilot signals, input and output data of each network layer in the channel estimation model, and intermediate results generated by irregular connections between network layers; and a weight cache module, used to cache the weights of all network layers in the channel estimation model. The composition and structure of the data cache module are described in detail below.

[0043] According to one embodiment of the present invention, the data caching module includes: a data caching unit for caching pilot signals and input / output data of each network layer in the channel estimation model; and an intermediate result caching unit for caching intermediate results generated by irregular connections between network layers in the channel estimation model. According to one embodiment of the present invention, the data caching unit includes: a first data sub-caching unit and a second data sub-caching unit for caching input / output data of corresponding network layers in the channel estimation model, respectively. The first data sub-caching unit is also used to cache pilot signals. The first and second data sub-caching units are configured to cache input or output data of corresponding network layers in the channel estimation model in the following manner: when performing a corresponding operation on the input data of a network layer in the channel estimation model to obtain the output data of that network layer, one data sub-caching unit is used to cache the output data of that network layer as input data for the next network layer, and the other data sub-caching unit is used to cache the output data of the next network layer. According to an embodiment of the present invention, the intermediate results generated by irregular connections between network layers include: intermediate results generated by irregular connections between multiple fixed structures composed of network layers of a preset number in the channel estimation model, and intermediate results generated by irregular connections between network layers in the fixed structure composed of network layers of a preset number. The intermediate result caching unit includes: a first intermediate result sub-caching unit for caching intermediate results generated by irregular connections between network layers in the fixed structure composed of network layers of a preset number in the channel estimation model; and a second intermediate result sub-caching unit for caching intermediate results generated by irregular connections between multiple fixed structures composed of network layers of a preset number in the channel estimation model.

[0044] As can be seen from the above embodiments, the present invention uses a group caching mechanism to cache the large amount of data generated by the channel estimation model during its operation in the accelerator, thereby solving the data access and mapping of the complex channel estimation model. At the same time, it can improve the data access efficiency and thus improve the inference efficiency of the channel estimation model.

[0045] (3) Computing Engine

[0046] Currently, research on deep learning accelerators for wireless communication applications is limited. Existing research on deep learning-based channel estimation accelerator design introduces a framework for generating target hardware description language (HDL) code and evaluates the resources and time required to implement the channel estimation model (i.e., the convolutional neural network used for channel estimation) in FPGA. Furthermore, it analyzes the quantization performance of the channel estimation model from design to hardware implementation. While existing technologies have addressed channel estimation accelerators, they primarily focus on the quantization portion of the channel estimation model and use relatively simple model structures. Hardware design mainly relies on Matlab tools for generation and is primarily targeted at a specific channel estimation model. However, new channel estimation models are increasingly complex, with diverse design structures and rapid iteration. The complexity of channel estimation models generated using this approach is limited, and hardware accelerators designed for a specific channel estimation model struggle to support the operation of different channel estimation models and the upgrading and iteration of new algorithms.

[0047] Therefore, according to one embodiment of the present invention, reference is still made to... Figure 3 ,from Figure 3 As can be seen, the computational operation further includes bilinear interpolation, and the computational engine further includes a bilinear interpolation computation module. The processing module is configured to perform convolution, element-wise addition, and attention operations on the channel estimation matrix at the pilot based on the weights of all network layers in the channel estimation model, and provide the results to the bilinear interpolation computation module. It also performs a preset number of convolution operations on the results obtained by the bilinear interpolation computation module to obtain the input and output data of each network layer in the channel estimation model and intermediate results generated by irregular connections between network layers, and feeds them back to the on-chip buffer. The bilinear interpolation computation module is used to perform bilinear interpolation on the received data and provide the results to the processing module. According to one embodiment of the present invention, the processing module includes: multiple convolution execution units, multiple element-wise addition execution units, multiple attention execution units, and a transposed convolution execution unit connected in a preset serial structure, wherein each execution unit is used to perform a corresponding operation. According to one embodiment of the present invention, the processing module is configured to select the corresponding execution unit to perform the corresponding operation based on the channel estimation instruction.

[0048] As can be seen from the above embodiments, the processing modules in the accelerator designed in this invention employ a serial execution method to perform corresponding operations. Each operation has a unique hardware module corresponding to it (i.e., one computational operation corresponds to one execution unit). This design of dedicated data paths and execution units avoids complex control logic and a large amount of data memory access. Furthermore, the accelerator designed in this invention can select the corresponding execution unit to perform the corresponding operation based on different channel estimation instructions to complete the operation of different channel estimation models. Simultaneously, it can also realize the upgrading and iteration of the execution algorithm within the accelerator.

[0049] To verify whether the channel estimation accelerator designed in the above embodiments of the present invention can support such... Figure 1 The efficient execution of the hardware accelerator logic framework shown below is described in detail with reference to the accelerator of this invention. Figure 1 The main execution flow and data flow layer execution flow of the accelerator logic framework are shown.

[0050] (1) Main execution flow of the accelerator logic framework

[0051] In summary, the main execution flow of this hardware accelerator logic framework is as follows: First, the transmitted pilot signal (including the transmitted subframe pilot signal and the received subframe pilot signal) is subjected to a least-squares operation at the pilot position to obtain the channel estimation matrix at the pilot position. The real and imaginary parts of the channel estimation matrix at the pilot position are then used as two channels of the input feature map, and... Figure 1 The sequence shown involves N convolution operations, M attention-dense connection blocks (also known as a fixed structure composed of network layers according to a preset number of layers), and upsampling using transposed convolution or bilinear interpolation, finally yielding the channel estimation result (i.e., the channel estimation matrix in the subframe). Figure 1 The activation functions are merged into convolutional, transposed convolutional, or fully connected layers for simplified representation. Each attention-dense block contains L convolutional operations and 1 attention operation, employing a densely connected structure, where the attention operation precedes the last convolutional operation.

[0052] (2) Execution process at the data flow level of the accelerator logic framework

[0053] First, the data storage locations in the hardware accelerator logic framework are mapped one-to-one with the data storage locations of the accelerator designed in this invention to achieve efficient data access. Schematic, the data caching unit in the above embodiments of this invention is mapped to Cache 1, the first data sub-caching unit to Cache 11, the second data sub-caching unit to Cache 12, the first intermediate result sub-caching unit to Cache 21, and the second intermediate result sub-caching unit to Cache 22. Simultaneously, before the computation begins, the weight parameters of each network layer in the channel estimation model are sequentially cached in the weight caching module, while the input pilot signal and channel estimation command are cached in the data caching module and command caching module, respectively. At the start of the computation, according to the channel estimation command, the weight parameters of the channel estimation model and the pilot signal are sent together to the corresponding module of the computation engine for corresponding computation operations, and the computation results are stored back in the data caching module and the final result is output from the data caching module.

[0054] Indicative, still for reference Figure 1 ,from Figure 1 As can be seen from this, the execution flow of the hardware accelerator's logical framework at the data flow level is as follows:

[0055] (1) The pilot signal to be transmitted (including the pilot signal to be transmitted and the pilot signal to be received) is taken out from the first data sub-buffer unit (buffer 11) and sent to the least squares calculation module to perform the least squares operation to obtain the result of the least squares (i.e. the channel estimation matrix at the pilot), and the channel estimation matrix at the pilot is stored back to the second data sub-buffer unit (buffer 12).

[0056] (2) Take out the channel estimation matrix at the pilot from the second data sub-buffer unit (buffer 12) and send it to the convolution execution unit C1 of the processing module to perform convolution operation and store the result back to the first data sub-buffer unit (buffer 11), the first intermediate result sub-buffer unit (buffer 21) and the second intermediate result sub-buffer unit (i.e., buffer 22).

[0057] (3) The calculation of the next attention-dense connection block is as follows: a. Take the result from the first data sub-cache unit (cache 11) and send it to the convolution execution unit B. 11a) Perform convolution operation and store the result back to the second data sub-cache unit (cache 12); b) Take the results from the second data sub-cache unit (cache 12) and the first intermediate result sub-cache unit (cache 21) and send them into the matrix element-wise addition execution unit to perform matrix element-wise addition operation and store the result back to the first data sub-cache unit (cache 11); c) Take the results from the first data sub-cache unit (cache 11) and the first intermediate result sub-cache unit (cache 21) and send them into the matrix element-wise addition execution unit to perform matrix element-wise addition operation and store the result back to the first intermediate result sub-cache unit (cache 21); d) Repeat the above steps ac for a total of L-1 times and store the result back to the first data sub-cache unit (cache 11);

[0058] e. Retrieve the result from the first data sub-cached unit (cached 11), send it to the attention execution unit to perform the attention operation (i.e., the corresponding operation in the attention module), and store the result back to the second data sub-cached unit (cached 12); f. Retrieve the results from the second data sub-cached unit (cached 12) and the first intermediate result sub-cached unit (cached 21), send them to the matrix element-by-element addition execution unit to perform the matrix element-by-element addition operation, and store the result back to the second data sub-cached unit (cached 12); g. Retrieve the result from the second data sub-cached unit (cached 12), send it to the convolution execution unit B. 1L Perform convolution operations and store the results back into the first data sub-cache unit (cache 11).

[0059] (4) After completing the calculation of one attention-dense connection block, the results from the first data sub-caching unit (caching 11) and the second intermediate result sub-caching unit (caching 22) are taken out and sent to the matrix element-by-element addition execution unit to perform the matrix element-by-element addition operation and store the result back to the second intermediate result sub-caching unit (caching 22) (i.e., the intermediate result generated by the irregular connection between multiple fixed structures composed of network layers according to a preset number of layers), thereby completing one inter-block residual operation. Then, the attention-dense connection block and the inter-block residual operation are alternately executed M-1 times and the result is stored back to the first data sub-caching unit (caching 11).

[0060] (5) Take the result from the first data sub-cache unit (cache 11) and send it into the convolution execution unit C2 to perform the convolution operation and store the result back into the second data sub-cache unit (cache 12).

[0061] (6) Take the results from the second data sub-caching unit (caching 12) and the second intermediate cache unit (caching 22) and send them to the matrix element-by-element addition execution unit to perform the matrix element-by-element addition operation and store the results back to the first data sub-caching unit (caching 11), thereby completing the calculation of all network layers before the upsampling layer.

[0062] (7) Take the result from the first data sub-cache unit (cache 11) and send it to the transposed convolution execution unit to perform the transposed convolution operation or the bilinear interpolation calculation module to perform the bilinear interpolation operation to realize the calculation of the upsampling layer and store the result back to the second data sub-cache (cache 12).

[0063] (8) Take out the result from the second data sub-buffer unit (buffer 12) and send it into the convolution execution unit C3 to perform the convolution operation. Then store the result back into the first data sub-buffer unit (buffer 11) and repeat the convolution operation L-4 times to obtain the final channel estimation result (i.e., the subframe channel estimation matrix).

[0064] The aforementioned hardware accelerator logic framework supports data streams from various novel channel estimation models, including ReEsNet, Interpolation-ResNet, RRDBNet, and AttRNet. The channel estimation accelerator designed for this framework can execute corresponding processes by configuring channel estimation instructions for different channel estimation models. The channel estimation instructions for the four channel estimation models—ReEsNet, Interpolation-ResNet, RRDBNet, and AttRNet—are shown in Tables 1 and 2. Table 1 displays the parameter information in the channel estimation instructions that determines the structure of each channel estimation model, and Table 2 displays the parameter information in the channel estimation instructions that determines the execution process of each channel estimation model. By configuring the parameter information shown in Tables 1 and 2, support for the aforementioned channel estimation models (i.e., ReEsNet, Interpolation-ResNet, RRDBNet, and AttRNet) can be achieved. In Table 1, the values ​​of m range from 0 ≤ m ≤ M, n range from 0 ≤ n ≤ N, and l range from 0 ≤ l ≤ L, corresponding to specific values ​​and the corresponding channel estimation models. The parameter configurations in Table 2 are primarily represented by a one-hot mask, where 0 indicates skipping and 1 indicates selection. It should be noted that the accelerator of this invention can not only achieve efficient inference for four channel estimation models—ReEsNet, Interpolation-ResNet, RRDBNet, and AttRNet—but, with the development of channel estimation models, it can also be further used for inference for other channel estimation models; no specific limitations are made here.

[0065] Table 1

[0066]

[0067] Table 2

[0068]

[0069] When the accelerator designed in the above embodiments of the present invention is applied in practice, according to one embodiment of the present invention, the present invention proposes a reasoning method for a channel estimation model, the method comprising: acquiring pilot signals, channel estimation instructions and channel estimation models; and using the accelerator described in the above embodiments to obtain channel estimation results based on the pilot channel, channel estimation instructions and channel estimation models.

[0070] To better understand the execution flow of the channel estimation model at the data layer in the accelerator designed in this invention, the ReEsNet channel estimation model is taken as an example (i.e., the ReEsNet channel estimation model determined by the parameter configuration in Tables 1 and 2). Figure 4 As shown, it illustrates the execution logic framework at the ReEsNet data flow level under the accelerator of this invention. The specific process is as follows:

[0071] (1) The pilot signal to be transmitted (including the pilot signal to be transmitted and the pilot signal to be received) is taken out from the first data sub-buffer unit (buffer 11) and sent to the least squares calculation module to perform the least squares operation to obtain the result of the least squares (i.e. the channel estimation matrix at the pilot), and the channel estimation matrix at the pilot is stored back to the second data sub-buffer unit (buffer 12).

[0072] (2) Take out the channel estimation matrix at the pilot from the second data sub-buffer unit (buffer 12) and send it to the convolution execution unit C1 of the processing module to perform convolution operation and store the result back to the first data sub-buffer unit (buffer 11), the first intermediate result sub-buffer unit (buffer 21) and the second intermediate result sub-buffer unit (i.e., buffer 22).

[0073] (3) The calculation of the next attention-dense connection block is as follows: a. Take the result from the first data sub-cache unit (cache 11) and send it to the convolution execution unit B. 11 a) Perform convolution operation and store the result back to the second data sub-cache unit (cache 12); b) Retrieve the result from the second data sub-cache unit (cache 12) and send it to the convolution execution unit B. 12 c. Perform convolution operation in the first data sub-cache unit (cache 11) and store the result back in the first data sub-cache unit (cache 11); d. Take the result from the first data sub-cache unit (cache 11) and the first intermediate result sub-cache unit (cache 21) and send it into the matrix element-wise addition execution unit to perform element-wise addition operation and store the result back in the first data sub-cache unit (cache 11);

[0074] (4) After completing the calculation of one attention-dense connection block, retrieve the result from the first data sub-caching unit (caching 11), execute the attention-dense connection block 3 times in sequence, and store the result back to the first data sub-caching unit (caching 11).

[0075] (5) Take the result from the first data sub-cache unit (cache 11) and send it into the convolution execution unit C2 to perform the convolution operation and store the result back into the second data sub-cache unit (cache 12).

[0076] (6) Take the results from the second data sub-caching unit (caching 12) and the second intermediate cache unit (caching 22) and send them to the matrix element-by-element addition execution unit to perform the matrix element-by-element addition operation and store the results back to the first data sub-caching unit (caching 12), thereby completing the calculation of all network layers before the upsampling layer.

[0077] (7) Take the result from the first data sub-cache unit (cache 11) and send it to the transposed convolution execution unit to perform the transposed convolution operation to realize the calculation of the upsampling layer and store the result back to the second data sub-cache (cache 12).

[0078] (8) Take the result from the second data sub-buffer unit (buffer 12) and send it into the convolution execution unit C3 to perform convolution operation to obtain the final channel estimation result.

[0079] It should be noted that in the accelerator designed in this invention, the execution logic framework and execution process of other channel estimation model data flow layers are implemented according to the configured channel estimation instructions, which will not be elaborated here.

[0080] As can be seen from the above, the accelerator designed in this invention can efficiently realize the inference of the channel estimation model and the memory access operation of the data corresponding to the instruction through different channel estimation instruction configurations, while improving the hardware execution efficiency of the channel estimation model and reducing inference latency.

[0081] It should be noted that although the steps are described in a specific order above, it does not mean that the steps must be executed in the above specific order. In fact, some of these steps can be executed concurrently, or even in a different order, as long as the required function can be achieved.

[0082] This invention can be a system, method, and / or computer program product. A computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for causing a processor to implement various aspects of the invention.

[0083] Computer-readable storage media can be tangible devices that hold and store instructions for use by an instruction execution device. Computer-readable storage media can be, for example, including but not limited to, electrical storage devices, magnetic storage devices, optical storage devices, electromagnetic storage devices, semiconductor storage devices, or any suitable combination thereof. More specific examples (a non-exhaustive list) of computer-readable storage media include: portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), portable compact disc read-only memory (CD-ROM), digital multifunction disc (DVD), memory sticks, floppy disks, mechanical encoding devices, such as punch cards or recessed protrusions storing instructions thereon, and any suitable combination thereof.

[0084] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen to best explain the principles, practical application, or technical improvements to the embodiments in the market, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A channel estimation accelerator, wherein the channel estimation accelerator is used to obtain channel estimation results based on pilot signals, channel estimation commands, and a channel estimation model, characterized in that, The channel estimation accelerator includes: a central controller, an on-chip cache, and a computing engine, wherein... The overall controller is used to generate the address corresponding to the on-chip cache based on the channel estimation instruction and configure the computation operations in the computing engine, wherein the computation operations include: least squares operation, convolution operation, matrix element-wise addition operation, transpose convolution operation and attention operation; The on-chip cache is used to cache pilot signals, weights of all network layers in the channel estimation model based on their corresponding addresses, and cache the input and output data of each network layer in the channel estimation model and intermediate results generated by irregular connections between network layers. The computing engine includes a least squares calculation module and a processing module, wherein... The least squares calculation module is used to perform a least squares operation on the pilot signal cached in the on-chip cache to obtain the channel estimation matrix at the pilot. The processing module is used to perform convolution, element-wise addition, transpose convolution and attention operations on the channel estimation matrix at the pilot based on the weights of all network layers in the channel estimation model to obtain the input and output data of each network layer in the channel estimation model and the intermediate results generated by the irregular connections between each network layer, and feed them back to the on-chip buffer. The output data of the last network layer in the channel estimation model is the channel estimation result.

2. The accelerator according to claim 1, characterized in that, The main controller includes: The instruction caching module is used to cache the channel estimation instruction; A finite state machine module is used to generate the address corresponding to the on-chip cache and configure the computational operations in the computing engine based on the channel estimation instructions cached by the instruction cache module.

3. The accelerator according to claim 1, characterized in that, The on-chip cache includes: The data caching module is used to cache pilot signals, input and output data of each network layer in the channel estimation model, and intermediate results generated by irregular connections between network layers. The weight caching module is used to cache the weights of all network layers in the channel estimation model.

4. The accelerator according to claim 3, characterized in that, The data caching module includes: The data caching unit is used to cache pilot signals and input / output data of each network layer in the channel estimation model. The intermediate result caching unit is used to cache intermediate results generated by irregular connections between network layers in the channel estimation model.

5. The accelerator according to claim 4, characterized in that, The data caching unit includes a first data sub-caching unit and a second data sub-caching unit, used to cache the input and output data of the corresponding network layer in the channel estimation model, respectively. The first data sub-caching unit is also used to cache pilot signals. The first data sub-caching unit and the second data sub-caching unit are configured to cache the input or output data of the corresponding network layer in the channel estimation model in the following manner: When performing corresponding operations on the input data of a network layer in the channel estimation model to obtain the output data of that network layer, one data sub-buffer unit is used to buffer the output data of that network layer as the input data of the next network layer, and the other data sub-buffer unit is used to buffer the output data of the next network layer.

6. The accelerator according to claim 4, characterized in that, The intermediate results generated by irregular connections between network layers include: intermediate results generated by irregular connections between multiple network layers arranged in a fixed structure according to a preset number of layers in the channel estimation model, and intermediate results generated by irregular connections between network layers in the fixed structure arranged in a preset number of layers. The intermediate result caching unit includes: The first intermediate result sub-caching unit is used to cache intermediate results generated by irregular connections between network layers in the fixed structure composed of network layers according to a preset number of layers in the channel estimation model. The second intermediate result sub-caching unit is used to cache intermediate results generated by irregular connections between multiple fixed structures composed of network layers of a preset number in the channel estimation model.

7. The accelerator according to claim 1, characterized in that, The computational operation further includes bilinear interpolation, and the computational engine further includes a bilinear interpolation computation module; wherein, The processing module is configured to perform convolution, element-wise addition, and attention operations on the channel estimation matrix at the pilot based on the weights of all network layers in the channel estimation model, and feed the results to the bilinear interpolation calculation module. It also performs a preset number of convolution operations on the results obtained by the bilinear interpolation calculation module to obtain the input and output data of each network layer in the channel estimation model and the intermediate results generated by the irregular connections between each network layer, and feeds them back to the on-chip cache. The bilinear interpolation calculation module is used to perform bilinear interpolation on the received data and send the result to the processing module.

8. The accelerator according to claim 7, characterized in that, The processing module includes: multiple convolution execution units, multiple matrix element-wise addition execution units, multiple attention execution units, and a transposed convolution execution unit connected in series according to a preset serial structure, wherein each execution unit is used to perform a corresponding operation.

9. The accelerator according to claim 8, characterized in that, The processing module is configured to select the corresponding execution unit to perform the corresponding operation based on the channel estimation instruction.

10. A reasoning method for a channel estimation model, characterized in that, The method includes: Acquire pilot signals, channel estimation commands, and channel estimation models; The channel estimation result is obtained by using the accelerator as described in any one of claims 1-9 based on the pilot signal, the channel estimation command, and the channel estimation model.

11. A computer-readable storage medium, characterized in that, It stores a computer program that can be executed by a processor to implement the steps of the method of claim 10.

12. An electronic device, characterized in that, include: One or more processors; A storage device for storing one or more programs that, when executed by one or more processors, cause the electronic device to perform the steps of the method as claimed in claim 10.

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