Power consumption control circuit, chip and electronic device

Abstract

The application provides a power consumption control circuit, a chip and an electronic device, which comprise a data series-parallel conversion module, a data counting module, a data latch control module and a power consumption mode determination module. The data series-parallel conversion module converts serial input data into parallel data and outputs the lowest bit of the parallel data in sequence. The data counting module generates a valid flag bit when the number of valid data bits of the serial data reaches a preset value. The data latch control module generates a valid latch pulse after a to-be-controlled circuit completes data reception and transmission. The power consumption mode determination module generates a power consumption control signal of the to-be-controlled circuit, controls the to-be-controlled circuit to enter a working mode when valid data is received and the lower-level circuit needs to be controlled, and controls the to-be-controlled circuit to enter a power saving mode otherwise. When no data is received, invalid data is received or the lower-level circuit does not need to be controlled, the output control signal makes the to-be-controlled circuit in the power saving mode; when valid data is received and the lower-level circuit needs to be controlled, the output control signal makes the to-be-controlled circuit work normally.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and in particular to a power consumption control circuit, chip, and electronic device. Background Technology

[0002] In current mainstream LED lighting circuit designs, the LED driver chip (circuit) consumes a certain amount of operating current after power-on, regardless of whether it receives data or needs to light the LEDs. This current is typically around 1mA. When LED driver chips are used in portable electronic devices, this constant operating current consumed by the LED driver chip (circuit) reduces the battery life of the electronic devices, especially portable ones.

[0003] Therefore, how to reduce the operating current consumed by LED driver chips (circuits) in non-operating states and extend the battery life of electronic devices equipped with LED driver chips (circuits) has become one of the problems that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a power consumption control circuit, chip and electronic device to solve the problem that the operating current consumed by the LED driver chip (circuit) in the non-operating state affects the battery life in the prior art.

[0005] To achieve the above and other related objectives, the present invention provides a power consumption control circuit for controlling the power consumption of a circuit under control, the power consumption control circuit comprising at least:

[0006] Data serial-to-parallel conversion module, data counting module, data latch control module, and power consumption mode determination module;

[0007] The serial-to-parallel conversion module receives serial input data from the circuit under control, converts the serial input data into parallel data, and outputs the least significant bit of the parallel data in sequence. The circuit under control controls the next-level circuit based on the serial input data.

[0008] The data counting module receives the serial input data and counts the number of valid data bits in the serial input data. When the number of valid data bits in the serial data reaches a preset value, a valid flag bit is generated.

[0009] The data latch control module generates an effective latch pulse after the controlled circuit completes the data reception and transmission;

[0010] The power consumption mode determination module is connected to the output terminals of the data serial-to-parallel conversion module, the data counting module, and the data latch control module. It receives the serial input data and the power-on reset signal of the circuit under control, and generates a power consumption control signal for the circuit under control. When the circuit under control receives valid data and needs to control the lower-level circuit, it controls the circuit under control to enter the working mode; otherwise, it controls the circuit under control to enter the power-saving mode.

[0011] Optionally, the data serial-to-parallel conversion module includes N trigger units and logic units;

[0012] The logic unit receives the power-on reset signal and the latch pulse, and generates a first reset signal when the power-on reset signal or the latch pulse is valid;

[0013] Each trigger unit is connected in series, with its clock terminal connected to a clock signal and its reset terminal connected to the first reset signal; based on the triggering of the clock signal, each bit of data in the serial input data is transmitted sequentially.

[0014] Where N is a natural number greater than or equal to 1.

[0015] Alternatively, the logic unit is a first NOR gate.

[0016] Alternatively, the triggering unit is a D flip-flop.

[0017] Alternatively, when the circuit to be controlled is an LED driver circuit, the preset value is equal to M*N, where M is the number of LED channels and N is the number of bits of grayscale data for each LED channel; where M is a natural number greater than or equal to 1.

[0018] Alternatively, the power consumption mode determination module includes a data determination unit, a power consumption mode determination result latching unit, and a reset unit;

[0019] The data determination unit determines whether the controlled circuit has received valid data and whether it needs to control the lower-level circuit based on the output signals of the data serial-to-parallel conversion module and the data counting module, and resets the data determination unit when the power-on reset signal or the latch pulse is valid.

[0020] The power consumption mode determination result latching unit generates the power consumption control signal based on the output signal of the data determination unit and the latching pulse;

[0021] The reset unit is connected to the output of the power consumption mode determination result latch unit and receives the power-on reset signal. When the power-on reset signal is valid or the controlled circuit switches from the working mode to the power saving mode, a second reset signal is generated to perform a reset operation on the data determination unit and the power consumption mode determination result latch unit.

[0022] Alternatively, the data determination unit includes a first RS flip-flop and a first D flip-flop; the first reset terminal of the first RS flip-flop receives the power-on reset signal, the second reset terminal receives the latch pulse, and the set terminal is connected to the output terminal of the data serial-to-parallel conversion module; the data input terminal of the first D flip-flop is connected to the output terminal of the first RS flip-flop, the clock terminal receives the flag bit, the reset terminal receives the second reset signal, and the inverted output terminal serves as the output terminal of the data determination unit.

[0023] Alternatively, the power mode determination result latching unit includes a second D flip-flop and a second RS flip-flop; the data input terminal of the second D flip-flop is connected to the output terminal of the data determination unit, the clock terminal receives the latch pulse, and the reset terminal receives the second reset signal; the first reset terminal of the second RS flip-flop is connected to the output terminal of the second D flip-flop, the second reset terminal receives the power-on reset signal, the set terminal receives the serial input data, and the output terminal outputs the power control signal.

[0024] Alternatively, the reset unit includes an inverter and a second NOR gate; the input of the inverter is connected to the power consumption control signal, and the output is connected to the first input of the second NOR gate; the second input of the second NOR gate receives the power-on reset signal and outputs the second reset signal.

[0025] To achieve the above and other related objectives, the present invention provides a chip, the chip comprising at least the aforementioned power consumption control circuit.

[0026] To achieve the above and other related objectives, the present invention provides an electronic device, which includes at least: a controllable circuit and the power consumption control circuit described above.

[0027] Optionally, the circuit to be controlled is an LED driver circuit.

[0028] As described above, the power consumption control circuit, chip, and electronic device of the present invention have the following beneficial effects:

[0029] 1. The power consumption control circuit, chip, and electronic device of the present invention can enable the controlled circuit to be in power-saving mode when powered on. When the controlled circuit receives data, and receives valid data, and needs to control the lower-level circuit, the controlled circuit can be controlled to enter the normal working state; which can significantly reduce the standby power consumption of electronic devices.

[0030] 2. The power consumption control circuit, chip and electronic device of the present invention can effectively distinguish various data (whether data has been received, whether valid data has been received, whether it is necessary to control the lower-level circuit) with very little circuit resource consumption, and has low cost and high accuracy.

[0031] 3. The power consumption control circuit and chip of the present invention can make the controlled circuit more suitable for the application scenarios of portable electronic devices. Attached Figure Description

[0032] Figure 1 The diagram shown is a structural schematic of the power consumption control circuit of the present invention.

[0033] Figure 2 The diagram shown is a structural schematic of the data serial-to-parallel conversion module of the present invention.

[0034] Figure 3 The diagram shown is a structural schematic of the power consumption mode determination module of the present invention.

[0035] Figure 4 The diagram shown is a structural schematic of the chip or electronic device of the present invention.

[0036] Component designation explanation

[0037] 1 Power Consumption Control Circuit

[0038] 10. Data serial-to-parallel conversion module

[0039] 101 Trigger Unit

[0040] 102 Logic Units

[0041] 11 Data counting module

[0042] 12 Data latch control module

[0043] 13 Power Consumption Mode Determination Module

[0044] 131 Data Decision Unit

[0045] 131a First RS Flip-Flop

[0046] 131b First D Flip-Flop

[0047] 132 Power Mode Determination Result Latch Unit

[0048] 132a Second D Flip-Flop

[0049] 132b Second RS Flip-Flop

[0050] 133 Reset Unit

[0051] 2 LED driver circuit Detailed Implementation

[0052] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0053] Please see Figures 1-4 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0054] like Figure 1 As shown, this invention provides a power consumption control circuit 1 for controlling the power consumption of a circuit under control. In this embodiment, the circuit under control is an LED driver circuit. In practical use, any circuit operating based on serial input data is applicable to this invention, and will not be described in detail here. The power consumption control circuit 1 includes:

[0055] The system includes a serial-to-parallel conversion module 10, a data counting module 11, a data latch control module 12, and a power consumption mode determination module 13.

[0056] like Figure 1 As shown, the serial-to-parallel data conversion module 10 receives the serial input data DIN from the LED driver circuit (controlled circuit), converts the serial input data DIN into parallel data, and outputs the least significant bit REG0 of the parallel data in sequence.

[0057] It should be noted that the controlled circuit controls the lower-level circuit based on the serial input data DIN. In this embodiment, the serial input data DIN includes the grayscale information of the LED driven by the LED driving circuit.

[0058] Specifically, in this embodiment, the data serial-to-parallel conversion module 10 also receives the power-on reset signal Reset from the LED driving circuit and the latch pulse data_lock provided by the data latch control module 12. When the power-on reset signal Reset or the latch pulse data_lock is valid (i.e., power-on reset or data latch), the data serial-to-parallel conversion module 10 is reset.

[0059] Specifically, in this embodiment, the data serial-to-parallel conversion module 10 is implemented using a set of shift registers. As an example, such as... Figure 2As shown, the data serial-to-parallel conversion module includes N trigger units 101 and logic units 102, where N is the number of bits of grayscale data in the LED channel (N can be defined according to the actual application scenario and is not limited to this embodiment), and N is a natural number greater than or equal to 1. In this example, N = 8. The logic unit 102 receives the power-on reset signal Reset and the latch pulse data_lock. When the power-on reset signal Reset or the latch pulse data_lock is valid, a first reset signal is generated. In this example, the logic unit 102 is implemented using a first NOR gate. The power-on reset signal Reset and the latch pulse data_lock are active high, and the first reset signal is active low. In actual use, the circuit structure of the logic unit 102 can be set as needed to achieve the logical relationship of this invention. Each trigger unit 101 is connected in series. The clock terminal CK is connected to the clock signal clk_sample, and the reset terminal is connected to the first reset signal. Based on the triggering of the clock signal clk_sample, each bit of data in the serial input data DIN is transmitted sequentially. The data output by each trigger unit, from high to low, are REG7, REG6, REG5, REG4, REG3, REG2, REG1, and REG0, respectively. As the clock signal clk_sample arrives one by one, the least significant bit data REG0 output by the circuit is sequentially the data in the serial input data DIN. The least significant bit data REG0 will participate in the data determination function of the power consumption mode determination module 13. In this example, the trigger unit 101 is implemented using a D flip-flop (including but not limited to D flip-flop structures implemented using JK flip-flops or other forms).

[0060] It should be noted that any circuit structure capable of sequentially outputting each bit of the serial input data DIN without interfering with each other is applicable to the data serial-to-parallel conversion module 10 of the present invention, and will not be described in detail here. The clock signal clk_sample can also be set or not set according to the actual circuit needs, and is not limited to this embodiment. In the present invention, power consumption control is only based on the least significant bit data REG0; in actual use, each bit of the parallel data REG7, REG6, REG5, REG4, REG3, REG2, REG1, and REG0 needs to be output, which can be used as the control basis for other circuits (including but not limited to the circuit to be controlled), and will not be described in detail here.

[0061] like Figure 1 As shown, the data counting module 11 receives the serial input data DIN and counts the number of valid data bits of the serial input data DIN. When the number of valid data bits of the serial data DIN reaches a preset value, a valid flag bit data_valid_flag is generated.

[0062] Specifically, in this embodiment, the preset value is equal to M*N, where M is the number of LED channels and N is the number of bits of grayscale data for each LED channel; M is a natural number greater than or equal to 1, and N is a natural number greater than or equal to 1. The data counting module 11 counts the number of valid data bits of the serial input data DIN received by the LED driving circuit. If the LED driving circuit receives some erroneous data signals (e.g., glitches, which are invalid data) or the number of data bits does not reach the preset value, the flag bit data_valid_flag remains at 0 (invalid state); if the LED driving circuit receives normal data signals (valid data), and the data counting module 11 counts to M*N, the output signal data_valid_flag of the data counting module 11 is a positive pulse signal (valid state), and the pulse width of this pulse signal can be from a few nanoseconds to several hundred nanoseconds. The flag bit data_valid_flag will participate in the data determination function of the power consumption mode determination module 13.

[0063] It should be noted that the preset value can be set according to actual needs, as long as it enables the controlled circuit to obtain a complete signal. The definitions of M and N are set according to specific needs and are not limited to this embodiment.

[0064] like Figure 1 As shown, the data latch control module 12 generates an effective latch pulse data_lock after the LED driver circuit (controlled circuit) completes the data reception and transmission.

[0065] Specifically, in this embodiment, the data latch control module 12 is equipped with a timer. When data is input to the LED driver circuit (including but not limited to valid data required for the operation of the LED driver circuit itself and data forwarded to other cascaded circuits), this data will reset the timer. When the data transmission is complete, the timer resets and starts counting. When the count reaches the timer's set value, a valid latch pulse, data_lock, is output. The latch pulse, data_lock, causes the LED driver circuit to latch the valid data. The pulse width of the latch pulse, data_lock, can be from a few nanoseconds to a few microseconds. The latch pulse, data_lock, participates in the latching of the power consumption enable determination result and the reset of the data determination result in the power consumption mode determination module 13.

[0066] It should be noted that the structure of the data latch control module 12 is not limited. Any structure that can trigger a pulse signal after the controlled circuit completes the data reception and transmission is applicable to the present invention, and will not be described in detail here.

[0067] like Figure 1As shown, the power consumption mode determination module 13 is connected to the output terminals of the data serial-to-parallel conversion module 10, the data counting module 11, and the data latch control module 12, and receives the serial input data DIN and the power-on reset signal Reset to generate the power consumption control signal Power_ctr for the LED driver circuit. When the LED driver circuit (controlled circuit) receives valid data and there is an LED lighting instruction (the controlled circuit needs to control its lower-level circuit), it controls the LED driver circuit (controlled circuit) to enter the working mode; otherwise, it controls the LED driver circuit (controlled circuit) to enter the power saving mode.

[0068] Specifically, in this embodiment, the power consumption mode determination module 13 includes a data determination unit 131, a power consumption mode determination result latching unit 132, and a reset unit 133.

[0069] More specifically, the data determination unit 131 determines whether the LED driving circuit has received valid data and whether there is an LED lighting command in the valid data based on the output signals of the data serial-to-parallel conversion module 10 and the data counting module 12, and resets the data determination unit 131 when the power-on reset signal Reset or the latch pulse data_lock is valid. Figure 3As shown in the example, the data determination unit 131 includes a first RS flip-flop 131a and a first D flip-flop 131b. The first reset terminal of the first RS flip-flop 131a receives the power-on reset signal Reset, the second reset terminal receives the latch pulse data_lock, and the set terminal is connected to the output terminal (least significant bit data REG0) of the data serial-to-parallel conversion module 10, outputting the determination result RS0_Y. In this example, the first RS flip-flop 131a is implemented using two NOR gates. In actual use, any circuit structure that can realize the RS trigger function is applicable to this invention, and will not be described in detail here. During power-on reset or during the valid level pulse of the latch pulse data_lock, the output of the first RS flip-flop 131a is reset to 0. When all valid data of the LED driver circuit is 0 (in this embodiment, it indicates that no LED needs to be lit; in actual use, it indicates that the controlled circuit does not need to control the lower-level circuit), it indicates that the LED driver circuit does not need to drive the LED to light up. The LED driver circuit can remain in power-saving mode (if the current state is power-saving mode) or switch to power-saving mode (if the current state is working mode). At this time, the output of the first RS flip-flop 131a is RS0_Y = 0. When any bit in the valid data of the LED driver circuit is 1 (in this embodiment, it indicates that the corresponding LED is lit; in actual use, it indicates that the controlled circuit needs to control the lower-level circuit), it indicates that the LED driver circuit needs to drive the LED to light up. The LED driver circuit can remain in working mode (if the current state of the chip is working mode) or switch to working mode (if the current state of the chip is power-saving mode). At this time, the output of the first RS flip-flop 131a is RS0_Y = 1. Therefore, the first RS flip-flop 131a realizes the conditional determination of whether the LED needs to be driven to light up (whether the controlled circuit needs to control the lower-level circuit). The data input terminal D of the first D flip-flop 131b is connected to the output terminal of the first RS flip-flop 131a, the clock terminal CK receives the flag bit data_valid_flag, the reset terminal receives the second reset signal rstb provided by the reset unit 133, and the inverted output terminal serves as the output terminal of the data determination unit 131 (the output signal D0_QB of the data determination unit 131). When the flag bit data_valid_flag is invalid (low level), the first D flip-flop 131b cannot latch the determination result of the first RS flip-flop 131a. When the flag bit data_valid_flag is valid (positive pulse signal), the first D flip-flop 131b latches the determination result of the first RS flip-flop 131a under the action of the pulse signal.

[0070] Therefore, through the combined action of the first RS flip-flop 131a and the first D flip-flop 131b, when the LED driving circuit receives valid data and any bit in the valid data is 1 (to light up the corresponding LED), it means that the LED driving circuit needs to drive the LED to light up. The LED driving circuit can maintain (if the current state is the working mode) or switch to the working mode (if the current state is the power saving mode). At this time, the first D flip-flop 131b outputs D0_QB = 0. When the LED driving circuit receives invalid data, or all valid data are 0 (no LED needs to be lit), it means that the LED driving circuit does not need to drive the LED to light up. The LED driving circuit can maintain (if the current state is the power saving mode) or switch to the power saving mode (if the current state is the working mode). At this time, the first D flip-flop 131b outputs D0_QB = 1.

[0071] More specifically, the power consumption mode determination result latch unit 132 generates the power consumption control signal Power_ctr based on the output signal of the data determination unit 131 and the latch pulse data_lock. For example... Figure 3As shown in the example, the power mode determination result latching unit 132 includes a second D flip-flop 132a and a second RS flip-flop 132b. The data input terminal D of the second D flip-flop 132a is connected to the output terminal of the data determination unit 131, the clock terminal CK receives the latch pulse data_lock, the reset terminal receives the second reset signal rstb, and the output signal D1_Q. When the latch pulse data_lock is valid (positive pulse), the output signal D0_QB of the data determination unit 131 is latched by the second D flip-flop 132a; when the latch pulse data_lock is invalid (low level), the output signal D0_QB of the data determination unit 131 is not latched by the second D flip-flop 132a. The first reset terminal of the second RS flip-flop 132b is connected to the output terminal of the second D flip-flop 132a, the second reset terminal receives the power-on reset signal Reset, the set terminal receives the serial input data DIN, and the output terminal outputs the power control signal Power_ctr. In this example, the second RS flip-flop 132b is implemented using two NOR gates. In actual use, any circuit structure that can realize the RS trigger function is applicable to this invention, and will not be described in detail here.After the LED driver circuit is powered on and reset, the power consumption control signal Power_ctr output by the second RS flip-flop 132b remains at 0, controlling the LED driver circuit to be in power-saving mode. When the LED driver circuit receives the serial input data DIN, regardless of whether the data is valid or invalid, the power consumption control signal Power_ctr output by the second RS flip-flop 132b becomes 1, controlling the LED driver circuit to switch to normal operating mode. Then, based on the output signal of the data determination unit 131, it is determined whether the output of the second RS flip-flop 132b remains at 1 (controlling the LED driver circuit to maintain the operating mode state) or switches to 0 (controlling the LED driver circuit to switch to power-saving mode state): if the data received by the LED driver circuit is valid data, and any bit of 1 exists in the valid data, then the data determination unit 131... When the output is D0_QB = 0, the second D flip-flop 132a latches D0_QB under the action of the latch signal data_lock, that is, the output D1_Q of the second D flip-flop 132a is 0, and the power control signal Power_ctr output by the second RS flip-flop 132b remains at 1, controlling the LED driving circuit to maintain the working mode state; if the LED driving circuit receives invalid data or receives valid data with all 0s, then the output of the data determination unit 131 is D0_QB = 1, the second D flip-flop 132a latches D0_QB under the action of the latch signal data_lock, that is, the output D1_Q of the second D flip-flop 132a is 1, and the power control signal Power_ctr output by the second RS flip-flop 132b becomes 0, controlling the LED driving circuit to switch to the power saving mode state.

[0072] More specifically, the reset unit 133 is connected to the output of the power consumption mode determination result latch unit 32 and receives the power-on reset signal Reset. When the power-on reset signal Reset is valid or the LED driving circuit switches from the working mode to the power saving mode, it generates the second reset signal rstb to reset the data determination unit 131 and the power consumption mode determination result latch unit 132, so that the power consumption mode determination module 13 returns to its initial state and does not affect the power consumption control circuit's judgment of the next received data. Figure 3 As shown in the figure, as an example, the reset unit 133 includes an inverter and a second NOR gate. The input terminal of the inverter is connected to the power consumption control signal Power_ctr, and the output terminal is connected to the first input terminal of the second NOR gate; the second input terminal of the second NOR gate receives the power-on reset signal Reset and outputs the second reset signal rstb.

[0073] In this embodiment, the power consumption control circuit puts the LED driver circuit into a power-saving mode as soon as it is powered on, and when the LED driver circuit receives valid data and needs to drive the LED to light up, it outputs a control signal to control the LED driver circuit to enter a normal working mode, thus achieving a simple, flexible and reliable circuit.

[0074] It should be noted that the level (high or low) and pulse (positive or negative pulse) corresponding to the valid signal in this invention can be set according to actual needs, and the connection relationship of the corresponding circuit can be adjusted adaptively to achieve the logical relationship of this invention, and is not limited to this embodiment.

[0075] The present invention also provides a chip, the chip including the power consumption control circuit 1. The power consumption control circuit 1 provides a power consumption control signal Power_ctr to the controlled circuit, thereby reducing the power consumed by the controlled circuit itself during non-operating periods.

[0076] like Figure 4 As shown, the present invention also provides an electronic device, which includes at least the power consumption control circuit 1 and a controlled circuit. In this embodiment, the controlled circuit is an LED driver circuit 2. The power consumption control circuit 1 provides a power consumption control signal Power_ctr to the LED driver circuit 2. The LED driver circuit 2 enters a working state or a power-saving state based on the power consumption control signal Power_ctr, thereby reducing the power consumed by the LED driver circuit itself during non-working periods. As an example, the LED driver circuit 2 also drives the LED based on, but is not limited to, the serial input data DIN and the power-on reset signal Reset, which will not be elaborated here. The power consumption control circuit 1 can effectively reduce the power consumed by the LED driver circuit itself during non-working periods, extending the battery life of the electronic device (especially a portable electronic device).

[0077] Currently, in mainstream LED decorative light circuit designs, the typical no-load current of a single driver chip is between 200uA and 600uA. Even a light strip or small LED display with 1000 LEDs still has a standby current of 0.2A to 0.6A when the entire strip or screen is not displaying. With a 5V power supply, this standby power consumption is 1W to 3W. The power consumption control circuit, chip, and electronic equipment of this invention can significantly reduce the standby power consumption of LED light strips or LED displays.

[0078] In summary, this invention provides a power consumption control circuit, chip, and electronic device, comprising: a data serial-to-parallel conversion module, a data counting module, a data latch control module, and a power consumption mode determination module; the data serial-to-parallel conversion module receives serial input data from the circuit under control, converts the serial input data into parallel data, and outputs the least significant bit of the parallel data sequentially, wherein the circuit under control controls the lower-level circuit based on the serial input data; the data counting module receives the serial input data and counts the number of valid data bits of the serial input data, generating a valid flag bit when the number of valid data bits of the serial data reaches a preset value; the data latch control module generates a valid latch pulse after the circuit under control completes data reception and transmission; the power consumption mode determination module is connected to the output terminals of the data serial-to-parallel conversion module, the data counting module, and the data latch control module, and receives the serial input data and the power-on reset signal of the circuit under control, generating a power consumption control signal for the circuit under control; when the circuit under control receives valid data and needs to control the lower-level circuit, the circuit under control is controlled to enter a working mode; otherwise, the circuit under control is controlled to enter a power-saving mode. The power consumption control circuit, chip, and electronic device of this invention can shut down each working module of the controlled circuit when the controlled circuit does not receive data, receives invalid data, or does not need to control the lower-level circuit, thus putting the controlled circuit into a power-saving mode. When the controlled circuit receives valid data and needs to control the lower-level circuit, the output control signal can turn on each working module of the controlled circuit, enabling the controlled circuit to operate normally. Therefore, this invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0079] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A power consumption control circuit for controlling the power consumption of a circuit under control, characterized in that, The power consumption control circuit includes at least: Data serial-to-parallel conversion module, data counting module, data latch control module, and power consumption mode determination module; The serial-to-parallel conversion module receives serial input data from the circuit under control, converts the serial input data into parallel data, and outputs the least significant bit of the parallel data in sequence. The circuit under control controls the next-level circuit based on the serial input data. The data counting module receives the serial input data and counts the number of valid data bits in the serial input data. When the number of valid data bits in the serial data reaches a preset value, a valid flag bit is generated. The data latch control module generates an effective latch pulse after the controlled circuit completes the data reception and transmission; The power consumption mode determination module is connected to the output terminals of the data serial-to-parallel conversion module, the data counting module, and the data latch control module. It receives the serial input data and the power-on reset signal of the circuit under control, and generates a power consumption control signal for the circuit under control. When the circuit under control receives valid data and needs to control the lower-level circuit, it controls the circuit under control to enter the working mode; otherwise, it controls the circuit under control to enter the power-saving mode. The power consumption mode determination module includes a data determination unit and a power consumption mode determination result latching unit. The data determination unit determines whether the controlled circuit has received valid data and whether it needs to control the lower-level circuit based on the output signals of the data serial-to-parallel conversion module and the data counting module, and resets the data determination unit when the power-on reset signal or the latch pulse is valid. The power consumption mode determination result latching unit generates the power consumption control signal based on the output signal of the data determination unit and the latching pulse.

2. The power consumption control circuit according to claim 1, characterized in that: The data serial-to-parallel conversion module includes N trigger units and logic units; The logic unit receives the power-on reset signal and the latch pulse, and generates a first reset signal when the power-on reset signal or the latch pulse is valid; Each trigger unit is connected in series, with its clock terminal connected to a clock signal and its reset terminal connected to the first reset signal; based on the triggering of the clock signal, each bit of data in the serial input data is transmitted sequentially. Where N is a natural number greater than or equal to 1.

3. The power consumption control circuit according to claim 2, characterized in that: The logic unit is a first NOR gate.

4. The power consumption control circuit according to claim 2, characterized in that: The triggering unit is a D flip-flop.

5. The power consumption control circuit according to claim 2, characterized in that: When the circuit to be controlled is an LED driver circuit, the preset value is equal to M*N, where M is the number of LED channels and N is the number of bits of grayscale data for each LED channel; where M is a natural number greater than or equal to 1.

6. The power consumption control circuit according to any one of claims 1-5, characterized in that: The power consumption mode determination module also includes a reset unit; The reset unit is connected to the output of the power consumption mode determination result latch unit and receives the power-on reset signal. When the power-on reset signal is valid or the controlled circuit switches from the working mode to the power saving mode, a second reset signal is generated to perform a reset operation on the data determination unit and the power consumption mode determination result latch unit.

7. The power consumption control circuit according to claim 6, characterized in that: The data determination unit includes a first RS flip-flop and a first D flip-flop; the first reset terminal of the first RS flip-flop receives the power-on reset signal, the second reset terminal receives the latch pulse, and the set terminal is connected to the output terminal of the data serial-to-parallel conversion module. The data input terminal of the first D flip-flop is connected to the output terminal of the first RS flip-flop, the clock terminal receives the flag bit, the reset terminal receives the second reset signal, and the inverted output terminal serves as the output terminal of the data determination unit.

8. The power consumption control circuit according to claim 6, characterized in that: The power consumption mode determination result latching unit includes a second D flip-flop and a second RS flip-flop; the data input terminal of the second D flip-flop is connected to the output terminal of the data determination unit, the clock terminal receives the latching pulse, and the reset terminal receives the second reset signal. The first reset terminal of the second RS flip-flop is connected to the output terminal of the second D flip-flop, the second reset terminal receives the power-on reset signal, the set terminal receives the serial input data, and the output terminal outputs the power consumption control signal.

9. The power consumption control circuit according to claim 6, characterized in that: The reset unit includes an inverter and a second NOR gate; the input of the inverter is connected to the power consumption control signal, and the output is connected to the first input of the second NOR gate; the second input of the second NOR gate receives the power-on reset signal and outputs the second reset signal.

10. A chip, characterized in that, The chip includes at least the power consumption control circuit as described in any one of claims 1-9.

11. An electronic device, characterized in that, The electronic device includes at least: a controllable circuit and a power consumption control circuit as described in any one of claims 1-9.

12. The electronic device according to claim 11, characterized in that: The circuit to be controlled is an LED driver circuit.

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