Method for designing a decoder and electronic device

Abstract

The present disclosure relates to a method, device and equipment for designing a decoder. The method comprises forming an initial decoder based on netlist data, and training a binary neural network model by using a test vector set, and modifying the connection relationship of the decoding circuit of each decoding layer in the initial decoder based on the obtained binary neural network to obtain a target decoder. Since the input connection of each decoding layer of the target decoder is obtained through BNN iterative update, the connection of each decoding circuit is optimized, and the encoding success rate for the target decoder is also correspondingly improved.

Description

Technical Field

[0001] This disclosure relates to the field of electronics, and more specifically to methods and electronic devices for designing decoders. Background Technology

[0002] During the chip manufacturing and packaging process, defects are inevitably introduced due to various reasons (such as process technology and materials), causing the chip to malfunction. The main task of chip testing is to identify defective chips. Because the costs incurred by defective chips entering the market far outweigh the costs of chip testing itself, chip testing is a crucial part of the chip manufacturing process.

[0003] Specifically, design for testability (DFT) structures, such as scan chains, can be added to the chip during the chip design phase, and chips with DFT structures can be manufactured. Automatic test pattern generation (ATPG) tools can be used to generate chip test patterns, and automatic test equipment (ATE) can be used to input these test patterns into the chip under test. By comparing the response of the chip under test with the expected response, quality inspection can be performed immediately after production.

[0004] As chip integration and complexity continue to increase, the required test vector sets are also growing rapidly. This leads to a several-fold increase in chip testing time, which in turn significantly increases testing costs. To alleviate this problem, test compression techniques have been developed. However, conventional test compression techniques suffer from problems such as a large number of encoded bits. Summary of the Invention

[0005] In view of the above problems, embodiments of this disclosure aim to provide a method, apparatus, and device for designing a decoder, as well as a test circuit for testing a circuit under test, wherein the decoder is designed as part of the test circuit. The decoder in the test circuit is used to test the circuit under test in the same chip.

[0006] According to a first aspect of this disclosure, a method for designing a decoder is provided, the decoder being designed to be located within a test circuit. The method includes: determining an initialization decoder based at least on netlist data representing a circuit under test; and modifying the connections of the decoding circuitry in the initialization decoder to obtain a target decoder for the test circuitry, the test circuitry being configured to be coupled to the circuit under test in a chip, based at least on a first test vector set for testing the circuit under test. By changing the connections of the decoder's decoding circuitry using the test vector set, a decoder with optimized input connection numbers and / or connection methods can be obtained. Since the decoder connections are optimized for the circuit under test, the number and / or complexity of coded bits associated with the input connections can be reduced compared to conventional equalized XOR gate networks. Furthermore, the combinations of coded bits received by the decoder are also optimized. Accordingly, the encoding success rate can be improved. Additionally, the overhead of computational resources can be reduced.

[0007] In one possible implementation of the first aspect, the initialization decoder includes at least one decoding layer, each decoding layer including multiple decoding circuits. Determining the initialization decoder includes: using netlist data to determine the number of scan chains in the circuit under test; using the number of scan chains to calculate the number of layers in the at least one decoding layer; using the number of scan chains and the number of layers to calculate a decoding array, the decoding array including the number of decoding circuits in each of the at least one decoding layer; and constructing the initialization decoder based on the number of layers and the decoding array. By using the number of scan chains to determine the number of layers, an appropriate number of decoding layers can be ensured, thereby reducing the hardware implementation cost of the decoder while maintaining decoding success rate, and correspondingly reducing decoding overhead.

[0008] In one possible implementation of the first aspect, the multiple decoding circuits include accumulators and comparators coupled to the accumulators. Constructing the initialization decoder includes: setting up multiple decoding layers arranged in series according to the number of layers; setting up a corresponding number of decoding circuits in each of the multiple decoding layers according to the decoding array; and connecting each comparator of the previous level decoding layer to each accumulator of the next level decoding layer to construct the initialization decoder. By using accumulators and comparators, the decoding circuits can be implemented with a relatively simple circuit structure, thereby reducing the circuit implementation cost of the decoder. Furthermore, since the decoding circuits all use the same or similar architecture, the design cost of the decoder can be reduced.

[0009] In one possible implementation of the first aspect, modifying the connections of multiple decoding circuits in the initialized decoder based at least on a first test vector set to obtain a target decoder for testing the circuit includes: expanding the first test vector set into a second test vector set based on features of the circuit under test, the features of which include at least one of the scan chain distribution of multiple scan chains of the circuit under test during the test period or the distribution of unknown states of unknown states during the test period; and modifying the connections of multiple decoding circuits in the initialized decoder using at least the second test vector set to obtain the target decoder. By expanding the test vector set, the large amount of test data required for binary neural networks can be avoided through extensive automatic test vector generation, thereby reducing testing costs and ensuring testing accuracy.

[0010] In one possible implementation of the first aspect, expanding the first test vector set into a second test vector set based on the characteristics of the circuit under test includes: determining the usage frequency of multiple scan chains during the test cycle using a scan chain distribution or an unknown state distribution; randomly generating multiple random test vectors based on the usage frequency and a predetermined power threshold; and adding multiple random test vectors to the first test vector set to generate the second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is uniformly distributed, and the specified bits represent the bits with the first value in the test vector. By adding random test vector sets based on usage frequency, a large number of random test vectors conforming to the characteristics of the test vectors can be obtained, thereby ensuring the decoding accuracy of the decoder obtained by the binary neural network.

[0011] In one possible implementation of the first aspect, expanding the first test vector set into a second test vector set based on the characteristics of the circuit under test includes: randomly merging multiple test vectors in the first test vector set to generate multiple random test vectors; adding the multiple random test vectors to the first test vector set to generate the second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is normally distributed, and the specified bits represent the bits with the first value in the test vectors. By adding random test vector sets based on random merging, a large number of random test vectors that conform to the characteristics of the test vectors can be obtained, thereby ensuring the decoding accuracy of the decoder obtained by the binary neural network.

[0012] In one possible implementation of the first aspect, modifying the connections of multiple decoding circuits in the initialized decoder using at least a second set of test vectors to obtain the target decoder includes: representing the initialized decoder using a binary neural network model; training the binary neural network model using a first set of test vectors from the second set of test vectors to obtain a candidate binary neural network; validating the candidate binary neural network using a second set of test vectors from the second set of test vectors to obtain the target binary neural network; and determining the target decoder based on the target binary neural network. By using a training-validation approach to determine the target decoder, the decoding accuracy of the target decoder is further improved.

[0013] In one possible implementation of the first aspect, training a binary neural network model using a first set of test vectors from a second set of test vectors to obtain a candidate binary neural network includes: initializing the initial connections between layers in the binary neural network model to the real number domain to obtain a continuous-domain neural model, wherein multiple weights between layers in the continuous-domain neural model are respectively located between a first value and a second value, and multiple threshold constants between layers in the continuous-domain neural model are respectively greater than the first value; iteratively performing at least once the following: training the continuous-domain neural model using the test vectors from the first set of test vectors to obtain an intermediate neural network in the real number domain; checking whether the output of the intermediate neural network satisfies the objective function value; and if the output of the intermediate neural network does not satisfy the objective function value, updating the intermediate neural network using a gradient descent algorithm to modify the values ​​of multiple weights and multiple threshold constants; and if the output of the intermediate neural network satisfies the objective function value, converting the intermediate neural network to the binary discrete domain to obtain a candidate binary neural network. By converting the binary neural network to the real number domain and training the binary neural network iteratively, candidate binary neural networks can be determined accurately and quickly.

[0014] In one possible implementation of the first aspect, converting the intermediate neural network into a binary discrete domain to obtain a candidate binary neural network includes: comparing the values ​​of multiple weights with weight thresholds respectively; if the value of a first weight among the multiple weights is lower than the weight threshold, then disconnecting the two decoding layers associated with the first weight; or if the value of a second weight among the multiple weights is lower than the weight threshold, then connecting the two decoding layers associated with the second weight. By using the values ​​of the weights to determine the connection relationships between the various decoding circuits in the decoding layers represented by the binary neural network, the target decoder can be determined in a simple and flexible manner.

[0015] In a second aspect of this disclosure, a computer-readable storage medium is provided storing a plurality of programs configured to be executed by one or more processors, the programs including instructions for performing the method of the first aspect. By using a test vector set to modify the connections of the decoder's decoding circuitry, a decoder with optimized input connection number and / or connection method can be obtained. Since the decoder connections are optimized for the circuit under test, the number and / or complexity of coded bits associated with the input connections can be reduced compared to conventional equalized XOR gate networks. Furthermore, the combination of coded bits received by the decoder is also optimized. Accordingly, the encoding success rate can be improved. Additionally, the overhead of computational resources can be reduced.

[0016] In a third aspect of this disclosure, a computer program product is provided, comprising a plurality of programs configured to be executed by one or more processors, the programs including instructions for the method of the first aspect. By using a test vector set to modify the connections of the decoder's decoding circuitry, a decoder with optimized input connection number and / or connection method can be obtained. Since the decoder connections are optimized for the circuit under test, the number and / or complexity of coded bits associated with the input connections can be reduced compared to conventional equalized XOR gate networks. Furthermore, the combination of coded bits received by the decoder is also optimized. Accordingly, the encoding success rate can be improved. Additionally, computational resource overhead can be reduced.

[0017] In a fourth aspect of this disclosure, an electronic device is provided. The electronic device includes: one or more processors; and a memory including computer instructions, which, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of the first aspect. By using a test vector set to modify the connections of the decoder's decoding circuitry, a decoder with optimized input connection number and / or connection method can be obtained. Since the decoder connections are optimized for the circuit under test, the number and / or complexity of the encoded bits associated with the input connections can be reduced compared to conventional equalized XOR gate networks. Furthermore, the combination of encoded bits received by the decoder is also optimized. Accordingly, the encoding success rate can be improved. In addition, the overhead of computational resources can be reduced.

[0018] In a fifth aspect of this disclosure, an electronic device is provided. The electronic device includes an initialization unit and a modification unit. The initialization unit is used to determine an initialization decoder based at least on netlist data representing a circuit under test (DUT). The modification unit is used to modify the connections of the decoding circuits in the initialization decoder based at least on a first test vector set used to test the DUT to obtain a target decoder for the test circuit, the test circuit being configured to be coupled to the DUT in a chip. By changing the connections of the decoder's decoding circuits using the test vector set, a decoder with optimized input connection number and / or connection method can be obtained. Since the decoder connections are optimized for the DUT, the number and / or complexity of coded bits associated with input connections can be reduced compared to conventional equalized XOR gate networks. Furthermore, the combination of coded bits received by the decoder is also optimized. Accordingly, the encoding success rate can be improved. Additionally, the overhead of computational resources can be reduced.

[0019] In one implementation of the fifth aspect, the initialization decoder includes at least one decoding layer, each decoding layer including multiple decoding circuits. The initialization unit is further configured to: determine the number of scan chains in the circuit under test using netlist data; calculate the number of layers in the at least one decoding layer using the number of scan chains; calculate a decoding array using the number of scan chains and the number of layers, the decoding array including the number of decoding circuits in each of the at least one decoding layer; and construct the initialization decoder based on the number of layers and the decoding array. By using the number of scan chains to determine the number of layers, it is possible to ensure that an appropriate number of decoding layers are provided, thereby reducing the hardware implementation cost of the decoder while ensuring decoding success rate, and correspondingly reducing decoding overhead.

[0020] In one implementation of the fifth aspect, the multiple decoding circuits include accumulators and comparators coupled to the accumulators. The initialization unit is further configured to: set up multiple decoding layers arranged in series according to the number of layers; set up a corresponding number of decoding circuits in each of the multiple decoding layers according to the decoding array; and connect each comparator of the previous level decoding layer to each accumulator of the next level decoding layer to construct an initialization decoder. By using accumulators and comparators, the decoding circuits can be implemented with a relatively simple circuit structure, thereby reducing the circuit implementation cost of the decoder. Furthermore, since the decoding circuits all use the same or similar architecture, the design cost of the decoder can be reduced.

[0021] In one implementation of the fifth aspect, the modification unit is further configured to: expand a first test vector set into a second test vector set based on the characteristics of the circuit under test, wherein the characteristics of the circuit under test include at least one of the scan chain distribution of multiple scan chains of the circuit under test in the test cycle or the unknown state distribution of unknown states in the test cycle; and modify the connections of multiple decoding circuits in the initialized decoder using at least the second test vector set to obtain the target decoder. By expanding the test vector set, the large amount of test data required for binary neural networks can be avoided through a large number of automatic test vector generation, thereby reducing testing costs and ensuring testing accuracy.

[0022] In one implementation of the fifth aspect, the modification unit is further configured to: determine the usage frequency of multiple scan chains during a test period using a scan chain distribution or an unknown state distribution; randomly generate multiple random test vectors based on the usage frequency and a predetermined power threshold; and add multiple random test vectors to a first test vector set to generate a second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is uniformly distributed, and the specified bits represent the bits with the first value in the test vector. By adding random test vector sets based on usage frequency, a large number of random test vectors conforming to the characteristics of test vectors can be obtained, thereby ensuring the decoding accuracy of the decoder obtained by the binary neural network.

[0023] In one implementation of the fifth aspect, the modification unit is further configured to: randomly merge multiple test vectors in the first test vector set to generate multiple random test vectors; and add the multiple random test vectors to the first test vector set to generate a second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is normally distributed, and the specified bits represent the bits with the first value in the test vector. By adding random test vector sets based on random merging, a large number of random test vectors that conform to the characteristics of test vectors can be obtained, thereby ensuring the decoding accuracy of the decoder obtained by the binary neural network.

[0024] In one implementation of the fifth aspect, the modification unit is further configured to: initialize the decoder using a binary neural network model representation; train the binary neural network model using a first set of test vectors in a second set of test vectors to obtain a candidate binary neural network; validate the candidate binary neural network using a second set of test vectors in the second set of test vectors to obtain a target binary neural network; and determine the target decoder based on the target binary neural network. By using a training-validation approach to determine the target decoder, the decoding accuracy of the target decoder is further improved.

[0025] In one implementation of the fifth aspect, the modification unit is further configured to: initialize the initial connections between the layers of the binary neural network model to the real number domain to obtain a continuous domain neural model, wherein multiple weights between the layers of the continuous domain neural model are respectively located between a first value and a second value, and multiple threshold constants between the layers of the continuous domain neural model are respectively greater than the first value; iteratively perform the following at least once: train the continuous domain neural model using a test vector set from a first set of test vectors to obtain an intermediate neural network in the real number domain; check whether the output of the intermediate neural network satisfies the objective function value; and if the output of the intermediate neural network does not satisfy the objective function value, update the intermediate neural network using a gradient descent algorithm to modify the values ​​of multiple weights and multiple threshold constants; and if the output of the intermediate neural network satisfies the objective function value, convert the intermediate neural network into a binary discrete domain to obtain a candidate binary neural network. By converting the binary neural network into the real number domain and training the binary neural network iteratively, candidate binary neural networks can be determined accurately and quickly.

[0026] In one implementation of the fifth aspect, the modification unit is further configured to: compare the values ​​of multiple weights with a weight threshold respectively; if the value of the first weight among the multiple weights is lower than the weight threshold, then disconnect the two decoding layers associated with the first weight; or if the value of the second weight among the multiple weights is lower than the weight threshold, then connect the two decoding layers associated with the second weight. By using the values ​​of the weights to determine the connection relationships between the various decoding circuits in the decoding layers represented by the binary neural network, the target decoder can be determined in a simple and flexible manner.

[0027] In a sixth aspect of this disclosure, a circuit for testing a circuit under test is provided. The circuit includes a first decoder coupled to the circuit under test and configured to decode a plurality of first coded bits into a plurality of first decoded bits. The first decoder includes at least one decoding layer, each of the at least one decoding layer including a plurality of decoding circuits, each decoding circuit including an accumulator and a comparator coupled to the accumulator. Because the connections of the decoder are optimized for the circuit under test, the number and / or complexity of coded bits associated with the input connections can be reduced compared to conventional equalized XOR gate networks. Furthermore, the combinations of coded bits received by the decoder are also optimized. Accordingly, the encoding success rate can be improved. Additionally, the overhead of computational resources can be reduced.

[0028] In one implementation of the sixth aspect, at least one decoding layer includes: a first decoding layer configured to output a plurality of first intermediate bits based on a plurality of first encoded bits; and a second decoding layer configured to output a plurality of first decoded bits based on a plurality of first intermediate bits, wherein the number of the plurality of first decoded bits is greater than the number of the plurality of first intermediate bits.

[0029] In one implementation of the sixth aspect, each decoding layer in at least one decoding layer includes a first decoding circuit and a second decoding circuit, wherein the connections of the first decoding circuit and the second decoding circuit are different.

[0030] In one implementation of the sixth aspect, multiple decoding circuits of the last level decoding layer in at least one decoding layer are coupled to multiple scan chains of the circuit under test via multiple first AND gates; or multiple decoding circuits of the last level decoding layer in at least one decoding layer are coupled to multiple second AND gates via multiple scan chains.

[0031] In one implementation of the sixth aspect, the circuit further includes a second decoder coupled to the circuit under test and configured to decode a plurality of second encoded bits into a plurality of second decoded bits. The second decoder includes at least one decoding layer, each decoding layer including a plurality of decoding circuits, each decoding circuit including an accumulator and a comparator coupled to the accumulator. By using accumulators and comparators, the decoding circuit can be implemented with a relatively simple circuit structure, thereby reducing the circuit implementation cost of the decoder. Furthermore, since the decoding circuits all use the same or similar architecture, the design cost of the decoder can be reduced.

[0032] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0033] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1 A schematic circuit diagram of a conventional decoder is shown.

[0034] Figure 2 A schematic diagram of an environment in which some embodiments of this disclosure may be implemented is shown.

[0035] Figure 3 A schematic diagram of an initial codec system according to some embodiments of the present disclosure is shown.

[0036] Figure 4 A schematic diagram of a target encoding / decoding system according to some embodiments of the present disclosure is shown.

[0037] Figure 5 A flowchart illustrating a method for designing a test circuit according to some embodiments of the present disclosure is shown.

[0038] Figure 6 A flowchart illustrating a method for obtaining a candidate binary neural network according to some embodiments of the present disclosure is shown.

[0039] Figure 7 A schematic block diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0040] Figure 8 A schematic block diagram of an example device that can be used to implement embodiments of the present disclosure is shown. Detailed Implementation

[0041] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0042] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. The term "and / or" indicates at least one of the two items associated therewith. For example, "A and / or B" means A, B, or A and B. Other explicit and implicit definitions may also be included below.

[0043] It should be understood that the technical solutions provided in the embodiments of this application may not be repeated in the following description of specific embodiments, but it should be regarded as that there are mutual references between these specific embodiments and they can be combined with each other.

[0044] In the electronic design automation (EDA) process for chips, users input configurations into EDA software, which generates logic circuits. The chips are then fabricated and manufactured. During chip testing, the chip can be mounted in an ATE (Automatic Design Equipment) system, and the ATE inputs test stimuli to the IC chip's input pins. By comparing the responses of the chip's output pins with the expected responses, the chip's qualification can be determined. As mentioned above, with the continuous increase in chip integration and complexity, the required test vector set also grows rapidly. This leads to an increase in chip testing costs. To control testing costs, test compression techniques have been proposed to ensure test coverage while compressing test vectors. Test compression techniques are based on scan chains. Scan chain technology essentially connects flip-flops in sequential circuits into multiple "shift registers," where the input and output values ​​of each shift register can be observed individually.

[0045] The feasibility of the compression test is based on the fact that a single raw test vector generated by ATPG contains the input values ​​of all shift registers on the scan chain, but only a small portion of the input values ​​on these shift registers are valid. Therefore, the raw test vector can be compressed and decompressed by the excitation decompressor to recover the valid values. Additionally, the output values ​​on the scan chain can also be compressed by the compactor. The compressed output value is sent to the ATE via an output pin, and the ATE compares the compressed output value with the expected value to locate the shift register position in the scan chain where the error occurred.

[0046] In test compression techniques, the compression ratio of the input and output values ​​of the scan chain shift register can often reach hundreds or thousands, thus greatly reducing the storage size of the test vector. However, this also introduces two of the most critical issues in the field of test compression. The first issue concerns power consumption. The original input values ​​of the shift register have very few valid values ​​(exhibiting sparsity), so the shift power consumption on the scan chain during the input phase is also very low. However, the input compressed values ​​often lose their sparsity after decompression. In the process of directly shifting the decompressed values ​​to the corresponding shift register, unacceptable shift power consumption will be generated. This will cause a decrease in chip test yield, a reduction in test stability, and may even lead to the chip overheating and burning out during testing. The second issue concerns the masking of unknown states (X states) generated during the test. Due to the unknown functions of some circuit modules, some unpredictable unknown values ​​will be output, which are called X states. Some circuits that generate X states are distributed on the scan chain output values. During compression by the compression module, these X states can mask the valid values ​​of other circuits being compressed simultaneously, resulting in unobservable locations in the circuit. This can lead to decreased fault coverage and an increase in the number of test vectors.

[0047] The conventional approach addresses these two issues by introducing a low-power control module and a mask control module, respectively. Functionally similar, both are decoders. The low-power control module's decoder output controls the input value of the scan chain. When the decoder output is 0, a fixed value is input to the shift register of the controlled scan chain; otherwise, the output value of the decompression module is input to the shift register of the controlled scan chain. The mask control module's decoder output controls the input value of the corresponding scan chain to the compression module. When the decoder output is 0, the input value of the controlled scan chain to the compression module is clamped to a fixed value; otherwise, the output value of the controlled scan chain is input to the compression module. The decoder outputs of these two control modules are connected to each scan chain, and setting the decoder output value to 1 or 0 enables the corresponding scan chain to be turned on or off. The low-power control module enables scan chains containing valid input values ​​to allow the excitation decompression module to input shift values ​​into the scan chains of the circuit under test (DUT), while the mask control module disables scan chains containing X-state outputs to prevent X-state outputs from the scan chains in the DUT. For example, in some conventional schemes, an XOR gate network can be used to form the decoder.

[0048] Figure 1 A schematic circuit diagram of a conventional decoder 100 is shown. The decoder 100 is a balanced logic gate network, and the logic gates used are XOR gates. The number of input connections for each logic gate in the balanced logic gate network is the same, for example, in... Figure 1In this configuration, each XOR operation has three input connections. Figure 1 In the decoder 100, there are 6 encoded bits X1, X2...X6 and 12 decoded bits Y1, Y2...Y12. Each XOR has three input connections that receive three encoded bits from the 6 encoded bits X1, X2...X6 respectively. Each XOR generates one of the 12 decoded bits Y1, Y2...Y12 by performing an XOR operation on the logical values ​​of the three encoded bits. In some embodiments, the logic gate network can also be based on XOR and AND gates. In general, this structure uses the value of the XOR operation on the three encoded bits to represent the control state of the corresponding scan chain. For low-power control modules, when the user-set input shift power threshold is low, this structure uses more encoded bits and further performs AND operations on multiple output values ​​of the XOR network structure to control a scan chain. However, this balanced XOR gate network structure provides equal control for each scan chain, but the actual frequency of use of each scan chain in the automatic test vector generation process is different. Therefore, using this type of balanced logic gate network can lead to a waste or inadequacy of encoding capacity. Furthermore, to ensure encoding success rate, this structure uses a large number of encoding bits, resulting in significant consumption of computational resources, including hardware and software overhead.

[0049] In some embodiments of this disclosure, a circuit for testing a circuit under test is provided. The circuit includes at least one decoder. Each decoder includes at least one decoding layer, and each decoding layer includes multiple decoding circuits. Each decoding circuit includes an accumulator and a comparator coupled to the accumulator. By optimizing the connections of each decoding circuit in the decoding layer, for example, by optimizing the connections of each decoding circuit using a binary neural network (BNN), encoded data with fewer encoded bits can be decoded, thereby achieving stronger encoding capabilities. Compared to conventional XOR network structures, the test circuit of this disclosure optimizes the control strength of each scan chain, thus reducing the use of encoded bits, improving encoding capabilities, and avoiding waste. Furthermore, since one of the prerequisites for optimization can be encoding success rate, the test circuit of this disclosure uses relatively fewer encoded bits, and the consumption of computational resources such as hardware and software overhead is relatively small.

[0050] Figure 2 Schematic diagrams are shown illustrating environments in which some embodiments of this disclosure can be implemented. For example... Figure 2As shown, chip 200 includes a circuit under test (DUT) 11, a low-power shift register 16, a mask register 18, a decompression module 12, a compression module 13, a low-power controller 14, a mask controller 15, and multiple AND gates 7-1, 7-2…..7-N and multiple AND gates 9-1, 9-2…9-N, where N represents an integer greater than 1. In chip 200, the low-power shift register 16, mask register 18, decompression module 12, compression module 13, low-power controller 14, mask controller 15, and multiple AND gates 7-1, 7-2…..7-N and multiple AND gates 9-1, 9-2…9-N are used to test the DUT 11. Therefore, in one embodiment, the test circuit of chip 200 may include at least one of the low-power controller 14 or the mask controller 15. In another embodiment, the test circuit of chip 200 may further include a low-power shift register 16, a mask register 18, a decompression module 12, a compression module 13, and multiple AND gates 7-1, 7-2…7-N and multiple AND gates 9-1, 9-2…9-N. During actual testing of chip 200, the ATE inputs the ATPG test vector to the low-power shift register 16 of chip 200 through a small number of input pins. The ATPG test vector contains the input compressed value of the decompression module 12, i.e., the compressed seed, the encoded value of the low-power controller 14, and the encoded value of the mask controller 15, etc. The input compressed value is injected into the decompression module 12 via the low-power shift register 16 and the mask register 18. The encoded value of the low-power controller 14 is injected into the low-power controller 14 via the low-power shift register 16, and the encoded value of the mask controller 15 is injected into the mask controller 15 via the low-power shift register 16 and the mask register 18. During the input phase, the low-power controller 14 decodes the encoded value to open the appropriate scan chain. The decompression module 12 decompresses the input compressed value of the low-power shift register 16 and, under the control of the low-power controller 14, fills the decompressed value into the corresponding shift register through shifting.

[0051] During the output stage, the mask controller 15 decodes the encoded value, masks the X-state in the scan chain output value by using the decoded bit value, and sends the processed output value to the compression module 13 for compression. In one embodiment, the circuit under test 11 includes multiple scan chains 11-1, 11-2...11-N (hereinafter individually or collectively referred to as 11), the number of scan chains corresponding to multiple AND gates 7-1, 7-2...7-N (hereinafter individually or collectively referred to as 7) and multiple AND gates 9-1, 9-2...9-N (hereinafter individually or collectively referred to as 9). Each scan chain may include one or more sequential logic circuits in the circuit under test, such as registers. The sequential logic XOR gate network generates a shift output in response to a shift output. The low-power controller 14 includes a low-power register 141 and a decoder 142, which generates control signals through decoding to control the on or off of one or more AND gates among AND gates 7-1, 7-2...7-N. For example, over multiple cycles, decoder 142 can continuously generate logic values ​​"1" for AND gate 7-1, causing the decompressed value to be successively shifted and input to scan chain 11-1. Simultaneously, decoder 142 can output "0" to turn off AND gates 7-2…7-N, allowing scan chains 11-2…11-N to continuously receive "0". Since scan chains 11-2…11-N do not change logic values, the sequential logic gates in the chip do not operate. Because the sequential logic gates do not operate, power consumption during testing can be reduced. Mask controller 15 includes mask register 151 and mask decoder 152. Mask decoder 152 generates control signals through decoding to control the on / off state of one or more AND gates 9-1, 9-2…9-N. Similarly, mask decoder 152 can generate control signals through decoding to turn off the AND gates 9-1, 9-2…9-N corresponding to the scan chain with state X.

[0052] It should be understood that the embodiments of this application do not limit the structure of the decompression module 12. The decompression module 12 can be any circuit capable of expanding a small number of test stimuli into a large number of scan chain test vectors and outputting the test vectors. The decompression module 12 can be based on a random signal generator, for example. In some embodiments of this disclosure, the decompression module 12 may include a pseudo-random sequence generator 121 and a phase shifter 122 based on a logic gate network. The pseudo-random sequence generator 121 can decompress the injected input compressed value for the first time to generate a pseudo-random sequence with a larger bit width. The phase shifter 122 decodes the pseudo-random sequence to obtain the shift values ​​of each scan chain corresponding to each period. For a given pseudo-random sequence bit width, the pseudo-random sequence state space generated by the pseudo-random sequence generator 121 is preferred, and the maximum number of pseudo-random sequences is fixed. This also determines the upper limit of the solution space that the decompression structure can utilize. Therefore, designing a better phase shifter 122 under the premise of a finite and fixed solution space of the decompression structure is also a core issue of the decompression module. In some embodiments of this disclosure, a phase shift code generator 122 based on an unbalanced logic gate network is provided, wherein at least some of the logic gates in the unbalanced logic gate network may have different numbers of input connections.

[0053] Similarly, this application embodiment does not limit the structure of the compression module 13. The compression module 13 can be any circuit capable of receiving test responses and performing logical operations on the received test responses to output them from a small number of output channels. The compression module 13 can be, for example, a compression module based on a multiple-input signature register (MISR) or a logic gate network such as an XOR gate network.

[0054] Figure 3 A schematic diagram of an initial encoding / decoding system 300 according to some embodiments of the present disclosure is shown. The initial encoding / decoding system 300 can be designed using an electronic device such as a computer. The initial encoding / decoding system 300 includes an initial encoding input unit 310, an encoder 320, an initial decoding input unit 330, a decoder 340, and an initial decoding output unit 350. The initial encoding input unit 310 includes inputs I11, I12, I13, I14, I15, I16...I1A of a plurality of initial bits to receive the plurality of initial bits, where A represents an integer greater than 1. The plurality of initial bits may be derived from a first test vector set, which may be obtained from an original test vector set including a plurality of test data. A specific method for forming the first test vector set will be described below.

[0055] The encoder 320 includes at least one coding layer, wherein, in the case of multiple coding layers, the multiple coding layers are connected in series to form multiple coding layers arranged in a hierarchical manner. Figure 3 The encoder 320 is shown to include two coding layers 321 and 322. It is understood that this is merely illustrative and not intended to limit the scope of this disclosure. The encoder 320 may include other numbers of coding layers, such as one coding layer or three or more coding layers. The first coding layer 321 includes multiple coding circuits X11, X12, X13, X14…X1B, and the second coding layer 322 includes multiple coding circuits X21, X22…X2C, where B and C represent integers greater than 1.

[0056] Each coding layer includes multiple coding circuits. In one embodiment, the multi-level coding layers in encoder 320 can be arranged in a manner that decreases progressively in the number of coding circuits. For example, the number of coding circuits included in the first-level coding layer 321 is greater than the number of coding circuits included in the second-level coding layer 322. That is, the value of B is greater than the value of C.

[0057] The input of each initial bit in the initial encoding input unit 310 is provided to multiple encoding circuits in the first-level encoding layer 321 of the encoder 320. For example, the input of the first initial bit I11 is provided to each encoding circuit in the first-level encoding layer 321. The input of the second initial bit I12 is also provided to each encoding circuit in the first-level encoding layer 321, and so on. (The remaining text is incomplete and likely refers to a separate illustration.) Figure 3 The connections of the multiple initial bit inputs I12, I13, I14, I15, I16...I1A to each encoding circuit in the first-level encoding layer 321 are not shown, but it is understood that such connections exist in the initial encoding and decoding system 300.

[0058] Similarly, each coding circuit in the first-level coding layer 321, such as the first coding circuit X11, is connected to each of the multiple coding circuits X21, X22...X2C in the second-level coding layer 322. Figure 3 In encoder 320, each encoding circuit includes an accumulator and a comparator. For example, the first encoding circuit X11 in the first-level encoding layer 321 includes a first accumulator X111 and a first comparator 112 connected to the first accumulator X111. The first accumulator X111 can accumulate multiple input values, and the first comparator 112 can compare the accumulated value with a predetermined value and output the comparison result to the second-level encoding layer 322. Multiple encoding circuits in the second-level encoding layer 322 can perform similar operations.

[0059] The last coding layer in encoder 320, in Figure 3The second-level coding layer 322 provides multiple encoded outputs to the initial decoding input unit 330. The initial decoding input unit 330 includes multiple initial intermediate bits Z1, Z2...ZD, where D represents an integer greater than 1. In one embodiment, the value of D is less than the value of C. Alternatively, the value of D can be equal to the value of C.

[0060] Decoder 340 includes at least one decoding layer, wherein, in the case of multiple decoding layers, the multiple decoding layers are connected in series to form multiple decoding layers arranged in a hierarchical manner. Figure 3 The decoder 340 is shown to include two decoding layers 341 and 342. It is understood that this is merely illustrative and not intended to limit the scope of this disclosure. The decoder 340 may include other numbers of decoding layers, such as one decoding layer or three or more decoding layers. The first decoding layer 341 includes multiple encoding circuits Y11, Y12…Y1E, and the second decoding layer 342 includes multiple decoding circuits Y21, Y22, Y23, Y24…Y2F, where E and F represent integers greater than 1.

[0061] Each decoding layer includes multiple decoding circuits. In one embodiment, the multi-level coding layers in decoder 340 can be arranged in a progressively increasing manner in terms of the number of decoding circuits. For example, the number of decoding circuits included in the first decoding layer 341 is less than the number of decoding circuits included in the second decoding layer 342. That is, the value of E is less than the value of F.

[0062] The input of each initial intermediate bit in the initial decoding input unit 330 is provided to each of the multiple decoding circuits Y11, Y12...Y1E in the first decoding layer 341 of the decoder 340. For example, the input of the first initial intermediate bit Z1 is provided to each decoding circuit in the first decoding layer 341. The input of the second initial bit Z2 is also provided to each decoding circuit in the first decoding layer 341, and so on. (The remaining text is for illustrative purposes only.) Figure 3 The connections of the inputs Z2...ZD of the multiple initial intermediate bits to each decoding circuit in the first decoding layer 341 are not shown, but it is understood that such connections exist in the initial codec system 300.

[0063] Similarly, each decoding circuit in the first decoding layer 341, such as the first decoding circuit Y11, is connected to each of the multiple decoding circuits Y21, Y22...Y2F in the second decoding layer 342. Figure 3In the decoder 340, each decoding circuit includes an accumulator and a comparator. For example, the first decoding circuit Y11 in the first decoding layer 341 includes a first accumulator X111 similar to the first encoding circuit X11 and a first comparator 112 connected to the first accumulator X111. The first accumulator X111 can accumulate multiple input values, and the first comparator 112 can compare the accumulated value with a predetermined value and output the comparison result to the second decoding layer 342. Multiple decoding circuits in the second decoding layer 342 can perform similar operations.

[0064] The last decoding layer in decoder 340, in Figure 3 The second decoding layer 342 provides multiple decoding outputs to the initial decoding output unit 350. The initial decoding output unit 350 includes multiple initial output bits O11, O12, O13, O14, O15, O16...O1G, where G represents an integer greater than 1. In one embodiment, the value of G is greater than the value of F. Alternatively, the value of G can be equal to the value of F. Since the initial decoding output unit 350 corresponds to multiple scan chains in the circuit under test 11, the value of G can be the same as the number of scan chains in the circuit under test 11.

[0065] exist Figure 3 In the initial codec system 300, in one embodiment, it can be modified... Figure 3 The connection relationships of the various encoding and decoding circuits in the initial encoding / decoding system 300 are used to obtain the target encoding / decoding system. For example, BNN can be used to modify the connection relationships of the encoding and decoding circuits in the initial encoding / decoding system 300 to obtain an optimized target encoding / decoding system. Figure 4 A schematic diagram of a target encoding / decoding system 400 according to some embodiments of the present disclosure is shown. The target encoding / decoding system 400 can be designed using electronic devices such as computers. The target encoding / decoding system 400 includes a target encoding input unit 410, an encoder 420, a target decoding input unit 430, a decoder 440, and a target decoding output unit 450. Figure 4The target encoding / decoding system 400 has a similar architecture to the initial encoding / decoding system 300, except that the connection methods of the various encoding and decoding circuits are optimized. For example, the first encoded bit in the target encoding input unit 410 is only provided to the first encoding circuit X11 and encoding circuit X1B in the first encoding layer 421. For example, the output of the first encoding circuit X11 in the first encoding layer 421 is optimized to be provided only to the encoding circuits X21, X22, and X2C in the second encoding layer 422. For example, the output of the encoding circuit X21 in the second encoding layer 422 is optimized to be provided only to the decoding inputs Z2 and ZD in the target decoding input unit 430. For example, the output of the target decoding input Z1 in the target decoding input unit 430 is optimized to be provided only to the decoding circuits Y11, Y12, and Y1E in the first decoding layer 441, and the output of the decoding circuit Y11 in the first decoding layer 441 is optimized to be provided only to the decoding circuits Y21, Y24, and Y2F in the second decoding layer 442. For example, the output of the decoding circuit Y21 in the second decoding layer 442 is optimized to be provided only to the target decoding outputs O11 and O1G in the target decoding output unit 450. It is understood that the optimized connections illustrated above are for illustrative purposes only and are not intended to limit the scope of this disclosure. Different connection relationships may be used for different circuits under test 11. Furthermore, although in Figure 3 The target encoding input unit 410 and encoder 420 are shown separately, and the target decoding output unit 450 and decoder 440 are shown separately, but this is only illustrative and not intended to limit the scope of this disclosure. In some embodiments, the target encoding input unit 410 may be part of the encoder 420, and the target decoding output unit 450 may be part of the decoder 440.

[0066] Decoder 440 includes at least one decoding layer, wherein, in the case of multiple decoding layers, the multiple decoding layers are connected in series to form multiple decoding layers arranged in a hierarchical manner. Figure 4 The decoder 440 is shown to include two decoding layers 441 and 442. It is understood that this is merely illustrative and not intended to limit the scope of this disclosure. The decoder 440 may include other numbers of decoding layers, such as one decoding layer or three or more decoding layers. The first decoding layer 441 includes multiple encoding circuits Y11, Y12…Y1E, and the second decoding layer 442 includes multiple decoding circuits Y21, Y22, Y23, Y24…Y2F, where E and F represent integers greater than 1.

[0067] Each decoding layer includes multiple decoding circuits. In one embodiment, the multi-level coding layers in decoder 440 can be arranged in a progressively increasing manner in terms of the number of decoding circuits. For example, the number of decoding circuits included in the first decoding layer 441 is less than the number of decoding circuits included in the second decoding layer 442. That is, the value of E is less than the value of F.

[0068] The input of each first encoded bit in the target decoding input unit 430 is provided to multiple decoding circuits Y11, Y12, and Y1E in the first decoding layer 341 of the decoder 340. The input of the first encoded bit Z2 is similarly provided to at least one decoding circuit in the first decoding layer 341, and so on. (The remaining text is incomplete and likely refers to a separate illustration.) Figure 4 The connections of the inputs Z2...ZD of the multiple first encoded bits to each decoding circuit in the first decoding layer 441 are not shown, but it is understood that such connections exist in the target encoding and decoding system 400.

[0069] Similarly, each decoding circuit in the first decoding layer 441 is selectively connected to at least one decoding circuit in the second decoding layer 342. Figure 4 In the decoder 440, each decoding circuit includes an accumulator and a comparator, and... Figure 3 Similarly, the last decoding stage in decoder 440... Figure 4 The second decoding layer 442 provides multiple first decoded bits to the target decoding output unit 450. The target decoding output unit 450 includes multiple target output bits O11, O12, O13, O14, O15, O16...O1G, where G represents an integer greater than 1. In one embodiment, the value of G is greater than the value of F. Alternatively, the value of G can be equal to the value of F. Since the target decoding output unit 450 corresponds to multiple scan chains in the circuit under test 11, the value of G can be the same as the number of scan chains in the circuit under test 11.

[0070] To ensure encoding success rate, during the bit reduction encoding process from the target encoding input 410 to the target decoding input 430 and the bit increase decoding process from the target decoding input 430 to the target decoding output 450, the encoding / decoding system 400 needs to recover the bit data output from the target decoding output 450 as accurately as possible from the bit data input at the target encoding input 410. When this requirement is met, the decoder 440 obtained by the electronic device can be considered a satisfactory decoder. Based on this, the design of the decoder 440 can be integrated into a chip design including the circuit under test 11 and implemented in chip manufacturing. For example, a target decoder such as decoder 440 can be used to implement low-power decoder 142 and / or mask decoder 152. In some embodiments, multiple alternative decoders can be designed using the electronic device, and the target decoder can be selected based on additional or other factors, as specifically described below.

[0071] Figure 5 A schematic flowchart of a method 500 for designing a test circuit according to some embodiments of the present disclosure is shown. Method 500 can be performed by an electronic device such as a computer. It will be understood that the above is aimed at... Figures 2-4 The described aspects can be selectively applied to method 500. The following will combine... Figures 2-4 The features in the method are used to describe method 500.

[0072] In step 502, the electronic device can determine an initialization decoder based at least on netlist data representing the circuit under test 11. The netlist data can describe various characteristics of the circuit, such as the properties of individual devices in the circuit and their interconnections. For example, the number of scan chains used for testing in the circuit under test 11 can be determined based on the netlist data. In one embodiment, the initialization decoder includes at least one decoding layer, and each decoding layer includes multiple decoding circuits. For example, the initialization decoder could be... Figure 3 The decoder 340 is used in the process. Therefore, in one embodiment, the initialization decoder can be determined based on the number of scan chains.

[0073] In one embodiment, the electronic device can use netlist data to determine the number N of scan chains in the circuit under test. The number N of scan chains can be used to determine... Figure 3 The number of coding layers L in the encoder 320 of the coding and decoding system 300 shown. E The number of decoding layers L in decoder 340 D For example, the number of coding layers L can be calculated using the following equation (1). E and the number of decoding layers L D .

[0074] L E =LD =log (N / D0) (1) Where D0 represents a predetermined value, which can be preset based on the circuit under test 11. Alternatively, the number of layers can also be determined using other methods.

[0075] Electronic devices can then use the number of scan chains N and the number of layers L. E or L D The encoding or decoding array is calculated. The encoding array includes the number of encoding circuits in at least one encoding layer in each encoding layer, and the decoding array represents the number of decoding circuits in at least one decoding layer in each decoding layer. In one embodiment, the layer relationship of the encoder can be determined using the following formula (2).

[0076] (2) Where d el Let d represent the number of encoding circuits in the el-th layer, and d el+1 This represents the number of coding circuits in the (el+1)th layer. Since the number of coding circuits in each layer is different (decreasing progressively), a coding array can be created to represent the number of coding circuits in each layer.

[0077] In one embodiment, the following equation (3) can be used to determine the layer relationship of the decoder.

[0078] (3) Where d dl Let d represent the number of decoding circuits in the dl-th layer, and d dl+1 This represents the number of decoding circuits in the (dl+1)th layer. Since the number of decoding circuits in each layer is different (increasing progressively), a decoding array can be created to represent the number of decoding circuits in each layer.

[0079] Alternatively, other methods can be used to determine the number of encoding or decoding circuits in each layer. This disclosure does not limit this. Since each decoding and encoding circuit has a substantially similar structure, such as a series-coupled accumulator and comparator, the electronic device can construct an initialization decoder based on the number of layers and the decoding array, or an initialization encoder based on the number of layers and the encoding array.

[0080] In one embodiment, the multiple decoding circuits include an accumulator and a comparator coupled to the accumulator. The electronic device can be configured according to the number of layers L. DThe electronic device sets up multiple decoding layers arranged in series. Based on the decoding array, the electronic device sets up a corresponding number of decoding circuits in each of the multiple decoding layers. Furthermore, the electronic device can connect each comparator in the previous decoding layer to each accumulator in the next decoding layer to construct an initialization decoder. It can be understood that the electronic device can be similarly configured for an encoder.

[0081] In 504, the electronic device can modify the connections of multiple decoding circuits in an initialized decoder, at least based on a first set of test vectors used to test the circuit under test, to obtain a target decoder for testing the circuit. The test circuits are configured to be coupled to the circuit under test within the chip. In one embodiment, the target decoder may be, for example, a... Figure 4 The target decoder 440. Additionally, a target encoder, such as a target encoder 420, may also be available. It is understood that in one specific implementation, since the circuit under test 11 only needs to be tested by the decoder 440, and the actual test vectors can be directly provided to the decoder 440, the design of the encoder 420 may not be integrated into the chip design including the circuit under test 11 in one embodiment. In other words, the encoder 420 can be implemented in software within the electronic device without being implemented as hardware circuitry. The decoder 440 can be implemented in the chip as a low-power decoder 142 or a mask decoder 152. In one embodiment, the first test vector set is, for example, automatic test pattern generation (ATPG) data.

[0082] To obtain the target decoder 440, in one embodiment of this disclosure, a Block Neural Network (BNN) can be used to optimize the connection relationships of the decoding circuits of the initial decoder 340. BNNs typically require a large amount of training data. However, ATPG data obtained by fault sampling of the original circuit under test typically includes multiple test data packets. Such a large amount of test data is often insufficient for BNN training. Using ATPG data that meets the BNN training requirements would incur significant sampling costs and time, which is generally undesirable. Therefore, in some embodiments of this disclosure, a first test vector set, such as ATPG data, can be augmented to obtain a second test vector set for BNN training. ATPG data includes, for example, scan chain distributions and / or unknown state distributions. For the low-power decoder 142, the connection relationships of the multiple decoding circuits used to form the low-power decoder 142 can be modified using the scan chain distribution of the scan chain of the circuit under test 11 during the test cycle to obtain the target decoder for forming the low-power decoder 142. For the mask decoder 152, the connection relationships of the multiple decoding circuits used to form the mask decoder 152 can be modified respectively using the unknown state distribution in the test cycle. Furthermore, the connection relationships of the multiple decoding circuits used to form the mask decoder 152 can also be modified respectively using the unknown state distribution and the second test vector set to obtain the target decoder used to form the mask decoder 152.

[0083] To expand the first test vector set into a second test vector set, in one embodiment, for the low-power decoder 142, the electronic device can determine the usage frequency of multiple scan chains during the test cycle using a scan chain distribution or an unknown state distribution, randomly generate multiple random test vectors based on the usage frequency and a predetermined power threshold, and add multiple random test vectors to the first test vector set to generate the second test vector set. In one embodiment, the proportion of specified bits in the test vectors in the second test vector set is uniformly distributed. A specified bit represents a bit in the test vector that has the first value, such as the logic value "1". In other words, the specified bits satisfy the uniform distribution shown in equation (4) below.

[0084] (4) Where S represents a specified bit and Pth represents a predetermined power threshold. Therefore, the first test vector set can be randomly expanded to the second test vector set by uniformly distributing the specified bits according to the usage frequency of the scan chains in the first test vector set. The predetermined power threshold represents the maximum number of scan chains that can be turned on in one cycle. This is because exceeding this threshold results in excessive energy being injected into the chip under test, which may cause damage or failure of the chip.

[0085] In another embodiment, to expand the first test vector set into a second test vector set, the electronic device can randomly merge multiple test vectors from the first test vector set to generate multiple random test vectors, and add multiple random test vectors to the first test vector set to generate the second test vector set. The proportion of specified bits in the test vectors of the second test vector set is normally distributed, where a specified bit represents a bit in the test vector that has the first value, such as a bit with the logic value "1". The specified bits can satisfy the normal distribution shown in equation (5) below.

[0086] (5) Where S represents the specified bit. This represents the mean of a specified number of bits. This represents its variance. Specifically, randomly merging multiple test vectors in the first test vector set to generate multiple random test vectors can include at least one of the following two methods: 1) Randomly selecting a portion of data packets from the first test vector set for merging, extracting the scan chain usage of the merged data, and forming a 0 / 1 vector as the generated random test vector; or 2) Randomly selecting a portion of data packets from the first test vector set as background, incrementally merging them one by one with the remaining data packets, retaining the intermediate results obtained from each incremental merging, extracting the scan chain usage to form a 0 / 1 vector, and using it as the random test vector.

[0087] By ensuring that specified bits follow a uniform or normal distribution, the second test vector set can still substantially conform to the characteristics of the first test vector set, such as the frequency or distribution of scan chain usage. Therefore, using the second test vector set for training satisfies the BNN's requirement for a large amount of training data and also ensures that the trained decoder is optimized for the circuit under test 11.

[0088] In one embodiment, for the mask decoder 152, the electronic device can first extract the distribution of unknown states of the circuit under test. A masked BNN learning dataset is generated based on the low-power BNN learning dataset (random test vector set) described above. This masked BNN learning dataset includes an observation dataset and an unknown state masking dataset. Each element in both the observation dataset and the unknown state masking dataset is a binary vector with a length equal to the total number of scan chains. Specifically, the dataset augmentation method for the mask decoder 152 includes: the scan chain output values ​​corresponding to the merged data packets forming the random test vectors must be observed; the scan chain numbers are extracted, and the values ​​at the corresponding positions in the binary vectors are set to 1, while the values ​​at the remaining positions are 0. The set of these binary vectors constitutes the observation dataset. The scan chain numbers containing the unknown states that prevent the observation of these scan chain output values ​​are extracted, and the values ​​at the corresponding positions in the binary vectors are set to 1, while the values ​​at the remaining positions are 0. The set of these binary vectors constitutes the unknown state masking dataset. In this way, a second test vector set for the mask decoder 152 can also be obtained. To address the need for large amounts of training and validation data for BNNs, some embodiments of this disclosure use a test dataset augmentation method to expand the test dataset while maintaining data consistency. This reduces the amount of data extracted from ATPG data, thereby reducing design and simulation costs.

[0089] Due to the layered structure of BNNs, the electronic device uses a binary neural network model to represent the initial encoder or decoder. One layer in each BNN corresponds to an encoding layer in the initial encoder or a decoding layer in the initial decoder. For ease of description, the following description focuses only on the decoder; the encoder has a similar case and will not be repeated. The electronic device then trains the binary neural network model using the first set of test vectors in the second test vector set to obtain a candidate binary neural network. After obtaining the candidate binary neural network, the electronic device can validate the candidate binary neural network using the second set of test vectors in the second test vector set to obtain the target binary neural network. In other words, the second test vector set is divided into two parts: a training set and a validation set. When the target binary neural network meets the performance requirements, the electronic device can determine the target binary neural network as the target decoder.

[0090] Since the weights in a BNN are binary and discrete, and the algorithm cannot handle this discrete situation, the aforementioned BNN model cannot be directly trained. It needs to be transformed into a continuous model, which has the same structure as the discrete BNN model, but its connection weights and comparison thresholds are continuous. Specifically, the connection between the decoding circuits in one decoding layer and the decoding circuits in another layer is represented in the continuous model as connection weights between 0 and 1, and the comparison threshold in the comparator can be represented as a continuous value greater than 0. For example, in one embodiment, the input X of the (i+1)th layer... i+1 With the i-th layer input X i The relationship is simulated by the following equation (6): (6) Where, mean(X) i ) represents X i The mean of all elements, var(X) i ) represents X i The variance of , w represents the weight connection matrix from the i-th layer to the (i+1)-th layer, and C represents a vector where the k-th component represents the threshold in the k-th comparator.

[0091] Because low-power BNNs and masked BNNs use the same dataset format and employ the same optimization objective function, they use the same BNN training algorithm. During BNN training, the encoder BNN and decoder BNN can be trained according to... Figure 3 These methods are combined to train the corresponding continuous models simultaneously. In one embodiment, the training algorithm employs a stochastic gradient descent optimization algorithm.

[0092] Figure 6 A flowchart illustrating a method 600 for obtaining candidate BNNs according to some embodiments of the present disclosure is shown. It will be understood that method 600 may be... Figure 5 Method 600 is a specific implementation of at least a portion of step 504 of method 500. Method 600 does not limit method 500; the individual steps in method 500 may have other implementations. Method 600 may be executed by a computing-capable electronic device such as a computer.

[0093] In 602, the electronic device initializes the initial connections between the layers of the binary neural network model to the real number domain to obtain a continuous-domain neural model. Multiple weights between the layers in the continuous-domain neural model are located between 0 and 1, and multiple threshold constants between the layers in the continuous-domain neural model are greater than 0.

[0094] In 604, the continuous domain neural model is trained using test vectors from the first set of test vectors to obtain an intermediate neural network in the real domain.

[0095] At 606, check whether the output of the intermediate neural network satisfies the objective function value. For BNN, it is expected that the open state of the scan chain can be restored after encoding and decoding, which can be represented by the following equation (7).

[0096] (7) Where Xj represents the input bits of the target encoding input section, for example Figure 4 The input bits at the target encoding input section 410 in the middle. j represents the output bit of the target decoder output section, for example Figure 4 In the target decoding output section, the output bit at position 450 is defined as follows: e represents the encoding mapping or encoding function; X represents the binary vector to be encoded; d represents the decoding mapping or decoding function; and p represents the number of scan chains. The target function value can have different representations depending on the application scenario. In one embodiment, for a low-power BNN, the percentage of scan chains in the open state after encoding and decoding relative to the total number of scan chains can be set to satisfy the following equation (8): (8) For the mask BNN, in order to minimize the decoding cost, it can be constrained by the following formula (9).

[0097] (9) Therefore, training from the initial BNN to the target BNN is actually a multi-objective optimization problem, because it includes constraints and objectives for both the low-power decoder and the mask decoder. A weighted approach can be used to synthesize and optimize this. In one embodiment, multi-objective optimization can be performed using Equation 10 below.

[0098] (10) Where X represents the binary vector to be encoded. This represents a binary vector after encoding and decoding. This indicates the number of scan chains where encoding failed. This indicates the number of additional scan chains that are opened / closed after encoding and decoding. β represents the weighting coefficient and can be preset according to the actual circuit. For example, β is between 0 and 1.

[0099] If the output of the intermediate neural network does not satisfy the objective function value, the electronic device at 608 updates the intermediate neural network using the gradient descent algorithm to modify the values ​​of multiple weights and multiple threshold constants. If the output of the intermediate neural network satisfies the objective function value, the electronic device at 610 converts the intermediate neural network into a binary discrete domain to obtain a candidate binary neural network. In the case that the objective function value is satisfied, the intermediate neural network can be represented by the following equation (11).

[0100] (11) in , , Represents the weighted connection matrix. This represents a comparison threshold. In one embodiment, when an intermediate neural network is determined, the electronic device can further convert the intermediate neural network into a binary discrete domain to obtain a candidate binary neural network. Specifically, the weights can be compared with weight thresholds respectively. If the weight is greater than a predetermined threshold, it is considered that the connection between the two decoding circuits corresponding to different decoding layers actually exists or needs to be retained, and the two associated decoding layers can be connected. If the weight is less than the threshold, it is considered that the connection between the two decoding circuits corresponding to different decoding layers actually does not exist or does not need to be retained, and the connection between the two associated decoding layers can be disconnected. Thus, for example, Figure 4 The target encoding / decoding system of encoding / decoding system 400 is shown.

[0101] Electronic devices can generate a target decoder in a target codec system as part of a netlist for testing circuits under test (DUT) 11, and merge the netlist data of the test circuit with the netlist data of the DUT for manufacturing a chip including the DUT and test circuits (e.g., low-power decoder 142 and mask decoder 152). In some embodiments of this disclosure, by using a BNN, a densely connected initial codec system can be simplified to a sparsely connected target codec system, thereby achieving a higher coding success rate with fewer coding bits. Furthermore, to address the need for large amounts of training and validation data for BNNs, in some embodiments of this disclosure, the test dataset is augmented using a test dataset augmentation method while maintaining data consistency. This reduces the amount of data extracted from ATPG data, thereby reducing design and simulation costs.

[0102] While a BNN-trained model is used herein to describe the optimization process from the initial decoder to the target decoder, this disclosure is not limited thereto. Other machine learning methods, such as evolutionary algorithms, can also be used to optimize the initial decoder. For example, an evolutionary algorithm can be used to crossbreed, mutate, and / or add or remove connections to the connection circuits of the individual decoding circuits in the initial decoder, evaluate the evolved decoder, and select the target decoder based on the evaluation results.

[0103] Figure 7 A schematic block diagram of an electronic device 700 according to some embodiments of the present disclosure is shown. The electronic device 700 may include multiple modules for performing, for example... Figure 5 or Figure 6 The corresponding steps in method 500 or 600 discussed herein. For example... Figure 7 As shown, the electronic device 700 includes an initialization unit 702 and a modification unit 704. The initialization unit 702 is used to determine an initialization decoder based at least on netlist data representing the circuit under test (DUT). The initialization decoder includes at least one decoding layer, and each decoding layer includes multiple decoding circuits. The modification unit 704 is used to modify the connections of the multiple decoding circuits in the initialization decoder based at least on a first test vector set used to test the DUT to obtain a target decoder for the test circuit, the test circuits being configured to be coupled to the DUT within the chip.

[0104] In some embodiments, the initialization unit is further configured to use netlist data to determine the number of scan chains in the circuit under test; use the number of scan chains to calculate the number of layers in at least one decoding layer; use the number of scan chains and the number of layers to calculate a decoding array, the decoding array including the number of decoding circuits in at least one decoding layer in each decoding layer; and construct an initialization decoder based on the number of layers and the decoding array.

[0105] In some embodiments, the plurality of decoding circuits include accumulators and comparators coupled to the accumulators. The initialization unit is further configured to: configure the plurality of decoding layers arranged in series according to the number of layers; configure a corresponding number of decoding circuits in each of the plurality of decoding layers according to the decoding array; and connect each comparator of the previous level decoding layer in the plurality of decoding layers to each accumulator of the next level decoding layer in the plurality of decoding layers to construct an initialization decoder.

[0106] In some embodiments, the modification unit is further configured to expand the first test vector set into a second test vector set based on the characteristics of the circuit under test, the characteristics of the circuit under test including at least one of the scan chain distribution of multiple scan chains of the circuit under test in the test cycle or the unknown state distribution of unknown states in the test cycle; and to modify the connection of multiple decoding circuits in the initialized decoder using at least the second test vector set to obtain the target decoder.

[0107] In some embodiments, the modification unit is further configured to determine the usage frequency of multiple scan chains during the test period using a scan chain distribution or an unknown state distribution; randomly generate multiple random test vectors based on the usage frequency and a predetermined power threshold; and add multiple random test vectors to a first test vector set to generate a second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is uniformly distributed, and the specified bits represent the bits in the test vectors that have the first value.

[0108] In some embodiments, the modification unit is further configured to randomly merge multiple test vectors in the first test vector set to generate multiple random test vectors; and to add multiple random test vectors to the first test vector set to generate a second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is normally distributed, and the specified bit represents the bit in the test vector that has the first value.

[0109] In some embodiments, the modification unit is further configured to initialize the decoder using a binary neural network model representation; train the binary neural network model using a first set of test vectors in a second set of test vectors to obtain a candidate binary neural network; verify the candidate binary neural network using a second set of test vectors in the second set of test vectors to obtain a target binary neural network; and determine the target decoder based on the target binary neural network.

[0110] In some embodiments, the modification unit is further configured to initialize the initial connections between the layers in the binary neural network model to the real number domain to obtain a continuous domain neural model, wherein multiple weights between the layers in the continuous domain neural model are respectively between 0 and 1 and multiple threshold constants between the layers in the continuous domain neural model are respectively greater than 0; iteratively perform the following at least once: train the continuous domain neural model using a test vector set from a first set of test vectors to obtain an intermediate neural network in the real number domain; check whether the output of the intermediate neural network satisfies the objective function value; and if the output of the intermediate neural network does not satisfy the objective function value, update the intermediate neural network using a gradient descent algorithm to modify the values ​​of multiple weights and multiple threshold constants; and if the output of the intermediate neural network satisfies the objective function value, convert the intermediate neural network into a binary discrete domain to obtain a candidate binary neural network.

[0111] In some embodiments, the modification unit is further configured to compare the values ​​of the plurality of weights with a weight threshold respectively: if the value of the first weight among the plurality of weights is lower than the weight threshold, then disconnect the two decoding layers associated with the first weight, or if the value of the second weight among the plurality of weights is lower than the weight threshold, then connect the two decoding layers associated with the second weight.

[0112] Figure 8 A schematic block diagram of an example device 800 that can be used to implement embodiments of the present disclosure is shown. Device 800 can be used to implement electronic device 700. As shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to computer program instructions stored in random access memory (RAM) and / or read-only memory (ROM) 802 or computer program instructions loaded into RAM and / or ROM 802 from storage unit 807. Various programs and data required for the operation of device 800 may also be stored in RAM and / or ROM 802. The computing unit 801 and RAM and / or ROM 802 are interconnected via bus 803. Input / output (I / O) interface 804 is also connected to bus 803.

[0113] Multiple components in device 800 are connected to I / O interface 804, including: input unit 805, such as keyboard, mouse, etc.; output unit 806, such as various types of monitors, speakers, etc.; storage unit 807, such as disk, optical disk, etc.; and communication unit 808, such as network card, modem, wireless transceiver, etc. Communication unit 808 allows device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0114] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above, such as method 500 and / or method 600. For example, in some embodiments, method 500 and / or method 600 may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 807. In some embodiments, part or all of the computer program may be loaded and / or installed on device 800 via RAM and / or ROM and / or communication unit 808. When the computer program is loaded into RAM and / or ROM and executed by the computing unit 801, one or more steps of method 500 and / or method 600 described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to perform method 500 and / or method 600 by any other suitable means (e.g., by means of firmware).

[0115] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0116] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0117] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this disclosure. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0118] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for designing a decoder, the decoder being designed to be located in a test circuit, the method comprising: The initialization decoder is determined based at least on the netlist data representing the circuit under test; as well as Based at least on a first set of test vectors used to test the circuit under test, the connections of the decoding circuits in the initialization decoder are modified to obtain a target decoder for the test circuit, the test circuit being configured to be coupled to the circuit under test in the chip.

2. The method of claim 1, wherein the initialization decoder comprises at least one decoding layer, each decoding layer comprising a plurality of decoding circuits, and determining the initialization decoder comprises: The netlist data is used to determine the number of scan chains in the circuit under test. The number of scan chains is used to calculate the number of the at least one decoding layer; The decoding array is calculated using the number of scan chains and the number of layers, the decoding array including the number of decoding circuits in each of the at least one decoding layer; as well as The initialization decoder is constructed based on the number of layers and the decoding array.

3. The method according to claim 2, wherein, The plurality of decoding circuits include an accumulator and a comparator coupled to the accumulator. Constructing the initialization decoder includes: Based on the number of layers, multiple decoding layers are arranged in series. According to the decoding array, a corresponding number of decoding circuits are provided in each of the plurality of decoding layers; and The initialization decoder is constructed by connecting each comparator of the previous level of the plurality of decoding layers to each accumulator of the next level of the plurality of decoding layers.

4. The method of claim 3, wherein modifying the connections of a plurality of decoding circuits in the initialization decoder based at least on a first test vector set to obtain a target decoder for the test circuits comprises: Based on the characteristics of the circuit under test, the first test vector set is expanded into a second test vector set. The characteristics of the circuit under test include at least one of the scan chain distribution of multiple scan chains of the circuit under test in the test cycle or the distribution of unknown states of unknown states in the test cycle. as well as The connection of multiple decoding circuits in the initialization decoder is modified using at least the second test vector set to obtain the target decoder.

5. The method according to claim 4, wherein expanding the first test vector set into a second test vector set based on the characteristics of the circuit under test comprises: The frequency of use of the plurality of scan chains during the test period is determined using the scan chain distribution or the unknown state distribution. Based on the usage frequency and the predetermined power threshold, multiple random test vectors are randomly generated. as well as The plurality of random test vectors are added to the first test vector set to generate the second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is uniformly distributed, and the specified bits represent the bits in the test vector that have the first value.

6. The method according to claim 4, wherein expanding the first test vector set into a second test vector set based on the characteristics of the circuit under test comprises: Multiple test vectors in the first test vector set are randomly merged to generate multiple random test vectors; The plurality of random test vectors are added to the first test vector set to generate the second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is normally distributed, and the specified bit represents the bit in the test vector that has the first value.

7. The method according to any one of claims 4-6, wherein modifying the connections of the plurality of decoding circuits in the initialization decoder using at least the second test vector set to obtain the target decoder comprises: The initialization decoder is represented using a binary neural network model; The binary neural network model is trained using the first set of test vectors in the second test vector set to obtain a candidate binary neural network; The candidate binary neural network is validated using the second set of test vectors in the second test vector set to obtain the target binary neural network; as well as The target decoder is determined based on the target binary neural network.

8. The method of claim 7, wherein training the binary neural network model using a first set of test vectors from the second test vector set to obtain a candidate binary neural network comprises: The initial connections between the layers in the binary neural network model are initialized to the real number domain to obtain a continuous domain neural model. The multiple weights between the layers in the continuous domain neural model are respectively located between the first value and the second value, and the multiple threshold constants between the layers in the continuous domain neural model are respectively greater than the first value. Perform the following items iteratively at least once: The continuous domain neural model is trained using the test vector set in the first set of test vectors to obtain an intermediate neural network in the real number domain. Check whether the output of the intermediate neural network satisfies the objective function value; as well as If the output of the intermediate neural network does not satisfy the objective function value, then the intermediate neural network is updated using a gradient descent algorithm to modify the values ​​of the multiple weights and the multiple threshold constants; and If the output of the intermediate neural network satisfies the objective function value, then the intermediate neural network is converted into a binary discrete domain to obtain the candidate binary neural network.

9. The method of claim 8, wherein converting the intermediate neural network into a binary discrete domain to obtain the candidate binary neural network comprises: The values ​​of the multiple weights are compared with the weight thresholds respectively: If the value of the first weight among the plurality of weights is lower than the weight threshold, then the two decoding layers associated with the first weight are disconnected, or If the value of the second weight among the plurality of weights is lower than the weight threshold, then the two decoding layers associated with the second weight are connected.

10. A computer-readable storage medium storing a plurality of programs configured to be executed by one or more processors, the plurality of programs including instructions for performing the method of any one of claims 1-9.

11. A computer program product comprising a plurality of programs configured to be executed by one or more processors, the plurality of programs comprising instructions for performing the method of any one of claims 1-9.

12. An electronic device, comprising: One or more processors; The electronic device includes a memory containing computer instructions that, when executed by the one or more processors of the electronic device, cause the electronic device to perform the method of any one of claims 1-9.

13. An electronic device, comprising: An initialization unit is used to determine an initialization decoder based at least on netlist data representing the circuit under test; as well as The modification unit is configured to modify the connections of the decoding circuits in the initialization decoder, based at least on a first test vector set for testing the circuit under test, to obtain a target decoder for testing the circuit, the test circuits being configured to be coupled to the circuit under test in the chip.

14. The electronic device of claim 13, wherein the initialization decoder comprises at least one decoding layer, each of the at least one decoding layer comprising a plurality of decoding circuits, and the initialization unit is further configured to: The netlist data is used to determine the number of scan chains in the circuit under test. The number of scan chains is used to calculate the number of the at least one decoding layer; The decoding array is calculated using the number of scan chains and the number of layers, the decoding array including the number of decoding circuits in each of the at least one decoding layer; as well as The initialization decoder is constructed based on the number of layers and the decoding array.

15. The electronic device according to claim 14, wherein, The plurality of decoding circuits include an accumulator and a comparator coupled to the accumulator, and the initialization unit is further configured to: Based on the number of layers, multiple decoding layers are arranged in series. According to the decoding array, a corresponding number of decoding circuits are set in each decoding layer of the plurality of decodings; as well as The initialization decoder is constructed by connecting each comparator of the previous level of the plurality of decoding layers to each accumulator of the next level of the plurality of decoding layers.

16. The electronic device of claim 15, wherein the modifying unit is further configured to: Based on the characteristics of the circuit under test, the first test vector set is expanded into a second test vector set. The characteristics of the circuit under test include at least one of the following: the distribution of multiple scan chains of the circuit under test during the test cycle, or the distribution of unknown states during the test cycle. The connection of multiple decoding circuits in the initialization decoder is modified using at least the second test vector set to obtain the target decoder.

17. The electronic device of claim 16, wherein the modification unit is further configured to: The frequency of use of the plurality of scan chains during the test period is determined using the scan chain distribution or the unknown state distribution. Based on the usage frequency and predetermined power threshold, multiple random test vectors are randomly generated; and The plurality of random test vectors are added to the first test vector set to generate the second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is uniformly distributed, and the specified bits represent the bits in the test vector that have the first value.

18. The electronic device of claim 16, wherein the modification unit is further configured to: Multiple test vectors from the first test vector set are randomly merged to generate multiple random test vectors; and The plurality of random test vectors are added to the first test vector set to generate the second test vector set, wherein the proportion of specified bits in the test vectors in the second test vector set is normally distributed, and the specified bit represents the bit in the test vector that has the first value.

19. The electronic device according to any one of claims 16-18, wherein the modification unit is further configured to: The initialization decoder is represented using a binary neural network model; The binary neural network model is trained using the first set of test vectors in the second test vector set to obtain a candidate binary neural network; The candidate binary neural network is validated using the second set of test vectors in the second test vector set to obtain the target binary neural network; as well as The target decoder is determined based on the target binary neural network.

20. The electronic device of claim 19, wherein the modification unit is further configured to: The initial connections between the layers in the binary neural network model are initialized to the real number domain to obtain a continuous domain neural model. The multiple weights between the layers in the continuous domain neural model are respectively located between a first value and a second value, and the multiple threshold constants between the layers in the continuous domain neural model are respectively greater than the first value. Perform the following items iteratively at least once: The continuous domain neural model is trained using the test vector set in the first set of test vectors to obtain an intermediate neural network in the real number domain. Check whether the output of the intermediate neural network satisfies the objective function value; as well as If the output of the intermediate neural network does not satisfy the objective function value, then the intermediate neural network is updated using a gradient descent algorithm to modify the values ​​of the multiple weights and the multiple threshold constants; and If the output of the intermediate neural network satisfies the objective function value, then the intermediate neural network is converted into a binary discrete domain to obtain the candidate binary neural network.

21. The electronic device of claim 20, wherein the modification unit is further configured to: The values ​​of the multiple weights are compared with the weight thresholds respectively: If the value of the first weight among the plurality of weights is lower than the weight threshold, then the two decoding layers associated with the first weight are disconnected, or If the value of the second weight among the plurality of weights is lower than the weight threshold, then the two decoding layers associated with the second weight are connected.

22. A circuit for testing a circuit under test, comprising: A first decoder, coupled to the circuit under test and configured to decode a plurality of first encoded bits into a plurality of first decoded bits, the first decoder including at least one decoding layer, each of the at least one decoding layer including a plurality of decoding circuits, each decoding circuit including an accumulator and a comparator coupled to the accumulator.

23. The circuit of claim 22, wherein the at least one decoding layer comprises: The first decoding layer is configured to output a plurality of first intermediate bits based on the plurality of first encoded bits; as well as The second decoding layer is configured to output the plurality of first decoded bits based on the plurality of first intermediate bits, wherein the number of the plurality of first decoded bits is greater than the number of the plurality of first intermediate bits.

24. The circuit of claim 23, wherein each of the at least one decoding layer comprises a first decoding circuit and a second decoding circuit, the connections of the first decoding circuit and the connections of the second decoding circuit being different.

25. The circuit of claim 24, wherein the plurality of decoding circuits of the last stage of the at least one decoding layer are coupled to the plurality of scan chains of the circuit under test via a plurality of first AND gates; or The multiple decoding circuits of the last level of the at least one decoding layer are respectively coupled to the multiple scan chains to multiple second AND gates.

26. The circuit according to any one of claims 22-25, further comprising: A second decoder, coupled to the circuit under test and configured to decode a plurality of second encoded bits into a plurality of second decoded bits, the second decoder including at least one decoding layer, each of the at least one decoding layer including a plurality of decoding circuits, each decoding circuit including an accumulator and a comparator coupled to the accumulator.

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