Silicon-based single-photon detector dark count rate simulation method, device, equipment and medium

Abstract

The application relates to the technical field of single-photon detector simulation, and provides a silicon-based single-photon detector dark count rate simulation method, device, equipment and medium, the method comprises the following steps: obtaining multiple breakdown voltages of a target silicon-based single-photon detector at different temperatures; obtaining an over-bias voltage range of the target silicon-based single-photon detector according to the breakdown voltages, and a breakdown probability and a carrier generation rate corresponding to the over-bias voltage range in a depletion region; and obtaining the dark count rate of the target silicon-based single-photon detector at different temperatures according to the breakdown probability and the carrier generation rate. In the application, the dark count rate of the silicon-based single-photon detector at different temperatures is obtained through simulation, so that the time and cost of optimizing the device dark count rate are reduced, and the applicable temperature range of the dark count rate simulation is widened.

Description

Technical Field

[0001] This application relates to the field of single-photon detector simulation technology, specifically to a method, apparatus, equipment, and medium for simulating the dark count rate of a silicon-based single-photon detector. Background Technology

[0002] Silicon-based optoelectronic devices combine the advantages of low cost, mass production, and high integration of large-scale integrated circuits with the high bandwidth, high speed, and high anti-interference capability of optoelectronic chips, making them ideal devices for optical interconnection in space missions such as satellites, spacecraft, and space stations. Among them, silicon-based single-photon avalanche diodes (SPADs), as solid-state photodetectors, offer higher sensitivity and dynamic range compared to traditional photomultiplier tubes, capable of detecting weak light signals with noise levels several orders of magnitude lower. Therefore, they are specifically used in high-precision space missions such as planetary altimeters, satellite laser time-of-motion, and deep-space lidar detection. However, due to lattice thermal vibrations and the presence of crystal defects and impurities, when the device bias voltage exceeds the breakdown voltage, SPADs can experience avalanche breakdown even without incident photons. This leads to an increase in the dark count rate (DCR), resulting in decreased detector efficiency and severely impacting the on-orbit mission and reliability of space payloads. Therefore, design optimization of the dark count rate performance of SPADs is urgently needed.

[0003] Current technologies for optimizing the dark count rate of SPADs through process optimization suffer from time-consuming and costly methods, and also lack a theoretical basis for design reference. In recent years, domestic and international researchers have attempted to utilize TCAD (Technology Computer-Aided Design) simulation tools to analyze the physical relationships between device structure and parameters. TCAD simulation is a numerical simulation tool based on semiconductor physics, describing the changes in internal physical parameters of the device by simultaneously coupling the physical equations controlling carrier migration, recombination, and transport with the external field equations providing the driving force. However, since the dark count rate of silicon-based single-photon detectors characterizes the dark count occurring per unit time and possesses random and statistical properties, additional integral calculations are required to achieve DCR simulation modeling. Furthermore, experimental results show that the physical mechanisms governing the generation of the device's dark count rate at different operating temperatures are not yet fully elucidated, requiring in-depth analysis through simulation.

[0004] Therefore, how to simulate the dark count rate of silicon-based single-photon detectors at different temperatures is a problem that urgently needs to be solved. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this application is to provide a method, apparatus, device and medium for simulating the dark count rate of silicon-based single-photon detectors, so as to solve the problem of how to simulate the dark count rate of silicon-based single-photon detectors at different temperatures in the prior art.

[0006] To achieve the above and other related objectives, this application provides a method for simulating the dark count rate of a silicon-based single-photon detector, the method comprising:

[0007] Obtain multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures;

[0008] Based on the breakdown voltages, the over-bias range of the target silicon-based single-photon detector is obtained, as well as the breakdown probability and carrier generation rate corresponding to the over-bias range in the depletion region.

[0009] Based on the breakdown probability and carrier generation rate, the dark count rate of the target silicon-based single-photon detector at different temperatures is obtained.

[0010] In one embodiment of this application, obtaining multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures includes:

[0011] Multiple electrical output characteristic curves of the target silicon-based single-photon detector at different temperatures are obtained, and each of the electrical output characteristic curves is used to indicate the change of the anode current of the target silicon-based single-photon detector with the bias voltage.

[0012] The plurality of breakdown voltages are obtained based on the inflection points of each of the aforementioned electrical output characteristic curves.

[0013] In one embodiment of this application, obtaining multiple electrical output characteristic curves of the target silicon-based single-photon detector at different temperatures includes:

[0014] The pre-configured OKOTU collisional ionization model, the target silicon-based single-photon detector SRH generation-recombination physics model, and the target silicon-based single-photon detector TRAP.TUNNEL physics model are invoked. The target silicon-based single-photon detector SRH generation-recombination physics model is used to indicate the carrier recombination process of the target silicon-based single-photon detector at room temperature, and the target silicon-based single-photon detector TRAP.TUNNEL physics model is used to indicate the trap-assisted tunneling process of the target silicon-based single-photon detector at low temperature.

[0015] By applying a reverse bias voltage to the photodiode region using the OKOTU collision ionization model, the SRH generation-recombination physical model of the target silicon-based single-photon detector, and the TRAP.TUNNEL physical model of the target silicon-based single-photon detector, a high electric field is generated in the depletion region to achieve carrier collection and avalanche breakdown, thereby obtaining the multiple electrical output characteristic curves.

[0016] In one embodiment of this application, the over-bias range of the target silicon-based single-photon detector, and the breakdown probability and carrier generation rate corresponding to the over-bias range in the depletion region are obtained based on the breakdown voltages, including:

[0017] The overbias range of the target silicon-based single-photon detector is obtained based on the plurality of reverse bias voltages and the breakdown voltage.

[0018] Multiple overbias are obtained based on the overbias range, and the carrier generation rate corresponding to the multiple overbias in the depletion region is extracted.

[0019] Using a pre-configured GEIGER single-photon avalanche model, the avalanche breakdown that occurs after a single electron or hole enters the multiplication region of the target silicon-based single-photon detector is simulated, and the avalanche breakdown probability is obtained. Based on the avalanche breakdown probability, the breakdown probability corresponding to the multiple over-bias voltages in the depletion region is obtained.

[0020] In one embodiment of this application, the overbias voltage is represented in the following ways:

[0021] V ex =V bias -V bd

[0022] Among them, V ex For the overbias voltage, V bias V is the reverse bias voltage. bd The breakdown voltage is denoted as .

[0023] In one embodiment of this application, the breakdown probability corresponding to each of the over-bias voltages is represented in the following ways:

[0024]

[0025]

[0026]

[0027] Among them, P tr P is the breakdown probability corresponding to the over-bias voltage. e P is the avalanche breakdown probability of electrons. h Let α be the avalanche breakdown probability of a hole. eα is the collisional ionization coefficient of electrons. h is the collisional ionization coefficient of a hole.

[0028] In one embodiment of this application, the dark count rate is represented in the following manner:

[0029] DCR(V ex ) = v g (V ex )×P tr (V ex )×V dep

[0030] Among them, DCR(V ex ) represents the dark count rate, v g (V ex P represents the carrier generation rate corresponding to the overbias voltage. tr (V ex V represents the breakdown probability corresponding to over-bias. dep The volume of the depletion region.

[0031] In one embodiment of this application, a silicon-based single-photon detector dark count rate simulation device is also provided, the device comprising:

[0032] The breakdown voltage acquisition module is used to acquire multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures;

[0033] The depletion region parameter calculation module is used to obtain the over-bias range of the target silicon-based single-photon detector, as well as the breakdown probability and carrier generation rate corresponding to the over-bias range in the depletion region, based on the breakdown voltages.

[0034] The dark count rate calculation module is used to obtain the dark count rate of the target silicon-based single-photon detector at different temperatures based on the breakdown probability and carrier generation rate.

[0035] In one embodiment of this application, an electronic device is also provided, the electronic device comprising:

[0036] One or more processors;

[0037] A storage device for storing one or more programs that, when executed by one or more processors, enable the electronic device to implement the silicon-based single-photon detector dark count rate simulation method as described above.

[0038] In one embodiment of this application, a computer-readable storage medium is also provided, on which a computer program is stored, which, when executed by a computer processor, causes the computer to perform the silicon-based single-photon detector dark count rate simulation method as described above.

[0039] The beneficial effects of this invention are:

[0040] This invention simulates the dark count rate of a silicon-based single-photon detector. First, multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures are obtained. Then, based on each breakdown voltage, the over-bias range of the target silicon-based single-photon detector is obtained, along with the breakdown probability and carrier generation rate corresponding to the over-bias range within the depletion region. Finally, based on the breakdown probability and carrier generation rate, the dark count rate of the target silicon-based single-photon detector at different temperatures is obtained. This invention, by simulating the dark count rate of a silicon-based single-photon detector at different temperatures, can reduce the time and cost of dark count rate optimization and broaden the applicable temperature range for dark count rate simulation. Furthermore, after obtaining the dark count rate, the microscopic electric field distribution during the dark count rate generation process can be intuitively analyzed, and the microscopic physical model underlying the evolution of the dark count rate can be obtained, providing theoretical support for the design of high-performance silicon-based single-photon detectors.

[0041] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0042] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. In the drawings:

[0043] Figure 1 This is a schematic diagram illustrating the implementation environment of a silicon-based single-photon detector dark count rate simulation method, as shown in an exemplary embodiment of this application.

[0044] Figure 2 This is a flowchart illustrating a method for simulating the dark count rate of a silicon-based single-photon detector, as shown in an exemplary embodiment of this application.

[0045] Figure 3 This is a schematic diagram illustrating a comparison of simulation and experimental results of dark count rate of a silicon-based single-photon detector at different temperatures, as shown in an exemplary embodiment of this application.

[0046] Figure 4 This is a block diagram illustrating a silicon-based single-photon detector dark count rate simulation device, as shown in an exemplary embodiment of this application.

[0047] Figure 5 A schematic diagram of the structure of a computer system suitable for an electronic device according to an embodiment of this application is shown. Detailed Implementation

[0048] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0049] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0050] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the invention. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the invention.

[0051] Figure 1 This is a schematic diagram illustrating the implementation environment of a silicon-based single-photon detector dark count rate simulation method, as shown in an exemplary embodiment of this application.

[0052] Reference Figure 1 As shown, the implementation environment may include a terminal device 110 and a server 120. The technical solution provided in this application embodiment can be applied to the terminal device 110. The terminal device 110 is used to obtain multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures and use the dark count rate simulation method of the silicon-based single-photon detector in this application embodiment to obtain the dark count rate simulation result. The terminal device 110 transmits the dark count rate simulation result to the server 120 for storage and analysis.

[0053] In one embodiment of this application, the terminal device 110 acquires multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures; based on each breakdown voltage, it obtains the over-bias range of the target silicon-based single-photon detector, as well as the breakdown probability and carrier generation rate corresponding to the over-bias range in the depletion region; based on the breakdown probability and carrier generation rate, it obtains the dark count rate of the target silicon-based single-photon detector at different temperatures. In this embodiment, by simulating the dark count rate of the silicon-based single-photon detector at different temperatures, the time and cost of dark count rate optimization can be reduced, and the applicable temperature range of dark count rate simulation can be broadened; in addition, after obtaining the dark count rate, the microscopic electric field distribution in the dark count rate generation process can be intuitively analyzed, and the microscopic physical model on which the dark count rate evolution is based can be analyzed, providing theoretical support for the design of high-performance silicon-based single-photon detectors.

[0054] It should be understood that Figure 1 The number of terminal devices 110 and servers 120 shown is merely illustrative. Any number of terminal devices 110 and servers 120 can be used as needed.

[0055] Among them, terminal device 110 corresponds to user terminal, which can input and call model according to user instructions and calculate parameters.

[0056] Among them, server 120 corresponds to the server side, which can be a server that provides various services. It can be an independent physical server, a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. This section does not impose any restrictions on this.

[0057] Terminal device 110 can communicate with server 120 via wireless networks such as 3G (third-generation mobile information technology), 4G (fourth-generation mobile information technology), and 5G (fifth-generation mobile information technology), and this is not restricted here.

[0058] The above section introduced the exemplary implementation environment of the technical solution of this application. Next, we will continue to introduce the dark count rate simulation method of silicon-based single-photon detector of this application.

[0059] To address the problem of simulating the dark count rate of silicon-based single-photon detectors at different temperatures in the prior art, embodiments of this application propose a method for simulating the dark count rate of silicon-based single-photon detectors, a device for simulating the dark count rate of silicon-based single-photon detectors, an electronic device, a computer-readable storage medium, and a computer program product. These embodiments will be described in detail below.

[0060] Please see Figure 2 , Figure 2 This is a flowchart illustrating an exemplary embodiment of the dark count rate simulation method for a silicon-based single-photon detector, which can be applied to... Figure 1 The implementation environment is shown. It should be understood that this method can also be applied to other exemplary implementation environments and specifically executed by devices in other implementation environments. This embodiment does not limit the implementation environment to which the method is applicable.

[0061] like Figure 2 As shown, in an exemplary embodiment, the silicon-based single-photon detector dark count rate simulation method includes at least steps S210 to S230, which are described in detail below:

[0062] In step S210, multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures are obtained.

[0063] For example, the OKOTU collisional ionization model is used to simulate the multiplication breakdown process of charge carriers in a target silicon-based single-photon detector at different temperatures, including charge generation, diffusion, recombination and collisional ionization reactions, to realize the breakdown characteristics of the device and determine multiple breakdown voltages.

[0064] In step S220, based on each of the breakdown voltages, the overbias range of the target silicon-based single-photon detector, as well as the breakdown probability and carrier generation rate corresponding to the overbias range in the depletion region, are obtained.

[0065] For example, after obtaining the overbias range of the target silicon-based single-photon detector, the carrier generation rate at position (x, y) in the depletion region of the target silicon-based single-photon detector under different overbias is extracted; the GEIGER single-photon avalanche model is used to extract the breakdown probability at position (x, y) in the depletion region of the target silicon-based single-photon detector under different overbias.

[0066] In step S230, the dark count rate of the target silicon-based single-photon detector at different temperatures is obtained based on the breakdown probability and the carrier generation rate.

[0067] For example, through experimental calibration, the physical model that dominates carrier generation at different operating temperatures is invoked to obtain the breakdown probability and carrier generation rate at different temperatures, and then the dark count rate of the silicon-based single-photon detector at the corresponding operating temperature is calculated.

[0068] As can be seen from steps S210 to S230 above, the scheme proposed in this embodiment can reduce the time and cost of dark count rate optimization and broaden the applicable temperature range of dark count rate simulation by simulating the dark count rate of silicon-based single-photon detectors at different temperatures. In addition, after obtaining the dark count rate, the microscopic electric field distribution in the dark count rate generation process can be analyzed intuitively, and the microscopic physical model on which the dark count rate evolution is based can be analyzed to provide theoretical support for the design of high-performance silicon-based single-photon detectors.

[0069] In one embodiment of this application, obtaining multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures includes:

[0070] Multiple electrical output characteristic curves of the target silicon-based single-photon detector at different temperatures are obtained, and each of the electrical output characteristic curves is used to indicate the change of the anode current of the target silicon-based single-photon detector with the bias voltage.

[0071] The plurality of breakdown voltages are obtained based on the inflection points of each of the aforementioned electrical output characteristic curves.

[0072] For example, by increasing the cathode bias voltage, an electrical output characteristic curve showing the change of anode current with cathode bias voltage is obtained. When the bias voltage exceeds the breakdown voltage, avalanche breakdown occurs, and the dark current value drops from approximately 10. -10 The order of magnitude increased to 10 -2 On the order of magnitude, the breakdown voltage of the target silicon-based single-photon detector at room temperature is approximately 150V.

[0073] In one embodiment of this application, obtaining multiple electrical output characteristic curves of the target silicon-based single-photon detector at different temperatures includes:

[0074] The pre-configured OKOTU collisional ionization model, the target silicon-based single-photon detector SRH generation-recombination physics model, and the target silicon-based single-photon detector TRAP.TUNNEL physics model are invoked. The target silicon-based single-photon detector SRH generation-recombination physics model is used to indicate the carrier recombination process of the target silicon-based single-photon detector at room temperature, and the target silicon-based single-photon detector TRAP.TUNNEL physics model is used to indicate the trap-assisted tunneling process of the target silicon-based single-photon detector at low temperature.

[0075] By applying a reverse bias voltage to the photodiode region using the OKOTU collision ionization model, the SRH generation-recombination physical model of the target silicon-based single-photon detector, and the TRAP.TUNNEL physical model of the target silicon-based single-photon detector, a high electric field is generated in the depletion region to achieve carrier collection and avalanche breakdown, thereby obtaining the multiple electrical output characteristic curves.

[0076] For example, the SRH generation-recombination physics model corresponds to room temperature conditions, while the TRAP.TUNNEL physics model corresponds to low-temperature conditions of 253K-273K. In the TCAD software simulation environment, the OKOTU collisional ionization model is used. The SRH generation-recombination physics model is called for room temperature conditions, and the TRAP.TUNNEL physics model is called for low-temperature conditions. By increasing the cathode bias voltage to 300V and applying a reverse bias voltage to the photodiode region, the reverse bias voltage generates a high electric field in the depletion region, achieving carrier collection and avalanche breakdown performance, and obtaining electrical output characteristic curves corresponding to different temperatures. In this embodiment, the target silicon-based single-photon detector operates in Geiger mode, and the device sensitivity increases sharply, generating a multiplication region with an extremely high electric field inside. After the generated electron-hole pairs enter the multiplication region, they are accelerated by the electric field and undergo cascade collisions, resulting in avalanche current.

[0077] In one embodiment of this application, the over-bias range of the target silicon-based single-photon detector, and the breakdown probability and carrier generation rate corresponding to the over-bias range in the depletion region are obtained based on the breakdown voltages, including:

[0078] The overbias range of the target silicon-based single-photon detector is obtained based on the plurality of reverse bias voltages and the breakdown voltage.

[0079] Multiple overbias are obtained based on the overbias range, and the carrier generation rate corresponding to the multiple overbias in the depletion region is extracted.

[0080] Using a pre-configured GEIGER single-photon avalanche model, the avalanche breakdown that occurs after a single electron or hole enters the multiplication region of the target silicon-based single-photon detector is simulated, and the avalanche breakdown probability is obtained. Based on the avalanche breakdown probability, the breakdown probability corresponding to the multiple over-bias voltages in the depletion region is obtained.

[0081] In one embodiment of this application, the overbias voltage is represented in the following ways:

[0082] V ex =V bias -V bd

[0083] Among them, V ex For the overbias voltage, V bias V is the reverse bias voltage.bd The breakdown voltage is denoted as .

[0084] In one embodiment of this application, the breakdown probability corresponding to each of the over-bias voltages is represented in the following ways:

[0085]

[0086]

[0087]

[0088] Among them, P tr P is the breakdown probability corresponding to the over-bias voltage. e P is the avalanche breakdown probability of electrons. h Let α be the avalanche breakdown probability of a hole. e α is the collisional ionization coefficient of electrons. h is the collisional ionization coefficient of a hole.

[0089] In one embodiment of this application, the dark count rate is represented in the following manner:

[0090] DCR(V ex ) = v g (V ex )×P tr (V ex )×V dep

[0091] Among them, DCR(V ex ) represents the dark count rate, v g (V ex P represents the carrier generation rate corresponding to the overbias voltage. tr (V ex V represents the breakdown probability corresponding to over-bias. dep The volume of the depletion region.

[0092] In one embodiment of this application, see Figure 3 , Figure 3 This is a schematic diagram illustrating a comparison of simulation and experimental results of the dark count rate of a silicon-based single-photon detector at different temperatures, as shown in an exemplary embodiment of this application. Figure 3 In the figure, curves (1) and (3) are the simulation results of the dark count rate of the silicon-based single-photon detector at different temperatures, and curves (2) and (4) are the experimental results of the dark count rate of the silicon-based single-photon detector at different temperatures. Figure 3A comparison of the four curves shows that the dark count rate increases with the increase of the overbias voltage. The trend of the dark count rate obtained by the simulation method in this embodiment is consistent with the trend of the experimental test results. The dark count rate simulation method in this embodiment can obtain the correct dark count rate and also intuitively show the influence of factors such as electric field distribution and temperature on the dark count rate, thereby providing ideas and methods for device optimization design in practical application scenarios.

[0093] Figure 4 This is a block diagram illustrating a silicon-based single-photon detector dark count rate simulation device, as shown in an exemplary embodiment of this application. The device can be applied to... Figure 1 The implementation environment shown is not limited to this embodiment. This device can also be applied to other exemplary implementation environments and specifically configured in other devices. This embodiment does not limit the implementation environment to which the device is applicable.

[0094] like Figure 4 As shown, this exemplary silicon-based single-photon detector dark count rate simulation device includes:

[0095] The breakdown voltage acquisition module 401 is used to acquire multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures.

[0096] The depletion region parameter calculation module 402 is used to obtain the over-bias range of the target silicon-based single-photon detector, as well as the breakdown probability and carrier generation rate corresponding to the over-bias range in the depletion region, based on each of the breakdown voltages.

[0097] The dark count rate calculation module 403 is used to obtain the dark count rate of the target silicon-based single-photon detector at different temperatures based on the breakdown probability and the carrier generation rate.

[0098] In this exemplary silicon-based single-photon detector dark count rate simulation device, by simulating the dark count rate of the silicon-based single-photon detector at different temperatures, the time and cost of dark count rate optimization can be reduced, and the applicable temperature range of dark count rate simulation can be broadened. In addition, after obtaining the dark count rate, the microscopic electric field distribution in the dark count rate generation process can be intuitively analyzed, and the microscopic physical model on which the dark count rate evolution is based can be analyzed, providing theoretical support for the design of high-performance silicon-based single-photon detectors.

[0099] It should be noted that the silicon-based single-photon detector dark count rate simulation device and the silicon-based single-photon detector dark count rate simulation method provided in the above embodiments belong to the same concept. The specific operation methods of each module and unit have been described in detail in the method embodiments and will not be repeated here. In practical applications, the silicon-based single-photon detector dark count rate simulation device provided in the above embodiments can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. This is not a limitation here.

[0100] Embodiments of this application also provide an electronic device, including: one or more processors; and a storage device for storing one or more programs, which, when executed by the one or more processors, cause the electronic device to implement the silicon-based single-photon detector dark count rate simulation method provided in the above embodiments.

[0101] Figure 5 A schematic diagram of a computer system suitable for an electronic device according to an embodiment of this application is shown. It should be noted that... Figure 5 The computer system 500 of the electronic device shown is merely an example and should not impose any limitation on the functionality and scope of use of the embodiments of this application.

[0102] like Figure 5 As shown, the computer system 500 includes a Central Processing Unit (CPU) 501, which can perform various appropriate actions and processes based on programs stored in Read-Only Memory (ROM) 502 or programs loaded from Storage Unit 508 into Random Access Memory (RAM) 503, such as performing the methods described in the above embodiments. The RAM 503 also stores various programs and data required for system operation. The CPU 501, ROM 502, and RAM 503 are interconnected via a bus 504. An Input / Output (I / O) interface 505 is also connected to the bus 504.

[0103] The following components are connected to I / O interface 505: an input section 506 including a keyboard, mouse, etc.; an output section 507 including a cathode ray tube (CRT), liquid crystal display (LCD), etc., and speakers, etc.; a storage section 508 including a hard disk, etc.; and a communication section 509 including a network interface card such as a LAN (Local Area Network) card, modem, etc. The communication section 509 performs communication processing via a network such as the Internet. A drive 510 is also connected to I / O interface 505 as needed. Removable media 511, such as a disk, optical disk, magneto-optical disk, semiconductor memory, etc., are installed on drive 510 as needed so that computer programs read from them can be installed into storage section 508 as needed.

[0104] Specifically, according to embodiments of this application, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this application include a computer program product comprising a computer program carried on a computer-readable medium, the computer program including a computer program for performing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network via communication section 509, and / or installed from removable medium 511. When the computer program is executed by central processing unit (CPU) 501, it performs various functions defined in the system of this application.

[0105] It should be noted that the computer-readable medium shown in the embodiments of this application can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM), flash memory, optical fiber, portable compact disc read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this application, a computer-readable signal medium may include a data signal propagated in baseband or as part of a carrier wave, carrying a computer-readable computer program. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. Computer-readable signal media can also be any computer-readable medium other than computer-readable storage media, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The computer program contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, etc., or any suitable combination thereof.

[0106] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this application. Each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram or flowchart, and combinations of blocks in a block diagram or flowchart, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0107] The units described in the embodiments of this application can be implemented in software or hardware, and the described units can also be located in a processor. The names of these units do not necessarily limit the specific unit itself.

[0108] Another aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a computer's processor, causes the computer to perform the silicon-based single-photon detector dark count rate simulation method as described above. This computer-readable storage medium may be included in the electronic device described in the above embodiments, or it may exist independently and not assembled into the electronic device.

[0109] Another aspect of this application provides a computer program product or computer program including computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the silicon-based single-photon detector dark count rate simulation method provided in the various embodiments above.

[0110] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method for simulating the dark count rate of a silicon-based single-photon detector, characterized in that, The method includes: Obtain multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures; Based on the breakdown voltages, the over-bias range of the target silicon-based single-photon detector is obtained, as well as the breakdown probability and carrier generation rate corresponding to the over-bias range in the depletion region. Based on the breakdown probability and carrier generation rate, the dark count rate of the target silicon-based single-photon detector at different temperatures is obtained.

2. The method for simulating the dark count rate of a silicon-based single-photon detector according to claim 1, characterized in that, Obtain multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures, including: Multiple electrical output characteristic curves of the target silicon-based single-photon detector at different temperatures are obtained, and each of the electrical output characteristic curves is used to indicate the change of the anode current of the target silicon-based single-photon detector with the bias voltage. The plurality of breakdown voltages are obtained based on the inflection points of each of the aforementioned electrical output characteristic curves.

3. The method for simulating the dark count rate of a silicon-based single-photon detector according to claim 2, characterized in that, Obtain multiple electrical output characteristic curves of the target silicon-based single-photon detector at different temperatures, including: The pre-configured OKUTO collisional ionization model, the target silicon-based single-photon detector SRH generation-recombination physics model, and the target silicon-based single-photon detector TRAP.TUNNEL physics model are invoked. The target silicon-based single-photon detector SRH generation-recombination physics model is used to indicate the carrier recombination process of the target silicon-based single-photon detector at room temperature, and the target silicon-based single-photon detector TRAP.TUNNEL physics model is used to indicate the trap-assisted tunneling process of the target silicon-based single-photon detector at low temperature. By applying a reverse bias voltage to the photodiode region using the OKUTO collision ionization model, the SRH generation-recombination physical model of the target silicon-based single-photon detector, and the TRAP.TUNNEL physical model of the target silicon-based single-photon detector, a high electric field is generated in the depletion region to achieve carrier collection and avalanche breakdown, thereby obtaining the multiple electrical output characteristic curves.

4. The method for simulating the dark count rate of a silicon-based single-photon detector according to claim 3, characterized in that, Based on the breakdown voltages, the over-bias range of the target silicon-based single-photon detector is obtained, along with the breakdown probability and carrier generation rate corresponding to the over-bias range within the depletion region, including: The overbias range of the target silicon-based single-photon detector is obtained based on the plurality of reverse bias voltages and the breakdown voltage. Multiple overbias are obtained based on the overbias range, and the carrier generation rate corresponding to the multiple overbias in the depletion region is extracted. Using a pre-configured GEIGER single-photon avalanche model, the avalanche breakdown that occurs after a single electron or hole enters the multiplication region of the target silicon-based single-photon detector is simulated, and the avalanche breakdown probability is obtained. Based on the avalanche breakdown probability, the breakdown probability corresponding to the multiple over-bias voltages in the depletion region is obtained.

5. The method for simulating the dark count rate of a silicon-based single-photon detector according to claim 4, characterized in that, The overbias voltage can be represented in the following ways: in, For the over-bias voltage, The reverse bias voltage is... The breakdown voltage is denoted as .

6. The method for simulating the dark count rate of a silicon-based single-photon detector according to claim 5, characterized in that, The breakdown probability corresponding to each of the aforementioned over-bias voltages is represented in the following ways: in, The breakdown probability corresponding to the over-bias voltage. This represents the avalanche breakdown probability of electrons. The probability of avalanche breakdown of a hole. The collisional ionization coefficient of electrons. is the collisional ionization coefficient of a hole.

7. The method for simulating the dark count rate of a silicon-based single-photon detector according to claim 6, characterized in that, The dark count rate is represented in the following ways: in, The dark count rate, This represents the carrier generation rate corresponding to the over-bias voltage. This represents the breakdown probability corresponding to over-bias. The volume of the depletion region.

8. A silicon-based single-photon detector dark count rate simulation device, characterized in that, The device includes: The breakdown voltage acquisition module is used to acquire multiple breakdown voltages of the target silicon-based single-photon detector at different temperatures; The depletion region parameter calculation module is used to obtain the over-bias range of the target silicon-based single-photon detector, as well as the breakdown probability and carrier generation rate corresponding to the over-bias range in the depletion region, based on the breakdown voltages. The dark count rate calculation module is used to obtain the dark count rate of the target silicon-based single-photon detector at different temperatures based on the breakdown probability and carrier generation rate.

9. An electronic device, characterized in that, The electronic device includes: One or more processors; A storage device for storing one or more programs that, when executed by one or more processors, cause the electronic device to implement the silicon-based single-photon detector dark count rate simulation method as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by the computer's processor, causes the computer to perform the silicon-based single-photon detector dark count rate simulation method as described in any one of claims 1 to 7.

Images