Reset circuits, chips and electronic devices

Abstract

This application discloses a reset circuit, chip, and electronic device. The reset circuit includes a power management control module and a reset module. The reset module, connected to the power management control module, generates and sends a reset signal to the power management control module. The power management control module, located within a system-on-a-chip (SoC), receives the reset signal from the reset module and resets the power supply according to the signal. This application achieves the reset function by integrating a power management control module within the SoC and combining it with a reset module connected to the SoC, thus replacing the dedicated RESET pin. This eliminates the need for a dedicated RESET pin, enhances chip pin flexibility, and simplifies the structure. It meets the product requirements for a reset button function while reducing cost and power consumption.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a reset circuit, chip, and electronic device. Background Technology

[0002] In integrated circuits, a single SoC (System on Chip) chip is often used in multiple product forms. The more flexible the pins of an SoC chip, the more product forms it can adapt to. In the consumer electronics field, lower-cost 128-pin or 88-pin packages can reduce chip costs and improve competitiveness, especially 88-pin packages where chip pin resources are very precious. Traditional SoC chips have a dedicated RESET pin for resetting the entire chip. Therefore, replacing the dedicated RESET pin with a GPIO pin or other functional pins can save chip pin resources and improve chip competitiveness.

[0003] Existing technologies propose integrating a POR (Power on Reset) circuit inside the chip to replace the RESET pin for resetting functionality. However, during the research and practice of existing technologies, the inventors of this application discovered some shortcomings. For example, when a product requires a reset button function, the existing technology of integrating a power-on reset circuit inside the chip cannot support the reset button function. Although existing technologies also propose building a reset button circuit to control the product's total power supply, this involves circuit complexity and high cost due to the need to control the total power supply. Furthermore, a large total power supply can lead to significant power loss and severe heat generation in the circuit itself.

[0004] The preceding description is intended to provide general background information and does not necessarily constitute prior art. Summary of the Invention

[0005] To address the issue of limited pin flexibility caused by the need for a dedicated RESET pin in existing technologies, this application provides a reset circuit, chip, and electronic device. Its main purpose is to replace the dedicated RESET pin for resetting functionality, eliminating the need for a separate RESET pin, enhancing pin flexibility, and simplifying the structure. This approach meets the product requirements for a reset button function while reducing cost and power consumption.

[0006] In a first aspect, embodiments of this application provide a reset circuit, including a power management control module and a reset module;

[0007] The reset module is connected to the power management control module and is used to generate a reset signal to control the power management control module and send the reset signal to the power management control module.

[0008] The power management control module is located within the system-on-a-chip and is used to receive the reset signal sent by the reset module and reset the power supply according to the reset signal.

[0009] Furthermore, in some embodiments of this application, the power management control module includes an output control circuit unit, and a first power control unit and a second power control unit respectively connected to the output control circuit unit, wherein the output control circuit unit is used to output a corresponding control signal to the first power control unit and the second power control unit according to the reset signal; the first power control unit and the second power control unit are respectively used to control the level state of the corresponding output pin according to the control signal.

[0010] Further, in some embodiments of this application, the first power control unit includes a second MOSFET, a fourth MOSFET, and a first power enable pin; the second power control unit includes a first MOSFET, a third MOSFET, and a second power enable pin; the gate of the first MOSFET is connected to the first terminal of the output control circuit unit; the source of the first MOSFET is connected to the source of the second MOSFET; the drain of the first MOSFET is connected to the drain of the third MOSFET; the gate of the second MOSFET is connected to the second terminal of the output control circuit unit; the drain of the second MOSFET is connected to the drain of the fourth MOSFET; the gate of the third MOSFET is connected to the third terminal of the output control circuit unit; the source of the third MOSFET is connected to the source of the fourth MOSFET and grounded; the gate of the fourth MOSFET is connected to the fourth terminal of the output control circuit unit; the first power enable pin is connected to the drain of the second MOSFET and the drain of the fourth MOSFET; and the second power enable pin is connected to the drain of the first MOSFET and the drain of the third MOSFET.

[0011] Furthermore, in some embodiments of this application, the equivalent internal resistance range of the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor is 200 ohms to 500 ohms, and the typical equivalent internal resistance value is 350 ohms.

[0012] Furthermore, in some embodiments of this application, the reset module includes a reset control unit, and a first reset unit and a second reset unit respectively connected to the reset control unit;

[0013] The reset control unit is used to collect the user's actions, generate corresponding reset control signals, and send the reset control signals to the first reset unit and the second reset unit.

[0014] The first reset unit is used to receive a reset control signal sent by the reset control unit, generate a first reset signal according to the reset control signal, and send the first reset signal to the power management control module.

[0015] The second reset unit is used to receive the reset control signal sent by the reset control unit, generate a second reset signal according to the reset control signal, and send the second reset signal to the power management control module.

[0016] Furthermore, in some embodiments of this application, the first reset unit includes a first resistor and a first diode, one end of the first resistor is connected to the first terminal of the power management control module, the other end of the first resistor is connected to the anode of the first diode, and the cathode of the first diode is connected to the reset control unit; the second reset unit includes a second resistor and a second diode, one end of the second resistor is connected to the second terminal of the power management control module, the other end of the second resistor is connected to the anode of the second diode, and the cathode of the second diode is connected to the reset control unit.

[0017] Furthermore, in some embodiments of this application, the forward voltage drop of both the first diode and the second diode is less than or equal to 0.4V, and their resistance values ​​are both greater than 1.43K ohms.

[0018] Furthermore, in some embodiments of this application, the reset module further includes a power enable network unit, which includes a first power enable network and a second power enable network for controlling the operating state of the power chip connected to the target device; one end of the first power enable network is connected to the first reset unit, and the other end of the first power enable network is connected to the power chip of the target device; one end of the second power enable network is connected to the second reset unit, and the other end of the second power enable network is connected to the power chip of the target device.

[0019] Furthermore, in some embodiments of this application, one end of the first power enable network is connected to the other end of the first resistor and the positive terminal of the first diode, the other end of the first power enable network is connected to the first terminal of the power chip of the target device, the other end of the second power enable network is connected to the other end of the second resistor and the positive terminal of the second diode, and the other end of the second power enable network is connected to the second terminal of the power chip of the target device.

[0020] Furthermore, in some embodiments of this application, the reset module further includes an anti-static unit, which is connected to the reset control unit, the first reset unit, and the second reset unit respectively, and is used to provide anti-static protection for the reset control unit.

[0021] Secondly, embodiments of this application provide a chip including the reset circuit provided in the first aspect.

[0022] Thirdly, embodiments of this application provide an electronic device, including a reset circuit as provided in the first aspect or a chip as provided in the second aspect.

[0023] Implementing the embodiments of this application has the following beneficial effects:

[0024] As described above, this application provides a reset circuit, chip, and electronic device. The reset circuit includes a power management control module and a reset module. The reset module is connected to the power management control module and is used to generate a reset signal to control the power management control module and send the reset signal to the power management control module. The power management control module is located within the system-on-a-chip (SoC) and is used to receive the reset signal sent by the reset module and reset the power supply according to the reset signal. This application achieves the reset function by setting the power management control module within the SoC and combining it with the reset function connected to the power management control module to replace the RESET pin. This eliminates the need to bring out a dedicated RESET pin on the SoC, enhancing the flexibility of the chip pins. Furthermore, by building a reset module with a reset button to control the power enable pin of the SoC to achieve the reset function, the structure is simple and can reduce circuit cost and power consumption while meeting the reset button function requirements. Attached Figure Description

[0025] Figure 1 This is a schematic diagram of the structure of a first embodiment of the reset circuit in this application;

[0026] Figure 2 This is a schematic diagram of a second embodiment of the reset circuit in one of the embodiments of this application;

[0027] Figure 3 This is a circuit schematic diagram of the power management control module in one embodiment of this application;

[0028] Figure 4 This is a schematic diagram of a third embodiment of the reset circuit in one of the embodiments of this application;

[0029] Figure 5 This is a circuit schematic diagram of a first embodiment of the reset module in this application;

[0030] Figure 6 This is a temperature characteristic diagram of the LBAT54XV2T1G diode in one embodiment of this application;

[0031] Figure 7 This is a schematic diagram of the structure of a first embodiment of the reset module in this application;

[0032] Figure 8 This is a circuit schematic diagram of a second embodiment of the reset module in one embodiment of this application;

[0033] Figure 9 This is a schematic diagram of a second embodiment of the reset module in one embodiment of this application;

[0034] Figure 10 This is a circuit schematic diagram of a third embodiment of the reset module in one embodiment of this application;

[0035] Figure 11 This is a circuit diagram of a fourth embodiment of the reset circuit in one embodiment of this application.

[0036] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0037] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0038] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0039] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0040] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0041] First, this application introduces the application scenarios that can be provided, such as providing a reset circuit, chip, and electronic device that can achieve the reset function without the need for a RESET pin, and while meeting the requirements of the reset button function, reduce the cost and power consumption of the circuit.

[0042] Please see Figure 1 , Figure 1 This is a schematic diagram of the reset circuit provided in an embodiment of this application. Specifically, the reset circuit may include a power management control module 100 and a reset module 200;

[0043] The reset module 200 is connected to the power management control module 100 and is used to generate a reset signal to control the power management control module 100 and send the reset signal to the power management control module 100.

[0044] The power management control module 100 is located within the system-on-a-chip 10 and is used to receive the reset signal sent by the reset module 200 and reset the power supply according to the reset signal.

[0045] Specifically, for the reset module 200, one end of the reset module is connected to one end of the power management control module 100, and the other end of the reset module is connected to the power supply. The reset module is used to collect the user's action command on the reset button, thereby generating a reset signal for controlling the power management control module, and sending the reset signal to the power management control module through the reset module. For the power management control module 100, the power management control module is set in the system-on-a-chip, for example, it can be integrated into the power management IP (Power Manage Controller, abbreviated as PMC) of the system-on-a-chip. One end of the power management control module is connected to one end of the reset module, and is used to receive the reset signal sent by the reset module, and control the power enable pin of the power management control module to perform reset according to the reset signal. For example, by controlling the power enable pin, the PCB board-level power devices of the target device 20 are powered on and off, thereby realizing the reset function.

[0046] Furthermore, such as Figure 2As shown, in some embodiments, the power management control module 100 may specifically include an output control circuit unit 101, and a first power control unit 102 and a second power control unit 103 respectively connected to the output control circuit unit 101. The output control circuit unit 101 is used to output a corresponding control signal to the first power control unit 102 and the second power control unit 103 according to a reset signal. The first power control unit 102 and the second power control unit 103 are respectively used to control the level state of the corresponding output pins according to the control signal.

[0047] Furthermore, such as Figure 3 As shown, in some embodiments, the first power control unit 101 may specifically include a second MOSFET MP2, a fourth MOSFET MN4, and a first power enable pin PWR_EN0; the second power control unit includes a first MOSFET MP1, a third MOSFET MN3, and a second power enable pin PWR_EN1; wherein the gate of the first MOSFET MP1 is connected to the first terminal of the output control circuit unit 101, the source of the first MOSFET MP1 is connected to the source of the second MOSFET MP2, the drain of the first MOSFET MP1 is connected to the drain of the third MOSFET MN3, and the gate of the second MOSFET MP2 is connected to the output control circuit. At the second terminal of unit 101, the drain of the second MOSFET MP2 is connected to the drain of the fourth MOSFET MN4. The gate of the third MOSFET MN3 is connected to the third terminal of the output control circuit unit 101. The source of the third MOSFET MN3 is connected to the source of the fourth MOSFET MN4 and grounded. The gate of the fourth MOSFET MN4 is connected to the fourth terminal of the output control circuit unit 101. The first power enable pin PWR_EN0 is connected to the drains of the second MOSFET MP2 and the fourth MOSFET MN4, respectively. The second power enable pin PWR_EN1 is connected to the drains of the first MOSFET MP1 and the third MOSFET MN3, respectively. The first MOSFET MP1 and the second MOSFET MP2 are P-type MOSFETs, and the third MOSFET MN3 and the fourth MOSFET MN4 are N-type MOSFETs.

[0048] It should be noted that the power management control module in this embodiment is integrated inside the chip and includes an output control circuit unit, two PWR_EN (Power Enable) pins, and PMOS transistors (first MOS transistor MP1 and second MOS transistor MP2) and NMOS transistors (third MOS transistor MN3 and fourth MOS transistor MN4) to drive the pins high and low.

[0049] Furthermore, in some embodiments, the equivalent internal resistance range of the first MOSFET MP1, the second MOSFET MP2, the third MOSFET MN3, and the fourth MOSFET MN4 is 200 ohms to 500 ohms, and the typical equivalent internal resistance value is 350 ohms.

[0050] The equivalent internal resistance of a PMOS transistor under all PVT (process, voltage, temperature) conditions ranges from 200 ohms to 550 ohms, with a typical equivalent internal resistance of 350 ohms; the equivalent internal resistance of an NMOS transistor under all PVT (process, voltage, temperature) conditions ranges from 200 ohms to 550 ohms, with a typical equivalent internal resistance of 350 ohms.

[0051] Furthermore, in some embodiments, the reset module includes a reset control unit, and a first reset unit and a second reset unit respectively connected to the reset control unit;

[0052] The reset control unit is used to collect the user's actions, generate corresponding reset control signals, and send the reset control signals to the first reset unit and the second reset unit.

[0053] The first reset unit is used to receive the reset control signal sent by the reset control unit, generate a first reset signal according to the reset control signal, and send the first reset signal to the power management control module.

[0054] The second reset unit is used to receive the reset control signal sent by the reset control unit, generate a second reset signal according to the reset control signal, and send the second reset signal to the power management control module.

[0055] Specifically, such as Figure 4 As shown, the reset module 200 in this embodiment may specifically include a reset control unit 201, a first reset unit 202, and a second reset unit 203. The first end of the reset control unit 201 is connected to the first end of the first reset unit 202 and the first end of the second reset unit 203, respectively, and the second end of the reset control unit is grounded. The reset control unit 201 is primarily a mechanical reset button. After the user manually presses the mechanical reset button, the reset control unit 201 collects the user's pressing action, generates a corresponding reset control signal, and sends the reset control signal to the first reset unit and / or the second reset unit connected to it. The first reset unit 202 receives the reset control signal sent by the reset control unit 201, generates a first reset signal for controlling the power management control module based on the reset control signal, and sends the first reset signal to the power management control module. The second reset unit 203 receives the reset control signal sent by the reset control unit 201, generates a second reset signal for controlling the power management module based on the reset control signal, and sends the second reset signal to the power management control module.

[0056] Furthermore, in some embodiments, the first reset unit includes a first resistor and a first diode. One end of the first resistor is connected to the first terminal of the power management control module, the other end of the first resistor is connected to the anode of the first diode, and the cathode of the first diode is connected to the reset control unit. The second reset unit includes a second resistor and a second diode. One end of the second resistor is connected to the second terminal of the power management control module, the other end of the second resistor is connected to the anode of the second diode, and the cathode of the second diode is connected to the reset control unit.

[0057] Specifically, such as Figure 5 As shown, the first reset unit in this embodiment may specifically include a first resistor R1 and a first diode D1. One end of the first resistor R1 is connected to the first terminal of the power management control module, and the other end of the first resistor R1 is connected to the positive terminal of the first diode D1. The negative terminal of the first diode D1 is connected to one end of the reset button SW1 in the reset control unit. The second reset unit in this embodiment may specifically include a second resistor R2 and a second diode D2. One end of the second resistor R2 is connected to the first terminal of the power management control module, and the other end of the second resistor R2 is connected to the positive terminal of the second diode D2. The negative terminal of the second diode D2 is connected to one end of the reset button SW1 in the reset control unit.

[0058] It should be noted that the first resistor R1 in the first reset unit and the second resistor R2 in the second reset unit are high-resistance resistors. The functions of the first resistor R1 and the second resistor R2 are mainly twofold: firstly, they provide ESD (Electro-Static Discharge) protection. Since the mechanical reset button is manually operated, contact discharge and air discharge can enter through the button. The first resistor R1 and the second resistor R2 "block" ESD intrusion, thus reducing the ESD voltage. Secondly, they reduce the current on the power enable pin of the on-chip system chip when the reset button is pressed. Without the high-resistance first and second resistors, the maximum current on the power enable pin is 16.5mA, and the total current on both pins is 33mA. Excessive current draw at the moment of pressing the reset button would cause a voltage drop, which could affect the stability of the PMC circuit. The high-resistance resistors, combined with the current on the latter two pins, result in a total current of 0.33mA, which is negligible. At the same time, choosing a high-resistance resistor helps to reduce the forward voltage of the first / second diode in the subsequent stage, so that when the reset button is pressed, the forward voltage of the first / second diode will not exceed the cutoff voltage value of the enable pin of the commonly used discrete power supply DC-DC / LDO device.

[0059] In this embodiment, the first diode D1 and the second diode D2 can be diodes with low forward voltage drop, which are used to isolate the two power enable pins (PWR_EN0 pin and PWR_EN1 pin) in the system-on-chip, to prevent the voltage of the PWR_EN1 pin from being affected when the product enters sleep mode and turns off the PWR_EN0 pin.

[0060] It is understood that the reset module in this embodiment is located on the periphery of the chip and is used in conjunction with the two PWR_EN pins (PWR_EN0 and PWR_EN1) of the power management control module. The reset module consists of two resistors (R1 and R2), two diodes (D1 and D2), a mechanical button (SW1), and two PWR-EN networks (PWR-EN0 and PWR-EN1). When the mechanical button is pressed, both sides of the button are conductive, and the two diodes are connected to ground (GND). When the mechanical button is released, both sides of the button are open-circuited, and the two diodes are not connected to ground.

[0061] Furthermore, in some embodiments, the forward voltage drop of the first diode D1 and the second diode D2 is less than or equal to 0.4V, and the resistance value is greater than 1.43K ohms.

[0062] In addition, to better implement the reset circuit provided in this embodiment, the forward voltage drop of the first diode D1 and the second diode D2 is <= 0.4V, the equivalent internal resistance range of the PMOS transistors (first MOS transistor MP1 and second MOS transistor MP2) and the NMOS transistors (third MOS transistor MN3 and fourth MOS transistor MN4) is 200 ohms to 550 ohms, the typical equivalent internal resistance value is 350 ohms, and the values ​​of the first resistor R1 and the second resistor R2 are both greater than 1.43K ohms.

[0063] Using the temperature characteristic diagrams of common diodes, taking the LBAT54XV2T1G diode as an example:

[0064] The prerequisite is that both diodes D1 and D2 must be low forward voltage drop diodes, with a forward voltage drop of <= 0.4V within a temperature range of -40 to 85°C and within the manufacturing tolerances of the diodes themselves. This is because the cutoff voltage of a DC / DC converter is approximately 0.4V. Figure 6As shown, the diode's forward voltage is highest at low temperatures, so using the -55℃ curve as the standard can cover the worst case. At this temperature, a 0.4V forward voltage corresponds to 0.002A, or 2mA. When the MOSFET is outputting, the internal resistance is 220Ω to 550Ω. When the internal resistance is 220Ω, the external resistance is at its minimum. Calculated based on a 2mA current and a 3.3V voltage, the resistance is 1.43K ohms. Therefore, the resistance values ​​of the first resistor R1 and the second resistor R2 should be greater than 1.43K ohms.

[0065] Furthermore, such as Figure 7 As shown, in some embodiments, the reset module 200 further includes a power enable network unit 204, which includes a first power enable network 2041 (PWR-EN1 network) and a second power enable network 2042 (PWR-EN1 network) for controlling the operating state of the power chip connected to the target device 20; one end of the first power enable network 2041 is connected to the first reset unit 202, and the other end of the first power enable network 2041 is connected to the power chip of the target device; one end of the second power enable network 2042 is connected to the second reset unit 203, and the other end of the second power enable network 2042 is connected to the power chip of the target device.

[0066] Furthermore, such as Figure 8 As shown, in some embodiments, one end of the first power enable network is connected to the other end of the first resistor R1 and the positive terminal of the first diode D1, the other end of the first power enable network is connected to the first terminal of the power chip of the target device, the other end of the second power enable network is connected to the other end of the second resistor R2 and the positive terminal of the second diode D2, and the other end of the second power enable network is connected to the second terminal of the power chip of the target device.

[0067] Specifically, the power enable network unit 204 in this embodiment includes a PWR-EN0 network and a PWR-EN1 network, which are power chip enable pins connected to the product. When the PWR-EN network is high, the power chip is turned on and the product is powered on. When the PWR-EN network is low, the power chip is turned off and the product is powered off.

[0068] Furthermore, in some embodiments, the reset module further includes an anti-static unit, which is connected to the reset control unit, the first reset unit, and the second reset unit respectively, for providing anti-static protection for the reset control unit.

[0069] Specifically, such as Figure 9As shown, the reset module 200 in this embodiment may further include an anti-static unit 205, wherein one end of the anti-static unit 205 is connected to one end of the reset control unit 201, one end of the first reset unit 202, and one end of the second reset unit 203, respectively. The anti-static unit 205 in this embodiment is mainly used to provide ESD protection for the reset button in the reset control unit.

[0070] Specifically, such as Figure 10 As shown, the anti-static unit in this embodiment may specifically include an ESD diode D3, wherein one end of the ESD diode D3 is connected to the negative terminal of the first diode D1, the negative terminal of the second diode D2 and one end of the reset button SW1 respectively, and the other end of the ESD diode D3 is grounded. The reset button in the reset control unit is protected by the ESD diode D3 to prevent the intrusion of contact discharge and air discharge.

[0071] To facilitate understanding of the reset circuit provided in this embodiment, the specific usage process of the reset circuit will be illustrated below with examples. Please refer to [link / reference needed]. Figure 11 .

[0072] When the chip is powered on, the power management control module hardware automatically turns on the PMOS transistors (MP1 and MP2) on the two PWR_EN pins through the output control circuit unit. At this time, the NMOS transistors (MN3 and MN4) are turned off, and the pins are driven high, with a voltage level of PMC-AVCC33, i.e., 3.3V. Meanwhile, the mechanical button of the reset button circuit module is released, creating an open circuit on both sides of the button. The two diodes (D1 and D2) cannot be connected to ground. Therefore, the voltage levels of the PWR-EN0 and PWR-EN1 networks are 3.3V, the power chip of the target device is turned on, and the product is in a powered-on state.

[0073] When a product encounters an malfunction and needs to be reset, the mechanical button is pressed, energizing both sides of the button. Two diodes (D1 and D2) are connected to ground. At this time, the PMC-AVCC33, PMOS transistor, resistor, diode, mechanical button, and ground form a current loop. Circuit analysis shows that the PWR-EN network level is pulled low, and the voltage is the diode's forward voltage. After the PWR-EN network level goes low, the power chip on the product is turned off, and the product is powered down. When the mechanical button is released, the power-on process returns to the aforementioned chip, and the product is powered on again. The power-down and power-on process triggered by pressing and releasing the mechanical button constitutes the reset process.

[0074] When the product is powered off, the power management control module turns on the NMOS transistors (MN3 and MN4) on the two PWR_EN pins through the output control circuit unit. At this time, the PMOS transistors (MP1 and MP2) are turned off. The power chip, PWR-EN network, resistor, NMOS transistor, and ground form a current loop. Circuit analysis shows that the level of the PWR-EN network is pulled low, the voltage is close to 0V, the power chip is turned off, and the chip is powered off.

[0075] Compared with existing technologies, the reset circuit provided in this embodiment has the following advantages: After the RESET button is pressed, the maximum voltage level of the PWR-EN0 and PWR-EN1 pins is 0.33V, while the enable pin turn-off threshold of mainstream discrete power supply DC-DC / LDO devices is >=0.4V, enabling control of the switching of mainstream discrete power supply DC-DC / LDO devices; the RESET button is a mechanical button, and there will be mechanical bounce when it is pressed and released, which this circuit can eliminate; the falling edge and rising edge times of the PWR-EN0 and PWR-EN1 pins corresponding to the pressing and releasing actions of the RESET button are very short, with the falling edge time of the pressing action being <1ms and the rising edge time of the releasing action being about 5.2ms, which are very short and meet the two actions of manual button operation: rapid pressing and normal pressing; after the RESET button is pressed, the current loss of the circuit itself is 0.33mA, and the heat generation is minimal. It meets the consumer-grade temperature range of 0℃-70℃, and after testing and verification, it can actually meet the temperature range of -40℃-125℃, far exceeding the requirements of consumer-grade applications.

[0076] This application also provides a chip including the reset circuit described above.

[0077] This application also provides an electronic device, including the reset circuit described above or the chip described above.

[0078] As can be seen from the above, the present application provides a reset circuit, chip, and electronic device. The reset circuit includes a power management control module and a reset module. The reset module is connected to the power management control module and is used to generate a reset signal to control the power management control module and send the reset signal to the power management control module. The power management control module is located within the system-on-a-chip (SoC) and is used to receive the reset signal sent by the reset module and reset the power supply according to the reset signal. This application achieves the reset function by setting a power management control module within the SoC and combining it with a reset function connected to the power management control module to replace the RESET pin. This eliminates the need to specifically bring out a dedicated RESET pin on the SoC, enhancing the flexibility of the chip pins. Furthermore, by building a reset module with a reset button to control the power enable pin of the SoC to achieve the reset function, the structure is simple and can reduce circuit cost and power consumption while meeting the reset button function requirements.

[0079] That is, the above description is only an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, such as the combination of technical features between different embodiments, or direct or indirect application in other related technical fields, are similarly included within the patent protection scope of this application.

[0080] Furthermore, for structural elements with the same or similar characteristics, this application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0081] In this application, the word "for example" is used to mean "used as an example, illustration, or explanation." Any embodiment described as "for example" in this application is not necessarily to be construed as more preferred or advantageous than other embodiments. This application has been provided above to enable any person skilled in the art to make and use it. Various details have been set forth in the above description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other embodiments, well-known structures and processes will not be described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

Claims

1. A reset circuit, characterized in that, Includes a power management control module and a reset module; The reset module is connected to the power management control module and is used to generate a reset signal to control the power management control module and send the reset signal to the power management control module. The power management control module, located within the system-on-a-chip (SoC), receives a reset signal from the reset module and resets the power supply according to the reset signal. The power management control module includes an output control circuit unit, and a first power control unit and a second power control unit connected to the output control circuit unit. The output control circuit unit outputs a corresponding control signal to the first power control unit and the second power control unit according to the reset signal. The first power control unit and the second power control unit control the level state of their respective output pins according to the control signal. The first power control unit includes a second MOSFET, a fourth MOSFET, and a first power enable pin. The second power control unit includes a first MOSFET, a third MOSFET, and a second power enable pin. The gate of the first MOSFET is connected to the first terminal of the output control circuit unit. The source of the first MOSFET is connected to the source of the second MOSFET. The drain of the first MOSFET is connected to the drain of the third MOSFET. The gate of the second MOSFET is connected to the second terminal of the output control circuit unit. The drain of the second MOSFET is connected to the drain of the fourth MOSFET. The gate of the third MOSFET is connected to the third terminal of the output control circuit unit. The source of the third MOSFET is connected to the source of the fourth MOSFET and grounded. The gate of the fourth MOSFET is connected to the fourth terminal of the output control circuit unit. The first power enable pin is connected to the drain of the second MOSFET and the drain of the fourth MOSFET. The second power enable pin is connected to the drain of the first MOSFET and the drain of the third MOSFET.

2. The reset circuit according to claim 1, characterized in that, The equivalent internal resistance range of the first MOSFET, the second MOSFET, the third MOSFET, and the fourth MOSFET is 200 ohms to 500 ohms, and the typical equivalent internal resistance value is 350 ohms.

3. The reset circuit according to claim 1, characterized in that, The reset module includes a reset control unit, and a first reset unit and a second reset unit respectively connected to the reset control unit; The reset control unit is used to collect the user's actions, generate corresponding reset control signals, and send the reset control signals to the first reset unit and the second reset unit. The first reset unit is used to receive a reset control signal sent by the reset control unit, generate a first reset signal according to the reset control signal, and send the first reset signal to the power management control module. The second reset unit is used to receive the reset control signal sent by the reset control unit, generate a second reset signal according to the reset control signal, and send the second reset signal to the power management control module.

4. The reset circuit according to claim 3, characterized in that, The first reset unit includes a first resistor and a first diode. One end of the first resistor is connected to the first terminal of the power management control module, and the other end of the first resistor is connected to the anode of the first diode. The cathode of the first diode is connected to the reset control unit. The second reset unit includes a second resistor and a second diode. One end of the second resistor is connected to the second terminal of the power management control module, and the other end of the second resistor is connected to the anode of the second diode. The cathode of the second diode is connected to the reset control unit.

5. The reset circuit according to claim 4, characterized in that, The forward voltage drop of both the first diode and the second diode is less than or equal to 0.4V, and their resistance is greater than 1.43K ohms.

6. The reset circuit according to claim 4, characterized in that, The reset module further includes a power enable network unit, which includes a first power enable network and a second power enable network for controlling the operating state of the power chip connected to the target device. One end of the first power enable network is connected to the first reset unit, and the other end of the first power enable network is connected to the power chip of the target device. One end of the second power enable network is connected to the second reset unit, and the other end of the second power enable network is connected to the power chip of the target device.

7. The reset circuit according to claim 6, characterized in that, One end of the first power enable network is connected to the other end of the first resistor and the positive terminal of the first diode, and the other end of the first power enable network is connected to the first terminal of the power chip of the target device. The other end of the second power enable network is connected to the other end of the second resistor and the positive terminal of the second diode, and the other end of the second power enable network is connected to the second terminal of the power chip of the target device.

8. The reset circuit according to claim 3, characterized in that, The reset module also includes an anti-static unit, which is connected to the reset control unit, the first reset unit, and the second reset unit respectively, and is used to provide anti-static protection for the reset control unit.

9. A chip, characterized in that, Includes the reset circuit as described in any one of claims 1-8.

10. An electronic device, characterized in that, Includes the reset circuit as described in any one of claims 1-8 or the chip as described in claim 9.

Images