Data storage device and cache size estimation method for data storage device

Abstract

The present invention relates to a data storage device and a method for estimating a cache size of a data storage device. The data storage device comprises a memory device and a memory controller. The memory device includes a plurality of memory blocks, which include one or more free memory blocks that have not yet been written with data, and one or more intended memory blocks configured as a cache to receive data from a host device. The memory controller obtains a total amount of remaining erasable times of the memory blocks, and determines a current setting value of a number of the one or more intended memory blocks according to a number of currently remaining free memory blocks, a number of intended memory blocks of the one or more intended memory blocks that have been written with data, a predetermined threshold value, and the total amount of remaining erasable times, and configures the number of intended memory blocks as the cache according to the current setting value.

Description

Technical Field

[0001] This invention relates to a method for estimating the current write cache size, and more particularly to a method for accurately estimating the current write cache size. Background Technology

[0002] With the rapid development of data storage technology in recent years, many data storage devices, such as those conforming to Secure Digital (SD) / Multi Media Card (MMC), Compact Flash (CF), Memory Stick (MS), Extreme Digital (XD) memory cards, solid-state drives, embedded Multi Media Card (eMMC), and Universal Flash Storage (UFS), have been widely used for various purposes.

[0003] Data storage devices typically employ write buffers to receive data from the host. The type and size of the write buffer affect the data write speed and the host's handling of the amount of data written, ultimately impacting the data storage device's access performance. Furthermore, the data storage device's access performance directly influences the user experience.

[0004] Therefore, accurately estimating the current configurable write cache size to avoid significant changes in data write speed and maintain a better user experience is a topic worthy of attention in this field. Summary of the Invention

[0005] One object of the present invention is to provide a method for accurately estimating the current write buffer size in order to avoid large variations in data write speed and maintain a better user experience.

[0006] According to one embodiment of the present invention, a data storage device includes a memory device and a memory controller. The memory device includes a plurality of memory blocks, including one or more free memory blocks that have not yet been written to, and one or more predetermined memory blocks configured as caches to receive data from a host device. The memory controller is coupled to the memory device for accessing the memory device. The memory controller obtains a total number of remaining eraseable counts for the memory blocks, and determines a current set value for a number of the one or more predetermined memory blocks based on a current number of remaining free memory blocks, a number of predetermined memory blocks that have been written to, a predetermined threshold, and the total number of remaining eraseable counts. The memory controller then configures that number of predetermined memory blocks as caches based on the current set value.

[0007] According to an embodiment of the present invention, a method for estimating the size of a buffer is applicable to a data storage device, the data storage device including a memory device and a memory controller, the memory device including a plurality of memory blocks, the memory blocks including one or more free memory blocks that have not yet been written to, and one or more predetermined memory blocks configured as buffers for receiving data from a host device, the method comprising: obtaining a number of currently remaining free memory blocks; obtaining a number of predetermined memory blocks that have been written to; obtaining a total number of remaining erasure counts for the memory blocks; determining a current set value for a number of the one or more predetermined memory blocks based on the number of currently remaining free memory blocks, the number of predetermined memory blocks that have been written to, the total number of remaining erasure counts for the memory blocks, and a predetermined threshold; and configuring the number of predetermined memory blocks as buffers according to the current set value. Attached Figure Description

[0008] Figure 1 Figure 1 This is a block diagram example of a data storage device according to an embodiment of the present invention.

[0009] Figure 2 The diagram shows a simplified flowchart of the buffer size estimation method according to the first embodiment of the present invention.

[0010] Figure 3 The diagram shows a detailed flowchart of the buffer size estimation method according to the first embodiment of the present invention.

[0011] Figure 4 The diagram shows a simplified flowchart of the buffer size estimation method according to the second embodiment of the present invention.

[0012] Figure 5The diagram shows a detailed flowchart of the buffer size estimation method according to the second embodiment of the present invention.

[0013] [Symbol Explanation] 100: Data storage device 110: Memory controller 112: Microprocessor 112C: Program Code 112M: Read-Only Memory 114: Memory Interface 116: Cache memory 118: Host Interface 120: Memory device 130: Main unit 132: Encoder 134: Decoder Detailed Implementation

[0014] Numerous specific details are described below to provide a thorough understanding of embodiments of the invention. However, those skilled in the art will appreciate how the invention can be practiced in the absence of one or more specific details or in reliance on other methods, elements, or materials. In other instances, well-known structures, materials, or operations have not been shown or described in detail to avoid obscuring the main concepts of the invention.

[0015] Throughout this specification, references to "an embodiment" or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one of the various embodiments of the invention. Therefore, the phrases "in an embodiment of the invention," "according to an embodiment of the invention," "in an example," or "according to an example" appearing in various places throughout this specification do not necessarily refer to the same embodiment or example. Furthermore, specific features, structures, or characteristics may be combined in any suitable combination and / or sub-combination in one or more embodiments or examples.

[0016] Furthermore, to make the objectives, features, and advantages of the present invention more apparent and understandable, specific embodiments of the present invention are described below in detail with reference to the accompanying drawings. The purpose is to illustrate the spirit of the present invention and not to limit the scope of protection of the present invention. It should be understood that the following embodiments can be implemented by software, hardware, firmware, or any combination thereof.

[0017] Figure 1This is a block diagram example of a data storage device according to an embodiment of the present invention. The data storage device 100 may include a memory device 120 and a memory controller 110. The memory controller 110 is used to access the memory device 120 and control the operation of the memory device 120. The memory device 120 may be a non-volatile (NV) memory device (e.g., a flash memory) and may include one or more memory elements (e.g., one or more flash memory dies, one or more flash memory chips, or other similar elements).

[0018] Data storage device 100 may be coupled to a host device 130. Host device 130 may include at least a processor, a power supply circuit, and at least one random access memory (RAM), such as at least one dynamic random access memory (DRAM), at least one static random access memory (SRAM), etc. (not shown above). Figure 1 The processor and random access memory (RAM) can be interconnected via a bus and coupled to a power supply circuit to obtain power. The processor controls the operation of the host device 130. The power supply circuit can supply power to the processor, RAM, and data storage device 100, for example, by outputting one or more drive voltages to the data storage device 100. The data storage device 100 can obtain the drive voltage from the host device 130 as its power source and provide storage space for the host device 130.

[0019] According to one embodiment of the present invention, the memory controller 110 may include a microprocessor 112, a read-only memory (ROM) 112M, a memory interface 114, a cache memory 116, and a host interface 118. The read-only memory 112M is used to store program code 112C. The microprocessor 112 is used to execute program code 112C to control access operations to the memory device 120. Program code 112C may include one or more program modules, such as boot loader program code. When the data storage device 100 receives power from the host device 130, the microprocessor 112 can execute an initialization program of the data storage device 100 by executing program code 112C. In the initialization program, the microprocessor 112 may load a set of in-system programming (ISP) program code (not shown) from the memory device 120. Figure 1The microprocessor 112 can execute this set of in-system programming code, enabling the data storage device 100 to possess various functions. According to one embodiment of the invention, this set of in-system programming code may include, but is not limited to: one or more program modules related to memory access (e.g., read, write, and erase), such as a read operation module, a lookup table module, a wear leveling module, a read refresh module, a read reclaim module, a garbage collection module, a sudden power off recovery (SPOR) module, and an uncorrectable error correction code (UECC) module, which are respectively provided to perform corresponding read, lookup table, wear leveling, read refresh, read reclaim, garbage collection, sudden power off recovery, and error handling of detected UECC errors.

[0020] The memory interface 114 includes an encoder 132 and a decoder 134, wherein the encoder 132 is used to encode the data to be written to the memory device 120, for example, by performing error correction code (ECC) encoding, and the decoder 134 is used to decode the data read from the memory device 120.

[0021] In a typical configuration, memory device 120 includes multiple memory elements, such as multiple flash memory dies or multiple flash memory chips, and each memory element may contain multiple memory blocks. The memory controller 110 performs data erasure operations on memory device 120 on a block-by-block basis. Additionally, a memory block may record (contain) a specific number of data pages, such as physical data pages, wherein the memory controller 110 performs data writing operations on memory device 120 on a page-by-page basis.

[0022] In practice, the memory controller 110 can use its internal components to perform various control operations, such as using the memory interface 114 to control the access operations of the memory device 120 (especially the access operations to at least one memory block or at least one data page), using the cache memory 116 to perform the necessary caching operations, and using the host interface 118 to communicate with the host device 130.

[0023] In one embodiment, the memory controller 110 communicates with the host device 130 via the host interface 118 and using a standard communication protocol. For example, the aforementioned standard communication protocol includes (but is not limited to): Universal Serial Bus (USB) standard, SD interface standard, Ultra High Speed-I (UHS-I) interface standard, Ultra High Speed-II (UHS-II) interface standard, CF interface standard, MMC interface standard, eMMC interface standard, UFS interface standard, Advanced Technology Attachment (ATA) standard, Serial ATA (SATA) standard, Peripheral Component Interconnect Express (PCI-E) standard, Parallel Advanced Technology Attachment (PATA) standard, etc.

[0024] In one embodiment, cache memory 116 is implemented as random access memory. For example, cache memory 116 may be static random access memory, but the invention is not limited thereto. In other embodiments, cache memory 116 may be dynamic random access memory.

[0025] In one embodiment, the data storage device 100 may be a portable storage device (e.g., a memory card conforming to SD / MMC, CF, MS, or XD standards), and the host device 130 may be an electronic device that can be connected to the data storage device, such as a mobile phone, laptop, desktop computer, etc. In another embodiment, the data storage device 100 may be a solid-state drive or an embedded storage device conforming to UFS or eMMC specifications, and may be disposed in an electronic device, such as a mobile phone, laptop, or desktop computer, in which case the host device 130 may be a processor of the electronic device.

[0026] The host device 130 may issue instructions to the data storage device 100, such as read instructions or write instructions, to access the data stored in the memory device 120, or the host device 130 may issue instructions to the data storage device 100 to further control and manage the data storage device 100.

[0027] Generally, the memory controller 110 can be configured with one or more predetermined memory blocks as cache memory, also known as buffers, current blocks, or active blocks, for receiving data from the host device 130. The configured predetermined memory blocks can be single-level cell (SLC) memory blocks, multiple-level cell (MLC) memory blocks, triple-level cell (TLC) memory blocks, or other memory blocks with more than one level of cells. When the utilization rate of the cache reaches a certain level, the memory controller 110 can perform a flush operation to write the data stored in the cache to another memory block (for example, merging the data stored in multiple SLC memory blocks and storing it in a TLC memory block), and make it a data block of the user area or data area of ​​the memory device 120, or directly update the memory block used as a cache to a data block of the user area or data area. In this way, the memory space of the cache can be released and reused.

[0028] Furthermore, the host device 130 can decide whether to enable the WriteBooster function on the data storage device 100. When the WriteBooster function is enabled, the memory controller 110 configures SLC memory blocks as caches to receive data from the host device 130. Since writing data to SLC memory blocks is faster than writing data to other types of memory blocks (e.g., MLC, TLC, or others), this allows data writing to operate in a high-speed mode.

[0029] The host device 130 can control the write accelerator of the data storage device 100 by issuing corresponding commands. For example, the host device 130 can set a corresponding flag or issue a command to enable the write accelerator to enable the write accelerator function on the data storage device 100 by issuing corresponding commands.

[0030] When the write accelerator function is enabled, the host device 130 may further issue an inquiry command to the data storage device 100 to inquire about the current buffer size configured by the memory controller 110. For example, the host device 130 may inquire about the status of the write accelerator from the data storage device 100 by reading attributes, which may include the current write accelerator buffer size (Current_Write_Booster_Buffer_Size), the remaining available write accelerator buffer size (Available_Write_Booster_Buffer_Size), etc.

[0031] Upon receiving an inquiry command from host device 130, host device 130 can calculate or estimate the current cache size (e.g., calculate or estimate the number of established memory blocks that can be configured as a cache) and send the estimate back to host device 130. Existing estimation methods only consider the number of free memory blocks within memory device 120, where free memory blocks are memory blocks whose data has been erased and have not yet been written to, nor configured for any other purpose. However, considering only the number of free memory blocks will begin to produce incorrect estimation results after data is written to the configured established memory blocks, causing host device 130 to fail to obtain accurate cache size information. Since host device 130 arranges subsequent data writes based on the obtained cache size information, incorrect cache size information will further cause significant changes in data write speed, which is an undesirable result.

[0032] To address the aforementioned issues, this invention proposes a method for estimating cache size, which can accurately calculate or estimate the currently configurable write cache size to avoid significant variations in data write speed.

[0033] Figure 2 This is a simplified flowchart of the cache size estimation method according to a first embodiment of the present invention, including the following steps performed by the memory controller 110: Step S202: Obtain the number of currently remaining free memory blocks.

[0034] Step S204: Obtain the number of predetermined memory blocks in one or more predetermined memory blocks that have been written with data.

[0035] Step S206: Determine a current set value (i.e., the latest cache size setting value) for the number of a given number of memory blocks based on the number of currently remaining free memory blocks, the number of given memory blocks that have been written with data, and a given threshold.

[0036] Step S208: Configure the predetermined number of memory blocks as a cache according to the current setting value.

[0037] In one embodiment of the present invention, as Figure 2 The process for estimating the buffer size shown can begin execution in response to receiving an inquiry command from the host device 130, and can send the current setting value back to the host device 130 after determining the current setting value.

[0038] According to an embodiment of the present invention, in step S206, the memory controller 110 may determine a number of valid free memory blocks based on the number of currently remaining free memory blocks and the predetermined number of memory blocks that have been written with data, and determine a current set value based on a difference between the number of valid free memory blocks and a predetermined threshold.

[0039] More specifically, in one embodiment of the present invention, the number of effective free memory blocks is the sum of the number of currently remaining free memory blocks and the number of predetermined memory blocks that have been written with data.

[0040] Furthermore, according to one embodiment of the present invention, in step S206, the memory controller 110 may further determine whether the number of valid free memory blocks is less than a predetermined threshold. The predetermined threshold may be a minimum allowed number of free memory blocks, or a free memory block number threshold configured to trigger a garbage collection (GC) process. That is, when the number of currently remaining free memory blocks is determined to be less than the predetermined threshold, the memory controller 110 will trigger a garbage collection process to release memory space storing invalid data, thereby increasing the number of free memory blocks.

[0041] In one embodiment of the present invention, if the number of valid free memory blocks is less than a predetermined threshold, the memory controller 110 may set the current setting value to 0 and send this current setting value back to the host device 130 in step S208. If the number of valid free memory blocks is not less than (i.e., greater than or equal to) the predetermined threshold, the memory controller 110 may set the current setting value to the difference between the number of valid free memory blocks and the predetermined threshold, so as to avoid triggering the garbage collection process due to insufficient free memory blocks during the process of receiving data from the host device 130.

[0042] Figure 3 This is a detailed flowchart of the buffer size estimation method according to the first embodiment of the present invention. Figure 3In this example, the write accelerator function is enabled, so the designated memory block used as a cache is configured as an SLC memory block, and the cache size estimation method of the first embodiment of the present invention includes the following steps initiated by the memory controller 110 in response to receiving an interrogation command from the host device 130: Step S302: Calculate or obtain the number of currently remaining free memory blocks (Left_Spare_Blk). The memory controller 110 can calculate the number of currently remaining free memory blocks based on the relevant values ​​it records, or it can obtain this information by reading a corresponding counter value used to record the number of remaining free memory blocks.

[0043] Step S304: Calculate or obtain a number (Used_SLC_Blk) of SLC memory blocks that have been written to in one or more SLC memory blocks (i.e., designated memory blocks) configured as a cache. The memory controller 110 may calculate the number of designated memory blocks that have been written to based on the relevant values ​​it records, or it may obtain this information by reading a counter value used to record the number of designated memory blocks that have been written to.

[0044] Step S306: Calculate the number of valid free memory blocks (Valid_Spare_Blk), wherein the memory controller 110 can add the number of currently remaining free memory blocks (Left_Spare_Blk) to the number of SLC memory blocks (Used_SLC_Blk) that have been written with data to obtain the number of valid free memory blocks (Valid_Spare_Blk), which can be expressed as (Valid_Spare_Blk = Left_Spare_Blk + Used_SLC_Blk). Since the existing memory blocks that have been written to (in this embodiment, SLC memory blocks) can be flushed and their stored data stored in another memory block (e.g., TLC memory block) or unmapped and their stored data discarded, and after these operations are completed, these existing memory blocks can be released as free memory blocks for reuse, the number of valid free memory blocks can be calculated by taking the sum of the number of currently remaining free memory blocks and the number of existing memory blocks that have been written to as the number of valid free memory blocks.

[0045] Step S308: Determine whether the number of valid free memory blocks (Valid_Spare_Blk) is greater than or equal to a predetermined threshold, such as a threshold number of free memory blocks (GC_TH) that will trigger garbage collection (GC). If not, it means the number of valid free memory blocks is less than the predetermined threshold, and proceed to step S310. If yes, it means the number of valid free memory blocks is not less than the predetermined threshold, and proceed to step S312.

[0046] Step S310: The memory controller 110 can set the current setting value of the predetermined number of memory blocks to 0, which can be expressed as (Current_Size=0) in mathematical terms. The value of Current_Size represents the write accelerator cache size currently estimated by the memory controller 110. Therefore, the write accelerator cache size currently estimated by the memory controller 110 is 0, and this estimate is sent back to the host device 130.

[0047] Step S312: The memory controller 110 can set the current setting to the difference between the number of valid free memory blocks and a predetermined threshold. This can be expressed as (Current_Size = Valid_Spare_Blk - GC_TH). Therefore, the write accelerator cache size currently estimated by the memory controller 110 is (Valid_Spare_Blk - GC_TH).

[0048] Step S314: The memory controller 110 sends this estimate (i.e., the current setting (Current_Size)) back to the host device 130.

[0049] By implementing the cache size estimation method proposed in this invention, the currently configurable write cache size can be accurately calculated or estimated to avoid significant changes in data write speed.

[0050] In a second embodiment of the present invention, when estimating the size of the cache, the memory controller 110 may further refer to the remaining number of erase operations that can still be performed on the memory blocks of the data storage device 100, thereby providing better protection for the data storage device 100 after it has been used for a period of time.

[0051] Figure 4 This is a simplified flowchart of the cache size estimation method according to a second embodiment of the present invention, including the following steps performed by the memory controller 110: Step S402: Obtain the number of currently remaining free memory blocks.

[0052] Step S404: Obtain the number of predetermined memory blocks in one or more predetermined memory blocks that have been written with data and configured as a cache.

[0053] Step S406: Obtain a total number of remaining erasure counts for the memory blocks of the data storage device 100.

[0054] Step S408: Determine a current set value (i.e., the latest cache size setting value) for the number of the one or more predetermined memory blocks based on the number of currently remaining free memory blocks, the number of predetermined memory blocks that have been written to, the total number of remaining erasure counts for memory blocks, and a predetermined threshold.

[0055] Step S410: Configure the predetermined number of memory blocks as a cache according to the current setting value.

[0056] In one embodiment of the present invention, as Figure 4 The process for estimating the buffer size shown can begin execution in response to receiving an inquiry command from the host device 130, and can send the current setting value back to the host device 130 after determining the current setting value.

[0057] According to one embodiment of the present invention, the memory controller 110 can record the number of times each memory block has been erased (Erase_Cnt), and can sum the number of times each memory block of the data storage device 100 has been erased (Erase_Cnt) to obtain the total number of erase counts corresponding to the data storage device 100. Furthermore, the memory controller 110 can also record an upper limit value for the total number of erase counts. This value can be set according to customer requirements, representing the upper limit of the total number of erase counts allowed for the data storage device 100, and can be written into the read-only memory (ROM) 112M during the manufacturing process. The memory controller 110 can obtain a total number of remaining eraseable counts (Left_Erase_Cnt) for the memory blocks of the data storage device 100 by subtracting the total number of erase counts corresponding to the current data storage device 100 from the upper limit value for the total number of erase counts.

[0058] Furthermore, according to an embodiment of the present invention, in step S408, the memory controller 110 may determine a number of valid free memory blocks based on the number of currently remaining free memory blocks and the predetermined number of memory blocks that have been written with data, and determine a current setting value (which may be an initial setting value) based on a difference between the number of valid free memory blocks and a predetermined threshold.

[0059] More specifically, in one embodiment of the present invention, the number of effective free memory blocks is the sum of one of the number of currently remaining free memory blocks and the number of predetermined memory blocks that have been written with data.

[0060] Furthermore, according to an embodiment of the present invention, in step S408, the memory controller 110 may further determine whether the number of valid free memory blocks is less than a predetermined threshold, wherein the predetermined threshold may be a minimum allowed number of free memory blocks, or a free memory block number threshold configured to trigger a garbage collection (GC) process.

[0061] In one embodiment of the present invention, if the number of valid free memory blocks is less than a predetermined threshold, the memory controller 110 may set the current setting value to 0, and in step S410, this current setting value is sent back to the host device 130. If the number of valid free memory blocks is not less than (i.e., greater than or equal to) the predetermined threshold, the memory controller 110 may set the current setting value to the difference between the number of valid free memory blocks and the predetermined threshold, so as to avoid triggering the garbage collection process due to insufficient free memory blocks during the process of receiving data from the host device 130.

[0062] Furthermore, in step S408, the memory controller 110 may determine whether to modify the current setting value based on a total number of remaining erasable counts (Left_Erase_Cnt). When the total number of remaining erasable counts is not less than the current setting value, the memory controller 110 does not modify the current setting value. When the total number of remaining erasable counts is less than the current setting value, the memory controller 110 may modify the current setting value to one of the total number of remaining erasable counts to avoid the total number of erasable counts for memory blocks of the data storage device 100 exceeding the upper limit of the total number of erasable counts. It should be noted that since the memory controller 110 performs data erasure operations on the memory device 120 on a block-by-block basis, the total number of remaining erasable counts can be regarded as the number of memory blocks that can still be erased.

[0063] Figure 5 This is a detailed flowchart of the buffer size estimation method according to the second embodiment of the present invention. Figure 5 In this example, the write accelerator function is enabled, so the designated memory block used as a cache is configured as an SLC memory block, and the cache size estimation method of the second embodiment of the present invention includes the following steps initiated by the memory controller 110 in response to receiving an interrogation command from the host device 130: Step S502: Calculate or obtain the number of currently remaining free memory blocks (Left_Spare_Blk). The memory controller 110 can calculate the number of currently remaining free memory blocks based on the relevant values ​​it records, or it can obtain this information by reading one of the count values ​​used to record the number of remaining free memory blocks.

[0064] Step S504: Calculate or obtain a number (Used_SLC_Blk) of SLC memory blocks that have been written to in one or more SLC memory blocks (i.e., designated memory blocks) configured as a cache. The memory controller 110 may calculate the number of designated memory blocks that have been written to based on the relevant values ​​it records, or it may obtain this information by reading a counter value used to record the number of designated memory blocks that have been written to.

[0065] Step S506: Calculate the number of valid free memory blocks (Valid_Spare_Blk), wherein the memory controller 110 can add the number of currently remaining free memory blocks (Left_Spare_Blk) to the number of SLC memory blocks (Used_SLC_Blk) that have been written with data to obtain the number of valid free memory blocks (Valid_Spare_Blk), which can be expressed as (Valid_Spare_Blk = Left_Spare_Blk + Used_SLC_Blk). Since the existing memory blocks that have been written to (in this embodiment, SLC memory blocks) can be flushed and their stored data stored in another memory block (e.g., TLC memory block) or unmapped and their stored data discarded, and after these operations are completed, these existing memory blocks can be released as free memory blocks for reuse, the number of valid free memory blocks can be calculated by taking the sum of the number of currently remaining free memory blocks and the number of existing memory blocks that have been written to as the number of valid free memory blocks.

[0066] Step S508: Determine whether the number of valid free memory blocks (Valid_Spare_Blk) is greater than or equal to a predetermined threshold, for example, a threshold number of free memory blocks (GC_TH) that will trigger garbage collection (GC). If not, it means the number of valid free memory blocks is less than the predetermined threshold, and proceed to step S510. If yes, it means the number of valid free memory blocks is not less than the predetermined threshold, and proceed to step S512.

[0067] Step S510: The memory controller 110 may set the current set value of the predetermined number of memory blocks to 0, which is expressed as the formula (Current_Size=0), wherein the value of Current_Size represents the size of the write accelerator buffer currently estimated by the memory controller 110. Therefore, the size of the write accelerator buffer currently estimated by the memory controller 110 is 0, and this estimated value is returned to the host device 130.

[0068] Step S512: The memory controller 110 may set the current set value to the difference between the number of valid free memory blocks and a predetermined threshold. Which is expressed as the formula (Current_Size=Valid_Spare_Blk- GC_TH).

[0069] Step S514: The memory controller 110 may calculate or obtain a total amount of remaining erasable times (Left_Erase_Cnt). As described above, the memory controller 110 may obtain the total amount of remaining erasable times of the memory blocks of the data storage device 100 (Left_Erase_Cnt) by subtracting the total amount of erasable times corresponding to the current data storage device 100 from the total upper limit of erasable times.

[0070] Step S516: It is determined whether the total amount of remaining erasable times (Left_Erase_Cnt) is greater than or equal to the current set value obtained in step S512. If not, which means that the total amount of remaining erasable times is less than the current set value (Left_Erase_Cnt<Current_Size), step S518 and step S520 for modifying the current set value are executed. If yes, which means that the total amount of remaining erasable times is not less than the current set value (Left_Erase_Cnt>=Current_Size), the memory controller 110 does not modify the current set value and directly executes step S520. Therefore, when the total amount of remaining erasable times is not less than the current set value, the size of the write accelerator buffer currently estimated by the memory controller 110 is still (Valid_Spare_Blk-GC_TH).

[0071] Step S518: The memory controller 110 may modify the current set value to a value of the total amount of remaining erasable times. Which is expressed as the formula (Current_Size= Left_Erase_Cnt). Therefore, the size of the write accelerator buffer currently estimated by the memory controller 110 is Left_Erase_Cnt.

[0072] Step S520: The memory controller 110 sends the estimated value (i.e., the current setting value (Current_Size)) back to the host device 130.

[0073] In summary, by implementing the cache size estimation method proposed in this invention, the currently configurable write cache size can be accurately estimated, thereby avoiding significant changes in data write speed. Furthermore, in some embodiments of this invention, when estimating the cache size, the memory controller 110 can further refer to the remaining number of erase operations that can be performed on the memory blocks of the data storage device 100, thus providing better protection for the data storage device 100 after it has been used for a period of time.

[0074] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A data storage device, comprising: A memory device comprising a plurality of memory blocks, including one or more free memory blocks that have not yet been written to, and one or more predetermined memory blocks configured as buffers for receiving data from a host device. as well as A memory controller, coupled to the memory device, for accessing the memory device, obtains a total number of remaining eraseable counts for these memory blocks, and determines a current set value for a number of the one or more predetermined memory blocks based on a current number of remaining free memory blocks, a number of predetermined memory blocks in which data has been written, a predetermined threshold, and the total number of remaining eraseable counts for these memory blocks, and configures the number of predetermined memory blocks as a cache based on the current set value; The predetermined threshold value is configured as a threshold value for the number of free memory blocks used to trigger a garbage collection process; the memory controller is further used to determine the sum of the number of currently remaining free memory blocks and the number of predetermined memory blocks that have been written with data, to determine the current setting value based on the difference between the sum and the predetermined threshold value, and to determine whether to modify the current setting value based on the total number of remaining erasure times of these memory blocks.

2. The data storage device as described in claim 1, characterized in that, The memory controller further determines whether the sum is less than the predetermined threshold. When the sum is less than the predetermined threshold, the memory controller sets the current setting value to 0.

3. The data storage device as described in claim 2, characterized in that, When the sum is not less than the predetermined threshold, the memory controller sets the current setting value to the difference between the sum and the predetermined threshold.

4. The data storage device as described in claim 3, characterized in that, The memory controller further determines whether the total number of remaining erasable counts for these memory blocks is less than the current setting value. When the total number of remaining erasable counts for these memory blocks is less than the current setting value, the memory controller modifies the current setting value to a value equal to the total number of remaining erasable counts for these memory blocks.

5. The data storage device as described in claim 4, characterized in that, The memory controller does not modify the current setting value when the total number of remaining erasure counts for these memory blocks is not less than the current setting value.

6. A method for estimating the size of a buffer, applicable to a data storage device including a memory device and a memory controller, the memory device comprising a plurality of memory blocks, the memory blocks including one or more free memory blocks that have not yet been written to, and one or more predetermined memory blocks configured as buffers for receiving data from a host device, the method comprising: Get the number of currently remaining free memory blocks; Obtain a number of predetermined memory blocks in which data has been written; Obtain the total number of remaining erasures for these memory blocks; A current set value for the number of one or more predetermined memory blocks is determined based on the number of currently remaining free memory blocks, the number of predetermined memory blocks that have been written to, the total number of remaining eraseable counts for these memory blocks, and a predetermined threshold; and Configure the predetermined number of memory blocks as a cache according to the current setting value; The predetermined threshold value is a threshold value for the number of free memory blocks configured to trigger a garbage collection process; the step of determining the current set value of the number of the one or more predetermined memory blocks based on the number of currently remaining free memory blocks, the number of predetermined memory blocks that have been written to, the total number of remaining eraseable times for these memory blocks, and the predetermined threshold value further includes: Determine the sum of the number of currently remaining free memory blocks and the number of given memory blocks that have been written with data; The current set value is determined based on the difference between the sum and the predetermined threshold. as well as The decision to modify the current setting is based on the total number of remaining erasure cycles for these memory blocks.

7. The method for estimating the buffer size as described in claim 6, characterized in that, The step of determining the current set value based on the difference between the sum and the predetermined threshold also includes: Determine whether the sum is less than the predetermined threshold; and When the sum is less than the predetermined threshold, the current setting value is set to 0.

8. The method for estimating the buffer size as described in claim 7, characterized in that, The step of determining the current set value based on the difference between the sum and the predetermined threshold also includes: When the sum is not less than the predetermined threshold, the current setting value is set to the difference between the sum and the predetermined threshold.

9. The method for estimating the buffer size as described in claim 8, characterized in that, The step of determining whether to modify the current setting based on the total number of remaining eraseable cycles for these memory blocks also includes: Determine whether the total number of remaining erasure cycles for these memory blocks is less than the current set value; and When the total number of remaining erasable counts for these memory blocks is less than the current setting, the current setting is modified to a value equal to the total number of remaining erasable counts for these memory blocks.

10. The method for estimating the buffer size as described in claim 9, characterized in that, The step of determining whether to modify the current setting based on the total number of remaining eraseable cycles for these memory blocks also includes: The current setting value is not modified when the total number of remaining erasure counts for these memory blocks is not less than the current setting value.

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