Fast fourier transform circuit for speech recognition and method of controlling the same

Abstract

The application discloses a fast Fourier transform circuit for speech recognition and a control method thereof. The circuit is composed of two basic stage circuits, and a plurality of transform circuits are connected in series. A product circuit is arranged between adjacent transform circuits. The product circuit comprises four shift adders, a first decoder, a second decoder, an addition calculator and a subtraction calculator. The shift adder comprises two shifters, a first input controller, a second input controller, a variable calculator and a complement unit. The fast Fourier transform circuit is based on base 2 2 The SDF pipeline type structure is combined with a low-bit programmable shifter, a simplified design shift adder circuit structure is used to replace a general multiplier, and then the data storage required bit width is reduced, so that the calculation power consumption and area are saved. Meanwhile, based on the non-zero bit discontinuous characteristic of CSD coding, the shift amount of the programmable shifter is reduced, and the hardware resource is saved.

Description

Technical Field

[0001] This invention relates to the technical field of circuits, and more particularly to a fast Fourier transform circuit for speech recognition and its control method. Background Technology

[0002] FFT (Fast Fourier Transform) is an algorithm widely used in signal processing and image processing to transform signals from the time domain to the frequency domain. It features fast computation speed and high efficiency and is applied in many fields, including speech processing, image processing, audio encoding and decoding, and wireless communication. It plays a very important role in modern digital technology, providing us with a fast and accurate frequency domain analysis tool.

[0003] FFT is frequently used in speech keyword recognition models to extract frequency domain features of speech signals, thereby improving the information processing efficiency of the speech keyword recognition model. However, existing Fast Fourier Transform (FFT) circuits used in speech keyword recognition systems are usually precisely calculated FFTs, which suffer from large computational and data storage requirements. This invention proposes a FFT circuit for speech keyword recognition. Although the calculation results of the FFT have significant errors, the neural network model has parameter redundancy, and the weights are adjusted during training to compensate for the computational errors caused by the FFT. Therefore, the final classification accuracy of the speech keyword recognition model does not decrease significantly. Furthermore, by approximating the rotation factor, the number of adders in the circuit can be reduced. A shift adder is designed based on the approximate rotation factor to replace the general multiplier, reducing the storage space of the rotation factor and achieving the goal of reducing area and power consumption. Summary of the Invention

[0004] This invention provides a Fast Fourier Transform (FFT) circuit and its control method for speech recognition, aiming to solve the problems of high power consumption and parameter redundancy in speech keyword recognition models in existing FFT circuit structures.

[0005] In a first aspect, embodiments of the present invention disclose a fast Fourier transform circuit for speech recognition, comprising a multi-stage transform circuit and multiple product circuits; the multi-stage transform circuits are connected in series sequentially.

[0006] A product circuit is connected in series between the signal output terminal of the previous stage conversion circuit and the signal input terminal of the next stage conversion circuit; each stage of the conversion circuit is composed of two basic stage circuits connected in series.

[0007] The product circuit includes four shift adders, a first decoder, a second decoder, an adder calculator, and a subtraction calculator. The output of the first decoder is connected to the first input of both the first and second shift adders. The second input of the first shift adder is connected to the second input of the third shift adder, and the connection point serves as the first numerical input of the product circuit. The second input of the fourth shift adder is connected to the second input of the second shift adder, and the connection point serves as the second numerical input of the product circuit. The output of the second decoder is connected to the first input of both the third and fourth shift adders.

[0008] The output terminals of the first shift adder and the fourth shift adder are respectively connected to the two input terminals of the subtraction calculator, the output terminals of the second shift adder and the third shift adder are respectively connected to the two input terminals of the addition calculator, the output terminal of the subtraction calculator serves as the first numerical output terminal of the product circuit, and the output terminal of the addition calculator serves as the second numerical output terminal of the product circuit.

[0009] The shift adder includes two shifters, a first input controller, a second input controller, a variable calculator, and a complement unit; the input terminals of the first and second input controllers are combined to form the second input terminal of the shift adder; the control signal input terminal of the first input controller is used to input a first input control signal, and the control signal input terminal of the second input controller is used to input a second input control signal;

[0010] The output of the first input controller is connected to the input of the first shifter, and the input of the second input controller is connected to the input of the second shifter. The outputs of the first and second shifters are respectively connected to the two inputs of the variable calculator. The output of the variable calculator is connected to the input of the complement unit, and the output of the complement unit serves as the output of the shift adder. The shift signal input of the first shifter is used to input the first shift control signal, and the shift signal input of the second shifter is used to input the second shift control signal. The transformation signal input of the variable calculator is used to input the transformation control signal. The complement signal input of the complement unit is used to input the complement signal. The control signal inputs of the first and second input controllers, the shift signal inputs of the first and second shifters, the transformation signal input of the variable calculator, and the complement signal input of the complement unit are combined to form the first input of the shift adder.

[0011] Secondly, embodiments of the present invention also disclose a control method for a Fast Fourier Transform (FFT) circuit for speech recognition. This control method is applied to a FFT system, which includes a circuit controller and the FFT circuit for speech recognition as described in the first aspect above. The circuit controller is communicatively connected to the input of the decoder in the FFT circuit. The control method includes:

[0012] The circuit controller filters values ​​within a preset value range according to a preset value filtering rule to obtain a candidate number corresponding to the value filtering rule. The preset value range corresponds to the bit width of the rotation factor.

[0013] The circuit controller approximates the rotation factors of the fast Fourier transform based on the candidate numbers, and obtains the approximate rotation factors corresponding to each group of rotation factors.

[0014] The circuit controller sequentially sorts and numbers the real and imaginary parts contained in each of the approximate rotation factors, and then stores the rotation factor number information in read-only mode.

[0015] The decoder reads and decodes the rotation factor number information corresponding to each product circuit, and inputs the decoded control signal corresponding to each rotation factor number information into the shift adder to which the product circuit belongs.

[0016] This application discloses a Fast Fourier Transform (FFT) circuit and its control method for speech recognition. The circuit uses two basic-level circuits to form a transform circuit, with multiple transform circuits connected in series sequentially. A product circuit is connected in series between adjacent transform circuits. The product circuit includes four shift adders, a first decoder, a second decoder, an adder, and a subtractor. The shift adder includes two shifters, a first input controller, a second input controller, a variable calculator, and a complement unit. The above-mentioned FFT circuit is based on radix-2. 2 The SDF pipelined architecture, combined with a low-bit programmable shifter, utilizes a simplified shift-add circuit structure to replace a general-purpose multiplier. Furthermore, it reduces the bit width required for data storage, thereby saving computational power and area. Simultaneously, based on the discontinuous nature of non-zero bits in CSD encoding, the shift amount of the programmable shifter is reduced, saving hardware resources. Attached Figure Description

[0017] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A circuit diagram of a Fast Fourier Transform circuit for speech recognition provided in an embodiment of the present invention;

[0019] Figure 2 The circuit structure diagram of the product circuit provided in the embodiment of the present invention;

[0020] Figure 3 This is a circuit diagram of a shift adder provided in an embodiment of the present invention;

[0021] Figure 4 The circuit structure diagram of the shifter provided in the embodiment of the present invention;

[0022] Figure 5 A flowchart illustrating the control method for a fast Fourier transform circuit for speech recognition provided in an embodiment of the present invention;

[0023] Figure 6 This is a schematic diagram of the data processing flow of the control method for the Fast Fourier Transform circuit for speech recognition provided in an embodiment of the present invention.

[0024] Reference numerals: C, Transformer circuit; M, Product circuit; S, Basic stage circuit; J, Shift register; B, Butterfly arithmetic unit; 11, First shift adder; 12, Second shift adder; 13, Third shift adder; 14, Fourth shift adder; 21, First decoder; 22, Second decoder; 23, Adder calculator; 24, Subtractor calculator; 25, First read-only memory; 26, Second read-only memory; 31, First shifter; 32, Second shifter; 33, First input controller; 34, Second input controller; 35, Variable calculator; 36, Complement unit; P1, AND gate; 30, Input controller; P2, Controllable AND gate. Detailed Implementation

[0025] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0026] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0027] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0028] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0029] This invention discloses a Fast Fourier Transform circuit for speech recognition, such as... Figure 1 As shown, it includes a multi-stage conversion circuit C and multiple product circuits M; the multiple stages of the conversion circuit C are connected in series; a product circuit M is connected in series between the signal output terminal of the previous stage conversion circuit C and the signal input terminal of the next stage conversion circuit C; each stage of the conversion circuit C is composed of two basic stage circuits S connected in series. Specifically, as shown... Figure 1 As shown, a multi-stage conversion circuit C can be configured, with a product circuit M connected in series between the signal output terminal of the previous stage conversion circuit C and the signal input terminal of the next stage conversion circuit C. The multi-stage conversion circuit C and multiple product circuits M combine to form a base 2. 2 SDF assembly line structure, 2 2 As a characteristic of SDF, SDF stands for Single-path Delay Feedback.

[0030] like Figure 2As shown, the product circuit M includes four shift adders, a first decoder 21, a second decoder 22, an adder 23, and a subtraction calculator 24. The output of the first decoder 21 is simultaneously connected to the first input of the first shift adder 11 and the first input of the second shift adder 12. The second input of the first shift adder 11 is connected to the second input of the third shift adder 13, and the connection point serves as the first numerical input of the product circuit M. The second input of the fourth shift adder 14 is connected to the second input of the second shift adder 12, and the connection point serves as the second numerical input of the product circuit M. The output of the second decoder 22 is simultaneously connected to the first input of the third shift adder 13 and the first input of the fourth shift adder 14; the output of the first shift adder 11 and the output of the fourth shift adder 14 are respectively connected to the two inputs of the subtraction calculator 24, the output of the second shift adder 12 and the output of the third shift adder 13 are respectively connected to the two inputs of the addition calculator 23, the output of the subtraction calculator 24 serves as the first numerical output of the product circuit M, and the output of the addition calculator 23 serves as the second numerical output of the product circuit M.

[0031] The first numerical input terminal of the product circuit M is used to input the numerical value X. r The second numerical input terminal of the product circuit M is used to input the numerical value X. i The first shift adder 11, the second shift adder 12, and the first decoder 21 are combined to process the real part of the input rotation factor; the third shift adder 13, the fourth shift adder 14, and the second decoder 22 are combined to process the imaginary part of the input rotation factor. The value Y output by the first numerical output terminal of the product circuit M is... r and the value Y output by the second numerical output terminal i The output is then sent to the next basic circuit S for further calculation.

[0032] The shift adder includes two shifters, a first input controller 33, a second input controller 34, a variable calculator 35, and a complement unit 36. The input terminals of the first input controller 33 and the second input controller 34 are combined to form the second input terminal of the shift adder. The control signal input terminal of the first input controller 33 is used to input a first input control signal, and the control signal input terminal of the second input controller 34 is used to input a second input control signal. All shifters are 6-bit programmable shifters. The output terminal of the first input controller 33 is connected to the input terminal of the first shifter 31, and the input terminal of the second input controller 34 is connected to the input terminal of the second shifter 32. The output terminals of the first shifter 31 and the second shifter 32 are respectively connected to the two input terminals of the variable calculator 35. The output terminal is connected to the input terminal of the complement unit 36, and the output terminal of the complement unit 36 ​​serves as the output terminal of the shift adder; the shift signal input terminal of the first shifter 31 is used to input the first shift control signal, and the shift signal input terminal of the second shifter 32 is used to input the second shift control signal; the transformation signal input terminal of the variable calculator 35 is used to input the transformation control signal; the complement signal input terminal of the complement unit 36 ​​is used to input the complement signal; the control signal input terminal of the first input controller 33, the control signal input terminal of the second input controller 34, the shift signal input terminal of the first shifter 31, the shift signal input terminal of the second shifter 32, the transformation signal input terminal of the variable calculator 35, and the complement signal input terminal of the complement unit 36 ​​are combined to form the first input terminal of the shift adder.

[0033] like Figure 3 As shown, the shift adder consists of two shifters (respectively...) Figure 3 The system comprises a first shifter 31 and a second shifter 32, a first input controller 33, a second input controller 34, a variable calculator 35, and a complement unit 36. The first input controller 33 controls its output through the input first input control signal. If the first input control signal I0 is 1, the first input controller outputs the input value |X|; if the first input control signal I0 is 0, the first input controller outputs "0". The second input controller controls its output through the input second input control signal I1, and its operating principle is the same as the first input controller. When the rotation factor encoding has two non-zero numbers, both I0 and I1 are set to 1, and the input of the input controller is selected as the input. When there is one non-zero number, I0 or I1 is set to 0 accordingly, and 0 is selected as the input of one of the shifters. When there is no non-zero number, both I0 and I1 are set to 0, and the inputs of both shifters are zero.

[0034] The first shifter performs shift calculations on its input value via the first shift control signal B0, and the second shifter performs shift calculations on its input value via the second shift control signal B1. The variable calculator changes its calculation mode via the input transformation signal d. For example, the variable calculator can be switched to perform addition or subtraction calculations via the transformation signal d. The variable calculator then performs addition or subtraction calculations on the values ​​output by the first and second shifters. The complement unit performs complement calculations on its input value via the input complement signal a, and the output result of the complement unit is Y.

[0035] In a more specific embodiment, such as Figure 4As shown, the shifter includes a first-row shift circuit, a middle-row shift circuit, and a last-row shift circuit; the first-row shift circuit contains several input terminals that combine to form the input terminals of the shifter, and the length of the input terminals is related to the bit width retained in the calculation results during the fast Fourier transform process. The output of the first row shift circuit is connected to the input of the middle row shift circuit, and the output of the middle row shift circuit is connected to the input of the last row shift circuit. The first row shift signal input of the first row shift circuit, the middle row shift signal input of the middle row shift circuit, and the last row shift signal input of the last row shift circuit are combined to form the shift signal input of the shifter. The last row shift circuit includes an AND gate P1, several input controllers 30, and a controllable AND gate P2 arranged in sequence. One input of the controllable AND gate P2 is connected to the output of a NOT gate. The output of the AND gate P1, the outputs of each input controller 30, and the output of the controllable AND gate P2 in the last row shift circuit are combined to form the output of the shifter. The control signal input terminal of the control gate 30 is connected to the control signal output terminal of the adjacent input controller 30 on the right or to the control signal output terminal of the adjacent controllable AND gate P2 on the left. The control signal input terminal of the AND gate P1 is connected to the control signal output terminal of the adjacent input controller 30 on the left. The control signal input terminal of the controllable AND gate P2 serves as the tail shift signal input terminal of the tail shift circuit. The first input terminal of each input controller 30 in the tail shift circuit is connected to the second input terminal of the adjacent input controller 30 on the left or to the control signal input terminal of the adjacent AND gate P1 on the left. The input terminal of the controllable AND gate P2 that is not connected to the NOT gate is connected to the second input terminal of the adjacent input controller 30 on the left. The input terminal of the NOT gate connected to the other input terminal of the controllable AND gate P2 is connected to the tail shift signal input terminal. Furthermore, the first row shift circuit includes two AND gates P1 arranged in sequence, six input controllers 30, and two controllable AND gates P2; the middle row shift circuit includes two AND gates P1 arranged in sequence, several input controllers 30, and two controllable AND gates P2, and the number of input controllers in each row of the shift controller corresponds to the bit width retained in the result during the fast Fourier operation.

[0036] The specific structure of the shifter is as follows: Figure 4As shown, this shifter can shift the input left by 0 to 5 bits. The shift signal input terminals of the shifter consist of the first row shift signal input terminal of the first row shift circuit, the middle row shift signal input terminal of the middle row shift circuit, and the last row shift signal input terminal of the last row shift circuit, receiving signals b2, b1, and b0 respectively. b0, b1, and b2 combine to form the shift control signal B0 of the shifter. Based on the non-zero bit discontinuous characteristic of CSD encoding, the output of shifter 0 can be shifted left by two bits and added or subtracted from the output of shifter 1. Compared to directly using an 8-bit shifter, the 6-bit shifter used here reduces the shift amount and also reduces some AND gates and selectors, thus reducing hardware resources. However, it can still achieve the function of an 8-bit product circuit.

[0037] If the sign bits of the two non-zero bits of the CSD encoding of the rotation factor are the same, the outputs of the two shifters will be added together; otherwise, they will be subtracted. The control signal for the variable calculator is the transformation signal d. If the sign bit of the rotation factor is the same as the sign bit of the input value of the product circuit, the result after addition and subtraction is directly output through the complement unit. If they are different, it means that the final result should be a negative number. However, the result after addition and subtraction is a positive number. Therefore, it is necessary to perform inversion and addition by one through the complement unit to obtain the two's complement form. Whether to perform inversion and addition is controlled by the complement signal a.

[0038] In a more specific embodiment, the base-level circuit S includes a shift register J and a butterfly arithmetic unit B; the register signal output terminal of the butterfly arithmetic unit B is connected to the input terminal of a corresponding shift register J, and the output terminal of the shift register J is connected to the register signal input terminal of a corresponding butterfly arithmetic unit B; the calculated value input terminal of the upstream butterfly arithmetic unit B in each stage of the conversion circuit C serves as the signal input terminal of the conversion circuit C, and the calculated value output terminal of the downstream butterfly arithmetic unit B in each stage of the conversion circuit C serves as the signal output terminal of the conversion circuit C; the calculated value output terminal of the upstream butterfly arithmetic unit B is connected to the calculated value input terminal of the downstream butterfly arithmetic unit B; the shift register functions as a delay unit, and its length is denoted as D. The first half of the input data from the upstream butterfly arithmetic unit passes through the current stage butterfly arithmetic unit and enters the shift register, where it is delayed by D cycles. Then, it enters the current stage butterfly arithmetic unit together with the second half of the input data for calculation and output. The addition portion of the output data is directly output to the next-level butterfly arithmetic unit, while the subtraction portion is delayed by D cycles through a shift register before being output to the next-level butterfly arithmetic unit. Each shift register corresponds to a basic level circuit S (corresponding to...). Figure 1 (Stages 1, 2, 3, 4, 5, 6, 7, and 8).

[0039] In a more specific embodiment, the Fast Fourier Transform circuit includes a four-stage transform circuit C and three product circuits M. The product circuits M further include a first read-only memory (ROM) 25 and a second ROM 26; the input of the first decoder 21 is connected to the output of the first ROM 25, and the input of the second decoder 22 is connected to the output of the second ROM 26. To reduce storage area and read / write power consumption, the twiddle factor is not directly stored in memory. Instead, it is first encoded into a smaller bit-width number and then stored in the ROM, thus reducing the storage space. During reading, the signal is first decoded by the decoder into the control signal of the designed product circuit, and then transmitted to the product circuit for calculation. Here, ROM stands for Read-Only Memory. By establishing the correspondence between the encoded number and the decoded control signal, a logical expression is obtained through a truth table, and then simplified using Karnaugh maps; finally, these expressions are constructed using logic gates to obtain the decoder. In one embodiment of this application, a four-stage conversion circuit and three product circuits are provided, and each stage of the conversion circuit is composed of two basic stage circuits connected in series.

[0040] This application also provides a control method for a Fast Fourier Transform (FFT) circuit for speech recognition. This control method is applied to a FFT system, which includes a circuit controller and the FFT circuit for speech recognition described in the above embodiment. The circuit controller is communicatively connected to the input of the decoder in the FFT circuit. Figure 5 As shown, the control method includes steps S110-S140.

[0041] S110. The circuit controller filters values ​​within a preset value range according to a preset value filtering rule to obtain a candidate number corresponding to the value filtering rule. The preset value range corresponds to the bit width of the rotation factor.

[0042] The control method of this application is illustrated using a Fast Fourier Transform (FFT) algorithm with 256 points, an 8-bit width for the bit rotation factor data, and a 17-bit width for the intermediate calculation results. The 256 points, 8-bit width for the rotation factor data, and 17-bit width for the intermediate results are just one specific implementation method. The FFT algorithm can also increase the number of stages of the transformation circuit and set other parameters.

[0043] First, values ​​within a preset range can be filtered according to numerical filtering rules. For example, if the bit width B of the rotation factor is set to 8, including the sign bit, then the corresponding preset numerical range is (0~2). B-1 First, within the bit width range (0~2).B-1 Natural numbers from 0 to 128 (excluding -1) are converted to CSD encoding. Then, numbers with only two or fewer non-zero bits are selected as candidate numbers. This means that if multiplication of the input with a rotation factor is implemented using shifting and addition, only one adder and two shifters are needed. CSD encoding differs from common binary encoding, where each bit can be 0, 1, or -1. CSD encoding effectively reduces the number of non-zero bits. The candidate numbers from 0 to 128 are: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 12, 14, 15, 16, 17, 18, 20, 24, 28, 30, 31, 32, 33, 34, 36, 40, 48, 56, 60, 62, 63, 64, 65, 66, 68, 72, 80, 96, 112, 120, 124, 126, 127, 128.

[0044] In a more specific embodiment, before step S110, the method further includes: calculating the bit width of the rotation factor minus one as a power of 2, so as to determine the corresponding preset numerical range based on the calculated value.

[0045] Specifically, before filtering and obtaining candidate numbers, the corresponding preset value range can be determined based on the data bit width of the rotation factor; the data bit width of the rotation factor minus one can be used as a power of 2 for calculation, with 0 as the lower bound of the preset value range and the calculated value as the upper bound of the preset value range, thereby determining the preset value range.

[0046] In a specific embodiment, the data bit width B of the rotation factor is 8, including the sign bit, then the corresponding preset value range is determined to be (0~2). B-1 ).

[0047] S120. The circuit controller approximates the rotation factors of the Fast Fourier Transform based on the candidate numbers to obtain the approximate rotation factors corresponding to each group of rotation factors.

[0048] In a more specific embodiment, step S120 includes: taking the absolute value of the values ​​to be solved in the rotation factors; the values ​​to be solved are the real part or imaginary part of the rotation factors; comparing the distance between the absolute value of the values ​​to be solved and each of the candidate numbers, and determining the candidate number with the closest distance to the absolute value as the approximation of the corresponding value to be solved; and combining the two approximations corresponding to each rotation factor to form the corresponding approximate rotation factor.

[0049] For example, After quantization to 8 bits, the result is 119 - j * 46, which serves as the rotation factor to be approximated. The real part of the rotation factor is 119, and the imaginary part is 46. Therefore, the candidate closest to 119 is 120, and the candidate closest to 46 is 48. Then W... 15 The approximate numbers obtained by approximation are 120 and 48, which combine to form the corresponding approximate twiddle factor 120-j*48. Using this technique, all twiddle factors can be approximated sequentially to obtain the approximate twiddle factor corresponding to each twiddle factor.

[0050] S130. The circuit controller sorts and numbers the real and imaginary parts contained in each of the approximate rotation factors in sequence, and then stores the rotation factor number information in read-only mode.

[0051] The real and imaginary parts of the approximated twitch factors are sorted and labeled in ascending order. During storage, the twitch factors are not directly stored; instead, their corresponding labels are stored. This reduces storage area and read / write power consumption. Because 8-bit rotation quantization (including the signed bit) requires 8 bits of storage, but after approximation, the number of distinct twitch factors is reduced, allowing for the use of labels with shorter bit widths. For example, in the second-level base circuit, after approximation, there are fewer than 64 distinct real parts of the twitch factors. Therefore, 0 to 63 are sufficient to represent the twitch factors of this base circuit. Storing 0 to 63 requires only 6 bits, compared to the 8 bits required before encoding. This reduction in storage area also lowers read / write power consumption.

[0052] In a specific embodiment, the circuit controller can communicate with each readable storage device (such as a first readable storage device and a second readable storage device). After obtaining the rotation factor number, the circuit controller can directly input the rotation factor number into the corresponding readable storage device for storage. The actual data processing procedure at this time is as follows: Figure 6 As shown.

[0053] S140. The decoder reads and decodes the rotation factor number information corresponding to each product circuit, and inputs the decoded control signal corresponding to each rotation factor number information into the shift adder to which the product circuit belongs.

[0054] When reading the rotation factor, since the stored content has been encoded, the value contained in the approximate rotation factor corresponding to the rotation factor number information corresponding to each product circuit will be decoded first. Each set of approximate rotation factor numbers corresponds to a set of control signals of the designed shift adder.

[0055] In a more specific embodiment, step S140 includes: obtaining the numerical value corresponding to the rotation factor number information and performing a shift input solution to obtain the corresponding solution result; generating a first input control signal and a second input control signal according to whether each digit in the solution result needs numerical input; generating a first shift control signal and a second shift control signal according to the shift value corresponding to each digit in the solution result; generating a corresponding transformation control signal according to the operators between the digits in the solution result; performing an XOR operation according to the numerical sign corresponding to the rotation factor number information and the sign of the numerical input value corresponding to the digit, and generating a corresponding complement signal according to the XOR operation result; combining the first input control signal, the second input control signal, the first shift control signal, the second shift control signal, the transformation control signal, and the complement signal as a control signal corresponding to the rotation factor number information.

[0056] Specifically, the numerical value corresponding to the rotation factor number information can be obtained and shifted to solve the problem. This numerical value is an approximation of the real or imaginary part of the rotation factor. For example, if x is the value to be multiplied, and the numerical value corresponding to the rotation factor number information is -28, the calculation process can be represented as x×(-28), where x is a positive number. Shifting x×(-28) yields -((x<<5)-(x<<2)) as the solution. Then, the first input control signal I0 is 1, and the second input control signal I1 is 1. If the first shift value is 5, the corresponding first shift control signal B0 is 101; if the second shift value is 2, the corresponding second shift control signal B1 is 010. The operator between digits in the solution is "-", and the generated transformation control signal d is "1". (-28) is negative, so sw is 1, which means inverting and adding 1; the sign of x is positive, so a is equal to the XOR operation of Sw and the sign bit of x. The result of a is 1, indicating that the product is negative. At this time, the complement unit inverts and adds 1 to the result obtained after addition and subtraction. For example, the control signal corresponding to the value "-28" in the approximate rotation factor corresponding to the rotation factor number information is shown in Table 2. Sending the input value x and the control signal to the shift adder can realize the operation of x×(-28).

[0057] Table 1

[0058] 1 1 1 0 1 0 1 0 1 1

[0059] By applying both the precisely calculated Fast Fourier Transform (FFT) and the approximate FFT of this invention to Basic LSTM, GRU, and GRNN respectively, it was found that the classification accuracy of the model using the approximate FFT decreased by no more than 0.5%, indicating that the impact of the approximate FFT calculation is relatively small. Under this error condition, the two circuits were simulated using a 65nm process, and the power consumption at 250K MHz was measured, as shown in Table 2. The overall power consumption can be reduced by 11.5%, as shown in Table 2. Table 2 shows the classification accuracy of the speech keyword recognition model using the FFT circuit provided in this embodiment of the invention and the power consumption optimization table of the circuit.

[0060] Table 2

[0061]

[0062] This invention discloses a Fast Fourier Transform (FFT) circuit for speech recognition and its control method. The circuit employs two basic-level circuits to form a transform circuit, with multiple transform circuits connected in series sequentially. A product circuit is connected in series between adjacent transform circuits. The product circuit includes four shift adders, a first decoder, a second decoder, an adder, and a subtractor. Each shift adder includes two shifters, a first input controller, a second input controller, a variable calculator, and a complement unit. The aforementioned FFT circuit is based on radix-2. 2 The SDF pipelined architecture, combined with a low-bit programmable shifter, utilizes a simplified shift-add circuit structure to replace a general-purpose multiplier. Furthermore, it reduces the bit width required for data storage, thereby saving computational power and area. Simultaneously, based on the discontinuous nature of non-zero bits in CSD encoding, the shift amount of the programmable shifter is reduced, saving hardware resources.

[0063] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A Fast Fourier Transform circuit for speech recognition, characterized in that, It includes a multi-stage conversion circuit and multiple product circuits; the multi-stage conversion circuits are connected in series in sequence; A product circuit is connected in series between the signal output terminal of the previous stage conversion circuit and the signal input terminal of the next stage conversion circuit; each stage of the conversion circuit is composed of two basic stage circuits connected in series. The product circuit includes four shift adders, a first decoder, a second decoder, an adder calculator, and a subtraction calculator. The output of the first decoder is connected to the first input of both the first and second shift adders. The second input of the first shift adder is connected to the second input of the third shift adder, and the connection point serves as the first numerical input of the product circuit. The second input of the fourth shift adder is connected to the second input of the second shift adder, and the connection point serves as the second numerical input of the product circuit. The output of the second decoder is connected to the first input of both the third and fourth shift adders. The output terminals of the first shift adder and the fourth shift adder are respectively connected to the two input terminals of the subtraction calculator, the output terminals of the second shift adder and the third shift adder are respectively connected to the two input terminals of the addition calculator, the output terminal of the subtraction calculator serves as the first numerical output terminal of the product circuit, and the output terminal of the addition calculator serves as the second numerical output terminal of the product circuit. The shift adder includes two shifters, a first input controller, a second input controller, a variable calculator, and a complement unit; the input terminals of the first and second input controllers are combined to form the second input terminal of the shift adder; the control signal input terminal of the first input controller is used to input a first input control signal, and the control signal input terminal of the second input controller is used to input a second input control signal; all shifters are programmable shifters. The output of the first input controller is connected to the input of the first shifter, and the input of the second input controller is connected to the input of the second shifter. The outputs of the first and second shifters are respectively connected to the two inputs of the variable calculator. The output of the variable calculator is connected to the input of the complement unit, and the output of the complement unit serves as the output of the shift adder. The shift signal input of the first shifter is used to input the first shift control signal, and the shift signal input of the second shifter is used to input the second shift control signal. The transformation signal input of the variable calculator is used to input the transformation control signal. The complement signal input of the complement unit is used to input the complement signal. The control signal inputs of the first and second input controllers, the shift signal inputs of the first and second shifters, the transformation signal input of the variable calculator, and the complement signal input of the complement unit are combined to form the first input of the shift adder.

2. The Fast Fourier Transform circuit for speech recognition according to claim 1, characterized in that, The shifter includes a first-row shift circuit, a middle-row shift circuit, and a last-row shift circuit. The first-row shift circuit comprises several input terminals that combine to form the input terminals of the shifter. The length of each input terminal corresponds to the bit width retained in the calculation results during the Fast Fourier Transform process. The output terminal of the first-row shift circuit is connected to the input terminal of the middle-row shift circuit, and the output terminal of the middle-row shift circuit is connected to the input terminal of the last-row shift circuit. The first-row shift signal input terminal of the first-row shift circuit, the middle-row shift signal input terminal of the middle-row shift circuit, and the last-row shift signal input terminal of the last-row shift circuit combine to form the shift signal input terminal of the shifter. The tail-shifting circuit includes an AND gate, several input controllers, and a controllable AND gate arranged in sequence. One input terminal of the controllable AND gate is connected to the output terminal of the NOT gate. The output terminal of the AND gate, the output terminals of each input controller, and the output terminal of the controllable AND gate in the tail-shifting circuit are combined to form the output terminal of the shifter. In the tail-shifting circuit, the control signal input terminal of each input controller is connected to the control signal output terminal of the adjacent input controller on the right or to the control signal output terminal of the adjacent controllable AND gate on the left. The control signal input terminal of the AND gate is connected to the control signal output terminal of the adjacent input controller on the left. The control signal input terminal of the controllable AND gate serves as the tail-shifting signal input terminal of the tail-shifting circuit. In the tail-shifting circuit, the first input terminal of each input controller is connected to the second input terminal of the adjacent input controller on the left or to the control signal input terminal of the adjacent AND gate on the left. The input terminal of the controllable AND gate that is not connected to the NOT gate is connected to the second input terminal of the adjacent input controller on the left. The input terminal of the NOT gate that is connected to the other input terminal of the controllable AND gate is connected to the tail-shifting signal input terminal.

3. The Fast Fourier Transform circuit for speech recognition according to claim 2, characterized in that, The first row shift circuit includes two AND gates, several input controllers, and two controllable AND gates arranged in sequence; the middle row shift circuit includes two AND gates, several input controllers, and two controllable AND gates arranged in sequence; the number of input controllers in each row of the shift circuit corresponds to the bit width retained in the result of the fast Fourier calculation process.

4. The Fast Fourier Transform circuit for speech recognition according to any one of claims 1-3, characterized in that, The basic circuit includes a shift register and a butterfly arithmetic unit; the register signal output terminal of the butterfly arithmetic unit is connected to the input terminal of a corresponding shift register, and the output terminal of the shift register is connected to the register signal input terminal of a corresponding butterfly arithmetic unit. In each stage of the conversion circuit, the input terminal of the upstream butterfly arithmetic unit serves as the signal input terminal of the conversion circuit, and the output terminal of the downstream butterfly arithmetic unit serves as the signal output terminal of the conversion circuit. The output terminal of the upstream butterfly arithmetic unit is connected to the input terminal of the downstream butterfly arithmetic unit.

5. The Fast Fourier Transform circuit for speech recognition according to claim 4, characterized in that, The Fast Fourier Transform circuit includes a four-stage transform circuit and three product circuits.

6. The Fast Fourier Transform circuit for speech recognition according to claim 5, characterized in that, The product circuit also includes a first read-only memory and a second read-only memory; The input of the first decoder is connected to the output of the first read-only memory, and the input of the second decoder is connected to the output of the second read-only memory.

7. A control method for a Fast Fourier Transform (FFT) circuit for speech recognition, the control method being applied to a FFT system, the FFT system comprising a circuit controller and a FFT circuit for speech recognition as described in any one of claims 1-6, wherein the circuit controller is communicatively connected to the input terminal of the decoder in the FFT circuit, characterized in that... The control method includes: The circuit controller filters values ​​within a preset value range according to a preset value filtering rule to obtain a candidate number corresponding to the value filtering rule. The preset value range corresponds to the bit width of the rotation factor. The circuit controller approximates the rotation factors of the fast Fourier transform based on the candidate numbers, and obtains the approximate rotation factors corresponding to each group of rotation factors. The circuit controller sequentially sorts and numbers the real and imaginary parts contained in each of the approximate rotation factors, and then stores the rotation factor number information in read-only mode. The decoder reads and decodes the rotation factor number information corresponding to each product circuit, and inputs the decoded control signal corresponding to each rotation factor number information into the shift adder to which the product circuit belongs.

8. The control method for the Fast Fourier Transform circuit for speech recognition according to claim 7, characterized in that, Before filtering values ​​within a preset range according to preset numerical filtering rules, the process further includes: The bit width of the rotation factor is reduced by one and calculated as a power of 2, so as to determine the corresponding preset value range based on the calculated value.

9. The control method for the Fast Fourier Transform circuit for speech recognition according to claim 7 or 8, characterized in that, By approximating the input multiple sets of rotation factors according to the candidate number, an approximate rotation factor corresponding to each set of rotation factors is obtained, including: Take the absolute value of each value to be solved in the rotation factor; the value to be solved is the real part or imaginary part of the rotation factor. Compare the absolute value of the value to be solved with the distance between each of the candidate numbers, and determine the candidate number that is closest to the absolute value as the approximation of the corresponding value to be solved; The two approximations corresponding to each rotation factor are combined to form the corresponding approximate rotation factor.

10. The control method for the Fast Fourier Transform circuit for speech recognition according to claim 9, characterized in that, The step of reading and decoding the rotation factor number information corresponding to each of the product circuits includes: Obtain the numerical value corresponding to the rotation factor number information and perform shift input to solve for the corresponding solution result; Based on whether each digit in the solution result requires numerical input, generate the corresponding first input control signal and second input control signal; Based on the shift values ​​corresponding to each digit in the solution result, generate the corresponding first shift control signal and second shift control signal; Generate corresponding transformation control signals based on the operators between digits in the solution results; An XOR operation is performed based on the numerical sign corresponding to the rotation factor number information and the sign of the input numerical value corresponding to the digits, and a corresponding complement signal is generated based on the XOR operation result. The first input control signal, the second input control signal, the first shift control signal, the second shift control signal, the transformation control signal, and the complement signal are combined as a control signal corresponding to the rotation factor number information.

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