A method for logical lock encryption using non-combining logic rings

Abstract

The present application relates to the field of hardware security encryption, and particularly relates to a method for logic locking encryption using a non-combination logic loop, which comprises the following steps: firstly, building a non-combination logic loop according to the external constraints of a combination logic circuit; secondly, determining the value of the non-combination logic loop; thirdly, adding the non-combination logic loop with the determined value to the combination logic circuit to form a combination logic circuit with a loop; and finally, adding a key gate to the non-combination logic loop to enable the non-combination logic loop according to the key value, so as to perform logic locking on the combination logic circuit with the loop. The present application converts the combination logic circuit without a loop into a combination logic circuit with a loop, and the logic loop in the combination logic circuit with the loop will affect the function output of the circuit, so that when an attacker removes the loop in the circuit, the function of the circuit will be wrong, thereby making the attacker unable to crack the encryption technology.

Description

Technical Field

[0001] This invention relates to the field of hardware security encryption, and more specifically to a method for logic locking encryption using a non-combinatorial logic ring. Background Technology

[0002] Logic locking is a technique used to protect the intellectual property of integrated circuit (IC) designs and prevent unauthorized use. Its core principle involves adding extra logic gates or circuits to the circuit design; these gates are called "locks," and they are only opened when the correct key (a specific series of binary values) is entered, allowing the circuit to function properly. Logic locking effectively prevents chip reverse engineering and cloning, making it a crucial tool for protecting electronic design intellectual property. This technology is particularly critical in the field of chip design because it helps ensure the uniqueness and security of the design.

[0003] Cyclic encryption is a cutting-edge area in combinational logic locking. Its initial implementation defends against SAT attacks by creating feedback loops in the circuit to break the directed acyclic graph structure. However, the CycSAT method was quickly cracked. CycSAT-I and CycSAT-II, respectively, limit the decryption space based on the assumptions of no cycles and no non-combinatorial logic cycles. While effective, CycSAT often misses loops due to the "none cycle" condition. BeSAT addresses this problem by preserving the DIP of the SAT solver and removing the key that causes stateful phenomena.

[0004] To combat CycSAT and BeSAT, methods such as SRCLock and LOOPLock2.0 have been proposed. SRCLock increases the number of loop layers and the number of loops, but this increases circuit routing costs and cannot theoretically prevent attacks. LOOPLock2.0 includes two loop structures, Type-I and Type-II, to defend against various attacks. Nevertheless, LOOPLock2.0 still has a flaw: its non-combinatorial logic loops cannot affect the output, and can be considered a "dead circuit." Attackers can directly open the loops and break the encryption technology. Summary of the Invention

[0005] To address the aforementioned technical problems in the existing technology, this invention proposes a method for logic locking encryption using a non-combinatorial logic ring, the specific technical solution of which is as follows: A method for logic locking encryption using a non-combinational logic ring involves first constructing a non-combinational logic ring based on the external constraints of the combinational logic circuit, then determining the latched value of the non-combinational logic ring, adding the non-combinational logic ring with the determined latched value to the combinational logic circuit to form a cyclic combinational logic circuit, and finally adding a key gate to the non-combinational logic ring to enable the non-combinational logic ring based on the key value, thereby performing logic locking on the aforementioned cyclic combinational logic circuit.

[0006] Furthermore, the combinational logic circuit is driven by a state machine, which includes: The Sf state ensures that the value latched in the non-combinatorial logic loop has no effect on the functional output of the circuit. The Sk state causes the non-combinatorial logic loop to output the latched value.

[0007] Furthermore, the external constraints of the combinational logic circuit are the constraints imposed on the state machine, and the constraints imposed on the state machine include: For transitions from state Sf to state Sf, the intermediate states and the number of transitions have no effect on the latched value or the functional output of the circuit. For the transition from the Sf state to the Sk state, there is only one and only one transition path, thus determining the latched value; The transition from Sk state to Sf state is the same as the transition from Sf state to Sf state. Jumping from one Sk state to another is not allowed.

[0008] Furthermore, the key gate is an AND gate, with one input of the AND gate receiving the key value and the other input connected to the output of the non-combinational logic loop. The output of the AND gate is connected to the input of the gate circuit in the non-combinational logic loop.

[0009] Advantages of this invention: This invention transforms acyclic combinational logic circuits into cyclic combinational logic circuits, and the logic loops within them affect the circuit's functional output. Therefore, when an attacker removes a loop from the circuit, the circuit's function will malfunction, making it impossible for the attacker to crack the encryption technology. Attached Figure Description

[0010] Figure 1 This is a flowchart illustrating a method for logic locking encryption using a non-combinatorial logic ring according to an embodiment of the present invention. Figure 2(a) is a schematic diagram of a non-combinatorial logic loop in an embodiment of the present invention; Figure 2(b) is the truth table of the circuit shown in Figure 2(a); Figure 2(c) is a schematic diagram of a combinational logic circuit according to an embodiment of the present invention. Figure 2(d) is a schematic diagram of the structure of a ring-shaped combinational logic circuit according to an embodiment of the present invention; Figure 3(a) is a schematic diagram of the circuit structure of a non-combinatorial logic ring with added key according to an embodiment of the present invention; Figure 3(b) is a schematic diagram of a state machine for the input of a constrained combinational logic circuit according to an embodiment of the present invention; Figure 3(c) is the truth table of the cyclic combinational logic circuit based on Figures 3(a) and 3(b). Detailed Implementation

[0011] To make the objectives, technical solutions, and technical effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0012] Typically, a circuit loop includes combinational logic loops and non-combinatorial logic loops. Combinatorial logic loops do not latch values, and their outputs are only related to the current input (CI). Non-combinatorial logic loops, on the other hand, latch values ​​(LatchedValue, LV), and their outputs are related not only to the current input CI, but also to the input latched at the previous moment (LatingInput, LI).

[0013] For circuits containing non-combinational logic loops, when the current input CI causes the current circuit output to be affected by the latched value, if the input LI at the time of latching corresponding to the latched value is free and unconstrained, then the latched value is considered to be 'X', meaning the circuit function will malfunction. To ensure that circuits containing non-combinational logic loops do not produce 'X', i.e., the latched value cannot be 'X', when the latched value affects the circuit output, the input LI at the time of latching in the previous moment must be determined.

[0014] Figure 2(a) shows a non-combinatorial logic loop circuit, whose latched value is represented by KEEP. The first three columns of Figure 2(b) are the truth table of the circuit shown in Figure 2(a). Depending on the constraints on inputs a and b of the circuit shown in Figure 2(a), the value of KEEP in the truth table is uncertain. Figure 2(b) shows one possible case of the value of KEEP, in which the output c of the circuit shown in Figure 2(a) is logically equivalent to input b. Assuming that the outputs a and b of the two registers in Figure 2(c) exactly match the case in the fourth column of Figure 2(b), the encryptor can directly embed the circuit in Figure 2(a) into the circuit in Figure 2(c), as shown in Figure 2(d). Because the output c is logically equivalent to the input b, the final circuit function will remain unchanged, and a non-combinatorial logic loop will be introduced.

[0015] Figure 3(a) shows a schematic diagram of a non-combinatorial logic loop circuit structure after adding a key. In the circuit shown in Figure 3(a), the AND gate 'K' is the key gate. When the input key Key is 0, the AND gate 'K' outputs 0, ultimately causing KEEP to be a constant 0, meaning the non-combinatorial logic loop in the circuit does not exist. When the input key Key is 1, the non-combinatorial logic loop in the circuit will be retained. The encryptor needs to construct multiple non-combinatorial logic loops in the circuit. When the constraints on the non-combinatorial logic loops make the latched value deterministic, the key value of the constructed non-combinatorial logic loop is 1; when the latched value is uncertain 'X', the key value is 0. The state machine shown in Figures 3(b) and 3(c) is an example of a constrained combinational logic circuit input. Under the drive of this state machine, the latched value is deterministic, therefore the introduced key value is 1.

[0016] Typical combinational logic circuits are driven by state machines. To ensure that the values ​​latched in non-combinatorial logic loops are deterministic, the encoding of state machines can be divided into two categories: The first type is the free encoding Sf. When the encoding is changed, the value latched in the circuit loop has no effect on the circuit's functional output PO. The second type is the state machine code Sk that makes the circuit output the value of ring KEEP.

[0017] Meanwhile, the transitions between state machines can be categorized as follows: 1) The intermediate state encoding of the jump between Sf will not affect the final functional output PO of the circuit, nor will it affect the latched value, because the latched value is the value under the influence of the final Sf.

[0018] 2) For the jump from Sf to Sk, since it is necessary to ensure that the value latched under the corresponding Sk is unique, there is only one jump path for each Sf entering Sk.

[0019] 3) Jumps from Sk to Sf are the same as jumps from Sf to Sf, and the number of jumps is also unrestricted.

[0020] 4) Jumps between Sk are not allowed due to the intermediate states of the state machine. For example, when jumping from '01' to '10', there is a high possibility of intermediate states '11' or '00'. These intermediate states change the latched values. Therefore, to ensure that there are no functional errors, jumps between Sk are not allowed.

[0021] When the state machine driving the combinational logic circuit is subject to the constraints of conditions 1) to 4) above, a non-combinational logic loop can be directly constructed. Under these constraints, the latched values ​​in the loop are deterministic. For multi-bit state machines, a few bits can be split and treated as a new state machine.

[0022] Specifically, this invention provides a method for logic locking and encryption of combinational logic circuits by utilizing the constraints imposed on the state machine driving the circuit. Figure 1 The diagram illustrates the encryption process of this method. The encryptor first constructs a non-combinational logic loop based on the external constraints of the combinational logic circuit. When the constructed non-combinational logic loop can guarantee that it will not introduce 'X' functionally, it can be directly added to the original combinational logic circuit. The circuit will retain the loop functionally. When the value latched in the non-combinational logic loop is uncertain, the added key will only form a loop structurally, and this loop will not affect the circuit function.

[0023] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention in any way. Although the implementation process of the present invention has been described in detail above, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A method for logic-locked encryption using a non-combinatorial logic ring, characterized in that, First, a non-combinational logic ring is constructed based on the external constraints of the combinational logic circuit. Then, the latched value of the non-combinational logic ring is determined. Next, the non-combinational logic ring with the latched value is added to the combinational logic circuit to form a combinational logic circuit with a ring. Finally, a key gate is added to the non-combinational logic ring, and the non-combinational logic ring is enabled according to the key value, thereby performing logic locking on the combinational logic circuit with a ring. The combinational logic circuit is driven by a state machine, which includes: The Sf state ensures that the value latched in the non-combinatorial logic loop has no effect on the functional output of the circuit. The Sk state causes the non-combinatorial logic loop to output the latched value; The external constraints of the combinational logic circuit are the constraints imposed on the state machine, and the constraints imposed on the state machine include: For transitions from state Sf to state Sf, the intermediate states and the number of transitions have no effect on the latched value or the functional output of the circuit. For the transition from the Sf state to the Sk state, there is only one and only one transition path, thus determining the latched value; The transition from Sk state to Sf state is the same as the transition from Sf state to Sf state. Jumping from one Sk state to another is not allowed.

2. The method for logic locking encryption using a non-combinatorial logic ring as described in claim 1, characterized in that, The key gate is an AND gate. One input of the AND gate is the key value, and the other input is connected to the output of the non-combinatorial logic ring. The output of the AND gate is connected to the input of the gate circuit in the non-combinatorial logic ring.

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