Gate driving circuit and display panel

Abstract

The application provides a gate driving circuit and a display panel. The gate driving circuit comprises a pull-up control module, an inverting module, and a pull-down maintaining module. The pull-up control module is electrically connected with a first voltage terminal, a first node, and a second node. The inverting module is electrically connected with the first voltage terminal, the first node, the second node, and a third node. The pull-down maintaining module is electrically connected with the first voltage terminal, the first node, and the third node. When the pull-up control module is electrically connected with the first voltage terminal and the second node according to a pull-up control signal, the inverting module is disconnected from a low-frequency clock signal terminal and the third node according to the potential of the second node, the inverting module is electrically connected with the first voltage terminal and the third node according to the potential of the first node, and the pull-down maintaining module is disconnected from the first voltage terminal and the first node according to the potential of the third node. Therefore, the control speed of the pull-down maintaining module in disconnecting the first voltage terminal and the first node is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to a gate driving circuit and a display panel. Background Technology

[0002] In gate drive circuits, two transistors are typically used to output the required gate control signal. One transistor raises the first node potential, and the other pulls it down, allowing the output transistor to be in either on or off state depending on the first node's potential. However, as the output transistor transitions from off to on state based on the first node's potential, the transistor pulling down the first node's potential undergoes a transition from on to off state. Therefore, while the transistor raising the first node's potential is used, the transistor pulling it down remains on for a certain period, affecting the raising effect and leading to temperature rise and reduced reliability in the gate drive circuit. Summary of the Invention

[0003] This invention provides a gate driving circuit and a display panel, which can improve the problems of temperature rise and reduced reliability of gate driving circuits.

[0004] This invention provides a gate driving circuit, comprising an inverting module, a pull-down sustaining module, and a pull-up control module. The inverting module is electrically connected to a first voltage terminal, a first node, a second node, and a third node. The inverting module is configured to control signal transmission between the first voltage terminal and the third node based on the potential of the first node, and to control signal transmission between a low-frequency clock signal terminal and the third node based on the potential of the second node. The pull-down sustaining module is electrically connected to the first voltage terminal, the first node, and the third node. The pull-down sustaining module is configured to control signal transmission between the first voltage terminal and the first node based on the potential of the third node. The pull-up control module is electrically connected to the first voltage terminal, the first node, and the second node. The pull-up control module is configured to pull up the potential of the first node based on a pull-up control signal, and to control signal transmission between the first voltage terminal and the second node based on the pull-up control signal. Wherein, the pull-up control module is configured to electrically connect the first voltage terminal and the second node according to the pull-up control signal, the inverting module is configured to disconnect the electrical connection between the low-frequency clock signal terminal and the third node according to the potential of the second node, and control the first voltage terminal to electrically connect with the third node according to the potential of the first node, and the pull-down sustaining module is configured to disconnect the electrical connection between the first voltage terminal and the first node according to the potential of the third node.

[0005] Optionally, in some embodiments, the pull-up control module includes a first control unit and a second control unit. The first control unit includes a first transistor, the control terminal of which is configured to receive the pull-up control signal. The input terminal of the first transistor is electrically connected to its control terminal, and the output terminal of the first transistor is electrically connected to the first node. The second control unit includes a second transistor, the control terminal of which is configured to receive the pull-up control signal. The input terminal of the second transistor is electrically connected to the first voltage terminal, and the output terminal of the second transistor is electrically connected to the second node.

[0006] Optionally, in some embodiments, the inverting module includes a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The control terminal of the third transistor is electrically connected to the low-frequency clock signal terminal, the input terminal of the third transistor is electrically connected to its control terminal, and the output terminal of the third transistor is electrically connected to the second node. The control terminal of the fourth transistor is electrically connected to the second node, the input terminal of the fourth transistor is electrically connected to the low-frequency clock signal terminal, and the output terminal of the fourth transistor is electrically connected to the third node. The control terminal of the fifth transistor is electrically connected to the first node, the input terminal of the fifth transistor is electrically connected to the first voltage terminal, and the output terminal of the fifth transistor is electrically connected to the second node. The control terminal of the sixth transistor is electrically connected to the first node, the input terminal of the sixth transistor is electrically connected to the first voltage terminal, and the output terminal of the sixth transistor is electrically connected to the third node.

[0007] Optionally, in some embodiments, the pull-down sustaining module includes a seventh transistor, the control terminal of the seventh transistor being electrically connected to the third node, the input terminal of the seventh transistor being electrically connected to the first voltage terminal, and the output terminal of the seventh transistor being electrically connected to the first node.

[0008] Optionally, in some embodiments, the pull-up control module further includes a third control unit, the third control unit including an eighth transistor, the control terminal of the eighth transistor being configured to receive the pull-up control signal, the input terminal of the eighth transistor being electrically connected to the first voltage terminal, and the output terminal of the eighth transistor being electrically connected to the third node.

[0009] Optionally, in some embodiments, the second node includes a first child node and a second child node, and the third node includes a third child node and a fourth child node. The low-frequency clock signal terminal includes a first low-frequency clock signal terminal and a second low-frequency clock signal terminal.

[0010] The inverting module includes a first inverting unit and a second inverting unit. The output terminal of the third transistor, the control terminal of the fourth transistor, and the output terminal of the fifth transistor of the first inverting unit are electrically connected to the first sub-node. The output terminal of the fourth transistor and the output terminal of the sixth transistor of the first inverting unit are electrically connected to the third sub-node. The control terminal of the third transistor and the input terminal of the fourth transistor of the first inverting unit are electrically connected to the first low-frequency clock signal terminal. The output terminal of the third transistor, the control terminal of the fourth transistor, and the output terminal of the fifth transistor of the second inverting unit are electrically connected to the second sub-node. The output terminal of the fourth transistor and the output terminal of the sixth transistor of the second inverting unit are electrically connected to the fourth sub-node. The control terminal of the third transistor and the input terminal of the fourth transistor of the second inverting unit are electrically connected to the second low-frequency clock signal terminal.

[0011] The pull-down sustaining module includes a first pull-down sustaining unit and a second pull-down sustaining unit. The control terminal of the seventh transistor of the first pull-down sustaining unit is electrically connected to the third sub-node, and the control terminal of the seventh transistor of the second pull-down sustaining unit is electrically connected to the fourth sub-node.

[0012] The second control unit of the pull-up control module includes a first sub-control unit and a second sub-control unit. The output terminal of the second transistor of the first sub-control unit is electrically connected to the first sub-node, and the output terminal of the second transistor of the second sub-control unit is electrically connected to the second sub-node.

[0013] The third control unit of the pull-up control module includes a third sub-control unit and a fourth sub-control unit. The output terminal of the eighth transistor of the third sub-control unit is electrically connected to the third sub-node, and the output terminal of the eighth transistor of the fourth sub-control unit is electrically connected to the fourth sub-node.

[0014] Optionally, in some embodiments, the pull-down sustaining module includes a ninth transistor, the control terminal of the ninth transistor being electrically connected to the third node, the input terminal of the ninth transistor being electrically connected to the first voltage terminal, and the output terminal of the ninth transistor being electrically connected to the signal output terminal of the gate drive circuit.

[0015] Optionally, in some embodiments, the gate driving circuit further includes an output module, a pull-down control module, and a reset module. The output module includes an output transistor and a first capacitor. The control terminal of the output transistor is electrically connected to the first node, the input terminal of the output transistor is electrically connected to a high-frequency clock signal terminal, and the output terminal of the output transistor is electrically connected to the signal output terminal of the gate driving circuit. The first capacitor is connected in series between the first node and the signal output terminal. The pull-down control module includes a first pull-down transistor. The control terminal of the first pull-down transistor is configured to receive a pull-down control signal. The input terminal of the first pull-down transistor is electrically connected to a first voltage terminal, and the output terminal of the first pull-down transistor is electrically connected to the first node. The reset module includes a first reset transistor and a second reset transistor. The control terminals of the first and second reset transistors are configured to receive a reset control signal. The input terminals of the first and second reset transistors are electrically connected to the first voltage terminal, the output terminal of the first reset transistor is electrically connected to the first node, and the output terminal of the second reset transistor is electrically connected to the signal output terminal of the gate driving circuit.

[0016] This application also provides a display panel including a gate driving unit, wherein the gate driving unit includes a plurality of gate driving circuits as described above, and the plurality of gate driving circuits are cascaded. The gate control signal output by the (n-4)th stage gate driving circuit serves as the pull-up control signal received by the pull-up control module of the nth stage gate driving circuit.

[0017] Optionally, in some embodiments, the voltage of the low-frequency clock signal transmitted by the low-frequency clock signal terminal during the sensing phase of the display panel is less than the voltage of the low-frequency clock signal during the display phase of the display panel.

[0018] This invention provides a gate driving circuit and a display panel. By electrically connecting a pull-up control module to a first voltage terminal, a first node, and a second node, an inverting module to the first voltage terminal, the first node, the second node, and a third node, and a pull-down sustaining module to the first voltage terminal, the first node, and the third node, when the pull-up control module electrically connects the first voltage terminal and the second node according to the pull-up control signal, the inverting module disconnects the electrical connection between the low-frequency clock signal terminal and the third node according to the potential of the second node. The inverting module also controls the electrical connection between the first voltage terminal and the third node according to the potential of the first node, while the pull-down sustaining module disconnects the electrical connection between the first voltage terminal and the first node according to the potential of the third node. Therefore, when the pull-up control module electrically connects the first voltage terminal and the second node according to the pull-up control signal, the low-frequency clock signal transmitted by the low-frequency clock signal terminal no longer acts on the third node; only the first voltage signal supplied by the first voltage terminal acts on the third node. This improves the control speed of the pull-down sustaining module disconnecting the electrical connection between the first voltage terminal and the first node, thereby improving the problems of temperature rise and reduced reliability in the gate driving circuit. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic block diagram of the gate driving circuit provided in an embodiment of the present invention;

[0021] Figure 2 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0022] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0023] Figure 4 This is a timing diagram of the corresponding gate driving circuit provided in an embodiment of the present invention;

[0024] Figure 5 This is a simulation timing diagram of the corresponding gate drive circuit before improvement provided in the embodiments of the present invention;

[0025] Figure 6 This is a simulation timing diagram of the corresponding improved gate drive circuit provided in the embodiments of the present invention;

[0026] Figure 7 This is a schematic diagram of the structure of the display panel provided in an embodiment of the present invention;

[0027] Figure 8 This is a cascade diagram of multiple gate drive circuits provided in an embodiment of the present invention;

[0028] Figure 9 This is a schematic diagram showing the correspondence between the gate drive circuit and the high-frequency clock signal provided in an embodiment of the present invention;

[0029] Figure 10 This is a driving timing diagram of the display panel provided in an embodiment of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0031] Specifically, Figure 1 This is a schematic block diagram of the gate driving circuit provided in an embodiment of the present invention. The gate driving circuit includes an inverting module 10, a pull-down sustaining module 20, and a pull-up control module 30.

[0032] The inverting module 10 is electrically connected to the first voltage terminal VGL, the first node N1, the second node N2, and the third node N3. The inverting module 10 is configured to control the signal transmission between the first voltage terminal VGL and the third node N3 according to the potential of the first node N1, and to control the signal transmission between the low-frequency clock signal terminal LC and the third node N3 according to the potential of the second node N2.

[0033] The pull-down sustaining module 20 is electrically connected to the first voltage terminal VGL, the first node N1 and the third node N3. The pull-down sustaining module 20 is configured to control the signal transmission between the first voltage terminal VGL and the first node N1 according to the potential of the third node N3.

[0034] The pull-up control module 30 is electrically connected to the first voltage terminal VGL, the first node N1 and the second node N2. The pull-up control module 30 is configured to pull up the potential of the first node N1 according to the pull-up control signal UCS, and to control the signal transmission between the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS.

[0035] Wherein, the pull-up control module 30 is configured to electrically connect the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS, the inverting module 10 is configured to disconnect the electrical connection between the low-frequency clock signal terminal LC and the third node N3 according to the potential of the second node N2, and the inverting module 10 is configured to control the electrical connection between the first voltage terminal VGL and the third node N3 according to the potential of the first node N1, and the pull-down sustaining module 20 is configured to disconnect the electrical connection between the first voltage terminal VGL and the first node N1 according to the potential of the third node N3, so as to achieve the pull-up control... When module 30 electrically connects the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS, the low-frequency clock signal transmitted by the low-frequency clock signal terminal LC no longer acts on the third node N3, and only the first voltage signal supplied by the first voltage terminal VGL acts on the third node N3. This allows the pull-down sustaining module 20 to control the electrical connection between the first voltage terminal VGL and the first node N1 to be disconnected only according to the action of the first voltage signal. This helps to advance the time when the electrical connection between the first voltage terminal VGL and the first node N1 is disconnected, thereby improving the problems of temperature rise and reduced reliability of the gate drive circuit.

[0036] Alternatively, please continue reading Figure 1 In some embodiments, the pull-up control module 30 includes a first control unit 301 and a second control unit 302. The first control unit 301 is configured to control the rise of the potential of the first node N1 according to the pull-up control signal UCS, and the second control unit 302 is configured to control the signal transmission between the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS.

[0037] Figure 2 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention. Optionally, in some embodiments, the first control unit 301 includes a first transistor T1, and the second control unit 302 includes a second transistor T2.

[0038] The control terminal of the first transistor T1 is configured to receive the pull-up control signal UCS. The input terminal of the first transistor T1 is electrically connected to the control terminal of the first transistor T1, and the output terminal of the first transistor T1 is electrically connected to the first node N1.

[0039] The control terminal of the second transistor T2 is configured to receive the pull-up control signal UCS. The input terminal of the second transistor T2 is electrically connected to the first voltage terminal VGL, and the output terminal of the second transistor T2 is electrically connected to the second node N2.

[0040] Please continue reading. Figure 2 In some embodiments, the inverting module 10 includes an inverting unit, which includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a sixth transistor T6.

[0041] The control terminal of the third transistor T3 is electrically connected to the low-frequency clock signal terminal LC, the input terminal of the third transistor T3 is electrically connected to the control terminal of the third transistor T3, and the output terminal of the third transistor T3 is electrically connected to the second node N2.

[0042] The control terminal of the fourth transistor T4 is electrically connected to the second node N2, the input terminal of the fourth transistor T4 is electrically connected to the low-frequency clock signal terminal LC, and the output terminal of the fourth transistor T4 is electrically connected to the third node N3.

[0043] The control terminal of the fifth transistor T5 is electrically connected to the first node N1, the input terminal of the fifth transistor T5 is electrically connected to the first voltage terminal VGL, and the output terminal of the fifth transistor T5 is electrically connected to the second node N2.

[0044] The control terminal of the sixth transistor T6 is electrically connected to the first node N1, the input terminal of the sixth transistor T6 is electrically connected to the first voltage terminal VGL, and the output terminal of the sixth transistor T6 is electrically connected to the third node N3.

[0045] The third transistor T3 is configured to control the signal transmission between the low-frequency clock signal terminal LC and the second node N2 according to the low-frequency clock signal transmitted by the low-frequency clock signal terminal LC. The fourth transistor T4 is configured to control the signal transmission between the low-frequency clock signal terminal LC and the third node N3 according to the potential of the second node N2. The fifth transistor T5 is configured to control the signal transmission between the first voltage terminal VGL and the second node N2 according to the potential of the first node N1. The sixth transistor T6 is configured to control the signal transmission between the first voltage terminal VGL and the third node N3 according to the potential of the first node N1.

[0046] Please continue reading. Figure 2 In some embodiments, the pull-down sustaining module 20 includes a pull-down sustaining unit, which includes a seventh transistor T7. The control terminal of the seventh transistor T7 is electrically connected to the third node N3, the input terminal of the seventh transistor T7 is electrically connected to the first voltage terminal VGL, and the output terminal of the seventh transistor T7 is electrically connected to the first node N1.

[0047] Alternatively, please continue reading Figure 1 In some embodiments, the pull-up control module 30 further includes a third control unit 303, which is configured to control the signal transmission between the first voltage terminal VGL and the third node N3 according to the pull-up control signal UCS. This is to improve the control speed at which the pull-down maintenance module 20 disconnects the electrical connection between the first voltage terminal VGL and the first node N1 when the pull-up control module 30 electrically connects the first voltage terminal VGL and the second node N2 according to the pull-up control signal UCS, thereby further improving the problems of temperature rise and reduced reliability of the gate drive circuit.

[0048] Please continue reading. Figure 2 In some embodiments, the third control unit 303 includes an eighth transistor T8, the control terminal of which is configured to receive the pull-up control signal UCS, the input terminal of which is electrically connected to the first voltage terminal VGL, and the output terminal of which is electrically connected to the third node N3.

[0049] Optionally, in some embodiments, the pull-down sustaining module 20 is also electrically connected to the signal output terminal Gout of the gate drive circuit, and the pull-down sustaining module 20 is further configured to control the signal transmission between the first signal terminal and the signal output terminal Gout according to the potential of the third node N3.

[0050] Accordingly, please continue reading Figure 2In some embodiments, the pull-down sustaining module 20 includes a ninth transistor T9, the control terminal of the ninth transistor T9 is electrically connected to the third node N3, the input terminal of the ninth transistor T9 is electrically connected to the first voltage terminal VGL, and the output terminal of the ninth transistor T9 is electrically connected to the signal output terminal Gout of the gate drive circuit.

[0051] Optionally, in some embodiments, the pull-down sustaining module 20 can reduce the number of transistors used in the gate drive circuit by electrically connecting the output of the seventh transistor T7 to the signal output Gout, thereby omitting the ninth transistor T9 by reusing the seventh transistor T7.

[0052] Please continue reading. Figure 1 The gate drive circuit further includes an output module 40, which is electrically connected to the first node N1 and the signal output terminal Gout of the gate drive circuit. The output module 40 is configured to control the signal transmission between the high-frequency clock signal terminal CK and the signal output terminal Gout according to the potential of the first node N1.

[0053] Accordingly, please continue reading Figure 2 In some embodiments, the output module 40 includes an output transistor To and a first capacitor C1. The control terminal of the output transistor To is electrically connected to the first node N1, the input terminal of the output transistor To is electrically connected to the high-frequency clock signal terminal CK, and the output terminal of the output transistor To is electrically connected to the signal output terminal Gout of the gate drive circuit. The first capacitor C1 is connected in series between the first node N1 and the signal output terminal Gout.

[0054] Please continue reading. Figure 1 In some embodiments, the gate drive circuit further includes a pull-down control module 50, which is electrically connected to the first node N1 and the first voltage terminal VGL. The pull-down control module 50 is configured to control the signal transmission between the first node N1 and the first voltage terminal VGL according to the pull-down control signal DCS.

[0055] Accordingly, please continue reading Figure 2 In some embodiments, the pull-down control module 50 includes a first pull-down transistor Td1, the control terminal of the first pull-down transistor Td1 is configured to receive the pull-down control signal DCS, the input terminal of the first pull-down transistor Td1 is electrically connected to the first voltage terminal VGL, and the output terminal of the first pull-down transistor Td1 is electrically connected to the first node N1.

[0056] Optionally, in some embodiments, the pull-down control module 50 is also electrically connected to the signal output terminal Gout of the gate drive circuit, and the pull-down control module 50 is further configured to control the signal transmission between the first voltage terminal VGL and the signal output terminal Gout according to the pull-down control signal DCS.

[0057] Accordingly, the pull-down control module 50 includes a second pull-down transistor, the control terminal of the second pull-down transistor is configured to receive the pull-down control signal DCS, the input terminal of the second pull-down transistor is electrically connected to the first voltage terminal VGL, and the output terminal of the second pull-down transistor is electrically connected to the signal output terminal Gout.

[0058] Please continue reading. Figure 1 In some embodiments, the gate drive circuit further includes a reset module 60, which is electrically connected to the first node N1, the first voltage terminal VGL, and the signal output terminal Gout of the gate drive circuit. The reset module 60 is configured to control the signal transmission between at least one of the first node N1 and the signal output terminal Gout and the first voltage terminal VGL according to a reset control signal Rst.

[0059] Alternatively, please continue reading Figure 2 In some embodiments, the reset module 60 includes a first reset transistor Ti1 and a second reset transistor Ti2. The control terminals of the first reset transistor Ti1 and the second reset transistor Ti2 are configured to receive a reset control signal Rst. The input terminals of the first reset transistor Ti1 and the second reset transistor Ti2 are electrically connected to the first voltage terminal VGL. The output terminal of the first reset transistor Ti1 is electrically connected to the first node N1, and the output terminal of the second reset transistor Ti2 is electrically connected to the signal output terminal Gout of the gate drive circuit.

[0060] Optionally, in some embodiments, the reset module 60 may include one of the first reset transistor Ti1 and the second reset transistor Ti2.

[0061] Optionally, in some embodiments, the reset module 60 includes a reset transistor, the control terminal of which is configured to receive a reset control signal Rst. The input terminal of the reset transistor is electrically connected to the first voltage terminal VGL, and the output terminal of the reset transistor is electrically connected to at least one of the first node N1 and the signal output terminal Gout. By electrically connecting the output terminal of the reset transistor to both the first node N1 and the signal output terminal Gout, the number of transistors used in the gate drive circuit can be reduced, saving costs. Furthermore, when the gate drive circuit is applied to a display panel, it facilitates a narrow bezel design for the display panel.

[0062] Optionally, in some embodiments, the gate drive circuit further includes a stage transmission module, which is electrically connected to the first node N1, the high-frequency clock signal terminal CK, and the stage transmission output terminal of the gate drive circuit. The stage transmission module is configured to control the signal transmission between the high-frequency clock signal terminal CK and the stage transmission output terminal according to the potential of the first node N1.

[0063] Optionally, the cascading module includes a cascading transistor, the control terminal of which is electrically connected to the first node N1, the input terminal of which is electrically connected to the high-frequency clock signal terminal CK, and the output terminal of which is electrically connected to the cascading signal terminal.

[0064] Optionally, in some embodiments, the pull-down sustaining module 20 further includes a tenth transistor, the control terminal of which is electrically connected to the third node N3, the input terminal of which is electrically connected to the first voltage terminal VGL, and the output terminal of which is electrically connected to the cascade signal terminal.

[0065] Optionally, in some embodiments, the reset module 60 further includes a third reset transistor, the control terminal of which is configured to receive the reset control signal Rst, the input terminal of which is electrically connected to the first voltage terminal VGL, and the output terminal of which is electrically connected to the transmission signal terminal.

[0066] Understandably, to reduce the number of transistors included in the gate drive circuit, the tenth transistor can be omitted by reusing the seventh transistor T7. That is, the output of the seventh transistor T7 is still electrically connected to the stage output terminal. Similarly, the third reset transistor can be omitted by reusing the reset transistor. That is, the output of the reset transistor is still electrically connected to the stage output terminal.

[0067] Figure 3This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. In some embodiments, the gate driving circuit may be provided with two inverting units, so that the two inverting units work alternately at a certain time interval, thereby extending the life cycle of the gate driving circuit. Accordingly, to match the configuration of the two inverting units, the pull-down sustaining module 20 includes two pull-down sustaining units, the second control unit 302 of the pull-up control module 30 may include two sub-control units, and the third control unit 303 of the pull-up control module 30 may include two sub-control units.

[0068] Accordingly, the second node N2 includes a first child node N21 and a second child node N22, and the third node N3 includes a third child node N31 and a fourth child node N32. The low-frequency clock signal terminal LC includes a first low-frequency clock signal terminal LC1 and a second low-frequency clock signal terminal LC2.

[0069] The inverting module 10 includes a first inverting unit 101 and a second inverting unit 102. The output terminal of the third transistor T31, the control terminal of the fourth transistor T41, and the output terminal of the fifth transistor T51 of the first inverting unit 101 are electrically connected to the first sub-node N21. The output terminals of the fourth transistor T41 and the sixth transistor T61 of the first inverting unit 101 are electrically connected to the third sub-node N31. The control terminal of the third transistor T31 and the input terminal of the fourth transistor T41 of the first inverting unit 101 are electrically connected to the first low-frequency clock signal terminal LC1. The output terminal of the third transistor T32, the control terminal of the fourth transistor T42, and the output terminal of the fifth transistor T52 of the second inverter unit 102 are electrically connected to the second sub-node N22. The output terminal of the fourth transistor T42 and the output terminal of the sixth transistor T62 of the second inverter unit 102 are electrically connected to the fourth sub-node N32. The control terminal of the third transistor T32 and the input terminal of the fourth transistor T42 of the second inverter unit 102 are electrically connected to the second low-frequency clock signal terminal LC2.

[0070] The pull-down sustaining module 20 includes a first pull-down sustaining unit 201 and a second pull-down sustaining unit 202. The control terminal of the seventh transistor T71 of the first pull-down sustaining unit 201 is electrically connected to the third sub-node N31, and the control terminal of the seventh transistor T72 of the second pull-down sustaining unit 202 is electrically connected to the fourth sub-node N32.

[0071] Optionally, in some embodiments, the control terminal of the ninth transistor T91 of the first pull-down sustaining unit 201 is electrically connected to the third sub-node N31, and the control terminal of the ninth transistor T92 of the second pull-down sustaining unit 202 is electrically connected to the fourth sub-node N32.

[0072] The second control unit 302 of the pull-up control module 30 includes a first sub-control unit 3021 and a second sub-control unit 3022. The output terminal of the second transistor T21 of the first sub-control unit 3021 is electrically connected to the first sub-node N21, and the output terminal of the second transistor T22 of the second sub-control unit 3022 is electrically connected to the second sub-node N22.

[0073] The third control unit 303 of the pull-up control module 30 includes a third sub-control unit 3031 and a fourth sub-control unit 3032. The output terminal of the eighth transistor T81 of the third sub-control unit 3031 is electrically connected to the third sub-node N31, and the output terminal of the eighth transistor T82 of the fourth sub-control unit 3032 is electrically connected to the fourth sub-node N32.

[0074] It should be noted that the second transistor T21 of the first sub-control unit 3021 and the second transistor T22 of the second sub-control unit 3022 are two separate transistors, rather than multiplexing a single transistor. Similarly, the third transistor T31 of the first inverting unit 101 and the third transistor T32 of the second inverting unit 102 are two separate transistors; the fourth transistor T41 of the first inverting unit 101 and the fourth transistor T42 of the second inverting unit 102 are two separate transistors; the fifth transistor T51 of the first inverting unit 101 and the fifth transistor T52 of the second inverting unit 102 are two separate transistors; and the sixth transistor T61 of the first inverting unit 101 and the sixth transistor T62 of the second inverting unit 102 are two separate transistors. The seventh transistor T71 of the first pull-down sustaining unit 201 and the seventh transistor T72 of the second pull-down sustaining unit 202 are two transistors. The eighth transistor T81 of the third sub-control unit 3031 and the eighth transistor T82 of the fourth sub-control unit 3032 are two transistors. The ninth transistor T91 of the first pull-down sustaining unit 201 and the ninth transistor T92 of the second pull-down sustaining unit 202 are two transistors.

[0075] Figure 4 This is a timing diagram of the corresponding gate driving circuit provided in an embodiment of the present invention, wherein each transistor included in the gate driving circuit is an N-type transistor; in Figure 2 Taking the low-frequency clock signal transmitted via LC at the low-frequency clock signal terminal as an example in the gate drive circuit shown, for... Figure 2 The working principle of the gate drive circuit shown will be explained.

[0076] In the first stage t1: the reset signal Rst is at a high level, and the pull-up control signal UCS, the high-frequency clock signal CKa transmitted by the high-frequency clock signal terminal CK, and the pull-down control signal DCS are at a low level. The first reset transistor Ti1 and the second reset transistor Ti2 are turned on, and the first voltage terminal VGL, the first node N1, and the signal output terminal Gout are electrically connected.

[0077] In the second stage t2: the pull-up control signal UCS is at a high level, the high-frequency clock signal CKa transmitted by the high-frequency clock signal terminal CK and the pull-down control signal DCS are at a low level. The first transistor T1, the second transistor T2, the output transistor To, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 are turned on, while the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, the first pull-down transistor Td1, the first reset transistor Ti1, and the second reset transistor Ti2 are turned off.

[0078] In the third stage t3: the high-frequency clock signal CKa is at a high level, and the pull-up control signal UCS and the pull-down control signal DCS are at a low level. The first transistor T1, the second transistor T2, and the eighth transistor T8 are off, the output transistor To, the fifth transistor T5, and the sixth transistor T6 remain on, the fourth transistor T4, the seventh transistor T7, the ninth transistor T9, and the first pull-down transistor Td1 remain off, and the gate control signal Scan output by the signal output terminal Gout is at a high level.

[0079] In the fourth stage t4: the pull-down control signal DCS is at a high level, and the pull-up control signal UCS and the high-frequency clock signal CKa are at a low level. The first transistor T1, the second transistor T2, and the eighth transistor T8 remain off, the first pull-down transistor Td1 is on, the output transistor To, the fifth transistor T5, and the sixth transistor T6 are off, and the third transistor T3, the fourth transistor T4, the seventh transistor T7, and the ninth transistor T9 are on.

[0080] Among them, Figure 3 In the gate drive circuit shown, the first low-frequency clock signal LCa supplied by the first low-frequency clock signal terminal LC1 can have one of the states of high level and low level, and the second low-frequency clock signal LCb supplied by the second low-frequency clock signal terminal LC2 can have the other of the states of high level and low level.

[0081] Figure 5This is a simulation timing diagram of the corresponding gate drive circuit before improvement, provided in an embodiment of the present invention. Figure 6 This is a simulation timing diagram of the improved gate drive circuit provided in this embodiment of the invention. L1 represents the potential change curve of the first node N1, L21 represents the potential change curve of the second node N2 before improvement, L22 represents the potential change curve of the second node N2 after improvement, and L3 represents the gate control signal Scan at the signal output terminal Gout. The inventors of this invention conducted simulation analysis on the gate drive circuit before and after improvement. The simulation results show that, before improvement, there is an overlap time period ta between the potential rise process of the first node N1 and the potential fall process of the second node N2, causing the seventh transistor T7 to turn on during the corresponding time period ta, resulting in a leakage path between the first node N1 and the first voltage terminal VGL. After the improvement, before the potential of the first node N1 rises, the potential of the second node N2 can be pulled down to the voltage corresponding to the first voltage terminal VGL under the control of the pull-up control module 30. This reduces the leakage current between the first node N1 and the first voltage terminal VGL during the potential rise of the first node N1, improves the potential rise effect of the first node N1, and thus improves the problems of temperature rise and reduced reliability of the gate drive circuit.

[0082] Figure 7 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. This application also provides a display panel including a gate driving unit (GDU), wherein the gate driving unit includes a plurality of any of the aforementioned gate driving circuits (e.g., Figure 7 (as shown in GDC).

[0083] Please continue reading. Figure 7 The display panel includes multiple sub-pixels (Spi), multiple scan lines (SL), and multiple data lines (DL). The multiple sub-pixels (Spi) are electrically connected to the gate driving unit (GDU), the multiple scan lines (SL), and the multiple data lines (DL). The multiple sub-pixels (Spi) realize the display according to multiple gate control signals output by the gate driving unit (GDU). Specifically, the multiple gate control signals are transmitted to the multiple sub-pixels (Spi) via the scan lines (SL).

[0084] Figure 8 This is a cascade diagram of multiple gate driving circuits provided in an embodiment of the present invention. Optionally, in some embodiments, multiple gate driving circuits are cascaded. The pull-up control signal UCS received by the first x stages of the cascaded gate driving circuits is provided by a control chip or other device.

[0085] The pull-up control signal UCS received by the first two stages of the gate drive circuit in a cascaded gate drive circuit is provided by the control chip. Specifically, the control chip generates a first start signal STV1 and a second start signal STV2. The first start signal STV1 serves as the pull-up control signal UCS received by the first stage gate drive circuit GDC1 in the cascaded gate drive circuit, and the second start signal STV2 serves as the pull-up control signal UCS received by the second stage gate drive circuit GDC2 in the cascaded gate drive circuit.

[0086] Optionally, the control chip includes a timing controller, etc.

[0087] Optionally, the nth-stage gate control signal Scan(np) output by the nth-stage gate drive circuit GDC(np) from the signal output terminal Gout, or the nth-stage stage transmission control signal output by the nth-stage gate drive circuit GDC(np) from the stage transmission output terminal, corresponds to the pull-up control signal UCS received by the nth-stage gate drive circuit GDC(n). Wherein, n>1, m≥1.

[0088] Optionally, the gate control signal Scan(n-4) output by the gate drive circuit GDC(n-4) of the n-4th stage is used as the pull-up control signal UCS received by the pull-up control module 30 of the gate drive circuit GDC(n) of the nth stage.

[0089] Optionally, in some embodiments, the (n+q)th stage gate control signal Scan(n+q) output by the (n+q)th stage gate drive circuit GDC(n+q) from the signal output terminal Gout, or the (n+q)th stage transmission control signal output by the (n+q)th stage gate drive circuit GDC(n+q) from the stage transmission output terminal, corresponds to the pull-up control signal UCS received by the nth stage gate drive circuit GDC(n). Wherein, q ≥ 1.

[0090] Optionally, the gate control signal Scan(n+4) output by the gate drive circuit GDC(n+4) of the (n+4)th stage is used as the pull-down control signal DCS received by the gate drive circuit GDC(n) of the nth stage.

[0091] Optionally, in some embodiments, the multiple gate driving circuits share the low-frequency clock signal supplied by the low-frequency clock signal terminal LC, that is, the multiple gate driving circuits are all electrically connected to the low-frequency clock signal terminal LC. Further, the multiple gate driving circuits are all electrically connected to the first low-frequency clock signal terminal LC1 and the second low-frequency clock signal terminal LC2.

[0092] Optionally, in some embodiments, multiple gate drive circuits share multiple high-frequency clock signals CKa to save bezel layout space while reducing the number of high-frequency clock signals CKa applied to the display panel.

[0093] Optionally, multiple gate drive circuits may share y high-frequency clock signals CKa. Here, y can be 2, 4, 6, 8, 12, etc.

[0094] Figure 9 This is a schematic diagram illustrating the correspondence between the gate driving circuit and the high-frequency clock signal provided in an embodiment of the present invention. Optionally, in some embodiments, multiple gate driving circuits share eight high-frequency clock signals CKa. The high-frequency clock signal CKa received by the (8z+1)th stage gate driving circuit GDC(8z+1) corresponds to the first high-frequency clock signal CK1, the high-frequency clock signal CKa received by the (8z+2)th stage gate driving circuit GDC(8z+2) corresponds to the second high-frequency clock signal CK2, the high-frequency clock signal CKa received by the (8z+3)th stage gate driving circuit GDC(8z+3) corresponds to the third high-frequency clock signal CK3, and the high-frequency clock signal received by the (8z+4)th stage gate driving circuit GDC(8z+4) corresponds to the third high-frequency clock signal CK3. CKa corresponds to the fourth high-frequency clock signal CK4. The high-frequency clock signal CKa received by the 8z+5th stage gate drive circuit GDC(8z+5) corresponds to the fifth high-frequency clock signal CK5. The high-frequency clock signal CKa received by the 8z+6th stage gate drive circuit GDC(8z+6) corresponds to the sixth high-frequency clock signal CK6. The high-frequency clock signal CKa received by the 8z+7th stage gate drive circuit GDC(8z+7) corresponds to the seventh high-frequency clock signal CK7. The high-frequency clock signal CKa received by the 8z+8th stage gate drive circuit GDC(8z+8) corresponds to the eighth high-frequency clock signal CK8. Where z≥0.

[0095] Figure 10 This is a driving timing diagram of a display panel provided in an embodiment of the present invention. Optionally, in some embodiments, the display panel, in addition to supporting display functions, also supports functions including touch functions. Therefore, within one frame, there may be at least one display stage Dt and at least one sensing stage St. In some embodiments, the sensing stage St may correspond to the touch stage.

[0096] However, when the display panel transitions from the display stage Dt to the sensing stage St, the potential of the first node N1 of the gate drive circuit in some stages has been raised, but the corresponding received high-frequency clock signal CKa is not yet at a high level, resulting in the output gate control signal not yet having a valid level. Therefore, it is necessary to restore the operation of the gate drive circuit in some stages when the display panel re-enters the display stage Dt from the sensing stage St, so that the gate control signals output by the multiple gate drive circuits meet the display requirements.

[0097] If the potential of the first node N1 of the gate driving circuit of the partial stage changes during the sensing stage St, it will cause a change in the conduction level of the output transistor To. Consequently, when the display panel re-enters the display stage Dt from the sensing stage St, the voltage corresponding to the effective level state of the gate control signal output by the gate driving circuit of the partial stage will be different, thereby causing charging differences in the sub-pixels of the corresponding row in the display panel, resulting in problems such as horizontal stripes.

[0098] If, during the sensing stage St, the potential change of the first node N1 of the gate driving circuit of the partial stage causes the output transistor To to be turned off, then when the display panel re-enters the display stage Dt from the sensing stage St, the gate control signal output by the gate driving circuit of the partial stage will be in an ineffective level state. Furthermore, the subsequent multi-stage gate driving circuits will also output gate control signals with ineffective levels because the corresponding pull-up control signal UCS is in an ineffective level state. This will cause the sub-pixels of the corresponding row in the display panel to be unable to perform charging operations, resulting in display abnormalities and other problems.

[0099] Therefore, during the sensing phase St, it is necessary to maintain the potential stability of the first node N1 of at least some stages of the gate drive circuit so that when the display panel re-enters the display phase Dt from the sensing phase St, the multiple gate control signals output by the multi-stage gate drive circuit have a valid level state, thereby improving the display problem.

[0100] Therefore, during the sensing phase St, by controlling the low-frequency clock signal terminal LC to correspond to the low-frequency clock signal, the pull-down sustaining module 20 can be kept disconnected from the electrical connection between the first voltage terminal VGL and the first node N1, so that the potential of the first node N1 of at least a portion of the gate drive circuit remains stable.

[0101] Optionally, in some embodiments, the voltage of the low-frequency clock signal LCS transmitted by the low-frequency clock signal terminal LC during the sensing phase St of the display panel is less than the voltage of the low-frequency clock signal LCS during the display phase Dt of the display panel, so as to keep the potential of the first node N1 of at least a portion of the gate drive circuit stable.

[0102] Optionally, during the sensing phase St, the low-frequency clock signal LCS may switch between a first voltage and a second voltage, but in order to keep the potential of the first node N1 of at least a portion of the gate drive circuit stable during the sensing phase St, both the first voltage and the second voltage are less than the voltage of the low-frequency clock signal LCS during the display phase Dt of the display panel.

[0103] Optionally, in some embodiments, when the first inverting unit 101 is working and the second inverting unit 102 is not working, the voltage of the first low-frequency clock signal LCa transmitted by the first low-frequency clock signal terminal LC1 in the sensing stage St of the display panel is less than the voltage of the first low-frequency clock signal LCa in the display stage Dt of the display panel, so as to keep the potential of the first node N1 of at least a portion of the gate driving circuit stable.

[0104] Optionally, in some embodiments, when the first inverting unit 101 is not working and the second inverting unit 102 is working, the voltage of the second low-frequency clock signal LCb transmitted by the second low-frequency clock signal terminal LC2 during the sensing stage St of the display panel is less than the voltage of the second low-frequency clock signal LCb during the display stage Dt of the display panel, so as to keep the potential of the first node N1 of at least a portion of the gate driving circuit stable.

[0105] Optionally, during the display phase Dt, the first low-frequency clock signal LCa and the second low-frequency clock signal LCb are inverted so that only one of the inverting units operates during the display phase Dt.

[0106] Optionally, during the display phase Dt of consecutive t frames, the first low-frequency clock signal LCa has one of a high-level state and a low-level state, and the second low-frequency clock signal LCb has the other of a high-level state and a low-level state.

[0107] Optionally, every t frames of data displayed on the display panel, the first low-frequency clock signal LCa transitions from a first level state to a second level state, and the second low-frequency clock signal LCb transitions from the second level state to the first level state. The first level state is either a high-level state or a low-level state, and the second level state is either a high-level state or a low-level state. Optionally, t is 100.

[0108] Optionally, during the blanking interval phase, the first low-frequency clock signal LCa has a transition between a first level state and a second level state, and the second low-frequency clock signal LCb has a transition between a second level state and a first level state.

[0109] Optionally, the blanking interval stage includes a vertical blanking interval Bt stage.

[0110] Optionally, the reset control signal Rst may have an effective level state at the beginning of each frame, thereby enabling the reset module 60 to control the first voltage terminal VGL in the gate drive circuit to be electrically connected to at least one of the first node N1 and the signal output terminal Gout according to the reset control signal Rst.

[0111] Optionally, multiple gate driving circuits may share the same reset control signal Rst to reduce the number of control signals used by the gate driving unit and reduce the control complexity of the display panel.

[0112] It is understandable that when the gate drive circuit used in the display panel includes a transmission module, the settings and corresponding effects of each gate drive circuit in the gate drive unit can be derived by analogy to the description when the gate drive circuit does not include a transmission module, and will not be elaborated here.

[0113] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A gate driving circuit, characterized in that, include: The inverting module is electrically connected to the first voltage terminal, the first node, the second node, and the third node; The second node includes a first sub-node and a second sub-node, and the third node includes a third sub-node and a fourth sub-node; the inverting module includes a first inverting unit and a second inverting unit, wherein the output terminal of the third transistor, the control terminal of the fourth transistor, and the output terminal of the fifth transistor of the first inverting unit are electrically connected to the first sub-node, the output terminal of the fourth transistor and the output terminal of the sixth transistor of the first inverting unit are electrically connected to the third sub-node, and the control terminal of the third transistor and the input terminal of the fourth transistor of the first inverting unit are electrically connected to a first low-frequency clock signal terminal; the output terminal of the third transistor, the control terminal of the fourth transistor, and the output terminal of the fifth transistor of the second inverting unit are electrically connected to the second sub-node, the output terminal of the fourth transistor and the output terminal of the sixth transistor of the second inverting unit are electrically connected to the fourth sub-node, and the control terminal of the third transistor and the input terminal of the fourth transistor of the second inverting unit are electrically connected to a second low-frequency clock signal terminal; The pull-down sustaining module is electrically connected to the first voltage terminal, the first node, and the third node, and includes a first pull-down sustaining unit and a second pull-down sustaining unit. The control terminal of the seventh transistor of the first pull-down sustaining unit is electrically connected to the third sub-node, and the control terminal of the seventh transistor of the second pull-down sustaining unit is electrically connected to the fourth sub-node. as well as The pull-up control module is electrically connected to the first voltage terminal, the first node, and the second node, and is configured to pull up the potential of the first node according to the pull-up control signal; The second control unit of the pull-up control module includes a first sub-control unit and a second sub-control unit. The output terminal of the second transistor of the first sub-control unit is electrically connected to the first sub-node, and the output terminal of the second transistor of the second sub-control unit is electrically connected to the second sub-node. The third control unit of the pull-up control module includes a third sub-control unit and a fourth sub-control unit. The output terminal of the eighth transistor of the third sub-control unit is electrically connected to the third sub-node, and the output terminal of the eighth transistor of the fourth sub-control unit is electrically connected to the fourth sub-node. Wherein, the pull-up control module is configured to electrically connect the first voltage terminal and the second node according to the pull-up control signal, the inverting module is configured to disconnect the low-frequency clock signal terminal and the third node according to the potential of the second node, and control the first voltage terminal and the third node to be electrically connected according to the potential of the first node, and the pull-down sustaining module is configured to disconnect the first voltage terminal and the first node according to the potential of the third node; The low-frequency clock signal terminal includes a first low-frequency clock signal terminal and a second low-frequency clock signal terminal.

2. The gate driving circuit according to claim 1, characterized in that, The pull-up control module includes: A first control unit includes a first transistor, the control terminal of which is configured to receive the pull-up control signal, the input terminal of which is electrically connected to the control terminal, and the output terminal of which is electrically connected to the first node; and The second control unit includes a second transistor, the control terminal of which is configured to receive the pull-up control signal, and the input terminal of the second transistor is electrically connected to the first voltage terminal.

3. The gate driving circuit according to claim 2, characterized in that, The input terminal of the third transistor is electrically connected to the control terminal of the third transistor; The control terminal of the fifth transistor is electrically connected to the first node, and the input terminal of the fifth transistor is electrically connected to the first voltage terminal; and The control terminal of the sixth transistor is electrically connected to the first node, and the input terminal of the sixth transistor is electrically connected to the first voltage terminal.

4. The gate driving circuit according to claim 3, characterized in that, The input terminal of the seventh transistor is electrically connected to the first voltage terminal, and the output terminal of the seventh transistor is electrically connected to the first node.

5. The gate driving circuit according to claim 4, characterized in that, The control terminal of the eighth transistor is configured to receive the pull-up control signal, and the input terminal of the eighth transistor is electrically connected to the first voltage terminal.

6. The gate driving circuit according to claim 1, characterized in that, The pull-down sustaining module includes a ninth transistor, the control terminal of which is electrically connected to the third node, the input terminal of which is electrically connected to the first voltage terminal, and the output terminal of which is electrically connected to the signal output terminal of the gate drive circuit.

7. The gate driving circuit according to claim 1, characterized in that, The gate driving circuit further includes: The output module includes an output transistor and a first capacitor. The control terminal of the output transistor is electrically connected to the first node, the input terminal of the output transistor is electrically connected to a high-frequency clock signal terminal, and the output terminal of the output transistor is electrically connected to the signal output terminal of the gate drive circuit. The first capacitor is connected in series between the first node and the signal output terminal. A pull-down control module includes a first pull-down transistor, the control terminal of which is configured to receive a pull-down control signal, the input terminal of which is electrically connected to a first voltage terminal, and the output terminal of which is electrically connected to a first node; and The reset module includes a first reset transistor and a second reset transistor. The control terminals of the first reset transistor and the second reset transistor are configured to receive a reset control signal. The input terminals of the first reset transistor and the second reset transistor are electrically connected to the first voltage terminal. The output terminal of the first reset transistor is electrically connected to the first node. The output terminal of the second reset transistor is electrically connected to the signal output terminal of the gate drive circuit.

8. A display panel, characterized in that, include: A gate driving unit includes a plurality of gate driving circuits as described in any one of claims 1 to 7, wherein the plurality of gate driving circuits are cascaded. Wherein, the gate control signal output by the gate driving circuit of the (n-4)th stage serves as the pull-up control signal received by the pull-up control module of the gate driving circuit of the nth stage.

9. The display panel according to claim 8, characterized in that, The voltage of the low-frequency clock signal transmitted at the low-frequency clock signal terminal during the sensing phase of the display panel is less than the voltage of the low-frequency clock signal during the display phase of the display panel.

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