A gate driving circuit, driving method and display

Abstract

The application discloses a gate driving circuit, a driving method and a display, and relates to the technical field of display, the gate driving circuit comprises a first output circuit, a second output circuit, a first control circuit, a second control circuit and a potential locking circuit, wherein the first control circuit and the second control circuit control the first output circuit and the second output circuit to work respectively, the first control circuit comprises a first capacitor, the second circuit comprises a second capacitor, the waveform output of a subsequent output signal is fully ensured, the potential locking circuit prevents the second capacitor from coupling the output signal to a superior circuit, and the stability of the circuit is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a gate driving circuit, driving method, and display. Background Technology

[0002] In recent years, organic thin-film transistors (OTFTs) have attracted widespread attention from academia and industry due to their development potential in large-area and flexible electronic circuits. Their main advantages lie in low-cost, low-temperature solution-processed manufacturing techniques, suitable for flexible or plastic substrates. Inkjet printing is one of the most promising deposition technologies; this non-contact process saves on the masks required by conventional processes, further reducing the manufacturing cost of OTFTs. With the continuous maturation of fabrication processes, the mobility of OTFTs has surpassed that of amorphous silicon thin-film transistors (a-SiTFTs).

[0003] Gate-on-array (GOA) circuits based on thin-film transistors are crucial for achieving narrow bezels and reducing costs in screen manufacturing. Among various thin-film transistor technologies, low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have become the preferred material for high-end displays due to their high mobility and stability. With the continuous upgrading of display electronics, flexible displays are a major development trend. OTFTs offer advantages such as flexible device flexibility, low cost, and large-area fabrication, showing broad development prospects in large-area flexible display devices and smart electronic tags.

[0004] The main challenges currently facing OTFTs are: (1) low mobility, (2) poor reliability, and (3) device depletion, although dual-gate OTFTs can be converted from depletion-mode to enhancement-mode by adjusting the back gate voltage. These problems pose significant challenges to the circuit design of AMOLED display panels based on organic thin-film transistors. Therefore, it is crucial to design a GOA circuit based on depletion-mode devices, and the process tolerance of this circuit should be large enough to overcome device performance drift. Summary of the Invention

[0005] The purpose of this invention is to provide a gate driving circuit, driving method, and display that, with a simple structure, improves production efficiency and saves production costs.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] A first aspect of the present invention provides a gate driving circuit, the gate driving circuit comprising: a first output circuit and a second output circuit, wherein the output terminal of the first output circuit is connected to the output terminal of the second output circuit; a first control circuit, wherein the first control circuit is connected to the control terminal of the first output circuit for controlling the operation of the first output circuit; and a second control circuit, wherein the second control circuit is connected to the control terminal of the second output circuit for controlling the operation of the second output circuit.

[0008] In some embodiments, the first output circuit includes a first switch and a second switch. The input terminal of the first switch is connected to a first high-level signal, and the input terminal of the second switch is connected to a second high-level signal. The control terminals of the first switch and the second switch are both connected to the first control circuit, so that the first control circuit controls the first switch to output the first high-level signal according to the voltage timing, and controls the second switch to output the second high-level signal.

[0009] In some embodiments, the second output circuit includes a third switch and a fourth switch. The input terminal of the third switch is connected to a first clock signal, and the input terminal of the fourth switch is connected to a third clock signal. The control terminals of both the third and fourth switches are connected to the second control circuit, so that the second control circuit controls the third switch to output the first clock signal and controls the fourth switch to output the third clock signal according to the voltage timing sequence. The output terminal of the third switch is connected to the output terminal of the first switch, and the output terminal of the fourth switch is connected to the output terminal of the second switch, so as to output a corresponding level signal according to the voltage timing sequence.

[0010] In some embodiments, the first control circuit includes a fifth switch, a sixth switch, and a first capacitor. One end of the fifth switch is connected to one end of the sixth switch, one end of the first capacitor, and the control terminal of the first output circuit. The control terminal of the fifth switch is connected to a fourth clock signal. The fifth switch is used to provide a turn-off signal to the first output circuit, and the sixth switch is used to provide an turn-on signal to the first output circuit. The control terminal of the sixth switch and the other end of the first capacitor are connected to a first control signal of the previous stage circuit. When the fifth switch and the sixth switch are fully open, the resistance of the fifth switch is greater than the resistance of the sixth switch.

[0011] In some embodiments, the second control circuit includes a seventh switch and a second capacitor. One end of the seventh switch is connected to one end of the second capacitor and the control terminal of the second output circuit. The other end of the seventh switch is connected to the second control signal of the previous stage circuit. The seventh switch is used to control the operation of the second output circuit. The control terminal of the seventh switch is connected to a fourth clock signal. The other end of the second capacitor is connected to the output terminal of the first switch and the output terminal of the third switch.

[0012] In some embodiments, the first control circuit further includes an eighth switch, which is connected in parallel with the fifth switch, and the control terminal of the eighth switch is connected to a third control signal of the next stage circuit.

[0013] In some embodiments, the second control circuit further includes a ninth switch, one end of which is connected to one end of the seventh switch, and the other end of which is connected to one end of the second capacitor and the control terminal of the second output circuit. The ninth switch is a normally open switch.

[0014] In some embodiments, the gate driving circuit further includes a potential lockout circuit, which includes a tenth switch and an eleventh switch. The control terminal of the tenth switch is connected to one end of the fifth switch, one end of the sixth switch, and one end of the first capacitor. One end of the tenth switch is connected to one end of the ninth switch and one end of the seventh switch. The other end of the tenth switch is connected to one end of the eleventh switch. The other end of the eleventh switch is connected to a second clock signal, and its control terminal is connected to the first clock signal.

[0015] A second aspect of the present invention provides a driving method for a gate driving circuit, the driving method comprising: setting a first clock signal, a third clock signal, and a third control signal high, and setting a second clock signal, a fourth clock signal, a first control signal, and a second control signal low, so that the first capacitor and the second capacitor are pre-charged, and the gate driving circuit outputs a high level; setting the second clock signal, the fourth clock signal, the first control signal, the second control signal, and the third control signal high, and setting the first clock signal and the third clock signal low, so that the gate driving circuit outputs a low level signal; setting the first clock signal, the third clock signal, the first control signal, and the second control signal high, and setting the second clock signal, the fourth clock signal, and the third control signal low, so that the gate driving circuit outputs a high level; and setting the second clock signal, the fourth clock signal, the first control signal, the second control signal, and the third control signal high, and setting the first clock signal and the third clock signal low, so that the gate driving circuit maintains a high level output.

[0016] A third aspect of the present invention provides a display, the display including the gate driving circuit described above.

[0017] According to an embodiment of the present invention, a gate driving circuit, a driving method, and a display have at least the following beneficial effects:

[0018] (1) By designing a single-stage gate drive circuit, a non-overlapping GOA output signal can be achieved. This structure fully considers the influence of transistor size and has a high design capacity.

[0019] (2) Both the first capacitor and the second capacitor have a pre-charging mode. The first capacitor can be higher than the first high-level signal, and the second capacitor can be lower than the low-level signal, which fully ensures the waveform output of the output signal and makes it more stable.

[0020] (3) The process error tolerance of this structure can be effectively improved by using the first control circuit, the second control circuit, and the potential lock-in circuit. The potential lock-in circuit can effectively lock the potential at point B at all times, which greatly enhances the structure's ability to resist clock signal coupling. Even when the transistor threshold voltage drifts by ±7 to 8V, it can still ensure good output.

[0021] (5) The wiring structure is simple, easy to produce, and saves costs.

[0022] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a circuit schematic diagram according to an embodiment;

[0025] Figure 2 This is a voltage timing diagram according to an embodiment. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0028] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connection," "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0029] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0030] The gate drive circuit of the embodiment of this application will be briefly described below:

[0031] According to some embodiments, such as Figure 1 As shown, Figure 1 The circuit schematic 100 of this application is shown. This application provides a gate driving circuit, the gate driving circuit comprising:

[0032] A first output circuit and a second output circuit, wherein the output terminal of the first output circuit is connected to the output terminal of the second output circuit;

[0033] A first control circuit is connected to the control terminal of the first output circuit to control the operation of the first output circuit.

[0034] The second control circuit is connected to the control terminal of the second output circuit to control the operation of the second output circuit.

[0035] Based on the above embodiments, such as Figure 2 As shown, Figure 2A voltage timing diagram 200 is shown. In some embodiments, this application controls the gate drive circuit to operate according to the voltage timing diagram 200.

[0036] In the first stage (A), the first control circuit controls the first output circuit to reduce the output of the high-level OUT(N) signal and the high-level C(N) signal, and the second control circuit controls the second output circuit to output the high-level OUT(N) signal and the high-level C(N) signal.

[0037] In the second stage (B), the first control circuit controls the first output circuit to turn off, and the second control circuit controls the second output circuit to output a low-level OUT(N) signal and a low-level C(N) signal.

[0038] In the third stage (C), the first control circuit controls the first output circuit to output a high-level OUT(N) signal and a high-level C(N) signal, and the second control circuit controls the second output circuit to turn off.

[0039] In the fourth stage (D), the first control circuit controls the first output circuit to maintain a high-level OUT(N) signal and a high-level C(N) signal, while the second control circuit controls the second output circuit to remain off.

[0040] The following is in conjunction with the appendix to this instruction manual. Figures 1 to 2 The gate drive circuit of this application will be further described in detail.

[0041] According to some embodiments, the first output circuit includes a first switch T1 and a second switch T2. The input terminal of the first switch T1 is connected to a first high-level signal VGH1, and the input terminal of the second switch T2 is connected to a second high-level signal VGH2. The control terminals of the first switch T1 and the second switch T2 are both connected to the first control circuit, so that the first control circuit controls the first switch T1 to output the first high-level signal VGH1 and controls the second switch T2 to output the second high-level signal VGH2 according to the voltage timing.

[0042] Furthermore, the second output circuit includes a third switch T3 and a fourth switch T4. The input terminal of the third switch T3 is connected to a first clock signal CLK1, and the input terminal of the fourth switch T4 is connected to a third clock signal CLK3. The control terminals of both the third switch T3 and the fourth switch T4 are connected to the second control circuit, so that the second control circuit can control the third switch T3 to output the first clock signal CLK1 and control the fourth switch T4 to output the third clock signal CLK3 according to the voltage timing sequence. The output terminal of the third switch T3 is connected to the output terminal of the first switch T1, and the output terminal of the fourth switch T4 is connected to the output terminal of the second switch T2, so as to output a corresponding level signal according to the voltage timing sequence.

[0043] Based on the above embodiments, in the first stage (A), the first control circuit controls the first switch T1 and the second switch T2 to reduce their opening degree, further reducing the output of the first high-level signal VGH1 and the second high-level signal VGH2. However, as Figure 2 As shown, in the first stage (A), both the first clock signal CLK1 and the third clock signal CLK3 are at a high level. The second control circuit controls the third switch T3 and the fourth switch T4 to turn on. The third switch T3 outputs the first clock signal CLK1 at a high level, and the fourth switch T4 outputs the third clock signal CLK3 at a high level, so that the OUT(N) signal and the C(N) signal are both at a high level.

[0044] In the second stage (B), the first control circuit controls the first switch T1 and the second switch T2 to turn off, and the second control circuit controls the third switch T3 and the fourth switch T4 to turn on, such as... Figure 2 As shown, in the second stage (B), both the first clock signal CLK1 and the third clock signal CLK3 are at a low level. Therefore, both the OUT(N) signal and the C(N) signal are output as low-level signals.

[0045] In the third stage (C), the first control circuit controls the first switch T1 and the second switch T2 to turn on, and the second control circuit controls the third switch T3 and the fourth switch T4 to turn off. Therefore, both the OUT(N) signal and the C(N) signal are output as high-level signals.

[0046] In the fourth stage (D), the first control circuit keeps the first switch T1 and the second switch T2 open, and the second control circuit keeps the third switch T3 and the fourth switch T4 closed. Therefore, both the OUT(N) signal and the C(N) signal remain at a high level.

[0047] According to some embodiments, the first control circuit includes a fifth switch T5, a sixth switch T6, and a first capacitor C1. One end of the fifth switch T5 is connected to one end of the sixth switch T6, one end of the first capacitor C1, and the control terminal of the first output circuit. The control terminal of the fifth switch T5 is connected to a fourth clock signal CLK4. The fifth switch T5 is used to provide a turn-off signal to the first output circuit, and the sixth switch T6 is used to provide an turn-on signal to the first output circuit. The control terminal of the sixth switch T6 and the other end of the first capacitor C1 are connected to the first control signal C(N-1) of the previous stage circuit. When the fifth switch T5 and the sixth switch T6 are fully open, the resistance of the fifth switch T5 is greater than the resistance of the sixth switch T6.

[0048] Based on the above embodiments, in the first stage (A), as Figure 2 As shown, both the fourth clock signal CLK4 and the first control signal C(N-1) are low. At this time, both the fifth switch T5 and the sixth switch T6 are open. Because the resistance of the fifth switch T5 is greater than the resistance of the sixth switch T6 when both switches T5 and T6 are fully open, therefore... Figure 2 Point A is shown as a high-level signal. Point A is connected to the control terminals of the first switch T1 and the second switch T2 to close the first and second switches T2. However, because the fifth switch T5 is open, the first and second switches T1 and T2 are not completely closed, i.e., their opening degree is weakened. This reduces the ability of the first and second switches T1 and T2 to output the first high-level signal VGH1 and the second high-level signal VGH2. At this time, the first capacitor C1 enters the charging state.

[0049] Phase Two (B), such as Figure 2 As shown, both the fourth clock signal CLK4 and the first control signal C(N-1) are at a high level. The fifth switch T5 is turned off because the fourth clock signal CLK4 is at a high level, and the sixth switch T6 is turned off because the first control signal C(N-1) is at a high level. At this time, after the potential of the side of the first capacitor C1 connected to the first control signal C(N-1) becomes high, the high-level charge in the first stage (A) is discharged from the A side of the first capacitor C1, so that the control terminals of the first switch T1 and the second switch T2 are at a high level, thereby turning off the first switch T1 and the second switch T2.

[0050] Phase 3 (C), such as Figure 2As shown, the fourth clock signal CLK4 is low, the first control signal C(N-1) is high, the fifth switch T5 is turned on because the fourth clock signal CLK4 is low, and the sixth switch T6 is turned off because the first control signal C(N-1) is high. At this time, the A side of the first capacitor C1 discharges, the potential decreases, the control terminals of the first switch T1 and the second switch T2 are low, and the first switch T1 and the second switch T2 are turned on.

[0051] In the fourth stage (D), both the fourth clock signal CLK4 and the first control signal C(N-1) are at a high level. The fifth switch T5 is turned off because the fourth clock signal CLK4 is at a high level, and the sixth switch T6 is turned off because the first control signal C(N-1) is at a high level. At this time, the first capacitor C1 controls the first switch T1 and the second switch T2 to remain open.

[0052] According to some embodiments, the second control circuit includes a seventh switch T7 and a second capacitor C2. One end of the seventh switch T7 is connected to one end of the second capacitor C2 and the control terminal of the second output circuit. The other end of the seventh switch T7 is connected to the second control signal OUT(N-1) of the previous stage circuit. The seventh switch T7 is used to control the operation of the second output circuit. The control terminal of the seventh switch T7 is connected to the fourth clock signal CLK4. The other end of the second capacitor C2 is connected to the output terminal of the first switch T1 and the output terminal of the third switch T3.

[0053] Based on the above embodiments, in the first stage (A), as Figure 2 As shown, the first clock signal CLK1 and the third clock signal CLK3 are both high, while the fourth clock signal CLK4 and the second control signal OUT(N-1) are both low. The seventh switch T7 is turned on because the fourth clock signal CLK4 is low. Figure 2 As shown, the control terminal B of the third switch T3 and the fourth switch T4 is set low, and both the third switch T3 and the fourth switch T4 are turned on, outputting the first clock signal CLK1 and the third clock signal CLK3 at a high level.

[0054] Phase Two (B), such as Figure 2 As shown, the fourth clock signal CLK4 and the second control signal OUT(N-1) are both high, while the first clock signal CLK1 and the third clock signal CLK3 are both low. The seventh switch T7 is off because the fourth clock signal CLK4 is high. At this time, the second capacitor C2 keeps both the third switch T3 and the fourth switch T4 open. However, because the first clock signal CLK1 is low, as... Figure 2As shown, the second capacitor C2 couples point B to a low level below VGL, making the output of the first clock signal CLK1 and the third clock signal CLK3 from the third switch T3 and the fourth switch T4 smoother.

[0055] Phase 3 (C), such as Figure 2 As shown, the first clock signal CLK1, the third clock signal CLK3, and the second control signal OUT(N-1) are all at high level, while the fourth clock signal CLK4 is at low level. The seventh switch T7 is turned on because the fourth clock signal CLK4 is at low level, which causes point B to be set high by the second control signal OUT(N-1), charging the second capacitor C2, and turning off the third switch T3 and the fourth switch T4.

[0056] Phase 4 (D), such as Figure 2 As shown, the fourth clock signal CLK4 and the second control signal OUT(N-1) are both high, while the first clock signal CLK1 and the third clock signal CLK3 are both low. At this time, because the second capacitor C2 is charging in the third stage (C), the potential at point B is high. The seventh switch T7 is turned off because the fourth clock signal CLK4 is high, and the third switch T3 and the fourth switch T4 are kept off by the second capacitor C2.

[0057] According to some embodiments, the first control circuit further includes an eighth switch T8, which is connected in parallel with the fifth switch T5, and the control terminal of the eighth switch T8 is connected to the third control signal C(N+1) of the next stage circuit.

[0058] Based on the above embodiment, the eighth switch T8 is used to accelerate the pull-down of the potential at point A in the third stage (C). For example... Figure 2 As shown, the third control signal C(N+1) is low in the third stage (C), which controls the eighth switch T8 to turn on, and works with the fifth switch T5 to accelerate the pull-down of the potential at point A.

[0059] According to some embodiments, the second control circuit further includes a ninth switch T9, one end of which is connected to one end of the seventh switch T7, and the other end of which is connected to one end of the second capacitor C2 and the control terminal of the second output circuit. The ninth switch T9 is a normally open switch.

[0060] Based on the above embodiments, the ninth switch T9 is used for current limiting. In other embodiments, the ninth switch T9 can be replaced by a current limiting element such as a resistor.

[0061] According to some embodiments, the gate drive circuit further includes a potential lockout circuit, which includes a tenth switch T10 and an eleventh switch T11. The control terminal of the tenth switch T10 is connected to one end of the fifth switch T5, one end of the sixth switch T6, and one end of the first capacitor C1. One end of the tenth switch T10 is connected to one end of the ninth switch T9 and one end of the seventh switch T7. The other end of the tenth switch T10 is connected to one end of the eleventh switch T11. The other end of the eleventh switch T11 is connected to the second clock signal CLK2, and its control terminal is connected to the first clock signal CLK1.

[0062] Based on the above embodiment, in the fourth stage (D), point A is held at a low level by the first capacitor C1, and the tenth switch T10 is turned on, as follows. Figure 2 As shown, the first clock signal CLK1 is low, the second clock signal CLK2 is high, the eleventh switch T11 is turned on, point B is kept high, and the circuit before point B will not have serious fluctuations due to the strong coupling effect of CLK1 through the third switch T3.

[0063] In some embodiments, the first to eleventh switches in this application are all depletion-type organic thin-film transistors (OTFTs), P-type transistors, wherein the control terminal of the switch is the gate of the transistor, and the other two terminals are the source and drain, respectively. The end of the P-type transistor with a higher voltage is the source, and the other end with a lower voltage is the drain.

[0064] This application has at least the following beneficial effects:

[0065] (1) By designing a single-stage gate drive circuit, a non-overlapping GOA output signal can be achieved. This structure fully considers the influence of transistor size and has a high design capacity.

[0066] (2) Both the first capacitor and the second capacitor have a pre-charging mode. The first capacitor can be higher than the first high-level signal, and the second capacitor can be lower than the low-level signal, which fully ensures the waveform output of the output signal and makes it more stable.

[0067] (3) The process error tolerance of this structure can be effectively improved by using the first control circuit, the second control circuit, and the potential lock-in circuit. The potential lock-in circuit can effectively lock the potential at point B at all times, which greatly enhances the structure's ability to resist clock signal coupling. Even when the transistor threshold voltage drifts by ±7 to 8V, it can still ensure good output.

[0068] (5) The wiring structure is simple, easy to produce, and saves costs.

[0069] The driving method of the gate driving circuit in the embodiments of this application will be described below:

[0070] According to some embodiments, such as Figure 2 As shown, Figure 2 The present application provides a voltage timing diagram 200, which discloses a method for driving a gate driving circuit, applied to the gate driving circuit described above. The method includes:

[0071] The first clock signal CLK1, the third clock signal CLK3, and the third control signal C(N+1) are set high, while the second clock signal CLK2, the fourth clock signal CLK4, the first control signal C(N-1), and the second control signal OUT(N-1) are set low, so that the first capacitor C1 and the second capacitor C2 are pre-charged, and the gate drive circuit outputs a high level.

[0072] The second clock signal CLK2, the fourth clock signal CLK4, the first control signal C(N-1), the second control signal OUT(N-1), and the third control signal C(N+1) are set high, while the first clock signal CLK1 and the third clock signal CLK3 are set low, so that the gate drive circuit outputs a low-level signal.

[0073] The first clock signal CLK1, the third clock signal CLK3, the first control signal C(N-1), and the second control signal OUT(N-1) are set high, while the second clock signal CLK2, the fourth clock signal CLK4, and the third control signal C(N+1) are set low, so that the gate drive circuit outputs a high level.

[0074] The second clock signal CLK2, the fourth clock signal CLK4, the first control signal C(N-1), the second control signal OUT(N-1), and the third control signal C(N+1) are set high, while the first clock signal CLK1 and the third clock signal CLK3 are set low, so that the gate drive circuit maintains a high output level.

[0075] According to some embodiments, this application provides a display that includes the gate driving circuit described above.

[0076] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0077] Although this disclosure has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes: A first output circuit and a second output circuit, wherein the output terminal of the first output circuit is connected to the output terminal of the second output circuit; A first control circuit is connected to the control terminal of the first output circuit to control the operation of the first output circuit. The second control circuit is connected to the control terminal of the second output circuit to control the operation of the second output circuit. The first output circuit includes a first switch and a second switch. The input terminal of the first switch is connected to a first high-level signal, and the input terminal of the second switch is connected to a second high-level signal. The control terminals of the first switch and the second switch are both connected to the first control circuit, so that the first control circuit controls the first switch to output the first high-level signal and controls the second switch to output the second high-level signal according to the voltage timing. The second output circuit includes a third switch and a fourth switch. The input terminal of the third switch is connected to a first clock signal, and the input terminal of the fourth switch is connected to a third clock signal. The control terminals of the third switch and the fourth switch are both connected to the second control circuit, so that the second control circuit can control the third switch to output the first clock signal and control the fourth switch to output the third clock signal according to the voltage timing. The output terminal of the third switch is connected to the output terminal of the first switch, and the output terminal of the fourth switch is connected to the output terminal of the second switch, so as to output a corresponding level signal according to the voltage timing sequence; The first control circuit includes a fifth switch, a sixth switch, and a first capacitor. One end of the fifth switch is connected to one end of the sixth switch, one end of the first capacitor, and the control terminal of the first output circuit. The control terminal of the fifth switch is connected to a fourth clock signal. The fifth switch is used to provide a turn-off signal to the first output circuit. The other end of the fifth switch is connected to a low-level signal. The sixth switch is used to provide an turn-on signal to the first output circuit. The control terminal of the sixth switch and the other end of the first capacitor are connected to a first control signal. The other end of the sixth switch is connected to a first high-level signal. The first control signal is the level signal output from the output terminals of the second and fourth switches in the previous stage circuit. When the fifth switch and the sixth switch are fully open, the resistance of the fifth switch is greater than the resistance of the sixth switch.

2. The gate driving circuit according to claim 1, characterized in that, The second control circuit includes a seventh switch and a second capacitor. One end of the seventh switch is connected to one end of the second capacitor and the control terminal of the second output circuit. The other end of the seventh switch is connected to a second control signal. The seventh switch is used to control the operation of the second output circuit. The control terminal of the seventh switch is connected to a fourth clock signal. The other end of the second capacitor is connected to the output terminal of the first switch and the output terminal of the third switch. The second control signal is the level signal output by the output terminals of the first switch and the third switch in the previous stage circuit.

3. The gate driving circuit according to claim 2, characterized in that, The first control circuit further includes an eighth switch, which is connected in parallel with the fifth switch. The control terminal of the eighth switch is connected to a third control signal, which is a level signal output from the output terminals of the second and fourth switches in the next stage circuit.

4. The gate driving circuit according to claim 3, characterized in that, The second control circuit also includes a ninth switch, one end of which is connected to one end of the seventh switch, and the other end of which is connected to one end of the second capacitor and the control terminal of the second output circuit. The ninth switch is a normally open switch, and the control terminal of the ninth switch is connected to a low-level signal.

5. The gate driving circuit according to claim 4, characterized in that, The gate drive circuit further includes a potential lockout circuit, which includes a tenth switch and an eleventh switch. The control terminal of the tenth switch is connected to one end of the fifth switch, one end of the sixth switch, and one end of the first capacitor. One end of the tenth switch is connected to one end of the ninth switch and one end of the seventh switch. The other end of the tenth switch is connected to one end of the eleventh switch. The other end of the eleventh switch is connected to a second clock signal, and the control terminal is connected to the first clock signal.

6. A driving method for a gate driving circuit, applied to the gate driving circuit as described in claim 5, characterized in that, The driving method includes: The first clock signal, the third clock signal, and the third control signal are set high, while the second clock signal, the fourth clock signal, the first control signal, and the second control signal are set low, so that the first capacitor and the second capacitor are pre-charged, and the gate drive circuit outputs a high level. The second clock signal, the fourth clock signal, the first control signal, the second control signal, and the third control signal are set high, and the first clock signal and the third clock signal are set low, so that the gate drive circuit outputs a low-level signal. The first clock signal, the third clock signal, the first control signal, and the second control signal are set high, while the second clock signal, the fourth clock signal, and the third control signal are set low, so that the gate drive circuit outputs a high level. The second clock signal, the fourth clock signal, the first control signal, the second control signal, and the third control signal are set high, while the first clock signal and the third clock signal are set low, so that the gate drive circuit maintains a high output level.

7. A display, characterized in that, The display includes the gate driving circuit according to any one of claims 1 to 5.

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