A gate driving circuit, driving method and display

Abstract

The application discloses a gate driving circuit, a driving method and a display, and relates to the technical field of display, which comprises an output circuit, the output circuit comprises a first output circuit and a second output circuit, and the output end of the first output circuit is connected with the output end of the second output circuit; and a potential locking circuit, the output end of the potential locking circuit is connected with the output circuit, so as to prevent the electrical signal of the output circuit from affecting the upper circuit.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to a gate driving circuit, driving method, and display. Background Technology

[0002] In recent years, organic thin-film transistors (OTFTs) have attracted widespread attention from academia and industry due to their development potential in large-area and flexible electronic circuits. Their main advantages lie in low-cost, low-temperature solution-processed manufacturing techniques, suitable for flexible or plastic substrates. Inkjet printing is one of the most promising deposition technologies; this non-contact process saves on the masks required by conventional processes, further reducing the manufacturing cost of OTFTs. With the continuous maturation of fabrication processes, the mobility of OTFTs has surpassed that of amorphous silicon thin-film transistors (a-Si TFTs).

[0003] Gate-on-array (GOA) circuits based on thin-film transistors are crucial for achieving narrow bezels and reducing costs in screen manufacturing. Among various thin-film transistor technologies, low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) have become the preferred material for high-end displays due to their high mobility and stability. With the continuous upgrading of display electronics, flexible displays are a major development trend. OTFTs offer advantages such as flexible device flexibility, low cost, and large-area fabrication, showing broad development prospects in large-area flexible display devices and smart electronic tags.

[0004] The main challenges currently facing OTFTs are: (1) low mobility, (2) poor reliability, and (3) device depletion, although dual-gate OTFTs can be converted from depletion-mode to enhancement-mode by adjusting the back gate voltage. These problems pose significant challenges to the circuit design of AMOLED display panels based on organic thin-film transistors. Therefore, it is crucial to design a GOA circuit based on depletion-mode devices, and the process tolerance of this circuit should be large enough to overcome device performance drift. Summary of the Invention

[0005] The purpose of this invention is to provide a gate driving circuit, driving method, and display to solve the technical problem of component performance drift in the prior art.

[0006] To solve the above-mentioned technical problems, the present invention adopts the following technical solution:

[0007] A first aspect of the present invention provides a gate driving circuit, the gate driving circuit comprising: an output circuit, the output circuit including a first output circuit and a second output circuit, the output terminal of the first output circuit being connected to the output terminal of the second output circuit; and a potential lockout circuit, the output terminal of the potential lockout circuit being connected to the output circuit to prevent the electrical signal of the output circuit from affecting the upstream circuit.

[0008] In some embodiments, the first output circuit includes a first switch, a start circuit, and a stop circuit. The input terminal of the first switch is connected to a high-level signal. The start circuit and the stop circuit are both connected to the control terminal of the first switch to control the first switch to output a high-level signal according to the voltage timing.

[0009] In some embodiments, the start-up circuit includes a second switch and a third switch, one end of the second switch being connected to the control terminal of the first switch to provide a start signal to the first switch, and one end of the third switch being connected to the control terminal of the second switch to control the on / off state of the second switch.

[0010] In some embodiments, the start-up circuit further includes a fourth switch, one end of which is connected to the control terminal of the first switch, and the control terminal of the fourth switch is connected to a first control signal of the next stage circuit to provide an acceleration start signal to the first switch.

[0011] In some embodiments, the stop circuit further includes a fifth switch, a sixth switch, and a seventh switch. The control terminal of the fifth switch is connected to a first clock signal. One end of the fifth switch is connected to the control terminals of the sixth and seventh switches, and the other end is connected to a second control signal from the previous stage circuit to control the operation of the sixth and seventh switches. One end of the sixth switch is connected to the control terminal of the second switch to provide a turn-off signal to the second switch. One end of the seventh switch is connected to the control terminal of the first switch to provide a turn-off signal to the first switch. The stop circuit also includes a second capacitor. One end of the fifth switch, the control terminal of the sixth switch, and the control terminal of the seventh switch are connected to one end of the second capacitor. When the sixth switch and the third switch are fully open, the resistance of the third switch is greater than the resistance of the sixth switch.

[0012] In some embodiments, the second output circuit includes an eighth switch, a ninth switch, and a first capacitor. The input terminal of the eighth switch is connected to a second clock signal. One end of the first capacitor is connected to the output terminal of the eighth switch and the output terminal of the first switch. One end of the ninth switch is connected to the control terminal of the eighth switch and the other end of the first capacitor to provide a start signal to the eighth switch.

[0013] In some embodiments, the potential-locking circuit includes a tenth switch, an eleventh switch, and a twelfth switch. One end of the tenth switch is connected to the other end of the first capacitor to lock the potential of the other end of the first capacitor, preventing the output signal of the output circuit from affecting the upper-level circuit. The control terminal of the twelfth switch is connected to one end of the fifth switch and one end of the second capacitor. One end of the eleventh switch and one end of the twelfth switch are both connected to the other end of the tenth switch to provide a high-level signal or a low-level signal to the tenth switch. One end of the seventh switch and one end of the second switch are both connected to the control terminals of the tenth and eleventh switches to control the on / off state of the tenth and eleventh switches.

[0014] In some embodiments, the first switch, second switch, third switch, fourth switch, fifth switch, sixth switch, seventh switch, eighth switch, ninth switch, tenth switch, eleventh switch and twelfth switch are all depletion-type transistors.

[0015] A second aspect of the present invention provides a driving method for a gate driving circuit, applied to the gate driving circuit described above. The driving method includes: setting a first clock signal and a second control signal low, and setting the second clock signal and the first control signal high, so that the output circuit outputs a high-level signal; setting the first clock signal, the first control signal, and the second control signal high, and setting the second clock signal low, while keeping the eighth switch open through the first capacitor, so that the output circuit outputs a low-level signal; setting the first clock signal and the first control signal low, and setting the second clock signal and the second control signal high, so that the output circuit outputs a high-level signal; and setting the first clock signal, the first control signal, and the second control signal high, and setting the second clock signal low, so that the output circuit maintains the output of a high-level signal.

[0016] A third aspect of the present invention provides a gate driving circuit, wherein the display includes the gate driving circuit described above.

[0017] According to an embodiment of the present invention, a gate driving circuit, a driving method, and a display have at least the following beneficial effects:

[0018] (1) By designing a single-stage gate drive circuit, a non-overlapping GOA output signal can be achieved. This structure fully considers the influence of transistor size and has a high design capacity.

[0019] (2) Fewer clock control signals, only two DC levels, resulting in lower power consumption compared to existing technologies.

[0020] (3) The effect of CLK2 jump is reduced by the potential lockout circuit. Good output can still be guaranteed when the transistor threshold voltage drifts by ±5 to 6V.

[0021] (4) The number of switches used is small and the wiring structure is relatively simple, which saves costs.

[0022] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this disclosure. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a circuit schematic diagram according to an embodiment;

[0025] Figure 2 This is a voltage timing diagram according to an embodiment. Detailed Implementation

[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0027] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0028] The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0029] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connection," "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art. The drawings are merely illustrative of this disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0031] The gate drive circuit of the embodiment of this application will be briefly described below:

[0032] According to some embodiments, such as Figure 1 As shown, Figure 1 The circuit schematic 100 of this application is shown. This application provides a gate driving circuit, the gate driving circuit comprising:

[0033] An output circuit, comprising a first output circuit and a second output circuit, wherein the output terminal of the first output circuit is connected to the output terminal of the second output circuit.

[0034] A potential-locked circuit is provided, the output of which is connected to the output circuit to prevent the electrical signal of the output circuit from affecting the upstream circuit.

[0035] Based on the above embodiment, the input terminal of the first output circuit is connected to a high-level signal VGH for outputting a high-level OUT(N) signal. The input terminal of the second output circuit is connected to a second clock signal CLK2 for outputting the second clock signal CLK2.

[0036] like Figure 2 As shown, Figure 2 A voltage timing diagram 200 is shown. In some embodiments, this application controls the gate drive circuit to operate according to the voltage timing diagram 200.

[0037] In the first stage (A), the second clock signal CLK2 is high, the first output circuit is turned off, the second output circuit is turned on, and the OUT(N) signal is output as a high-level signal.

[0038] In the second stage (B), the second clock signal CLK2 is low, the first output circuit is turned off, the second output circuit is turned on, and the OUT(N) signal is output as a low-level signal.

[0039] In the third stage (C), the second clock signal CLK2 is high, the first output circuit is turned on, the second output circuit is turned off, and the OUT(N) signal is output as a high-level signal.

[0040] In the fourth stage (D), the second clock signal CLK2 is low, the first output circuit remains on, the second output circuit remains off, and the OUT(N) signal output is high.

[0041] In cases where the threshold voltage of the second output circuit is severely positively biased, the potential lockout circuit can suppress the influence of the second clock signal CLK2 on the upper-level circuit through the coupling effect of the second output circuit.

[0042] The following is in conjunction with the appendix to this instruction manual. Figures 1 to 2 The gate drive circuit of this application will be further described in detail.

[0043] According to some embodiments, the first output circuit includes a first switch T1, a start circuit, and a stop circuit. The input terminal of the first switch T1 is connected to a high-level signal VGH. The start circuit and the stop circuit are both connected to the control terminal of the first switch T1 to control the first switch T1 to output a high-level signal according to the voltage timing.

[0044] Furthermore, the start-up circuit includes a second switch T2 and a third switch T3. One end of the second switch T2 is connected to the control terminal of the first switch T1 to provide a start signal to the first switch T1. One end of the third switch T3 is connected to the control terminal of the second switch T2 to control the on / off state of the second switch T2.

[0045] Furthermore, the stop circuit also includes a fifth switch T5, a sixth switch T6, and a seventh switch T7. The control terminal of the fifth switch T5 is connected to the first clock signal CLK1. One end of the fifth switch T5 is connected to the control terminals of the sixth switch T6 and the seventh switch T7, and the other end is connected to the second control signal OUT(N-1) of the previous stage circuit to control the operation of the sixth switch T6 and the seventh switch T7. One end of the sixth switch T6 is connected to the control terminal of the second switch T2 to provide a turn-off signal to the second switch T2. One end of the seventh switch T7 is connected to the control terminal of the first switch T1 to provide a turn-off signal to the first switch T1.

[0046] The stop circuit also includes a second capacitor C2, and one end of the fifth switch T5, the control end of the sixth switch T6 and the control end of the seventh switch T7 are connected to one end of the second capacitor C2;

[0047] When the sixth switch T6 and the third switch T3 are fully open, the resistance of the third switch T3 is greater than the resistance of the sixth switch T6.

[0048] The other end of the second capacitor C2 is connected to the low level VGL, and the third switch T3 is set as a normally open switch.

[0049] Based on the above embodiments, in the first stage (A), as Figure 2 As shown, both the first clock signal CLK1 and the second control signal OUT(N-1) are low. The fifth switch T5 is turned on because the first clock signal CLK1 is low. The second control signal OUT(N-1) is input to the control terminals of the sixth switch T6, the seventh switch T7, and one end of the second capacitor C2, i.e. Figure 2 As shown at point NET2, switches T6 and T7 are open. Because when switches T6 and T3 are fully open, the resistance of switch T3 is greater than that of switch T6, the control terminal of switch T2 is set to a high level, i.e., point O2 is set to a high level, and switch T2 is closed. When switch T7 is open, the control terminal of switch T1 becomes high, i.e., point O3 is set to a high level, and switch T1 is closed.

[0050] In the second stage (B), such as Figure 2 As shown, both the first clock signal CLK1 and the second control signal OUT(N-1) are at a high level. The fifth switch T5 is closed because the first clock signal CLK1 is high, and the second capacitor C2 keeps the sixth switch T6 and the seventh switch T7 open. The opening of the sixth switch T6 and the seventh switch T7 causes point O3 to be set to a high level, and the first switch T1 is turned off.

[0051] In the third stage (C), such as Figure 2 As shown, the first clock signal CLK1 is low, the second control signal OUT(N-1) is high, the fifth switch T5 is turned on because the first clock signal CLK1 is low, the fifth switch T5 turns on and sets the high level of the second control signal OUT(N-1) to point NET2, the sixth switch T6 and the seventh switch T7 are turned off, point O2 is set to low level by the third switch T3, the third switch T3 controls the second switch T2 to turn on, the second switch T2 controls the first switch T1 to turn on, and the first switch T1 outputs a high level signal VGH.

[0052] In the fourth stage (D), such as Figure 2As shown, the first clock signal CLK1 and the second control signal OUT(N-1) are both high level. Point O2 is set to low level by the third switch T3. The third switch T3 controls the second switch T2 to open, the second switch T2 controls the first switch T1 to open, and the first switch T1 outputs a high level signal VGH.

[0053] According to some embodiments, the startup circuit further includes a fourth switch T4, one end of which is connected to the control terminal of the first switch T1, and the control terminal of the fourth switch T4 is connected to the first control signal OUT(N+1) of the next stage circuit to provide an acceleration startup signal to the first switch T1.

[0054] Based on the above embodiments, such as Figure 2 As shown, the first control signal OUT(N+1) is low in the third stage (C). It can be seen that the fourth switch T4 works with the second switch T2 in the third stage (C) to accelerate the pull-down of point O3 to accelerate the start of the first switch T1.

[0055] According to some embodiments, the second output circuit includes an eighth switch T8, a ninth switch T9, and a first capacitor C1. The input terminal of the eighth switch T8 is connected to a second clock signal CLK2. One end of the first capacitor C1 is connected to the output terminal of the eighth switch T8 and the output terminal of the first switch T1. One end of the ninth switch T9 is connected to the control terminal of the eighth switch T8 and the other end of the first capacitor C1 to provide a start signal to the eighth switch T8.

[0056] Based on the above embodiments, in the first stage (A), as Figure 2 As shown, the second clock signal CLK2 is high, the second control signal OUT(N-1) is low, and the ninth switch T9 is turned on because the second control signal OUT(N-1) is low. Figure 2 As shown, the ninth switch T9 supplies the low level VGL to point NET1, which is the control terminal of the eighth switch and the other end of the first capacitor C1, to control the eighth switch T8 to turn on. Since the second clock signal CLK2 is high, the OUT(N) signal output is high.

[0057] In the second stage (B), such as Figure 2As shown, the second clock signal CLK2 is low, the second control signal OUT(N-1) is high, the ninth switch T9 is turned off because the second control signal OUT(N-1) is high, the first capacitor C1 keeps the NET1 point low, the eighth switch T8 remains open, and the eighth switch T8 outputs a low-level OUT(N) signal because the second clock signal CLK2 is low. After the OUT(N) signal changes from high to low, the first capacitor C1 couples the NET1 point to a potential lower than the low level VGL, so that the eighth switch T8 can better transmit the low-level second clock signal CLK2.

[0058] In the third stage (C), such as Figure 2 As shown, the second clock signal CLK2 is at a high level, the second control signal OUT(N-1) is at a high level, and the ninth switch T9 is turned off because the second control signal OUT(N-1) is at a high level. The control terminal of the eighth switch T8 and the other end of the first capacitor C1 are also connected to a potential lock circuit. At this time, the potential lock circuit provides a high level to the control terminal of the eighth switch T8 and the other end of the first capacitor C1, that is, the potential lock circuit provides a high level to the NET1 point, and the eighth switch T8 is turned off.

[0059] In the fourth stage (D), such as Figure 2 As shown, the second clock signal CLK2 is low, the second control signal OUT(N-1) is high, the potential lock circuit continues to provide a high level to point NET1, and the eighth switch T8 is turned off.

[0060] According to some embodiments, the potential locking circuit includes a tenth switch T10, an eleventh switch T11, and a twelfth switch T12. One end of the tenth switch T10 is connected to the other end of the first capacitor C1 to lock the potential of the other end of the first capacitor C1, preventing the output signal of the output circuit from affecting the upper-level circuit.

[0061] The control terminal of the twelfth switch T12 is connected to one end of the fifth switch T5 and one end of the second capacitor C2. One end of the eleventh switch T11 and one end of the twelfth switch T12 are both connected to the other end of the tenth switch T10 to provide a high-level signal or a low-level signal to the tenth switch T10.

[0062] One end of the seventh switch T7 and one end of the second switch T2 are both connected to the control terminals of the tenth switch T10 and the eleventh switch T11, so as to control the on / off state of the tenth switch T10 and the eleventh switch T11.

[0063] Based on the above embodiments, in the first stage (A), as Figure 2As shown in the voltage timing diagram, the start-up circuit is turned off, the stop circuit is turned on, point O3 is set high by the stop circuit, point NET2 is low during this stage, both the tenth switch T10 and the eleventh switch T11 are turned off, the control terminal of the twelfth switch T12 is connected to point NET2, the twelfth switch T12 is turned on, and the twelfth switch T12 sets point O1 at one end of the eleventh switch T11, one end of the twelfth switch T12 and the other end of the tenth switch T10 to a low level.

[0064] In the second stage (B), such as Figure 2 As shown in the voltage timing diagram, the start-up circuit is turned off, the stop circuit is turned on, point O3 is set high by the stop circuit, point NET2 is kept low by the second capacitor C2 during this stage, the tenth switch T10 and the eleventh switch T11 are both turned off, the twelfth switch T12 is turned on, and the twelfth switch T12 sets point O1 to low level.

[0065] In the third stage (C), such as Figure 2 As shown in the voltage timing diagram, the start-up circuit is on, the stop circuit is off, point O3 is set low by the start-up circuit, and point NET2 is set high by the second control signal OUT(N-1) during this stage. Both the tenth switch T10 and the eleventh switch T11 are on, the twelfth switch T12 is off, the eleventh switch T11 sets point O1 to a high level, and the tenth switch T10 sets the high level of point O1 to point NET1. At this time, the eighth switch T8 can be firmly closed, preventing the eighth switch T8 from turning on due to the transition of the second clock signal CLK2.

[0066] In the fourth stage (D), such as Figure 2 As shown in the voltage timing diagram, the start-up circuit is on, the stop circuit is off, point O3 is set low by the start-up circuit, and point NET2 is held high by the second capacitor C2 during this stage. Both the tenth switch T10 and the eleventh switch T11 are on, the twelfth switch T12 is off, the eleventh switch T11 sets point O1 high, and the tenth switch T10 sets the high level of point O1 into point NET1. At this time, the eighth switch T8 can be firmly closed, preventing the second clock signal CLK2 from causing the eighth switch T8 to turn on.

[0067] According to some embodiments, the first switch T1, the second switch T2, the third switch T3, the fourth switch T4, the fifth switch T5, the sixth switch T6, the seventh switch T7, the eighth switch T8, the ninth switch T9, the tenth switch T10, the eleventh switch T11, and the twelfth switch T12 are all depletion-type transistors.

[0068] Based on the above embodiments, in some embodiments, the first switch T1 to the twelfth switch T12 all adopt P-type depletion-mode organic thin-film transistors (OTFTs), wherein the control terminal of the switch is the gate of the transistor, and the other two terminals are the source and drain, respectively. The end with the higher voltage of the P-type transistor is the source, and the other end with the lower voltage is the drain.

[0069] (1) By designing a single-stage gate drive circuit, a non-overlapping GOA output signal can be achieved. This structure fully considers the influence of transistor size and has a high design capacity.

[0070] (2) Fewer clock control signals, only two DC levels, resulting in lower power consumption compared to existing technologies.

[0071] (3) The effect of CLK2 jump is reduced by the potential lockout circuit. Good output can still be guaranteed when the transistor threshold voltage drifts by ±5 to 6V.

[0072] (4) The number of switches used is small and the wiring structure is relatively simple, which saves costs.

[0073] (5) To ensure sufficient discharge capacity at point O3 and reduce the impact of load on the OUT output terminal, T2 control is introduced. This function can also be achieved by increasing the voltage difference between VGH and VGL.

[0074] The driving method of the gate driving circuit in the embodiments of this application will be described below:

[0075] According to some embodiments, this application provides a driving method for a gate driving circuit, applied to the gate driving circuit described above, the driving method comprising:

[0076] Set the first clock signal CLK1 and the second control signal OUT(N-1) low, and set the second clock signal CLK2 and the first control signal OUT(N+1) high, so that the output circuit outputs a high-level signal;

[0077] Set the first clock signal CLK1, the first control signal OUT(N+1), and the second control signal OUT(N-1) high, and set the second clock signal CLK2 low. Keep the eighth switch T8 open through the first capacitor C1 so that the output circuit outputs a low-level signal.

[0078] Set the first clock signal CLK1 and the first control signal OUT(N+1) low, and set the second clock signal CLK2 and the second control signal OUT(N-1) high, so that the output circuit outputs a high-level signal;

[0079] The first clock signal CLK1, the first control signal OUT(N+1), and the second control signal OUT(N-1) are set high, and the second clock signal CLK2 is set low, so that the output circuit maintains a high-level output signal.

[0080] According to some embodiments, this application provides a display that includes the gate driving circuit described above.

[0081] In the description of the above embodiments, specific features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments or examples.

[0082] Although this disclosure has been described with reference to several typical embodiments, it should be understood that the terminology used is descriptive and exemplary, and not restrictive. Because this disclosure can be embodied in many forms without departing from the spirit or essence of the invention, it should be understood that the above embodiments are not limited to any of the foregoing details, but should be interpreted broadly within the spirit and scope defined by the appended claims. Therefore, all variations and modifications falling within the scope of the claims or their equivalents should be covered by the appended claims.

Claims

1. A gate drive circuit characterized by comprising: The gate driving circuit includes: An output circuit, comprising a first output circuit and a second output circuit, wherein the output terminal of the first output circuit is connected to the output terminal of the second output circuit. A potential lockout circuit, wherein the output terminal of the potential lockout circuit is connected to the output circuit to prevent the electrical signal of the output circuit from affecting the upstream circuit; The first output circuit includes a first switch, a start circuit, and a stop circuit. The input terminal of the first switch is connected to a high-level signal. The start circuit and the stop circuit are both connected to the control terminal of the first switch to control the first switch to output a high-level signal according to the voltage timing. The starting circuit includes a second switch and a third switch. One end of the second switch is connected to the control terminal of the first switch to provide a start signal to the first switch. The other end of the second switch is connected to a low-level signal. One end of the third switch is connected to the control terminal of the second switch to control the on / off state of the second switch. The other end of the third switch and the control terminal of the third switch are both connected to the low-level signal. The startup circuit further includes a fourth switch, one end of which is connected to the control terminal of the first switch, and the control terminal of the fourth switch is connected to a first control signal to provide an acceleration startup signal to the first switch. The other end of the fourth switch is connected to the low-level signal. The first control signal is the output signal of the previous stage output circuit. The stop circuit further includes a fifth switch, a sixth switch, and a seventh switch. The control terminal of the fifth switch is connected to a first clock signal. One end of the fifth switch is connected to the control terminals of the sixth and seventh switches, and the other end is connected to a second control signal to control the operation of the sixth and seventh switches. One end of the sixth switch is connected to the control terminal of the second switch to provide a turn-off signal to the second switch, and the other end of the sixth switch is connected to a high-level signal. One end of the seventh switch is connected to the control terminal of the first switch to provide a turn-off signal to the first switch, and the other end of the seventh switch is connected to the high-level signal. The second control signal is the output signal of the next-stage output circuit. The stop circuit also includes a second capacitor, one end of the fifth switch, the control terminal of the sixth switch, and the control terminal of the seventh switch are connected to one end of the second capacitor; the other end of the second capacitor is connected to the low-level signal. When the sixth switch and the third switch are fully open, the resistance of the third switch is greater than the resistance of the sixth switch.

2. The gate driving circuit according to claim 1, characterized in that, The second output circuit includes an eighth switch, a ninth switch, and a first capacitor. The input terminal of the eighth switch is connected to a second clock signal. One end of the first capacitor is connected to the output terminal of the eighth switch and the output terminal of the first switch. One end of the ninth switch is connected to the control terminal of the eighth switch and the other end of the first capacitor to provide a start signal to the eighth switch. The other end of the ninth switch is connected to the low-level signal. The control terminal of the ninth switch is connected to a second control signal.

3. The gate driving circuit according to claim 2, characterized in that, The potential locking circuit includes a tenth switch, an eleventh switch, and a twelfth switch. One end of the tenth switch is connected to the other end of the first capacitor to lock the potential of the other end of the first capacitor, preventing the output signal of the output circuit from affecting the upper-level circuit. The control terminal of the twelfth switch is connected to one end of the fifth switch and one end of the second capacitor. One end of the eleventh switch and one end of the twelfth switch are both connected to the other end of the tenth switch to provide a high-level signal or a low-level signal to the tenth switch. The other end of the eleventh switch is connected to the high-level signal, and the other end of the twelfth switch is connected to the low-level signal. One end of the seventh switch and one end of the second switch are both connected to the control terminals of the tenth and eleventh switches to control the on / off state of the tenth and eleventh switches.

4. The gate driving circuit according to claim 3, characterized in that, The first switch, second switch, third switch, fourth switch, fifth switch, sixth switch, seventh switch, eighth switch, ninth switch, tenth switch, eleventh switch and twelfth switch all use depletion-type transistors.

5. A driving method for a gate driving circuit, applied to the gate driving circuit as described in claim 4, characterized in that, The driving method includes: The first clock signal and the second control signal are set low, and the second clock signal and the first control signal are set high, so that the output circuit outputs a high-level signal; The first clock signal, the first control signal, and the second control signal are set high, and the second clock signal is set low. The eighth switch is kept open by the first capacitor so that the output circuit outputs a low-level signal. Set the first clock signal and the first control signal low, and set the second clock signal and the second control signal high, so that the output circuit outputs a high-level signal; The first clock signal, the first control signal, and the second control signal are set high, and the second clock signal is set low, so that the output circuit maintains a high-level output signal.

6. A display, characterized in that, The display includes the gate driving circuit according to any one of claims 1 to 4.

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