A delay-locked loop and memory

Abstract

The embodiment of the present disclosure provides a delay-locked loop and a memory, the delay-locked loop comprising: a first signal path comprising a first delay line, configured to receive a reference clock signal and output a feedback clock signal; a detection module, configured to receive the reference clock signal and the feedback clock signal; output a working indication signal based on a phase difference between the reference clock signal and the feedback clock signal; in the case that the phase difference is greater than or equal to a first threshold value, the working indication signal generates a pulse, and the pulse width indicates the size of the phase difference; in the case that the phase difference is less than the first threshold value, the level state of the working indication signal remains unchanged; a conversion module, configured to receive the working indication signal, convert the pulse width of the working indication signal, and output an initial value of a coarse adjustment control code. The delay-locked loop provided by the embodiment of the present disclosure can improve the error code problem of a time-to-digital converter.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more particularly to a delay phase-locked loop and a memory. Background Technology

[0002] In Dynamic Random Access Memory (DRAM), Delay-Locked Loops (PLLs) require delay lines to transmit four-phase clock signals (four clock signals with phases differing by 90 degrees) for subsequent data sampling. However, during PLL operation, the operating parameters of the delay lines need to be adjusted and locked. While a time-to-digital converter (TD-to-time converter) can speed up this adjustment, it can also experience bit errors in certain situations, negatively impacting delay line adjustment and increasing the PLL's locking time. Summary of the Invention

[0003] This disclosure provides a delay phase-locked loop and a memory that can improve the bit error rate problem of a time-to-digital converter and enhance the performance of the delay phase-locked loop.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a delay-locked loop (PLL), the PLL including a first signal path and a time-to-digital converter, the time-to-digital converter including a detection module and a conversion module; wherein...

[0006] The first signal path includes a first delay line, configured to receive a reference clock signal and output a feedback clock signal; wherein, the delay parameter of the first delay line is controlled by a coarse adjustment control code;

[0007] The detection module is configured to receive the reference clock signal and the feedback clock signal; and output a working indication signal based on the phase difference between the reference clock signal and the feedback clock signal; wherein, when the phase difference is greater than or equal to a first threshold, the working indication signal generates a pulse, and the pulse width indicates the magnitude of the phase difference; when the phase difference is less than the first threshold, the level state of the working indication signal remains unchanged.

[0008] The conversion module is configured to receive the working indication signal, convert the pulse width of the working indication signal, and output the initial value of the coarse adjustment control code.

[0009] In some embodiments, the detection module includes:

[0010] A pulse generation module is configured to receive the reference clock signal and the feedback clock signal, and output a phase pulse signal; wherein the phase pulse signal contains a single pulse, and the pulse width indicates the phase difference between the reference clock signal and the feedback clock signal;

[0011] The control module is configured to receive the phase pulse signal, the reference clock signal, and the feedback clock signal; when the phase difference between the reference clock signal and the feedback clock signal is greater than or equal to the first threshold, perform transmission processing on the phase pulse signal and output the working indication signal; when the phase difference is less than the first threshold, perform shielding processing on the phase pulse signal so that the level state of the working indication signal remains unchanged.

[0012] In some embodiments, the control module includes:

[0013] The comparison module is configured to receive the reference clock signal and the feedback clock signal, and output a comparison signal based on the phase difference between the reference clock signal and the feedback clock signal; wherein, if the phase difference is greater than or equal to the first threshold, the comparison signal is in a first state; if the phase difference is less than the first threshold, the comparison signal is in a second state.

[0014] The logic module is configured to receive the comparison signal and the phase pulse signal, perform logical operations on the comparison signal and the phase pulse signal, and output the working indication signal.

[0015] In some embodiments, the first state is a high-level state and the second state is a low-level state;

[0016] The logic module includes a first AND gate, the first input of which receives the comparison signal, the second input of which receives the phase pulse signal, and the output of which outputs the working indication signal.

[0017] In some embodiments, the comparison module includes two delay modules, two level comparators, and an arithmetic unit; wherein,

[0018] The first delay module is configured to receive the reference clock signal, perform delay processing on the reference clock signal, and output a reference delay signal, wherein the delay between the reference clock signal and the reference delay signal is the first threshold.

[0019] The second delay module is configured to receive the feedback clock signal, perform delay processing on the feedback clock signal, and output a feedback delay signal, wherein the delay between the feedback clock signal and the feedback delay signal is the first threshold.

[0020] The first level comparator is configured to receive the reference clock signal and the feedback delay signal, compare the rising edge of the reference clock signal and the rising edge of the feedback delay signal, and output a first result signal; wherein, if the reference clock signal leads the feedback delay signal, the first result signal is in a third state; if the reference clock signal lags the feedback delay signal, the first result signal is in a fourth state.

[0021] The second level comparator is configured to receive the feedback clock signal and the reference delay signal, compare the rising edge of the reference delay signal and the rising edge of the feedback clock signal, and output a second result signal; wherein, if the feedback clock signal leads the reference delay signal, the second result signal is in a third state; if the feedback clock signal lags the reference delay signal, the second result signal is in a fourth state.

[0022] The arithmetic unit is configured to receive the first result signal and the second result signal, perform logical operations on the first result signal and the second result signal, and output the comparison signal.

[0023] In some embodiments, the delay module includes a first NAND gate and a second NAND gate; wherein,

[0024] The first input terminal of the first NAND gate forms the input terminal of the delay module, the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the second input terminals of the first NAND gate and the second input terminal of the second NAND gate both receive the first power signal, and the output terminal of the second NAND gate forms the output terminal of the delay module.

[0025] In some embodiments, the level comparator includes a comparison unit, a latch unit, and a first NOT gate; wherein,

[0026] The comparison unit includes a first output terminal and a second output terminal, configured to receive a first input signal and a second input signal; when the first input signal is in a high-level state, the first input signal and the second input signal are compared in terms of level, and the first output terminal and the second output terminal are charged and discharged according to the comparison result, so as to compare the rising edge of the first input signal and the rising edge of the second input signal;

[0027] The latch unit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the latch unit is connected to the first output terminal of the comparison unit, the second input terminal of the latch unit is connected to the second output terminal of the comparison unit, and the output terminal of the comparison unit is connected to the input terminal of the first NOT gate.

[0028] Specifically, for the first level comparator, the first input signal is the reference clock signal, the second input signal is the feedback delay signal, and the output of the first NOT gate is used to output the first result signal; for the second level comparator, the first input signal is the feedback clock signal, the second input signal is the reference delay signal, and the output of the first NOT gate is used to output the second result signal.

[0029] In some embodiments, the comparison unit includes a cross-coupling component, a pre-charge component, an input component, a control component, and an equalization component; wherein,

[0030] The cross-coupling assembly includes a first switch, a second switch, a third switch, and a fourth switch; the control terminal of the first switch, the control terminal of the second switch, the second terminal of the third switch, and the first terminal of the fourth switch are connected to the first output terminal; the control terminal of the third switch, the control terminal of the fourth switch, the second terminal of the first switch, and the first terminal of the second switch are connected to the second output terminal; the first terminal of the first switch receives a second power signal, and the first terminal of the third switch receives a third power signal.

[0031] The precharge component includes a fifth switch, a sixth switch, and a seventh switch; the control terminals of the fifth switch, the sixth switch, and the seventh switch all receive the first input signal; the first terminal of the fifth switch receives a fourth power signal; the first terminal of the sixth switch receives a fifth power signal; the second terminals of the fifth switch and the first terminals of the seventh switch are connected to the first output terminal; and the second terminals of the sixth switch and the second terminals of the seventh switch are connected to the second output terminal.

[0032] The input component includes an eighth switch and a ninth switch. The control terminal of the eighth switch receives the first input signal, and the control terminal of the ninth switch receives the second input signal. The first terminal of the eighth switch is connected to the second terminal of the second switch, and the first terminal of the ninth switch is connected to the second terminal of the fourth switch.

[0033] The control component includes a tenth switch, the control terminal of which receives the first input signal, the first terminal of which is connected to the second terminal of the eighth switch and the second terminal of the ninth switch, and the second terminal of which is connected to ground.

[0034] The equalization component includes an eleventh switch, the control terminal of which receives the first input signal, the first terminal of which is connected to the second terminal of the fourth switch, and the second terminal of which is connected to the second terminal of the second switch.

[0035] In some embodiments, the first switch, the third switch, the fifth switch, the sixth switch, the seventh switch, and the eleventh switch are all P-type field-effect transistors, and the second switch, the fourth switch, the eighth switch, the ninth switch, and the tenth switch are all N-type field-effect transistors.

[0036] In some embodiments, the latching unit includes a third NAND gate and a fourth NAND gate; wherein,

[0037] The first input terminal of the third NAND gate constitutes the first input terminal of the latch unit, the second input terminal of the third NAND gate is connected to the output terminal of the fourth NAND gate, and the third input terminal of the third NAND gate receives a reset signal; the first input terminal of the fourth NAND gate constitutes the second input terminal of the latch unit, and the second input terminal of the fourth NAND gate is connected to the output terminal of the third NAND gate.

[0038] In some embodiments, the third state is a high-level state and the fourth state is a low-level state;

[0039] The arithmetic unit includes a second AND gate and a second NOT gate. The first input terminal of the second AND gate receives the first result signal, the second input terminal of the second AND gate receives the second result signal, the output terminal of the second AND gate is connected to the input terminal of the second NOT gate, and the second NOT gate is used to output the comparison signal.

[0040] In some embodiments, the pulse generation module includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop, and a sixth flip-flop, and a third AND gate; wherein,

[0041] The clock terminals of the first flip-flop, the second flip-flop, and the third flip-flop all receive the feedback clock signal; the input terminal of the first flip-flop receives the phase-locked loop open signal; the positive output terminal of the first flip-flop is connected to the input terminal of the second flip-flop; the positive output terminal of the second flip-flop is connected to the input terminal of the third flip-flop; and the positive output terminal of the third flip-flop is connected to the first input terminal of the third AND gate.

[0042] The clock terminals of the fourth, fifth, and sixth flip-flops all receive the reference clock signal; the input terminal of the fourth flip-flop is connected to the inverted output terminal of the first flip-flop, the non-inverted output terminal of the fourth flip-flop is connected to the input terminal of the fifth flip-flop, the non-inverted output terminal of the fifth flip-flop is connected to the input terminal of the sixth flip-flop; the non-inverted output terminal of the sixth flip-flop is connected to the second input terminal of the third AND gate.

[0043] The output of the third AND gate outputs the phase pulse signal.

[0044] In some embodiments, the first delay line includes a coarse adjustment delay line; wherein...

[0045] The first delay line is further configured to adjust the working state of the coarse adjustment delay line through the coarse adjustment control code, so as to adjust the delay parameters;

[0046] The coarse adjustment delay line includes n+1 cascaded first delay units, the delay of which is the first threshold; the coarse adjustment control code includes n+1 sub-signals, the i-th first delay unit receives the i-th sub-signal of the coarse adjustment control code, and n is a natural number.

[0047] In some embodiments, the conversion module includes n+1 cascaded second delay units and n+1 seventh flip-flops; wherein,

[0048] The input terminal of the first second delay unit receives the working indication signal, and the output terminal of the i-th second delay unit is connected to the input terminal of the (i+1)-th second delay unit; the input terminal of the i-th seventh flip-flop is connected to the output terminal of the i-th second delay unit, the clock terminal of the i-th seventh flip-flop receives the inverted signal of the working indication signal, and the positive output terminal of the i-th seventh flip-flop outputs the i-th sub-signal of the coarse adjustment control code;

[0049] The delay of the second delay unit is the first threshold.

[0050] In some embodiments, the delay phase-locked loop further includes a clock processing module and a plurality of second delay lines. The clock processing module is connected to both the first delay line and the plurality of second delay lines. The first delay line and the second delay lines have identical structures, and the delay parameters of the second delay lines are controlled by the coarse adjustment control code.

[0051] The clock processing module is configured to receive an initial clock signal and, based on the initial clock signal, output multiple phase clock signals; wherein, the reference clock signal is one of the phase clock signals.

[0052] The second delay line is configured to receive one of the phase clock signals, perform delayed transmission and adjustment processing on the received phase clock signal, and output a target clock signal; wherein the target clock signal is used for data sampling processing after transmission.

[0053] In a second aspect, embodiments of this disclosure provide a memory including a delay phase-locked loop as described in the first aspect.

[0054] This disclosure provides a delay phase-locked loop and a memory. When the phase difference between the reference clock signal and the feedback clock signal is small, the time-to-digital converter does not need to operate because the level of the working indication signal remains unchanged. This can improve the bit error rate, accelerate the locking speed of the delay phase-locked loop, and improve the performance of the delay phase-locked loop. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of a delay phase-locked loop provided in an embodiment of the present disclosure;

[0056] Figure 2 This is a schematic diagram illustrating an application scenario of a delay phase-locked loop provided in an embodiment of this disclosure;

[0057] Figure 3 This is a schematic diagram of another delayed phase-locked loop provided in an embodiment of the present disclosure;

[0058] Figure 4 A partial structural diagram of a delay phase-locked loop provided in this embodiment of the present disclosure. Figure 1 ;

[0059] Figure 5 A signal timing diagram provided for an embodiment of this disclosure Figure 1 ;

[0060] Figure 6 A partial structural diagram of a delay phase-locked loop provided in this embodiment of the present disclosure. Figure 2 ;

[0061] Figure 7 A signal timing diagram provided for an embodiment of this disclosure Figure 2 ;

[0062] Figure 8 A partial structural diagram of a delay phase-locked loop provided in this embodiment of the present disclosure. Figure 3 ;

[0063] Figure 9 A partial structural diagram of a delay phase-locked loop provided in this embodiment of the present disclosure. Figure 4 ;

[0064] Figure 10A signal timing diagram provided for an embodiment of this disclosure Figure 3 ;

[0065] Figure 11 This is a schematic diagram of another delayed phase-locked loop provided in an embodiment of the present disclosure;

[0066] Figure 12 A signal timing diagram provided for an embodiment of this disclosure Figure 4 ;

[0067] Figure 13 This is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure. Detailed Implementation

[0068] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are merely for explaining the relevant applications and not for limiting the applications. It should also be noted that, for ease of description, only the parts related to the relevant applications are shown in the accompanying drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with each other without conflict. It should be noted that the terms "first, second, third" involved in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0069] Dynamic Random Access Memory (DRAM);

[0070] Synchronous Dynamic Random Access Memory (SDRAM);

[0071] Double Data Rate SDRAM (DDR);

[0072] Low-power DDR (LPDDR).

[0073] Taking DRAM as an example, the initial clock signal from the outside is internally divided into four-phase clock signals. These four-phase clock signals are then fed into a delay-locked loop (DLL) for phase synchronization and locking. The adjusted four-phase clock signals, after transmission, are used to sample and select the output of the data signal DQ. The DLL includes a first delay line and multiple second delay lines (typically four). The second delay lines are used to adjust and transmit the four-phase clock signals, while the first delay lines replicate the processing of the second delay lines. The transmission results of the first delay lines serve as the basis for adjusting the operating parameters of all delay lines. Here, the structures of the first and second delay lines are identical, both including coarse-adjustment delay lines, fine-adjustment delay lines, and duty cycle adjustment modules. The DLL achieves locking after steps such as coarse-adjustment, fine-adjustment, and duty cycle adjustment.

[0074] This disclosure primarily relates to the process of coarse delay adjustment, specifically adjusting the delay parameters of the coarse delay lines in the first / second delay lines using coarse adjustment control codes. In the coarse delay adjustment step, the initial value of the coarse adjustment control code can be determined by a time-to-digital converter (TDD). Specifically, the DTD receives a reference clock signal and a feedback clock signal. The reference clock signal refers to the input signal of the first delay line, and the feedback clock signal is used to simulate the waveform of the reference clock signal after transmission through a delay-locked loop (DLL). Then, the DTD converts the phase pulse signal (whose pulse width indicates the phase difference between the reference clock signal and the feedback clock signal) into the initial value of the coarse adjustment control code. Currently, DTDs generally implement transcoding using flip-flops (DFFs). However, when the phase pulse signal is too narrow, the DTD is in a metastable state, resulting in bit errors. In this case, the initial value of the coarse adjustment control code obtained is incorrect, which actually prolongs the locking time of the DLL.

[0075] This disclosure provides a delay phase-locked loop (PLL) in which the time-to-digital converter (TD-SCDMA) does not need to operate when the phase difference between the reference clock signal and the feedback clock signal is small. This improves bit error rate, speeds up the locking speed of the PLL, and enhances its performance.

[0076] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0077] In one embodiment of this disclosure, see Figure 1 This illustrates a schematic diagram of the structure of a delay phase-locked loop 10 provided in an embodiment of this disclosure. Figure 1 As shown, the delay phase-locked loop 10 includes a first signal path 11 and a time-to-digital converter 12. The time-to-digital converter 12 includes a detection module 121 and a conversion module 122; wherein,

[0078] The first signal path 11 includes a first delay line 111, configured to receive a reference clock signal and output a feedback clock signal; wherein the delay parameter of the first delay line 111 is controlled by a coarse adjustment control code.

[0079] The detection module 121 is configured to receive a reference clock signal and a feedback clock signal; and output a working indication signal based on the phase difference between the reference clock signal and the feedback clock signal; wherein, when the phase difference is greater than or equal to a first threshold, the working indication signal generates a pulse, and the pulse width indicates the magnitude of the phase difference; when the phase difference is less than the first threshold, the level of the working indication signal remains unchanged.

[0080] The conversion module 122 is configured to receive the working indication signal, convert the pulse width of the working indication signal, and output the initial value of the coarse adjustment control code.

[0081] It should be noted that the delay-locked loop 10 of this embodiment can be applied to, but is not limited to, memory, such as DRAM, SDRAM, DDR, LPDDR, etc. Furthermore, the delay-locked loop 10 provided in this embodiment can be used to achieve phase locking of clock signals in other analog / digital circuits.

[0082] Here, the reference clock signal, after adjustment by the delay phase-locked loop 10 and transmission through the corresponding signal path, is used for data sampling processing, while the feedback clock signal is used to simulate the signal waveform (corresponding to the reference clock signal) used for data sampling processing. It should be understood that the feedback clock signal and the reference clock signal need to be aligned within the allowable error range to achieve correct data sampling. Here, "alignment" means that the clock periods of the feedback clock signal and the reference clock signal are the same, their rising edges coincide, and their falling edges coincide.

[0083] In this embodiment, when the phase difference between the reference clock signal and the feedback clock signal is greater than or equal to a first threshold, the working indication signal contains pulses. The conversion module 122 converts the pulse width of the working indication signal into the initial value of the coarse adjustment control code. That is, the coarse adjustment control code is adjusted starting from the initial value output by the time-to-digital converter 12, thereby accelerating the adjustment process of the coarse adjustment control code. Conversely, when the phase difference between the reference clock signal and the feedback clock signal is less than the first threshold, the working indication signal does not contain pulses, the conversion module 122 does not operate, and the coarse adjustment control code is not assigned an initial value by the time-to-digital converter 12. This avoids the time-to-digital converter 12 being in a metastable state when the phase difference of the input signal is small, thus preventing it from outputting an error code value. This avoids adverse effects on the adjustment process of the coarse adjustment control code, prevents additional extension of the lock time of the delay phase-locked loop, and thus improves the working performance of the delay phase-locked loop.

[0084] It should also be noted that the first threshold can be determined based on the actual application scenario. For example, the first threshold is the delay adjustment granularity of the coarse adjustment control code. The delay adjustment granularity of the coarse adjustment control code refers to the delay adjustment amount of the first delay line 111 when the coarse adjustment control code makes the smallest unit adjustment.

[0085] In some embodiments, see Figure 2 This illustrates an application scenario for the delay phase-locked loop 10. For example... Figure 2 As shown, the delay phase-locked loop 10 also includes a clock processing module 13 and multiple second delay lines ( Figure 2 (Taking four second delay lines as an example), the clock processing module 13 is connected to the first delay line 111 and the multiple second delay lines. Here, the first delay line 111 and all the second delay lines have the same structure, and the delay parameters of the first delay line 111 and all the second delay lines are controlled by the aforementioned coarse adjustment control code.

[0086] Here, the clock processing module 13 is configured to receive an initial clock signal and, based on the initial clock signal, output multiple phase clock signals (e.g., ...). Figure 2 The reference clock signal is one of the phase clock signals. The second delay line is configured to receive a phase clock signal, perform delay transmission and adjustment processing on the received phase clock signal, and output a target clock signal (i.e., clk0, clk90, clk180, and clk270). Figure 2 (CLK_0, CLK_90, CLK_180, or CLK_270). The target clock signal, after transmission through the signal path, is used for data sampling processing.

[0087] It should be noted that, as Figure 2 As shown, the output of the second delay line is connected to the data selection module through a corresponding signal path, namely the four target clock signals (i.e., Figure 2 After passing through the signal path, CLK_0, CLK_90, CLK_180 and CLK_270 in the signal selection module arrive at the data selection module. The data selection module also receives the data signal DQ and uses the received target clock signal to sample and select the output of the data signal DQ.

[0088] Ideally, the waveforms of clk0 and CLK_0 after signal path transmission are identical, the waveforms of clk90 and CLK_90 after signal path transmission are identical, the waveforms of clk180 and CLK_180 after signal path transmission are identical, and the waveforms of clk270 and CLK_270 after signal path transmission are identical. Figure 2For example, the reference clock signal refers to the first phase clock signal clk0, and the feedback clock signal is used to simulate the waveform when CLK_0 is transmitted to the data selection module. In other words, the delay phase-locked loop 10 needs to simulate the delay of "second delay line + signal path" through the first signal path 11 to achieve feedback adjustment.

[0089] Therefore, in some embodiments, such as Figure 2 As shown, the first signal path 11 further includes a delay simulation module 112; wherein, the first delay line 111 is configured to receive a reference clock signal, perform delayed transmission and adjustment processing on the reference clock signal, and output a first target signal; the delay simulation module 112 is connected to the first delay line 111 and is configured to perform delayed transmission on the first target signal and output a feedback clock signal.

[0090] It should be noted that, with Figure 2 For example, the first delay line 111 is used to replicate the delay of the second delay line, and the delay simulation module is used to replicate the delay of the signal path. In this way, the phase difference between the feedback clock signal and the reference clock signal can reflect whether the delay parameters of the first delay line 111 are appropriate, and this phase difference is also the basis for adjusting the delay parameters.

[0091] In particular, after the delay phase-locked loop 10 enters a stable working state, the signal in the first signal path 11 can be frequency divided, thereby reducing the update frequency of the delay line adjustment signal, avoiding signal jitter caused by signal glitches, and reducing power consumption.

[0092] In some embodiments, such as Figure 3 As shown, the detection module 121 includes:

[0093] The pulse generation module 21 is configured to receive the reference clock signal REF_CLK and the feedback clock signal FB_CLK, and output a phase pulse signal Diff Pulse; wherein the phase pulse signal Diff Pulse contains a single pulse, and the pulse width indicates the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK;

[0094] The control module 22 is configured to receive a phase pulse signal Diff Pulse, a reference clock signal REF_CLK, and a feedback clock signal FB_CLK; when the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK is greater than or equal to a first threshold, the phase pulse signal Diff Pulse is processed for transmission and a working indication signal is output; when the phase difference is less than the first threshold, the phase pulse signal Diff Pulse is masked so that the level of the working indication signal remains unchanged.

[0095] In this way, the control module 22 can decide whether to transmit or block the phase pulse signal Diff Pulse, thereby determining whether the time-to-digital converter 12 should perform transcoding, which can avoid bit error problems when the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK is small.

[0096] In some embodiments, such as Figure 4 As shown, the pulse generation module 21 includes a first flip-flop 211, a second flip-flop 212, a third flip-flop 213, a fourth flip-flop 214, a fifth flip-flop 215, a sixth flip-flop 216, and a third AND gate 217; wherein the clock terminals of the first flip-flop 211, the second flip-flop 212, and the third flip-flop 213 all receive the feedback clock signal FB_CLK; the input terminal of the first flip-flop 211 receives the phase-locked loop start signal FCL start. The flag is connected to the input of the second flip-flop 212, the input of the second flip-flop 212, and the first input of the third flip-flop 213. The clock inputs of the fourth flip-flop 214, the fifth flip-flop 215, and the sixth flip-flop 216 all receive the reference clock signal REF_CLK. The input of the fourth flip-flop 214 is connected to the inverted output of the first flip-flop 211, the non-inverted output of the fourth flip-flop 214 is connected to the input of the fifth flip-flop 215, the non-inverted output of the fifth flip-flop 215 is connected to the input of the sixth flip-flop 216, and the non-inverted output of the sixth flip-flop 216 is connected to the second input of the third AND gate 217. The output of the third AND gate 217 outputs the phase pulse signal Diff Pulse.

[0097] It should be noted that the flip-flops involved in the embodiments of this disclosure are all D-type flip-flops (DFFs), whose function is to sample the signal at the input terminal at the rising edge of the clock signal to obtain the signal at the non-inverting output terminal (Q), and the inverting output terminal... The signal at the positive output terminal (Q) and the signal at the positive output terminal (Q) are a pair of inverted signals.

[0098] It should be noted that the phase-locked loop start signal FCL start flag indicates whether the pulse generation module 21 is working, and also indicates whether the time-delayed phase-locked loop 10 has entered the locking step. See [link / reference] Figure 5 This shows a signal timing diagram of the pulse generation module 21. For example... Figure 5 As shown, when the phase-locked loop start signal FCL start flag is low, the output of the pulse generation module 21 remains low; after the phase-locked loop start signal FCL start flag is high, the output signal FB_clk of the first flip-flop 211...st The output signal FB_clk of the second flip-flop 212 aligns to 2. nd The output signal FB_clk of the third flip-flop 213 aligns to 3. rd The signals are sequentially toggled to high levels, with their rising edges aligned sequentially with the rising edge of the feedback clock signal FB_CLK; simultaneously, the output signal REF_clk of the fourth flip-flop 214 is aligned to 1. st The output signal REF_clk of the fifth flip-flop 215 align2 nd The output signal REF_clk of the sixth flip-flop 216 aligns to 3. rd The levels are sequentially toggled to low, with each falling edge aligned with the rising edge of the reference clock signal REF_CLK. Thus, FB_clk align 3. rd and REF_clk align3 rd The result of the AND operation is the phase pulse signal Diff Pulse, which indicates the phase difference between the feedback clock signal FB_CLK and the reference clock signal REF_CLK.

[0099] like Figure 4 As shown, the first flip-flop 211 to the sixth flip-flop 216 all have a reset terminal, which is used to receive the reset signal RST and realize the reset process.

[0100] In some embodiments, such as Figure 3 As shown, the control module 22 includes:

[0101] The comparison module 221 is configured to receive a reference clock signal REF_CLK and a feedback clock signal FB_CLK, and output a comparison signal DL_PDT based on the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK; wherein, if the phase difference is greater than or equal to a first threshold, the comparison signal DL_PDT is in a first state; if the phase difference is less than the first threshold, the comparison signal DL_PDT is in a second state.

[0102] Logic module 222 is configured to receive comparison signal DL_PDT and phase pulse signal Diff Pulse, perform logical operations on comparison signal DL_PDT and phase pulse signal Diff Pulse, and output a working indication signal.

[0103] It should be noted that in the first implementation, the first state is a low-level state and the second state is a high-level state; the logic module includes a first AND gate, the first input of which receives the inverted signal of the comparison signal, the second input of which receives the phase pulse signal, and the output of which outputs a working indication signal. Alternatively, in the second implementation, the first state is a high-level state and the second state is a low-level state; the logic module includes a first AND gate, the first input of which receives the comparison signal, the second input of which receives the phase pulse signal, and the output of which outputs a working indication signal. The following explanation will follow this scenario.

[0104] In some embodiments, such as Figure 6 As shown, the comparison module 221 includes two delay modules (31, 32), two level comparators (33, 34), and an arithmetic unit 35; wherein,

[0105] The first delay module 31 is configured to receive the reference clock signal REF_CLK, perform delay processing on the reference clock signal REF_CLK, and output the reference delay signal REF_CLK_2g, wherein the delay between the reference clock signal REF_CLK and the reference delay signal REF_CLK_2g is a first threshold.

[0106] The second delay module 32 is configured to receive the feedback clock signal FB_CLK, perform delay processing on the feedback clock signal FB_CLK, and output the feedback delay signal FB_CLK_2g, wherein the delay between the feedback clock signal FB_CLK and the feedback delay signal FB_CLK_2g is a first threshold.

[0107] The first level comparator 33 is configured to receive a reference clock signal REF_CLK and a feedback delay signal FB_CLK_2g, compare the rising edge of the reference clock signal REF_CLK with the rising edge of the feedback delay signal FB_CLK_2g, and output a first result signal PD_OUT1; wherein, if the reference clock signal REF_CLK leads the feedback delay signal FB_CLK_2g, the first result signal PD_OUT1 is in the third state; if the reference clock signal REF_CLK lags the feedback delay signal FB_CLK_2g, the first result signal PD_OUT1 is in the fourth state;

[0108] The second level comparator 34 is configured to receive the feedback clock signal FB_CLK and the reference delay signal REF_CLK_2g, compare the rising edge of the reference delay signal REF_CLK_2g with the rising edge of the feedback clock signal FB_CLK, and output the second result signal PD_OUT2; wherein, if the feedback clock signal FB_CLK leads the reference delay signal REF_CLK_2g, the second result signal PD_OUT2 is in the third state; if the feedback clock signal FB_CLK lags the reference delay signal REF_CLK_2g, the second result signal PD_OUT2 is in the fourth state;

[0109] The arithmetic unit 35 is configured to receive the first result signal PD_OUT1 and the second result signal PD_OUT2, perform logical operations on the first result signal PD_OUT1 and the second result signal PD_OUT2, and output the comparison signal DL_PDT.

[0110] It should be noted that the third and fourth states are different and can be set according to the actual application scenario. This disclosure will subsequently use the example of the third state being a high-level state and the fourth state being a low-level state for explanation; other cases can be understood accordingly.

[0111] It should also be noted that, according to common industry practice, the delay adjustment granularity of the coarse adjustment control code is the delay value of 2 NAND gates, that is, the first threshold can be taken as the delay value of 2 NAND gates, represented as 2g.

[0112] See Figure 7 This shows a signal timing diagram of the comparison module 221. Combined with... Figure 7 This will be explained in three cases:

[0113] Scenario 1: The reference clock signal REF_CLK lags behind the feedback clock signal FB_CLK, and the phase difference is greater than or equal to the first threshold 2g. In this case, the reference clock signal REF_CLK lags behind the feedback delay signal FB_CLK_2g, and the feedback clock signal FB_CLK leads the reference delay signal REF_CLK_2g, as follows. Figure 7 As shown in (a), the first result signal PD_OUT1 is in a low-level state and the second result signal PD_OUT1 is in a high-level state.

[0114] Scenario 2 (This situation) Figure 7(Not shown): The reference clock signal REF_CLK leads the feedback clock signal FB_CLK, and the phase difference is greater than or equal to the first threshold 2g. At this time, the reference clock signal REF_CLK leads the feedback delay signal FB_CLK_2g, and the feedback clock signal FB_CLK lags behind the reference delay signal REF_CLK_2g. At this time, the first result signal PD_OUT1 is in a high-level state, and the second result signal PD_OUT1 is in a low-level state.

[0115] Scenario 3: If the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK is less than the first threshold 2g, then the reference clock signal REF_CLK leads the feedback delay signal FB_CLK_2g, and the feedback clock signal FB_CLK leads the reference delay signal REF_CLK_2g. Both the first result signal PD_OUT1 and the second result signal PD_OUT2 are high.

[0116] Thus, if the phase difference is greater than or equal to the first threshold 2g, the first result signal PD_OUT1 and the second result signal PD_OUT2 will have a low level; if the phase difference is less than the first threshold 2g, both the first result signal PD_OUT1 and the second result signal PD_OUT2 will change to a high level.

[0117] Correspondingly, such as Figure 6 As shown, the arithmetic unit 35 includes a second AND gate 351 and a second NOT gate 352. The first input terminal of the second AND gate 351 receives a first result signal PD_OUT1, and the second input terminal of the second AND gate 351 receives a second result signal PD_OUT2. The output terminal of the second AND gate 351 is connected to the input terminal of the second NOT gate 352. The second NOT gate 352 is used to output a comparison signal DL_PDT.

[0118] Thus, as Figure 7 As shown in (a), if the aforementioned phase difference is greater than or equal to the first threshold 2g, the comparison signal DL_PDT is in the first state (high level); Figure 7 As shown in (b), if the aforementioned phase difference is less than the first threshold 2g, the comparison signal DL_PDT is in the second state (low level). Specifically, in Figure 7 In the diagram, OUT indicates the output of the second AND gate 351.

[0119] The following provides a detailed description of the delay module and level comparator in comparison module 221.

[0120] It should be noted that the structure of the delay module is also the smallest structural unit in the coarse-tuning delay line. For example, such as... Figure 8As shown, the delay module includes a first NAND gate 311 and a second NAND gate 312; wherein, the first input terminal of the first NAND gate 311 forms the input terminal of the delay module, the first input terminal of the second NAND gate 312 is connected to the output terminal of the first NAND gate 311, the second input terminals of the first NAND gate 311 and the second input terminals of the second NAND gate 312 both receive the first power supply signal VDD, and the output terminal of the second NAND gate 312 forms the output terminal of the delay module.

[0121] It should be noted that, in combination Figure 6 and Figure 8 It can be seen that for the first delay module 31, its input terminal receives the reference clock signal REF_CLK, and its output terminal outputs the reference delay signal REF_CLK_2g. For the second delay module 32, its input terminal receives the feedback clock signal FB_CLK, and its output terminal outputs the feedback delay signal FB_CLK_2g.

[0122] In one embodiment, such as Figure 9 As shown, the level comparator includes a comparison unit 41, a latch unit 43, and a first NOT gate 45; wherein,

[0123] The comparison unit 41 includes a first output terminal and a second output terminal, configured to receive a first input signal XCLK and a second input signal CLK. When the first input signal XCLK is in a high-level state, the unit compares the levels of the first input signal XCLK and the second input signal CLK, and performs charging and discharging processing on the first output terminal and the second output terminal according to the comparison result, so as to compare the rising edge of the first input signal XCLK and the rising edge of the second input signal CLK.

[0124] The latch unit 43 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the latch unit 43 is connected to the first output terminal of the comparison unit 41, the second input terminal of the latch unit 43 is connected to the second output terminal of the comparison unit 41, and the output terminal of the comparison unit 41 is connected to the input terminal of the first NOT gate 45.

[0125] It should be noted that, for the first level comparator, the first input signal XCLK refers to the reference clock signal REF_CLK, the second input signal CLK refers to the feedback delay signal FB_CLK_2g, and the output of the first NOT gate 45 is used to output the first result signal PD_OUT1; for the second level comparator, the first input signal XCLK refers to the feedback clock signal FB_CLK, the second input signal CLK refers to the reference delay signal REF_CLK_2g, and the output of the first NOT gate 45 is used to output the second result signal PD_OUT2.

[0126] It should be noted that the comparison unit 41 can only compare the first input signal XCLK and the second output signal when the first input signal XCLK is in a high-level state.

[0127] It should also be noted that the latch unit 43 can be an SR latch composed of two NAND gates (such as...). Figure 9 (as shown), or, the latch unit 43 can also be an SR latch composed of two NOR gates.

[0128] The following provides a feasible structure for comparison unit 41.

[0129] like Figure 9As shown, the comparison unit 41 includes a cross-coupling component, a pre-charge component, an input component, a control component, and an equalization component; wherein, the cross-coupling component includes a first switch 401, a second switch 402, a third switch 403, and a fourth switch 404; the control terminals of the first switch 401, the second switch 402, the third switch 403, and the fourth switch 404 are connected to the first output terminal, and the control terminals of the third switch 403, the fourth switch 404, the first switch 401, and the second switch 404 are connected to the first output terminal. The first terminal of switch 401 is connected to the second output terminal. The first terminal of the first switch 401 receives the second power signal, and the first terminal of the third switch 403 receives the third power signal. The precharge assembly includes a fifth switch 405, a sixth switch 406, and a seventh switch 407. The control terminals of the fifth switch 405, the sixth switch 406, and the seventh switch 407 all receive the first input signal XCLK. The first terminal of the fifth switch 405 receives the fourth power signal, and the first terminal of the sixth switch 406 receives the fifth power signal. The second terminal and the first terminal of the seventh switch 407 are connected to the first output terminal, and the second terminals of the sixth switch 406 and the seventh switch 407 are connected to the second output terminal; the input component includes an eighth switch 408 and a ninth switch 409, the control terminal of the eighth switch 408 receives the first input signal XCLK, the control terminal of the ninth switch 409 receives the second input signal CLK, the first terminal of the eighth switch 408 is connected to the second terminal of the second switch 402, and the first terminal of the ninth switch 409 is connected to the second terminal of the fourth switch 404; control component The system includes a tenth switch 410, whose control terminal receives a first input signal. The first terminal of the tenth switch 410 is connected to the second terminals of the eighth switch 408 and the ninth switch 409, and the second terminal of the tenth switch 410 is connected to ground. The equalization component includes an eleventh switch 411, whose control terminal receives a first input signal XCLK. The first terminal of the eleventh switch 411 is connected to the second terminal of the fourth switch 404, and the second terminal of the eleventh switch 411 is connected to the second terminal of the second switch 402. Here, the first to fifth power signals mentioned above can be the same signal.

[0130] It should be noted that the first switch 401, the third switch 403, the fifth switch 405, the sixth switch 406, the seventh switch 407, and the eleventh switch 411 are all P-type field-effect transistors, while the second switch 402, the fourth switch 404, the eighth switch 408, the ninth switch 409, and the tenth switch 410 are all N-type field-effect transistors. Other cases can be understood accordingly.

[0131] It should be noted that if the first input signal XCLK is in a low-level state, the tenth switch 410 is not turned on, so the comparison unit 41 is not turned on as a whole. The first and second output terminals are charged to a high level by the pre-charge component and cannot reflect the level comparison result of the input signal. Conversely, only when the first input signal XCLK is in a high-level state will the first and second output terminals reflect the level comparison result of the input signal, that is, the comparison unit 41 can perform the signal comparison function.

[0132] Correspondingly, such as Figure 9 As shown, the latch unit 43 includes a third NAND gate 431 and a fourth NAND gate 432; wherein, the first input terminal of the third NAND gate 431 constitutes the first input terminal of the latch unit 43, the second input terminal of the third NAND gate 431 is connected to the output terminal of the fourth NAND gate 432, and the third input terminal of the third NAND gate 431 receives a reset signal LRSTB; the first input terminal of the fourth NAND gate 432 constitutes the second input terminal of the latch unit 43, and the second input terminal of the fourth NAND gate 432 is connected to the output terminal of the third NAND gate 431.

[0133] It should be noted that when both the first and second input terminals are high, the output terminal will maintain its previous level; when the first input terminal is high and the second input terminal is low, the output terminal will be low; when the first input terminal is low and the second input terminal is high, the output terminal will be high; when both the first and second input terminals are low, the output terminal's state is uncertain, and this situation should not occur in principle.

[0134] In addition, the reset signal LRSTB is used to reset the latch unit 43. Specifically, if the reset signal LRSTB is low, the output of the third NAND gate 431 is high, that is, the latch unit 43 is reset to high.

[0135] The working principle of the level comparator is explained below. For convenience, the output signal of the latch unit 43 is called the intermediate signal, and the output signal of the first NOT gate 45 is called the result signal PD_OUT. Due to the action of the reset signal LRSTB, the intermediate signal is initially at a high level, and the result signal PD_OUT is initially at a low level.

[0136] First, when the first input signal XCLK is low, the precharge component and the equalization component are turned on, but the control component is not turned on, that is, the comparison unit has not entered the comparison state, and the potentials of the first output terminal and the second output terminal are both pulled to high level by the precharge component.

[0137] Secondly, it is necessary to explain according to different situations: (1) such as Figure 10As shown in (a), when the rising edge of the first input signal XCLK lags behind the second input signal CLK, after the rising edge of the first input signal XCLK, the tenth switch 410 is turned on, causing the comparison unit 41 to enter the comparison state. The cross-coupling component, the eighth switch 408, the ninth switch 409, and the tenth switch 410 are all turned on, and the first output terminal and the second output terminal are at the same level. At this time, the cross-coupling component cannot perform differential amplification, and the latch unit 43 is always in the signal holding state, so the intermediate signal is high and the comparison signal DL_PDT is low. In addition, after the falling edge of the second input signal CLK, due to the shutdown of the ninth switch 409, a potential difference may occur between the first output terminal and the second output terminal. However, the falling edge of the first input signal XCLK will soon arrive, which will cause the fifth switch 405, the sixth switch 406, the seventh switch 407 and the eleventh switch 411 to all turn on. The potential difference between the first output terminal and the second output terminal has not been sufficiently amplified before it is charged to a high level, so it will not cause the intermediate signal and the result signal PD_OUT to flip. (2) Figure 10 As shown in (b), when the rising edge of the first input signal XCLK leads the second input signal CLK, after the rising edge of the first input signal XCLK, the tenth switch 410 is turned on to enable the comparator unit to enter the working state. The cross-coupling component, the eighth switch 408 and the tenth switch 410 are turned on. At this time, the ninth switch 409 is not yet turned on. The potential of the second output terminal gradually becomes lower than the potential of the first output terminal. After the difference is amplified by the cross-coupling component, the first output terminal outputs a high-level signal and the second output terminal outputs a low-level signal, so the intermediate signal becomes low-level and the resulting signal PD_OUT becomes high-level.

[0138] Thus, as Figure 7 As shown in (a), if the phase difference between the reference clock signal REF_CLK and the feedback clock signal FB_CLK is greater than or equal to the first threshold 2g, then one of the first result signal PD_OUT1 and the second result signal PD_OUT2 must be at a low level, and the comparison result signal DL_PDT is at a high level. If the phase difference is less than the first threshold 2g, then both the first result signal PD_OUT1 and the second result signal PD_OUT2 become high, and the comparison result signal DL_PDT becomes low.

[0139] It should also be noted that, such as Figure 9 As shown, an even number of inverters can be set on the connection path between the comparison unit 41 and the latch unit 43 to achieve delay matching and drive enhancement between signals.

[0140] As can be seen from the above, the embodiments of this disclosure provide a delay phase-locked loop (PLL). When the phase difference between the reference clock signal and the feedback clock signal is small, the time-to-digital converter does not need to work, which can improve the bit error rate, speed up the locking speed of the delay PLL, and improve the performance of the delay PLL.

[0141] In some embodiments, the first delay line 111 includes a coarse adjustment delay line; wherein,

[0142] The first delay line 111 is also configured to adjust the working state of the coarse adjustment delay line through a coarse adjustment control code, thereby adjusting the delay parameters. The coarse adjustment delay line includes n+1 cascaded first delay units, where the delay of each first delay unit is a first threshold value, which is also the delay value of the aforementioned delay module.

[0143] The coarse adjustment control code includes n+1 sub-signals, which can be represented as Q. <n:1>The i-th first delay unit receives the i-th sub-signal Q of the coarse adjustment control code. <i-1>.

[0144] It should be noted that, depending on the specific value of the coarse adjustment control code, the output signal of the coarse adjustment delay line can be controlled to be output from the first delay unit at a specific position, thereby controlling the delay parameters of the coarse adjustment delay line. For example, if the coarse adjustment control code Q... <n:1>=111000……0, then the output signal of the coarse adjustment delay line is output from the third first delay unit, that is, the coarse adjustment delay line can provide a delay of 3×(first threshold 2g); if the coarse adjustment control code Q <n:1>=1111100……0, then the output signal of the coarse adjustment delay line is output from the 5th first delay unit, that is, the coarse adjustment delay line can provide a delay of 5×(first threshold 2g).

[0145] Correspondingly, such as Figure 11 As shown, the conversion module 122 includes n+1 second delay units 51 connected in series and n+1 seventh flip-flops 52; wherein, the input terminal of the first second delay unit 51 receives the working indication signal, and the output terminal of the i-th second delay unit 51 is connected to the input terminal of the (i+1)-th second delay unit 51; the input terminal of the i-th seventh flip-flop 52 is connected to the output terminal of the i-th second delay unit 51, the clock terminal of the i-th seventh flip-flop 52 receives the inverted signal of the working indication signal, and the non-inverted output terminal of the i-th seventh flip-flop 52 outputs the i-th sub-signal of the coarse adjustment control code; the delay of the second delay unit 51 is a first threshold.

[0146] It should be noted that, see Figure 12 It shows a signal timing diagram of the conversion module 122. Figure 12 In the diagram, D00 refers to the input signal of the first seventh flip-flop 52, D01 refers to the input signal of the second seventh flip-flop 52, and so on. n This refers to the input signal of the (n+1)th seventh flip-flop 52. Thus, at the falling edge of the working indicator signal (i.e., the rising edge of the inverted working indicator signal), D00, D01, D02, D03, D04, D05...D0 n Sampling is performed to obtain Q0 (high level), Q1 (high level), Q2 (high level), Q3 (high level), Q4 (low level), Q5 (low level)...Qn (low level). Q0, Q1, Q2, Q3, Q4, Q5...Qn together form the coarse adjustment control code Q. <n:1>.

[0147] In this way, the coarse adjustment delay line processing can be simulated by n+1 series-connected second delay units 51, and the output signal of each second delay unit 51 can be sampled by n+1 seventh flip-flops 52 to obtain the coarse adjustment control code.

[0148] In summary, for a delay-locked loop (PLL), the time-to-digital converter (TD-SCDMA) generates a digital code (used as the initial value for the coarse adjustment control code) using the phase difference between the reference clock signal and the feedback clock signal. This digital code is generated by a trigger. However, if the phase difference between the reference clock signal and the feedback clock signal is small, and the phase pulse signal is too narrow, the TD-SCDMA will experience bit error problems, leading to coarse adjustment delay line (CDL) locking errors. This places a heavy burden on the adjustment process and prolongs the locking process of the PLL. In this embodiment, a detection module detects the phase difference between the reference clock signal and the feedback clock signal. When the phase difference is small, the TD-SCDMA is controlled not to perform transcoding, thus preventing an unexpected increase in the locking time of the PLL.

[0149] In another embodiment of this disclosure, see Figure 13 This illustrates a schematic diagram of the composition structure of a memory 50 provided in an embodiment of this disclosure. For example... Figure 13 As shown, the memory 50 includes at least the aforementioned delay phase-locked loop 10.

[0150] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A delay-locked loop, characterized in that, The delay-locked loop includes a first signal path and a time-to-digital converter, the time-to-digital converter including a detection module and a conversion module; wherein... The first signal path includes a first delay line, configured to receive a reference clock signal and output a feedback clock signal; wherein, the delay parameter of the first delay line is controlled by a coarse adjustment control code; The detection module is configured to receive the reference clock signal and the feedback clock signal; and output a working indication signal based on the phase difference between the reference clock signal and the feedback clock signal; wherein, when the phase difference is greater than or equal to a first threshold, the working indication signal generates a pulse, and the pulse width indicates the magnitude of the phase difference; when the phase difference is less than the first threshold, the level state of the working indication signal remains unchanged. The conversion module is configured to receive the working indication signal, convert the pulse width of the working indication signal, and output the initial value of the coarse adjustment control code; The detection module includes: A pulse generation module is configured to receive the reference clock signal and the feedback clock signal, and output a phase pulse signal; wherein the phase pulse signal contains a single pulse, and the pulse width indicates the phase difference between the reference clock signal and the feedback clock signal; The control module is configured to receive the phase pulse signal, the reference clock signal, and the feedback clock signal; when the phase difference between the reference clock signal and the feedback clock signal is greater than or equal to the first threshold, perform transmission processing on the phase pulse signal and output the working indication signal; when the phase difference is less than the first threshold, perform shielding processing on the phase pulse signal so that the level state of the working indication signal remains unchanged. The control module includes: The comparison module is configured to receive the reference clock signal and the feedback clock signal, and output a comparison signal based on the phase difference between the reference clock signal and the feedback clock signal; wherein, if the phase difference is greater than or equal to the first threshold, the comparison signal is in a first state; if the phase difference is less than the first threshold, the comparison signal is in a second state. The comparison module includes two delay modules, two level comparators, and an arithmetic unit; wherein, The first delay module is configured to receive the reference clock signal, perform delay processing on the reference clock signal, and output a reference delay signal, wherein the delay between the reference clock signal and the reference delay signal is the first threshold. The second delay module is configured to receive the feedback clock signal, perform delay processing on the feedback clock signal, and output a feedback delay signal, wherein the delay between the feedback clock signal and the feedback delay signal is the first threshold. The first level comparator is configured to receive the reference clock signal and the feedback delay signal, compare the rising edge of the reference clock signal and the rising edge of the feedback delay signal, and output a first result signal; wherein, if the reference clock signal leads the feedback delay signal, the first result signal is in a third state; if the reference clock signal lags the feedback delay signal, the first result signal is in a fourth state. The second level comparator is configured to receive the feedback clock signal and the reference delay signal, compare the rising edge of the reference delay signal and the rising edge of the feedback clock signal, and output a second result signal; wherein, if the feedback clock signal leads the reference delay signal, the second result signal is in a third state; if the feedback clock signal lags the reference delay signal, the second result signal is in a fourth state. The arithmetic unit is configured to receive the first result signal and the second result signal, perform logical operations on the first result signal and the second result signal, and output the comparison signal.

2. The delay phase-locked loop according to claim 1, characterized in that, The control module includes: The logic module is configured to receive the comparison signal and the phase pulse signal, perform logical operations on the comparison signal and the phase pulse signal, and output the working indication signal.

3. The delay phase-locked loop according to claim 2, characterized in that, The first state is a high-level state, and the second state is a low-level state; The logic module includes a first AND gate, the first input of which receives the comparison signal, the second input of which receives the phase pulse signal, and the output of which outputs the working indication signal.

4. The delay phase-locked loop according to claim 1, characterized in that, The delay module includes a first NAND gate and a second NAND gate; wherein... The first input terminal of the first NAND gate forms the input terminal of the delay module, the first input terminal of the second NAND gate is connected to the output terminal of the first NAND gate, the second input terminals of the first NAND gate and the second input terminal of the second NAND gate both receive the first power signal, and the output terminal of the second NAND gate forms the output terminal of the delay module.

5. The delay phase-locked loop according to claim 1, characterized in that, The level comparator includes a comparison unit, a latch unit, and a first NOT gate; wherein... The comparison unit includes a first output terminal and a second output terminal, configured to receive a first input signal and a second input signal; when the first input signal is in a high-level state, the first input signal and the second input signal are compared in terms of level, and the first output terminal and the second output terminal are charged and discharged according to the comparison result, so as to compare the rising edge of the first input signal and the rising edge of the second input signal; The latch unit includes a first input terminal, a second input terminal, and an output terminal. The first input terminal of the latch unit is connected to the first output terminal of the comparison unit, the second input terminal of the latch unit is connected to the second output terminal of the comparison unit, and the output terminal of the comparison unit is connected to the input terminal of the first NOT gate. Specifically, for the first level comparator, the first input signal is the reference clock signal, the second input signal is the feedback delay signal, and the output of the first NOT gate is used to output the first result signal; for the second level comparator, the first input signal is the feedback clock signal, the second input signal is the reference delay signal, and the output of the first NOT gate is used to output the second result signal.

6. The delay phase-locked loop according to claim 5, characterized in that, The comparison unit includes a cross-coupling component, a pre-charge component, an input component, a control component, and an equalization component; wherein, The cross-coupling assembly includes a first switch, a second switch, a third switch, and a fourth switch; the control terminal of the first switch, the control terminal of the second switch, the second terminal of the third switch, and the first terminal of the fourth switch are connected to the first output terminal; the control terminal of the third switch, the control terminal of the fourth switch, the second terminal of the first switch, and the first terminal of the second switch are connected to the second output terminal; the first terminal of the first switch receives a second power signal, and the first terminal of the third switch receives a third power signal. The precharge component includes a fifth switch, a sixth switch, and a seventh switch; the control terminals of the fifth switch, the sixth switch, and the seventh switch all receive the first input signal; the first terminal of the fifth switch receives a fourth power signal; the first terminal of the sixth switch receives a fifth power signal; the second terminals of the fifth switch and the first terminals of the seventh switch are connected to the first output terminal; and the second terminals of the sixth switch and the second terminals of the seventh switch are connected to the second output terminal. The input component includes an eighth switch and a ninth switch. The control terminal of the eighth switch receives the first input signal, and the control terminal of the ninth switch receives the second input signal. The first terminal of the eighth switch is connected to the second terminal of the second switch, and the first terminal of the ninth switch is connected to the second terminal of the fourth switch. The control component includes a tenth switch, the control terminal of which receives the first input signal, the first terminal of which is connected to the second terminal of the eighth switch and the second terminal of the ninth switch, and the second terminal of which is connected to ground. The equalization component includes an eleventh switch, the control terminal of which receives the first input signal, the first terminal of which is connected to the second terminal of the fourth switch, and the second terminal of which is connected to the second terminal of the second switch.

7. The delay phase-locked loop according to claim 6, characterized in that, The first, third, fifth, sixth, seventh, and eleventh switching transistors are all P-type field-effect transistors, while the second, fourth, eighth, ninth, and tenth switching transistors are all N-type field-effect transistors.

8. The delay phase-locked loop according to claim 5, characterized in that, The latch unit includes a third NAND gate and a fourth NAND gate; wherein... The first input terminal of the third NAND gate constitutes the first input terminal of the latch unit, the second input terminal of the third NAND gate is connected to the output terminal of the fourth NAND gate, and the third input terminal of the third NAND gate receives a reset signal; the first input terminal of the fourth NAND gate constitutes the second input terminal of the latch unit, and the second input terminal of the fourth NAND gate is connected to the output terminal of the third NAND gate.

9. The delay phase-locked loop according to claim 1, characterized in that, The third state is a high-level state, and the fourth state is a low-level state; The arithmetic unit includes a second AND gate and a second NOT gate. The first input terminal of the second AND gate receives the first result signal, the second input terminal of the second AND gate receives the second result signal, the output terminal of the second AND gate is connected to the input terminal of the second NOT gate, and the second NOT gate is used to output the comparison signal.

10. The delay phase-locked loop according to claim 1, characterized in that, The pulse generation module includes a first flip-flop, a second flip-flop, a third flip-flop, a fourth flip-flop, a fifth flip-flop, a sixth flip-flop, and a third AND gate; wherein, The clock terminals of the first flip-flop, the second flip-flop, and the third flip-flop all receive the feedback clock signal; the input terminal of the first flip-flop receives the phase-locked loop open signal; the positive output terminal of the first flip-flop is connected to the input terminal of the second flip-flop; the positive output terminal of the second flip-flop is connected to the input terminal of the third flip-flop; and the positive output terminal of the third flip-flop is connected to the first input terminal of the third AND gate. The clock terminals of the fourth, fifth, and sixth flip-flops all receive the reference clock signal; the input terminal of the fourth flip-flop is connected to the inverted output terminal of the first flip-flop, the non-inverted output terminal of the fourth flip-flop is connected to the input terminal of the fifth flip-flop, the non-inverted output terminal of the fifth flip-flop is connected to the input terminal of the sixth flip-flop; the non-inverted output terminal of the sixth flip-flop is connected to the second input terminal of the third AND gate. The output of the third AND gate outputs the phase pulse signal.

11. The delay phase-locked loop according to any one of claims 1-10, characterized in that, The first delay line includes a coarse adjustment delay line; wherein, The first delay line is further configured to adjust the working state of the coarse adjustment delay line through the coarse adjustment control code, so as to adjust the delay parameters; The coarse adjustment delay line includes n+1 cascaded first delay units, the delay of which is the first threshold; the coarse adjustment control code includes n+1 sub-signals, the i-th first delay unit receives the i-th sub-signal of the coarse adjustment control code, and n is a natural number.

12. The delay phase-locked loop according to claim 11, characterized in that, The conversion module includes n+1 cascaded second delay units and n+1 seventh flip-flops; wherein... The input terminal of the first second delay unit receives the working indication signal, and the output terminal of the i-th second delay unit is connected to the input terminal of the (i+1)-th second delay unit; the input terminal of the i-th seventh flip-flop is connected to the output terminal of the i-th second delay unit, the clock terminal of the i-th seventh flip-flop receives the inverted signal of the working indication signal, and the positive output terminal of the i-th seventh flip-flop outputs the i-th sub-signal of the coarse adjustment control code; The delay of the second delay unit is the first threshold.

13. The delay phase-locked loop according to claim 12, characterized in that, The delay-locked loop further includes a clock processing module and multiple second delay lines. The clock processing module is connected to both the first delay line and the multiple second delay lines. The first delay line and the second delay lines have identical structures, and the delay parameters of the second delay lines are controlled by the coarse adjustment control code. The clock processing module is configured to receive an initial clock signal and, based on the initial clock signal, output multiple phase clock signals; wherein the reference clock signal is one of the phase clock signals. The second delay line is configured to receive one of the phase clock signals, perform delayed transmission and adjustment processing on the received phase clock signal, and output a target clock signal; wherein the target clock signal is used for data sampling processing after transmission.

14. A memory, characterized in that, The memory includes a delay phase-locked loop as described in any one of claims 1-13.

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