Training circuit and training method suitable for receiving decision feedback equalization

Abstract

This invention provides a training circuit and method suitable for receiving decision feedback equalization. Different reference voltage training schemes can be selected based on different I / O operating speeds to perform received data equalization. For lower I / O operating speeds, training can be performed only on the first voltage to determine the most suitable reference voltage value, thus completing the reference voltage training quickly. As the I / O operating speed increases, two-dimensional training can be performed on the first and second voltages to determine their optimal values. A suitable voltage for the first voltage can be determined first, and the second voltage can be tested based on this suitable voltage, thereby narrowing the testing range and improving the efficiency of two-dimensional training. For very high speeds, a two-dimensional training module can be activated, allowing both the first and second voltages to be tested from 0 to obtain the most suitable voltage value, ensuring the correctness of high-speed data read / write operations.

Description

Technical Field

[0001] This invention relates to the field of signal equalization technology, and in particular to a training circuit and training method suitable for receiver decision feedback equalization. Background Technology

[0002] For high-speed devices such as DRAM, FLASH, HBM, PCIe, and D2D, these devices operate at high speeds and low voltages. Therefore, when receiving data, it is crucial to ensure that the input / output (I / O) circuits can receive data correctly and quickly, requiring special consideration for I / O circuit design. To achieve this, a robust training circuit is needed to ensure that the I / O circuits can quickly find a suitable operating reference voltage for their corresponding operating speed, thereby guaranteeing the normal operation of the equalizer in the receiving circuit and ensuring stable and reliable I / O performance. However, current digital equalization circuits are relatively complex and do not readily provide the optimal reference operating voltage required by the equalizer. Summary of the Invention

[0003] This invention provides a training circuit and training method suitable for receiving decision feedback equalization, in order to solve the problem of low efficiency in determining the reference operating voltage required for the most suitable equalizer in the prior art.

[0004] This invention provides a training circuit suitable for receiving decision feedback equalization, comprising:

[0005] The system comprises a training controller, a first receiver comparator, a first receiver buffer, a second receiver comparator, a second receiver buffer, a receiver equalization selection circuit, and a two-dimensional training module.

[0006] The training controller is used to control the first receiving comparator to acquire eye diagrams of the decoded data of the memory device's returned data at various test voltage values ​​of the first voltage. When the IO running speed is greater than a preset speed threshold, based on the eye diagrams acquired by the first receiving comparator at various test voltage values, the two-dimensional training module is controlled to test different combinations of voltage values ​​until the output data of the receiving equalization selection circuit meets preset conditions, and the current voltage value combination is determined as a reference voltage value combination. The voltage value combination includes test voltage values ​​of the first voltage and the second voltage. The first receiving comparator and the first receiving buffer are used to decode and store the decoded data of the memory device based on the test voltage value of the first voltage. The second receiving comparator and the second receiving buffer are used to decode and store the decoded data of the memory device based on the test voltage value of the second voltage. The receiving equalization selection circuit is used to select output data from the decoded data of the first receiving buffer and the second receiving buffer.

[0007] According to a training circuit for receiving decision feedback equalization provided by the present invention, when the IO running speed is less than a preset speed threshold, the training controller is further configured to determine the test voltage value corresponding to the maximum eye width in each eye diagram as the reference voltage value of the first voltage based on the eye diagram obtained by the first receiving comparator at each test voltage value of the first voltage.

[0008] According to a training circuit for receiver decision feedback equalization provided by the present invention, when the IO running speed is greater than a preset speed threshold, based on the eye diagram obtained by the first receiver comparator at various test voltage values, the two-dimensional training module is controlled to test different combinations of voltage values ​​until the output data of the receiver equalization selection circuit meets preset conditions, and the current voltage value combination is determined as a reference voltage value combination. Specifically, this includes:

[0009] Based on the eye diagrams obtained by the first receiving comparator at various test voltage values ​​of the first voltage, the maximum eye width in each eye diagram is determined.

[0010] If the maximum eye width in each eye diagram does not meet the preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions:

[0011] V1∈[0,Vref1], V2∈[0,Vref2]

[0012] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, Vref1 is the maximum voltage value of the first voltage, and Vref2 is the maximum voltage value of the second voltage;

[0013] The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

[0014] According to a training circuit for receiving decision feedback equalization provided by the present invention, after determining the maximum eye width in each eye diagram based on the eye diagrams obtained by the first receiving comparator at each test voltage value, the training controller is further configured to:

[0015] If the maximum eye width in each eye diagram meets a preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions:

[0016] V1 = V1', V2 ∈ [V1', Vref2]

[0017] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, V1' is the test voltage value corresponding to the maximum eye width in each eye diagram, and Vref2 is the maximum voltage value of the second voltage;

[0018] The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

[0019] According to the present invention, a training circuit suitable for receiving decision feedback equalization is provided, wherein the receiving equalization selection circuit is specifically used for:

[0020] Determine the higher test voltage value in the current voltage value combination;

[0021] If the test voltage value of the first voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the first receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the second receiving buffer.

[0022] If the test voltage value of the second voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the second receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the first receiving buffer.

[0023] The present invention also provides a training method for the training circuit as described in any of the above embodiments, comprising:

[0024] The eye diagram of the decoded data of the memory device's return data is obtained by the first receiving comparator controlled by the training controller at various test voltage values ​​of the first voltage.

[0025] When the IO running speed is greater than the preset speed threshold, the training controller is used to control the two-dimensional training module to test different voltage value combinations based on the eye diagram obtained by the first receiving comparator at each test voltage value, until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

[0026] The voltage value combination includes the test voltage value of the first voltage and the test voltage value of the second voltage. The output data of the receive equalization selection circuit is selected from the decoded data of the first receive buffer and the second receive buffer. The decoded data of the first receive buffer is stored after the first receive comparator decodes the return data of the memory device according to the test voltage value of the first voltage. The decoded data of the second receive buffer is stored after the second receive comparator decodes the return data of the memory device according to the test voltage value of the second voltage.

[0027] The training method provided by the present invention further includes:

[0028] When the IO running speed is less than a preset speed threshold, the training controller uses the eye diagrams obtained by the first receiving comparator at each test voltage value of the first voltage to determine the test voltage value corresponding to the maximum eye width in each eye diagram as the reference voltage value of the first voltage.

[0029] According to a training method provided by the present invention, when the IO running speed is greater than a preset speed threshold, the training controller, based on the eye diagram obtained by the first receiving comparator at various test voltage values, controls a two-dimensional training module to test different combinations of voltage values ​​until the output data of the receiving equalization selection circuit meets preset conditions, and determines the current voltage value combination as a reference voltage value combination. Specifically, this includes:

[0030] Based on the eye diagrams obtained by the first receiving comparator at various test voltage values ​​of the first voltage, the maximum eye width in each eye diagram is determined.

[0031] If the maximum eye width in each eye diagram does not meet the preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions:

[0032] V1∈[0,Vref1], V2∈[0,Vref2]

[0033] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, Vref1 is the maximum voltage value of the first voltage, and Vref2 is the maximum voltage value of the second voltage;

[0034] The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

[0035] According to a training method provided by the present invention, after determining the maximum eye width in each eye diagram obtained by the first receiving comparator at each test voltage value of the first voltage, the method further includes:

[0036] If the maximum eye width in each eye diagram meets a preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions:

[0037] V1 = V1', V2 ∈ [V1', Vref2]

[0038] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, V1' is the test voltage value corresponding to the maximum eye width in each eye diagram, and Vref2 is the maximum voltage value of the second voltage;

[0039] The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

[0040] According to a training method provided by the present invention, the output data of the receiving equalization selection circuit is determined based on the following steps:

[0041] Determine the higher test voltage value in the current voltage value combination;

[0042] If the test voltage value of the first voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the first receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the second receiving buffer.

[0043] If the test voltage value of the second voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the second receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the first receiving buffer.

[0044] The training circuit and method provided by this invention, applicable to receive decision feedback equalization, can select different reference voltage training schemes for receive data equalization based on different IO operating speeds. For IO operating speeds that are not too high, training can be performed only on the first voltage to determine the most suitable reference voltage value, thus completing the reference voltage training relatively quickly. As the IO operating speed increases, a two-dimensional training module can be used to perform two-dimensional training on the first and second voltages to determine their optimal values. During two-dimensional training, it is not necessary to start testing both the first and second voltages from 0 voltage; instead, a suitable voltage for the first voltage can be determined first, and the second voltage can be tested based on this suitable voltage, thereby narrowing the testing range and improving the efficiency of two-dimensional training. For very high speeds, a one-dimensional scan of the first voltage may not find a suitable value; in this case, the two-dimensional training module can be activated, allowing both the first and second voltages to be tested from 0 to obtain the most suitable voltage value, ensuring the correctness of high-speed data read and write. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the structure of a training circuit suitable for receiving decision feedback equalization provided by the present invention;

[0047] Figure 2 This is a schematic diagram illustrating the data balancing processing effect provided by the present invention;

[0048] Figure 3 This is a flowchart illustrating the training method provided by the present invention. Detailed Implementation

[0049] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0050] Figure 1 This is a schematic diagram of the structure of a training circuit suitable for receiving decision feedback equalization provided by the present invention, as shown below. Figure 1 As shown, the circuit includes:

[0051] The system includes a training controller 110, a first receiver comparator 120, a first receiver buffer 130, a second receiver comparator 140, a second receiver buffer 150, a receiver equalization selection circuit 160, and a two-dimensional training module 170.

[0052] The training controller 110 controls the first receiving comparator 120 to acquire the eye diagram of the decoded data of the memory device's returned data under various test voltage values ​​of the first voltage. When the IO running speed is greater than a preset speed threshold, based on the eye diagrams acquired by the first receiving comparator 120 under various test voltage values, the two-dimensional training module 170 is controlled to test different combinations of voltage values ​​until the output data of the receiving equalization selection circuit 160 meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination. The voltage value combination includes the test voltage values ​​of the first voltage and the second voltage. The first receiving comparator 120 and the first receiving buffer 130 are used to decode and store the decoded data of the memory device based on the test voltage value of the first voltage. The second receiving comparator 140 and the second receiving buffer 150 are used to decode and store the decoded data of the memory device based on the test voltage value of the second voltage. The receiving equalization selection circuit 160 is used to select output data from the decoded data of the first receiving buffer 130 and the second receiving buffer 150.

[0053] Specifically, the training controller 110 controls the first receiving comparator 120 to sequentially perform read operations on the memory device based on various test voltage values ​​of the first voltage (from 0 to the maximum voltage value), decode the returned data read back from the data loop (DQ loop) to obtain decoded data, and perform an eye scan on the decoded data to obtain the eye diagram of the decoded data. It can be seen that for each test voltage value of the first voltage, the first receiving comparator 120 can perform an eye scan to obtain the eye diagram corresponding to each test voltage value. Specifically, for any given test voltage value, when the first receiving comparator 120 decodes the returned data read back from the data loop of the memory device based on that test voltage value, if the voltage value of the current bit is higher than the test voltage value, the decoded data for the current bit is high; if the voltage value of the current bit is lower than the test voltage value, the decoded data for the current bit is low.

[0054] The current I / O speed is determined. If the current I / O speed is greater than a preset speed threshold (e.g., 3200), it indicates that the read / write speed of the current storage device is high. In this case, the training controller 110 can control the two-dimensional training module 170 to sequentially test different voltage value combinations based on the eye diagram obtained by the first receiver comparator 120 at various test voltage values. The voltage value combination includes the test voltage values ​​of the first voltage and the second voltage. When the two-dimensional training module 170 tests different voltage value combinations to train and obtain the optimal voltage value combination as a reference voltage value combination, for the current voltage value combination...<V1,V2> The first receiving comparator 120 and the first receiving buffer 130 are respectively used to decode and store the returned data of the memory device (i.e., the data read back from the data loop after the memory device performs a read operation) based on the current test voltage value V1 of the first voltage. The second receiving comparator 140 and the second receiving buffer 150 are respectively used to decode and store the returned data of the memory device based on the current test voltage value V2 of the second voltage. The decoding operations of the first receiving comparator 120 and the second receiving comparator 140 are as described above and will not be repeated here. The receiving equalization selection circuit 160 is used to select output data from the decoded data of the first receiving buffer 130 and the second receiving buffer 150. The two-dimensional training module 170 sequentially tests different voltage value combinations according to the above method, obtaining the output data of the receiving equalization selection circuit 160 corresponding to each voltage value combination, until the output data of the receiving equalization selection circuit 160 corresponding to a certain voltage value combination meets a preset condition, and determines that voltage value combination as a reference voltage value combination. The preset condition can be that the output data is consistent with the original data (i.e., the data to be read from the memory device).

[0055] After obtaining the reference voltage value combination, received data equalization processing can be performed based on this reference voltage value combination. Specifically, for the return data read back from the read / write loop of the memory device, the first receive comparator 120 and the first receive buffer 130 can decode the return data based on the voltage value of the first voltage in the reference voltage value combination and store the decoded data. The second receive comparator 140 and the second receive buffer 150 can decode the return data based on the voltage value of the second voltage in the reference voltage value combination and store the decoded data. Then, the receive equalization selection circuit 160 selects output data from the decoded data of the first receive buffer 130 and the second receive buffer 150, thereby realizing received data equalization processing, maximizing the accuracy of data restoration, improving the accuracy of memory device I / O, and the data equalization processing effect is as follows: Figure 2 As shown.

[0056] In some embodiments, when the two-dimensional training module 170 tests different combinations of voltage values ​​to train and obtain the optimal combination of voltage values ​​as a reference combination, it can determine the maximum eye width in each eye diagram based on the eye diagrams obtained by the first receiving comparator 120 at each test voltage value of the first voltage. If the maximum eye width in each eye diagram does not meet a preset eye width condition (which can be determined according to the actual application scenario), then multiple voltage value combinations are determined. The ranges of the test voltage values ​​of the first voltage and the second voltage in the voltage value combinations satisfy the following conditions:

[0057] V1∈[0,Vref1], V2∈[0,Vref2]

[0058] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, Vref1 is the maximum voltage value of the first voltage, and Vref2 is the maximum voltage value of the second voltage.

[0059] If the maximum eye width in each eye diagram meets the preset eye width condition, then multiple voltage value combinations are determined. Among these combinations, the ranges of the test voltage values ​​of the first voltage and the second voltage satisfy the following conditions:

[0060] V1 = V1', V2 ∈ [V1', Vref2]

[0061] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, V1' is the test voltage value corresponding to the maximum eye width in each eye diagram, and Vref2 is the maximum voltage value of the second voltage.

[0062] Subsequently, the control two-dimensional training module 170 tests multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit 160 meets the preset conditions.

[0063] In other embodiments, when testing the current voltage value combination, the two-dimensional training module 170 receives the equalization selection circuit 160 specifically for:

[0064] The higher test voltage value in the current voltage value combination is determined. If the test voltage value of the first voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit 160 is high, the current output data is selected from the decoded data of the first receiving buffer 130; when the previous output data of the receiving equalization selection circuit 160 is low, the current output data is selected from the decoded data of the second receiving buffer 150. If the test voltage value of the second voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit 160 is high, the current output data is selected from the decoded data of the second receiving buffer 150; when the previous output data of the receiving equalization selection circuit 160 is low, the current output data is selected from the decoded data of the first receiving buffer 130.

[0065] In other embodiments, if the IO operation speed is less than a preset speed threshold, the training controller 110 is further configured to determine the test voltage value corresponding to the maximum eye width in each eye diagram obtained by the first receiving comparator 120 at each test voltage value of the first voltage as the reference voltage value of the first voltage. After obtaining the reference voltage value of the first voltage, receiving data equalization processing can be performed based on the reference voltage value. Specifically, for the return data read back from the read / write loop of the memory device, the first receiving comparator 120 and the first receiving buffer 130 can decode the return data based on the reference voltage value of the first voltage and store the decoded data. The receiving equalization selection circuit 160 can directly read the decoded data from the first receiving buffer 130 as output data, thereby realizing receiving data equalization processing, restoring the data to the greatest extent possible, and improving the accuracy of memory device IO.

[0066] In summary, the training circuit provided in this embodiment of the invention can select different reference voltage training schemes to achieve balanced received data based on different IO operating speeds. For IO operating speeds that are not too high, training can be performed only on the first voltage to determine the most suitable reference voltage value, thereby completing the reference voltage training relatively quickly. As the IO operating speed increases, a two-dimensional training module can be used to perform two-dimensional training on the first and second voltages to determine the optimal voltage values ​​for the first and second voltages. During two-dimensional training, it is not necessary to start testing both the first and second voltages from 0 voltage. Instead, a suitable voltage for the first voltage can be determined first, and the second voltage can be tested based on the suitable voltage of the first voltage, thereby narrowing the testing range and improving the efficiency of two-dimensional training. For very high speeds, a one-dimensional scan of the first voltage may not find a suitable voltage value. In this case, the two-dimensional training module can be activated so that both the first and second voltages start testing from 0 to obtain the most suitable voltage value, ensuring the correctness of high-speed data read and write.

[0067] The training method provided by the present invention is described below. The training method described below can be referred to in correspondence with the training circuit described above.

[0068] Based on any of the above embodiments Figure 3 This is a flowchart illustrating the training method provided by the present invention, as shown below. Figure 3 As shown, the method includes:

[0069] Step 310: Based on the training controller, control the first receiving comparator to obtain the eye diagram of the decoded data of the returned data of the memory device at each test voltage value of the first voltage;

[0070] Step 320: When the IO running speed is greater than the preset speed threshold, the training controller is used to control the two-dimensional training module to test different voltage value combinations based on the eye diagram obtained by the first receiving comparator at each test voltage value until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

[0071] The voltage value combination includes the test voltage value of the first voltage and the test voltage value of the second voltage. The output data of the receive equalization selection circuit is selected from the decoded data of the first receive buffer and the second receive buffer. The decoded data of the first receive buffer is stored after the first receive comparator decodes the return data of the memory device according to the test voltage value of the first voltage. The decoded data of the second receive buffer is stored after the second receive comparator decodes the return data of the memory device according to the test voltage value of the second voltage.

[0072] Based on any of the above embodiments, the method further includes:

[0073] When the IO running speed is less than a preset speed threshold, the training controller uses the eye diagrams obtained by the first receiving comparator at each test voltage value of the first voltage to determine the test voltage value corresponding to the maximum eye width in each eye diagram as the reference voltage value of the first voltage.

[0074] Based on any of the above embodiments, when the IO running speed is greater than a preset speed threshold, the training controller, based on the eye diagram obtained by the first receiving comparator at various test voltage values, controls the two-dimensional training module to test different voltage value combinations until the output data of the receiving equalization selection circuit meets the preset conditions, and determines the current voltage value combination as the reference voltage value combination, specifically includes:

[0075] Based on the eye diagrams obtained by the first receiving comparator at various test voltage values ​​of the first voltage, the maximum eye width in each eye diagram is determined.

[0076] If the maximum eye width in each eye diagram does not meet the preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions:

[0077] V1∈[0,Vref1], V2∈[0,Vref2]

[0078] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, Vref1 is the maximum voltage value of the first voltage, and Vref2 is the maximum voltage value of the second voltage;

[0079] The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

[0080] Based on any of the above embodiments, after determining the maximum eye width in each eye diagram obtained by the first receiving comparator at each test voltage value of the first voltage, the method further includes:

[0081] If the maximum eye width in each eye diagram meets a preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions:

[0082] V1 = V1', V2 ∈ [V1', Vref2]

[0083] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, V1' is the test voltage value corresponding to the maximum eye width in each eye diagram, and Vref2 is the maximum voltage value of the second voltage;

[0084] The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

[0085] Based on any of the above embodiments, the output data of the receiving equalization selection circuit is determined based on the following steps:

[0086] Determine the higher test voltage value in the current voltage value combination;

[0087] If the test voltage value of the first voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the first receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the second receiving buffer.

[0088] If the test voltage value of the second voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the second receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the first receiving buffer.

[0089] The training method provided in this invention can select different reference voltage training schemes to achieve balanced received data based on different IO operating speeds. For IO operating speeds that are not too high, training can be performed only on the first voltage to determine the most suitable reference voltage value, thereby completing the reference voltage training relatively quickly. As the IO operating speed increases, a two-dimensional training module can be used to perform two-dimensional training on the first and second voltages to determine the optimal voltage values ​​for the first and second voltages. During two-dimensional training, it is not necessary to start testing both the first and second voltages from 0 voltage. Instead, a suitable voltage for the first voltage can be determined first, and the second voltage can be tested based on the suitable voltage of the first voltage, thereby narrowing the testing range and improving the efficiency of two-dimensional training. For very high speeds, a one-dimensional scan of the first voltage may not find a suitable voltage value. In this case, the two-dimensional training module can be activated so that both the first and second voltages start testing from 0 to obtain the most suitable voltage value, ensuring the correctness of high-speed data read and write.

[0090] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0091] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A training circuit suitable for receiving decision feedback equalization, characterized in that, include: The system comprises a training controller, a first receiver comparator, a first receiver buffer, a second receiver comparator, a second receiver buffer, a receiver equalization selection circuit, and a two-dimensional training module. The training controller is used to control the first receiving comparator to acquire eye diagrams of the decoded data of the memory device's returned data at various test voltage values ​​of the first voltage. When the IO running speed is greater than a preset speed threshold, based on the eye diagrams acquired by the first receiving comparator at various test voltage values, the two-dimensional training module is controlled to test different combinations of voltage values ​​until the output data of the receiving equalization selection circuit meets preset conditions, and the current voltage value combination is determined as a reference voltage value combination. The voltage value combination includes test voltage values ​​of the first voltage and the second voltage. The first receiving comparator and the first receiving buffer are used to decode and store the decoded data of the memory device based on the test voltage value of the first voltage. The second receiving comparator and the second receiving buffer are used to decode and store the decoded data of the memory device based on the test voltage value of the second voltage. The receiving equalization selection circuit is used to select output data from the decoded data of the first receiving buffer and the second receiving buffer.

2. The training circuit suitable for receiving decision feedback equalization according to claim 1, characterized in that, When the IO running speed is less than a preset speed threshold, the training controller is further configured to determine the test voltage value corresponding to the maximum eye width in each eye diagram as the reference voltage value of the first voltage based on the eye diagram obtained by the first receiving comparator at each test voltage value of the first voltage.

3. The training circuit suitable for receiving decision feedback equalization according to claim 1, characterized in that, When the IO operating speed is greater than a preset speed threshold, based on the eye diagram obtained by the first receiving comparator at various test voltage values, the two-dimensional training module is controlled to test different combinations of voltage values ​​until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination. Specifically, this includes: Based on the eye diagrams obtained by the first receiving comparator at various test voltage values ​​of the first voltage, the maximum eye width in each eye diagram is determined. If the maximum eye width in each eye diagram does not meet the preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions: V1∈[0,Vref1], V2∈[0,Vref2] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, Vref1 is the maximum voltage value of the first voltage, and Vref2 is the maximum voltage value of the second voltage; The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

4. The training circuit suitable for receiving decision feedback equalization according to claim 3, characterized in that, After determining the maximum eye width in each eye diagram based on the eye diagrams obtained by the first receiving comparator at each test voltage value, the training controller is further configured to: If the maximum eye width in each eye diagram meets a preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions: V1 = V1', V2 ∈ [V1', Vref2] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, V1' is the test voltage value corresponding to the maximum eye width in each eye diagram, and Vref2 is the maximum voltage value of the second voltage; The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

5. The training circuit suitable for receiving decision feedback equalization according to claim 1, characterized in that, The receiving equalization selection circuit is specifically used for: Determine the higher test voltage value in the current voltage value combination; If the test voltage value of the first voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the first receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the second receiving buffer. If the test voltage value of the second voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the second receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the first receiving buffer.

6. A training method based on the training circuit as described in any one of claims 1 to 5, characterized in that, include: The eye diagram of the decoded data of the memory device's return data is obtained by the first receiving comparator controlled by the training controller at various test voltage values ​​of the first voltage. When the IO running speed is greater than the preset speed threshold, the training controller is used to control the two-dimensional training module to test different voltage value combinations based on the eye diagram obtained by the first receiving comparator at each test voltage value, until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination. The voltage value combination includes the test voltage value of the first voltage and the test voltage value of the second voltage. The output data of the receive equalization selection circuit is selected from the decoded data of the first receive buffer and the second receive buffer. The decoded data of the first receive buffer is stored after the first receive comparator decodes the return data of the memory device according to the test voltage value of the first voltage. The decoded data of the second receive buffer is stored after the second receive comparator decodes the return data of the memory device according to the test voltage value of the second voltage.

7. The training method according to claim 6, characterized in that, Also includes: When the IO running speed is less than a preset speed threshold, the training controller uses the eye diagrams obtained by the first receiving comparator at each test voltage value of the first voltage to determine the test voltage value corresponding to the maximum eye width in each eye diagram as the reference voltage value of the first voltage.

8. The training method according to claim 6, characterized in that, When the IO operating speed exceeds a preset speed threshold, the training controller, based on the eye diagrams obtained by the first receiving comparator at various test voltage values, controls the two-dimensional training module to test different combinations of voltage values ​​until the output data of the receiving equalization selection circuit meets preset conditions, and determines the current voltage value combination as the reference voltage value combination. Specifically, this includes: Based on the eye diagrams obtained by the first receiving comparator at various test voltage values ​​of the first voltage, the maximum eye width in each eye diagram is determined. If the maximum eye width in each eye diagram does not meet the preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions: V1∈[0,Vref1], V2∈[0,Vref2] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, Vref1 is the maximum voltage value of the first voltage, and Vref2 is the maximum voltage value of the second voltage; The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

9. The training method according to claim 8, characterized in that, After determining the maximum eye width in each eye diagram obtained by the first receiving comparator at various test voltage values ​​of the first voltage, the method further includes: If the maximum eye width in each eye diagram meets a preset eye width condition, then multiple voltage value combinations are determined; wherein, the ranges of the test voltage values ​​of the first voltage and the test voltage values ​​of the second voltage in the voltage value combinations satisfy the following conditions: V1 = V1', V2 ∈ [V1', Vref2] Wherein, V1 and V2 are the test voltage values ​​of the first voltage and the second voltage, respectively, V1' is the test voltage value corresponding to the maximum eye width in each eye diagram, and Vref2 is the maximum voltage value of the second voltage; The two-dimensional training module is controlled to test the multiple voltage value combinations sequentially until the output data of the receiving equalization selection circuit meets the preset conditions, and the current voltage value combination is determined as the reference voltage value combination.

10. The training method according to claim 6, characterized in that, The output data of the receiving equalization selection circuit is determined based on the following steps: Determine the higher test voltage value in the current voltage value combination; If the test voltage value of the first voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the first receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the second receiving buffer. If the test voltage value of the second voltage in the current voltage value combination is higher, then when the previous output data of the receiving equalization selection circuit is high, the current output data is selected from the decoded data of the second receiving buffer; when the previous output data of the receiving equalization selection circuit is low, the current output data is selected from the decoded data of the first receiving buffer.

Images