A method for manufacturing a soft-fast-recovery (FRD) diode chip

Abstract

The present application relates to the technical field of soft fast recovery diode chip, and particularly relates to a preparation method of soft fast recovery FRD diode chip, which comprises diffusion process and GPP process, characterized in that the diffusion process comprises the following steps: step one, pre-treatment before diffusion; step two, phosphorus diffusion treatment: the N surface of the silicon wafer after step one is subjected to diffusion treatment, first one diffusion is performed by using low-concentration phosphorus paper, and then two diffusion is performed by using normal-concentration phosphorus paper; step three, first sandblasting; step four, boron diffusion treatment; and step five, second sandblasting: after the diffusion process is completed, the chip made of the silicon wafer can obtain higher reverse breakdown voltage without significant increase in forward voltage, and by adopting double-base diffusion process, the impurity concentration of the new base N is higher than that of the original base N ‑ , the time for removing the carrier is prolonged when the reverse bias is applied, that is, the value of tb is increased, the value of softness factor S is increased to about 0.65, and the softness of the diode is effectively improved.

Description

Technical Field

[0001] This invention relates to the field of soft fast recovery diode chip technology, and in particular to a method for fabricating a soft fast recovery FRD diode chip. Background Technology

[0002] Modern power electronics technology widely uses switching devices such as IGBTs (Insulated Gate Bipolar Transistors) and power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which places higher demands on the fast recovery diodes (FRDs) used in conjunction with them. These FRDs not only require high reverse blocking voltage, low forward transient voltage drop, and short reverse recovery time, but also soft recovery characteristics (i.e., a large softness factor). Fast recovery diodes with these characteristics are called soft fast recovery diodes (SFRDs).

[0003] Currently, the parameters of domestically produced fast recovery diodes are: reverse breakdown voltage 1100V, reverse recovery time 500ns, and softness factor around 0.35, exhibiting very stiff characteristics. Internationally, fast recovery diodes have a reverse breakdown voltage of 1300V, a reverse recovery time of 300ns, and a softness factor of around 0.55. With the in-depth development of power electronics technology and the continuous advancement of various semiconductor device technologies, frequencies are constantly increasing, placing new demands on the corresponding fast recovery diodes, namely, smaller TRR and larger softness factors. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing technologies by proposing a method for fabricating a soft fast recovery FRD diode chip.

[0005] To achieve the above objectives, the present invention adopts the following technical solution:

[0006] A method for fabricating a soft fast recovery FRD diode chip includes a diffusion process and a GPP process, wherein the diffusion process includes the following steps:

[0007] Step 1, Pre-diffusion treatment: The silicon wafer raw material is first mechanically polished to obtain a polished substrate, and then the surface of the polished substrate is cleaned with a silicon wafer cleaning solution;

[0008] Step 2, Phosphorus diffusion treatment: The N-side of the silicon wafer after Step 1 is subjected to diffusion treatment. First, a low-concentration phosphorus paper is used for the first diffusion, and then a normal-concentration phosphorus paper is used for the second diffusion.

[0009] Step 3, First Sandblasting: The phosphorus-distilled silicon wafer is fed into the vacuum sandblasting chamber at a speed of 40-50 cm / min, with the P-side facing upwards, and blown at a speed of 0.9-1.0 kg / cm. 2 Sandblasting is performed under pressure;

[0010] Step 4, Boron diffusion treatment: Boron diffusion is performed on the P-side of the silicon wafer;

[0011] Step 5, Secondary Sandblasting: The boron-expanded silicon wafer is fed into the vacuum sandblasting chamber at a speed of 40-50 cm / min, and blew on both sides at a rate of 0.9-1.0 kg / cm². 2 The pressure is used for sandblasting to complete the diffusion process.

[0012] Preferably, in step one, a silicon wafer with a resistivity of 45-50 Ω·cm and a thickness T = 250 ± 5 μm is selected.

[0013] Preferably, in step one, the silicon wafer cleaning solution comprises the following components in parts by weight: 80-100 parts deionized water, 5-8 parts nano-abrasive, 1-3 parts amphoteric surfactant, and 4-6 parts organic amine; the nano-abrasive is amino-terminated polyether-coated nano-alumina with a particle size of 20-40 nm, and the mass ratio of nano-alumina to amino-terminated polyether is (3-8):1; the amphoteric surfactant is one or more of alkylaminopropionate, alkyl dimethyl betaine, alkyl hydroxysulfonyl betaine, and alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethylammonium hydroxide, tetraethylammonium hydroxide, tetrapropylammonium hydroxide, tetrabutylammonium hydroxide, trimethylbenzylammonium hydroxide, trimethylhydroxyethylammonium hydroxide, dimethyl dihydroxyethylammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine, and diethanolamine.

[0014] Preferably, in step two, a phosphorus preheating treatment is performed before the primary diffusion treatment. The silicon wafer is placed flat on a quartz boat with the N side facing up. Then, low-concentration phosphorus paper is attached to the N side of the silicon wafer, and it is sealed with a baffle and put into a low-temperature furnace for preheating to 280-300°C.

[0015] Preferably, in step two, a low-concentration phosphorus paper is first used for primary diffusion at a temperature of 1180-1220℃ for 6-10 hours, resulting in a final diffusion depth of 80μm; then, a normal-concentration phosphorus paper is used for secondary diffusion at a temperature of 1230-1280℃ for 2-4 hours, resulting in a final diffusion depth of 50μm.

[0016] Preferably, in step two, after the first diffusion is completed, during the cooling process of the diffusion furnace, the normal concentration phosphorus paper is preheated to 250-300°C, the diffusion furnace is cooled to 250-300°C, the normal concentration phosphorus paper is heated to 250-300°C, the normal concentration phosphorus paper is loaded, and it is sealed with baffles into the diffusion furnace for a second diffusion process.

[0017] Preferably, in step four, during the boron expansion process, boron impurities are first coated onto the P-side of the silicon wafer. The coated silicon wafer is then placed on a hot plate to dry. Next, the boron-sides of the silicon wafers are placed face to face, and the two wafers are stacked together. After stacking, the silicon wafers are placed vertically on a quartz boat and sealed with baffles. The wafers are then placed in a boron expansion furnace for boron expansion treatment. The boron expansion treatment temperature is 950-1050℃, and the time is 1-3 hours.

[0018] Preferably, in steps three and five, after sandblasting is completed, the silicon wafer is cleaned.

[0019] The beneficial effects of this invention are:

[0020] 1. By selecting silicon wafers with a resistivity of 45-50 Ω·cm and a thickness T = 250 ± 5 μm, compared with traditional FRD chips, chips made from these silicon wafers can achieve higher reverse breakdown voltages without a significant increase in forward voltage. Through the use of a double-base diffusion process, the newly added base region N is larger than the original base region N. - The high impurity concentration of the diode increases the time it takes to remove carriers when a reverse bias voltage is applied, resulting in a larger tb value. This increases the softness factor S value to about 0.65, effectively improving the softness of the diode.

[0021] 2. The diffusion process uses a double-base diffusion process. When a reverse bias voltage is applied, the reverse recovery time Trr also increases significantly. In order to reduce the reverse recovery time to a reasonable range and improve the operating frequency of the device, the platinum diffusion temperature is increased from 880℃ to about 920℃, so that the reverse recovery time of the diode is controlled below 250ns. The platinum diffusion temperature is increased and the Trr level is reduced. Passivation protection is performed according to the traditional GPP process.

[0022] 3. During the diffusion process, after the diffusion furnace cools down after the first diffusion, the normal concentration phosphorus paper is preheated, which can effectively save operation time, save energy and improve processing efficiency.

[0023] 4. During the diffusion process, the surface of the polishing substrate is cleaned with a silicon wafer cleaning solution. The cleaning solution contains a small amount of nano-abrasives, which are amino-terminated polyether-coated nano-alumina. This further improves the polishing effect, and the nano-abrasives have elastic encapsulation, which can prevent scratches from being generated on the silicon wafer. Attached Figure Description

[0024] Figure 1This is a schematic diagram of the double-base diffusion structure of a soft fast recovery FRD diode chip proposed in this invention;

[0025] Figure 2 The diagram shows the current and voltage waveforms during the reverse recovery process of a soft fast recovery FRD diode chip proposed in this invention.

[0026] In the picture:

[0027] 1. Single-base region diffuser; 110. Original N + District; 111, former N - District; 112, original P + 2. Double-base diffusion sheet; 220, N + Zones; 221, N; 222, N - District; 223, P + district. Detailed Implementation

[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0029] In Example 1, a method for fabricating a soft fast recovery FRD diode chip includes a diffusion process and a GPP process. The diffusion process includes the following steps:

[0030] Step 1, Pre-diffusion treatment: The silicon wafer raw material is first mechanically polished to obtain a polished substrate, and then the surface of the polished substrate is cleaned with a silicon wafer cleaning solution;

[0031] Step 2, Phosphorus diffusion treatment: The N-side of the silicon wafer after Step 1 is subjected to diffusion treatment. First, a low-concentration phosphorus paper is used for the first diffusion, and then a normal-concentration phosphorus paper is used for the second diffusion.

[0032] Step 3, First Sandblasting: The phosphorus-distilled silicon wafer is fed into the vacuum sandblasting chamber at a speed of 40 cm / min, with the P-side facing upwards, and blown at a speed of 0.9 kg / cm. 2 Sandblasting is performed under pressure;

[0033] Step 4, Boron diffusion treatment: Boron diffusion is performed on the P-side of the silicon wafer;

[0034] Step 5, Secondary Sandblasting: The boron-expanded silicon wafer is fed into the vacuum sandblasting chamber at a transmission speed of 40 cm / min, and blown on both sides at a speed of 0.9 kg / cm². 2 The pressure is used for sandblasting to complete the diffusion process.

[0035] In step one, a silicon wafer with a resistivity of 45 Ω·cm and a thickness of T = 245 μm is selected.

[0036] In step one, the silicon wafer cleaning solution comprises the following components by weight: 80 parts deionized water, 5 parts nano-abrasive, 1 part amphoteric surfactant, and 4 parts organic amine; the nano-abrasive is alumina nanoparticles coated with amino-terminated polyether, the particle size of the alumina nanoparticles is 20-40 nm, and the mass ratio of alumina nanoparticles to amino-terminated polyether is 3:1; the amphoteric surfactant is one or more of alkylaminopropionate, alkyl dimethyl betaine, alkyl hydroxysulfonyl betaine, and alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethylammonium hydroxide, tetraethylammonium hydroxide, tetrapropylammonium hydroxide, tetrabutylammonium hydroxide, trimethylbenzylammonium hydroxide, trimethylhydroxyethylammonium hydroxide, dimethyl dihydroxyethylammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine, and diethanolamine.

[0037] In step two, a phosphorus preheating treatment is performed before the primary diffusion treatment. The silicon wafer is placed flat on a quartz boat with the N side facing up. Then, low-concentration phosphorus paper is attached to the N side of the silicon wafer, and it is sealed with a baffle and put into a low-temperature furnace for preheating to 280°C.

[0038] In step two, a first diffusion is performed using low-concentration phosphorus paper at a temperature of 1180℃ for 6 hours, resulting in a final diffusion depth of 75μm. Then, a second diffusion is performed using normal-concentration phosphorus paper at a temperature of 1230℃ for 2 hours, resulting in a final diffusion depth of 45μm.

[0039] In step two, after the first diffusion is completed, during the cooling process of the diffusion furnace, the normal concentration phosphorus paper is preheated, the diffusion furnace is cooled to 250°C, the normal concentration phosphorus paper is heated to 250°C, the normal concentration phosphorus paper is loaded, and it is sealed with baffles before entering the diffusion furnace for a second diffusion process.

[0040] In step four, during the boron expansion process, boron impurities are first coated onto the P-side of the silicon wafer. The coated silicon wafer is then placed on a hot plate to dry. Next, the boron-sides of the silicon wafers are placed face to face, and the two wafers are stacked together. After stacking, the silicon wafers are placed vertically on a quartz boat and sealed with baffles. The wafers are then placed in a boron expansion furnace for boron expansion treatment at a temperature of 950°C for 1 hour.

[0041] In steps three and five, after sandblasting is completed, the silicon wafer is cleaned.

[0042] In Example 2, a method for fabricating a soft fast recovery FRD diode chip includes a diffusion process and a GPP process. The diffusion process includes the following steps:

[0043] Step 1, Pre-diffusion treatment: The silicon wafer raw material is first mechanically polished to obtain a polished substrate, and then the surface of the polished substrate is cleaned with a silicon wafer cleaning solution;

[0044] Step 2, Phosphorus diffusion treatment: The N-side of the silicon wafer after Step 1 is subjected to diffusion treatment. First, a low-concentration phosphorus paper is used for the first diffusion, and then a normal-concentration phosphorus paper is used for the second diffusion.

[0045] Step 3, First Sandblasting: The phosphorus-distilled silicon wafer is fed into the vacuum sandblasting chamber at a speed of 50 cm / min, with the P-side facing upwards, and blown at a speed of 1.0 kg / cm. 2 Sandblasting is performed under pressure;

[0046] Step 4, Boron diffusion treatment: Boron diffusion is performed on the P-side of the silicon wafer;

[0047] Step 5, Secondary Sandblasting: The boron-expanded silicon wafer is fed into the vacuum sandblasting chamber at a transmission speed of 50 cm / min, and blown on both sides at a speed of 1.0 kg / cm². 2 The pressure is used for sandblasting to complete the diffusion process.

[0048] In step one, a silicon wafer with a resistivity of 50 Ω·cm and a thickness of T = 255 μm is selected.

[0049] In step one, the silicon wafer cleaning solution comprises the following components by weight: 100 parts deionized water, 8 parts nano-abrasive, 3 parts amphoteric surfactant, and 6 parts organic amine; the nano-abrasive is alumina nanoparticles coated with amino-terminated polyether, the particle size of the alumina nanoparticles is 20-40 nm, and the mass ratio of alumina nanoparticles to amino-terminated polyether is 8:1; the amphoteric surfactant is one or more of alkylaminopropionate, alkyl dimethyl betaine, alkyl hydroxysulfonyl betaine, and alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethylammonium hydroxide, tetraethylammonium hydroxide, tetrapropylammonium hydroxide, tetrabutylammonium hydroxide, trimethylbenzylammonium hydroxide, trimethylhydroxyethylammonium hydroxide, dimethyl dihydroxyethylammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine, and diethanolamine.

[0050] In step two, a phosphorus preheating treatment is performed before the primary diffusion treatment. The silicon wafer is placed flat on a quartz boat with the N side facing up. Then, low-concentration phosphorus paper is attached to the N side of the silicon wafer, and it is sealed with a baffle and put into a low-temperature furnace for preheating to 300°C.

[0051] In step two, a first diffusion is performed using low-concentration phosphorus paper at a temperature of 1220℃ for 10 hours, resulting in a final diffusion depth of 85μm. Then, a second diffusion is performed using normal-concentration phosphorus paper at a temperature of 1280℃ for 4 hours, resulting in a final diffusion depth of 55μm.

[0052] In step two, after the first diffusion is completed, during the cooling process of the diffusion furnace, the normal concentration phosphorus paper is preheated, the diffusion furnace is cooled to 300°C, the normal concentration phosphorus paper is heated to 300°C, the normal concentration phosphorus paper is loaded, and it is sealed with baffles before entering the diffusion furnace for a second diffusion process.

[0053] In step four, during the boron expansion process, boron impurities are first coated onto the P-side of the silicon wafer. The coated silicon wafer is then placed on a hot plate to dry. Next, the boron-sides of the silicon wafers are placed face to face, and two wafers are stacked together. After stacking, the silicon wafers are placed vertically on a quartz boat and sealed with baffles. The wafers are then placed in a boron expansion furnace for boron expansion treatment at a temperature of 1050°C for 3 hours.

[0054] In steps three and five, after sandblasting is completed, the silicon wafer is cleaned.

[0055] In Example 3, a method for fabricating a soft fast recovery FRD diode chip includes a diffusion process and a GPP process. The diffusion process includes the following steps:

[0056] Step 1, Pre-diffusion treatment: The silicon wafer raw material is first mechanically polished to obtain a polished substrate, and then the surface of the polished substrate is cleaned with a silicon wafer cleaning solution;

[0057] Step 2, Phosphorus diffusion treatment: The N-side of the silicon wafer after Step 1 is subjected to diffusion treatment. First, a low-concentration phosphorus paper is used for the first diffusion, and then a normal-concentration phosphorus paper is used for the second diffusion.

[0058] Step 3, First Sandblasting: The phosphorus-distilled silicon wafer is fed into the vacuum sandblasting chamber at a speed of 45 cm / min, with the P-side facing upwards, and blown at a speed of 0.9 kg / cm. 2 Sandblasting is performed under pressure;

[0059] Step 4, Boron diffusion treatment: Boron diffusion is performed on the P-side of the silicon wafer;

[0060] Step 5, Secondary Sandblasting: The boron-expanded silicon wafer is fed into the vacuum sandblasting chamber at a speed of 45 cm / min, with the P-side facing upwards, and blown at a speed of 0.9 kg / cm. 2 The pressure is used for sandblasting to complete the diffusion process.

[0061] In step one, a silicon wafer with a resistivity of 48 Ω·cm and a thickness of T = 250 μm is selected.

[0062] In step one, the silicon wafer cleaning solution comprises the following components by weight: 90 parts deionized water, 7 parts nano-abrasive, 2 parts amphoteric surfactant, and 5 parts organic amine; the nano-abrasive is alumina nanoparticles coated with amino-terminated polyether, the particle size of the alumina nanoparticles is 20-40 nm, and the mass ratio of alumina nanoparticles to amino-terminated polyether is 5:1; the amphoteric surfactant is one or more of alkylaminopropionate, alkyl dimethyl betaine, alkyl hydroxysulfonyl betaine, and alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethylammonium hydroxide, tetraethylammonium hydroxide, tetrapropylammonium hydroxide, tetrabutylammonium hydroxide, trimethylbenzylammonium hydroxide, trimethylhydroxyethylammonium hydroxide, dimethyl dihydroxyethylammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine, and diethanolamine.

[0063] In step two, a phosphorus preheating treatment is performed before the primary diffusion treatment. The silicon wafer is placed flat on a quartz boat with the N side facing up. Then, low-concentration phosphorus paper is attached to the N side of the silicon wafer, and it is sealed with a baffle and put into a low-temperature furnace for preheating to 290°C.

[0064] In step two, a first diffusion is performed using low-concentration phosphorus paper at a temperature of 1200℃ for 8 hours, resulting in a final diffusion depth of 80μm. Then, a second diffusion is performed using normal-concentration phosphorus paper at a temperature of 12350℃ for 3 hours, resulting in a final diffusion depth of 50μm.

[0065] In step two, after the first diffusion is completed, during the cooling process of the diffusion furnace, the normal concentration phosphorus paper is preheated, the diffusion furnace is cooled to 270°C, the normal concentration phosphorus paper is heated to 270°C, the normal concentration phosphorus paper is loaded, and it is sealed with baffles before entering the diffusion furnace for a second diffusion process.

[0066] In step four, during the boron expansion process, boron impurities are first coated onto the P-side of the silicon wafer. The coated silicon wafer is then placed on a hot plate to dry. Next, the boron-sides of the silicon wafers are placed face to face, and the two wafers are stacked together. After stacking, the silicon wafers are placed vertically on a quartz boat and sealed with baffles. The wafers are then placed in a boron expansion furnace for boron expansion treatment at a temperature of 1000℃ for 2.5 hours.

[0067] In steps three and five, after sandblasting is completed, the silicon wafer is cleaned.

[0068] In Example 3, refer to Figure 1-2 A soft fast recovery FRD diode chip includes a silicon wafer, the silicon wafer employing a double-base diffusion sheet 2, the double-base diffusion sheet 2 including P + District 223, P + The thickness of region 223 is 90 μm, P + N is set on one side of zone 223 - Zone 222, N- The thickness of zone 222 is 60 μm, N - Area 222 is far from P + An N-region 221 is provided on one side of region 223. The thickness of N-region 221 is 30 μm. An N-region 221 is provided on one side of N-region 221. + Zone 220, N + The thickness of zone 220 is 50 μm.

[0069] The thickness of the silicon wafer material is 250 μm, the resistivity is 45-50 Ω·cm, and the total thickness of the double-base diffusion sheet 2 is 230 μm.

[0070] N in the double-base diffuser 2 - Region 222 is the lightly doped substrate region of the original silicon wafer, while N-region 221 is the heavily doped region, with a higher doping concentration than N-region. - Zone 222, and much lower than N + District 220.

[0071] The softness factor of the double-base diffuser 2 is 0.65, the reverse breakdown voltage is 1300V, and the reverse recovery time is 250ns.

[0072] In this implementation scheme, a dual-base diffusion process is used instead of a single-base diffusion process. The single-base diffusion process mainly uses a single-base diffusion sheet 1, which is composed of the original N... + District 110, former N - District 111 and the original P + Composed of region 112, due to the low impurity concentration of the single-base diffusion sheet 1, it can be seen from the softness factor formula that to increase the softness factor S value, only tb needs to be increased. When a reverse bias voltage is applied, the S value is low, and the reverse recovery characteristic is hard. After adopting the double-base diffusion process, the newly added N region 221 is more than the original N region. - The high impurity concentration in region 111 leads to a significant slowdown in the expansion of the depletion region after reaching the buffer layer during reverse recovery due to the higher impurity concentration in the buffer layer compared to the substrate. This results in a large number of carriers remaining unrecombined or unremoved in the buffer layer after a short carrier storage time, increasing the recombination time and thus the softness factor (tb). Increasing the carrier removal time (tb value) also raises the softness factor (S value), as indicated by the reverse recovery time formula. It can be seen that τ p For a large injected carrier lifetime, J F Forward current density, J RM For the reverse peak current density, the reverse recovery time Trr and the large injection lifetime τ p Proportional to the reverse peak current density J RMInversely proportional to the reverse recovery time Trr, when a double-base diffusion process is used and a reverse bias is applied, the reverse recovery time Trr also increases significantly. In order to reduce the reverse recovery time to a reasonable range and increase the operating frequency of the device, the platinum diffusion temperature is increased from 880℃ to about 920℃, so that the reverse recovery time of the diode is controlled to below 250ns.

[0073] Through formula (W, where W is the base region width, τH is the carrier lifetime, and DH is the bipolar diffusion coefficient) It can be seen that Vm is proportional to the base region width W, and simultaneously, Vm is proportional to the silicon wafer resistivity ρ. Therefore, to reduce the forward Vm (i.e., Vf), a silicon wafer with a narrower base region width and lower resistivity should be selected; conversely, to increase the reverse Vm (i.e., VB), a silicon wafer with a wider base region width and higher resistivity should be selected. It is evident that the requirements of the forward and reverse electrical parameters on the base region width and resistivity are contradictory. Therefore, considering the need to improve the reverse breakdown voltage of the chip, the selection of silicon wafer thickness and resistivity should be taken into account. Thus, a silicon wafer with a thickness of about 250 micrometers and a resistivity of 45-50 Ω·cm is used for diffusion. Compared with traditional FRD chips, the chip made of this silicon wafer can obtain a higher reverse breakdown voltage without a significant increase in forward voltage.

[0074] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A method for fabricating a soft fast recovery FRD diode chip, comprising a diffusion process and a GPP process, characterized in that, The diffusion process includes the following steps: Step 1, Pre-diffusion treatment: The silicon wafer raw material is first mechanically polished to obtain a polished substrate, and then the surface of the polished substrate is cleaned with a silicon wafer cleaning solution; Step 2, Phosphorus diffusion treatment: The N-side of the silicon wafer after Step 1 is subjected to diffusion treatment. First, a low-concentration phosphorus paper is used for the first diffusion, and then a normal-concentration phosphorus paper is used for the second diffusion. Step 3, First sandblasting: The phosphorus-distilled silicon wafer is fed into the vacuum sandblasting chamber at a speed of 40-50 cm / min, with the P-side facing up, and sandblasted at a pressure of 0.9-1.0 kg / cm2. Step 4, Boron diffusion treatment: Boron diffusion is performed on the P-side of the silicon wafer; Step 5, Secondary sandblasting: The boron-diffused silicon wafer is fed into the vacuum sandblasting chamber at a transmission speed of 40-50 cm / min, and is blown on both sides with a pressure of 0.9-1.0 kg / cm2 to complete the diffusion process; In step one, a silicon wafer with a resistivity of 45-50 Ω·cm and a thickness of T=250±5μm is selected. In step two, a phosphorus preheating treatment is performed before the primary diffusion treatment. The silicon wafer is placed flat on a quartz boat with the N side facing up. Then, low-concentration phosphorus paper is attached to the N side of the silicon wafer, and it is sealed with a baffle and put into a low-temperature furnace for preheating to 280-300°C. In step two, a low-concentration phosphorus paper is first used for primary diffusion at a temperature of 1180-1220℃ for 6-10 hours, resulting in a final diffusion depth of 75-85μm. Then, a normal-concentration phosphorus paper is used for secondary diffusion at a temperature of 1230-1280℃ for 2-4 hours, resulting in a final diffusion depth of 45-55μm. In step two, after the first diffusion is completed, during the cooling process of the diffusion furnace, the normal concentration phosphorus paper is preheated to 250-300°C, the diffusion furnace is cooled to 250-300°C, the normal concentration phosphorus paper is heated to 250-300°C, the normal concentration phosphorus paper is loaded, and it is sealed with baffles before entering the diffusion furnace for a second diffusion process.

2. The method for fabricating a soft fast recovery FRD diode chip according to claim 1, characterized in that, In step one, the silicon wafer cleaning solution comprises the following components by weight: 80-100 parts deionized water, 5-8 parts nano-abrasive, 1-3 parts amphoteric surfactant, and 4-6 parts organic amine; the nano-abrasive is amino-terminated polyether-coated nano-alumina with a particle size of 20-40 nm, and the mass ratio of nano-alumina to amino-terminated polyether is (3-8):1; the amphoteric surfactant is one or more of alkylaminopropionate, alkyl dimethyl betaine, alkyl hydroxysulfonyl betaine, and alkyl dimethyl hydroxypropyl phosphate betaine; the organic amine is one or more of tetramethylammonium hydroxide, tetraethylammonium hydroxide, tetrapropylammonium hydroxide, tetrabutylammonium hydroxide, trimethylbenzylammonium hydroxide, trimethylhydroxyethylammonium hydroxide, dimethyl dihydroxyethylammonium hydroxide, diethylamine, triethylamine, ethylenediamine, monoethanolamine, and diethanolamine.

3. The method for fabricating a soft fast recovery FRD diode chip according to claim 1, characterized in that, In step four, during the boron expansion process, boron impurities are first coated onto the P-side of the silicon wafer. The coated silicon wafer is then placed on a hot plate to dry. Next, the boron-sides of the silicon wafers are placed face to face, and the two wafers are stacked together. After stacking, the silicon wafers are placed vertically on a quartz boat and sealed with baffles. The wafers are then placed in a boron expansion furnace for boron expansion treatment. The boron expansion treatment temperature is 950-1050℃, and the time is 1-3 hours.

4. The method for fabricating a soft fast recovery FRD diode chip according to claim 1, characterized in that, In steps three and five, after sandblasting is completed, the silicon wafer is cleaned.

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