An epitaxial wafer and its preparation method

Abstract

This invention provides an epitaxial wafer and its fabrication method. The fabrication method includes: patterning a substrate to form multiple groove structures; growing a first sub-buffer layer on one side of the substrate where the groove structures are formed to form a front buffer layer; wherein a void structure penetrating the first sub-buffer layer and communicating with the groove structures is formed on the first sub-buffer layer; and growing an insertion layer on the surface of the first sub-buffer layer away from the substrate, a portion of the inner wall of the void structure, and the groove structures. By adopting the solution provided by this invention, the lateral epitaxy of the front buffer layer is increased, improving the crystal quality of the epitaxial layer, enhancing light reflection, and improving the luminous efficiency of the epitaxial wafer; moreover, the increased lateral epitaxy of subsequent film layers interrupts dislocations from the substrate, reduces the extension of defects or dislocations into the interior of the luminescent layer, improves the crystal quality of the epitaxial wafer, and improves leakage current performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to an epitaxial wafer and its preparation method. Background Technology

[0002] Since group III nitrides are generally heteroepitaxially grown on heterostructures such as sapphire or SiC, the lattice constants and thermal mismatches between different materials can generate dislocations or defects, which extend upwards as the epitaxial layer grows. These dislocations act as nonradiative recombination centers during device operation, affecting device efficiency. At the same time, they act as leakage channels, causing an increase in leakage current and leading to rapid device aging, which affects device efficiency and lifespan, thus limiting their application in the semiconductor electronics field. Summary of the Invention

[0003] This invention provides an epitaxial wafer and its preparation method, which increases the lateral epitaxy of the pre-buffer layer, improves the crystal quality of the epitaxial layer, enhances light reflection, and improves the luminescence efficiency of the epitaxial wafer; moreover, the lateral epitaxy of the subsequent film layer interrupts dislocations from the substrate, reduces the extension of defects or dislocations into the interior of the luminescent layer, improves the crystal quality of the epitaxial wafer, and improves leakage current performance.

[0004] In a first aspect, embodiments of the present invention provide a method for preparing an epitaxial wafer, comprising:

[0005] The substrate is patterned to form multiple groove structures;

[0006] A first sub-buffer layer is grown on one side of the substrate where the groove structure is formed to form a front buffer layer; wherein, a void structure is formed on the first sub-buffer layer that penetrates the first sub-buffer layer and communicates with the groove structure;

[0007] An insertion layer is grown on the surface of the first sub-buffer layer away from the substrate, on a portion of the inner wall of the void structure, and on the groove structure.

[0008] Optionally, the insertion layer includes a nitride layer, a diffusion-miscible structure layer, and an aluminide layer. The insertion layer is grown on the surface of the first sub-buffer layer away from the substrate, a portion of the inner wall of the void structure, and the groove structure, including:

[0009] The nitride layer is grown on the surface of the first sub-buffer layer away from the substrate, on a portion of the inner wall of the void structure, and on the groove structure;

[0010] Under the first condition, a first aluminum source is introduced to form the diffusion-mutually dissolved structure layer on the nitride layer;

[0011] A second aluminum source is introduced to form the aluminum compound layer on the diffusion-intersoluble structure layer;

[0012] The flow rate of the first aluminum source is greater than the flow rate of the second aluminum source.

[0013] Optionally, a second aluminum source is introduced to form the aluminide layer on the diffusion-mutually dissolved structure layer, including:

[0014] Under the second condition, the second aluminum source is introduced to form an aluminum layer on the diffusion-mutually dissolved structure layer; under the third condition, the aluminide layer is formed on the aluminum layer; and / or

[0015] Before introducing a first aluminum source to form the diffusion-mutually dissolved structure layer on the nitride layer under the first condition, the method further includes:

[0016] Under the fourth condition, the nitride layer is subjected to thermal annealing.

[0017] Optionally, under the first condition, a first aluminum source is introduced to form the diffusion-mutually soluble structure layer on the nitride layer, including:

[0018] In an inert gas atmosphere, a first aluminum source with a flow rate of 100-300 sccm and a duration of 2-10 s is introduced to form the diffusion-mutually dissolved structure layer.

[0019] Under the second condition, the second aluminum source is introduced to form an aluminum layer on the diffusion-mutually dissolved structure layer, including:

[0020] In an inert gas atmosphere, a second aluminum source with a flow rate of 5–100 sccm and a flow time of 5–15 s is introduced to form the aluminum layer.

[0021] Optionally, under the third condition, forming the aluminide layer on the aluminum layer includes:

[0022] The aluminum layer is subjected to nitrogen heat treatment for 5 to 20 seconds in an inert gas atmosphere at a temperature of 1000 to 1200°C to form the aluminum oxide layer.

[0023] Under the fourth condition, the nitride layer is subjected to thermal annealing, including:

[0024] The nitride layer is subjected to thermal annealing for 2 to 5 seconds under a reducing gas atmosphere, a temperature of 1000 to 1200°C, and a pressure of 50 to 500 torr.

[0025] Optionally, the front buffer layer further includes a second sub-buffer layer, which, after the insertion layer is grown on the surface of the first sub-buffer layer away from the substrate, a portion of the inner wall of the void structure, and the groove structure, further includes:

[0026] The second sub-buffer layer is grown on the insertion layer;

[0027] A post-buffer layer, an electron-providing layer, a light-emitting layer, and a hole-providing layer are sequentially grown on the second sub-buffer layer;

[0028] The growth temperature of the second sub-buffer layer is lower than that of the first sub-buffer layer, and the growth pressure of the second sub-buffer layer is greater than that of the first sub-buffer layer.

[0029] Optionally, a first sub-buffer layer is grown on the side of the substrate where the groove structure is formed, comprising:

[0030] Under conditions of temperature of 1120–1250 °C and pressure of 50–150 torr, a first sub-buffer layer with a thickness of 0.5–1 μm is grown on the substrate;

[0031] Growing the second sub-buffer layer on the insertion layer includes:

[0032] The second sub-buffer layer is grown on the insertion layer under conditions of temperature of 1050–1150°C and pressure of 200–400 torr.

[0033] In a second aspect, an epitaxial wafer prepared by the preparation method described in the first aspect is provided, the epitaxial wafer comprising:

[0034] The substrate includes multiple groove structures;

[0035] A front buffer layer is located on the side of the substrate where the groove structure is provided; wherein, the front buffer layer includes a first sub-buffer layer and a plurality of void structures; in a direction perpendicular to the substrate, the void structures penetrate the first sub-buffer layer; each void structure is connected to a corresponding groove structure;

[0036] An insertion layer is located on the side of the first sub-buffer layer away from the substrate, covering the surface of the first sub-buffer layer away from the substrate, a portion of the inner wall of the void structure, and the groove structure.

[0037] Optionally, the insertion layer comprises a nitride layer, a diffusion-miscible structure layer, an aluminum layer, and an aluminum nitride layer stacked sequentially; or, the insertion layer comprises a nitride layer, a diffusion-miscible structure layer, and an aluminum nitride layer stacked sequentially.

[0038] The nitride layer is located between the diffusion-miscible structure layer and the first sub-buffer layer.

[0039] Optionally, the intercalation layer is a nanoporous thin film structure.

[0040] When epitaxial wafers are grown using heteroepitaxial technology, dislocations or defects can occur between different materials during the growth process due to lattice constants and thermal mismatches. Setting the intercalation layer as a nanoporous thin film structure can, on the one hand, increase the lateral epitaxy of subsequent layers, and on the other hand, interrupt dislocations from the substrate, reduce the extension of defects or dislocations into the interior of the light-emitting layer, and improve the crystal quality of the epitaxial wafer. It can also enhance the reflection of light from the light-emitting layer toward the substrate at the hollow structure, enhance forward light emission, improve the luminous efficiency of the epitaxial wafer, and improve leakage current performance.

[0041] Optionally, the projected area of ​​the groove structure on the substrate is larger than the projected area of ​​the void structure on the substrate, and the insertion layer is further disposed on the surface of the first sub-buffer layer adjacent to the substrate and exposing the groove structure; or

[0042] The projected area of ​​the groove structure on the substrate is smaller than the projected area of ​​the void structure on the substrate, and the insertion layer also covers the surface of the substrate adjacent to the first sub-buffer layer and exposes the void structure.

[0043] The epitaxial wafer fabrication method provided by this invention first involves patterning a substrate to form multiple groove structures. Then, a first sub-buffer layer is grown on one side of the substrate with the groove structures to form a front buffer layer. A void structure is formed on the first sub-buffer layer, penetrating the first sub-buffer layer and communicating with the groove structures. Next, an insertion layer is grown on the surface of the first sub-buffer layer away from the substrate, part of the inner wall of the void structure, and the groove structure. The structure formed by the one-to-one correspondence between the void structure and the groove structure can be referred to as a hollow structure. Utilizing the hollow structure, on the one hand, the lateral epitaxy of the front buffer layer is increased, improving the crystal quality of the epitaxial layer and reducing the extension of defects into the light-emitting layer; on the other hand, the reflection of light from the light-emitting layer onto the substrate is enhanced at the hollow structure, improving forward light emission, increasing the luminous efficiency of the epitaxial wafer, and improving leakage current performance. The fabrication method and process are simple.

[0044] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1This is a flowchart of a method for preparing an epitaxial wafer provided by the present invention;

[0047] Figure 2 This is a schematic diagram of the preparation process of an epitaxial wafer provided by the present invention;

[0048] Figure 3 This invention provides Figure 1 Detailed flowchart of step S130;

[0049] Figure 4 This is a schematic diagram of another epitaxial wafer fabrication process provided by the present invention;

[0050] Figure 5 This is a flowchart of another method for preparing an epitaxial wafer provided by the present invention;

[0051] Figure 6 This is a schematic diagram of another epitaxial wafer fabrication process provided by the present invention;

[0052] Figure 7 This is a schematic diagram of the structure of an epitaxial wafer provided by the present invention;

[0053] Figure 8 This is a schematic diagram of another epitaxial wafer provided by the present invention;

[0054] Figure 9 This is a schematic diagram of another epitaxial wafer provided by the present invention;

[0055] Figure 10 This is a schematic diagram of another epitaxial wafer provided by the present invention;

[0056] Figure 11 This is a schematic diagram of another epitaxial wafer provided by the present invention;

[0057] Figure 12 This is a schematic diagram of another epitaxial wafer provided by the present invention;

[0058] Figure 13 This is a schematic diagram of another epitaxial wafer provided by the present invention. Detailed Implementation

[0059] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0060] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0061] Please see Figure 1 and Figure 2 , Figure 1 This is a flowchart of a method for preparing an epitaxial wafer provided by the present invention. Figure 2 This is a schematic diagram of the preparation process of an epitaxial wafer provided by the present invention. The preparation method of the epitaxial wafer includes:

[0062] S110. The substrate is patterned to form multiple groove structures.

[0063] For example, the radial dimension of the groove structure 2 is 100 in a plane parallel to the base 1.

[0064] ~1000nm; for example, the radial dimensions of the groove structure 2 are 100nm, 200nm, 300nm,

[0065] 400nm, 500nm, 600nm, 700nm, 800nm, 900nm, or 1000nm. In the direction perpendicular to the substrate 1, the depth of the groove structure 2 is 500 to 1000nm; for example, the depth of the groove structure 2 is 500nm, 600nm, 700nm, 800nm, 900nm, or 1000nm.

[0066] In one implementation, such as Figure 2 As shown in (a), a substrate 1 is provided; as Figure 2 As shown in (b), the substrate 1 is patterned to form multiple groove structures 2.

[0067] S120. A first sub-buffer layer is grown on the side of the substrate where the groove structure is formed to form a front buffer layer; wherein, a void structure is formed on the first sub-buffer layer that penetrates the first sub-buffer layer and communicates with the groove structure.

[0068] In one implementation, such as Figure 2 As shown in (c), a first sub-buffer layer 3 is grown on the side of the substrate 1 where the groove structure 2 is formed.

[0069] Exemplarily, substrate 1 is placed in a metal-organic chemical vapor deposition (MOCVD) apparatus, and a first sub-buffer layer 3 is grown on substrate 1 using the MOCVD apparatus. The material of the first sub-buffer layer 3 can be any nitride or a combination of at least two, and this embodiment is not limited in this respect.

[0070] like Figure 2 As shown in (d), the portion of the first sub-buffer layer 3 located on the groove structure 2 is etched to form a void structure 4 that penetrates the first sub-buffer layer 3 and communicates with the groove structure 2.

[0071] For example, the portion of the first sub-buffer layer 3 located on the groove structure 2 is etched to expose the groove structure 2, forming a void structure 4 that penetrates the first sub-buffer layer 3. That is, the void structure 4 is disposed on the inner sidewall of the first sub-buffer layer 3 and penetrates the first sub-buffer layer 3. The angle between the void structure 4 and the substrate 1 can be customized according to requirements, and this embodiment of the invention does not limit this. The groove structure 2 and the void structure 4 are connected to form a hollow structure.

[0072] In another embodiment, it is not necessary to form the void structure 4 on the entire first sub-buffer layer 3 by etching. Instead, the first sub-buffer layer 3 with void structure 4 can be formed by increasing the lateral growth rate of the first sub-buffer layer 3 under high temperature and low pressure process conditions.

[0073] S130, grow an insertion layer on the surface of the first sub-buffer layer away from the substrate, on a portion of the inner wall of the void structure, and on the groove structure.

[0074] like Figure 2 As shown in (e), an insertion layer 5 is grown on the surface of the first sub-buffer layer 3 away from the substrate 1, on part of the inner wall of the void structure 4, and on the groove structure 2.

[0075] For example, the material of the insertion layer 5 can be SiN, and the insertion layer 5 covers the surface of the first sub-buffer layer 3 away from the substrate 1, part of the inner wall of the void structure 4 and the groove structure 2.

[0076] Furthermore, the insertion layer 5 is a nanoporous thin film structure with multiple pores having a pore size of 5–150 nm. For example, the pore size of the insertion layer nanopores can be 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, 105 nm, 110 nm, 115 nm, 120 nm, 125 nm, 130 nm, 135 nm, 140 nm, 145 nm, or 150 nm.

[0077] The epitaxial wafer fabrication method provided in this invention utilizes a hollow structure. On one hand, this increases the lateral epitaxy of the pre-buffer layer, improving the crystal quality of the epitaxial layer and reducing the extension of defects into the light-emitting layer. On the other hand, it enhances the reflection of light emitted from the light-emitting layer towards the substrate 1 at the hollow structure, enhancing forward light emission, improving the luminous efficiency of the epitaxial wafer, and improving leakage current performance. The fabrication method and process are simple. Furthermore, when the epitaxial wafer substrate is grown using a heteroepitaxial process, dislocations or defects may arise between different materials during growth due to lattice constants and thermal mismatches. The insertion layer 5, with its nanoporous thin film structure, can increase the lateral epitaxy of subsequent film layers and interrupt dislocations from the substrate 1, reducing the extension of defects or dislocations into the light-emitting layer and improving the crystal quality of the epitaxial wafer. It can also enhance the reflection of light emitted from the light-emitting layer towards the substrate 1 at the hollow structure, enhancing forward light emission, improving the luminous efficiency of the epitaxial wafer, and improving leakage current performance.

[0078] In a specific embodiment, please refer to the following: Figures 1 to 4 , Figure 3 This invention provides Figure 1 Detailed flowchart of step S130 Figure 4 This is a schematic diagram of another epitaxial wafer fabrication process provided by the present invention. The insertion layer 5 includes a nitride layer 51, a diffusion-miscible structure layer 52, and an aluminide layer 54. Step S130 includes:

[0079] S131. A nitride layer is grown on the surface of the first sub-buffer layer away from the substrate, on part of the inner wall of the void structure, and on the groove structure.

[0080] like Figure 4 As shown in (e1), a nitride layer 51 is grown on the first sub-buffer layer 3.

[0081] For example, the material of the nitride layer 51 can be SiN. At a temperature of 1000–1200 °C...

[0082] Under conditions of ℃ and pressure of 50–500 torr, a nitride layer 51 with a thickness of 5–100 nm is grown on the first sub-buffer layer 3. For example, the thickness of the nitride layer 51 is 5 nm, 15 nm, 25 nm, 35 nm, 50 nm, 70 nm, 90 nm, or 100 nm; the growth temperature of the nitride layer 51 is 1000℃, 1025℃, 1050℃, 1075℃, 1100℃, 1125℃, 1150℃, etc.

[0083] ℃, 1175℃ or 1200℃; the growth pressure of nitride layer 51 is 50 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, 350 torr, 400 torr, 450 torr or 500 torr.

[0084] Optionally, after growing the nitride layer 51 on the first sub-buffer layer 3, the nitride layer 51 can be thermally annealed under a fourth condition. The nitride layer 51 has a nanoporous structure. Thermal annealing the nitride layer 51 can decompose dislocations on the surface of the nitride layer 51 and on the surface of the first sub-buffer layer 3 of the nitride layer 51 with exposed nanopores, thereby reducing the distribution of defect centers.

[0085] For example, the nitride layer 51 can be subjected to a heat annealing treatment for 2 to 5 seconds under a reducing gas atmosphere, a temperature of 1000–1200°C, and a pressure of 50–500 torr. Specifically, the reducing gas can be H2; the heat annealing temperature can be 1000°C, 1025°C, 1050°C, 1075°C, 1100°C, 1125°C, 1150°C, 1175°C, or 1200°C; the heat annealing pressure can be 50 torr, 100 torr, 150 torr, 200 torr, 250 torr, 300 torr, 350 torr, 400 torr, 450 torr, or 500 torr; and the heat annealing time can be 2 seconds, 2.5 seconds, 3 seconds, 3.5 seconds, 4 seconds, 4.5 seconds, or 5 seconds.

[0086] S132. Under the first condition, a first aluminum source is introduced to form a diffusion-mutually dissolved structure layer on the nitride layer.

[0087] like Figure 4 As shown in (e2), a diffusion-mutually dissolved structure layer 52 is formed on the nitride layer 51.

[0088] For example, in an inert gas atmosphere, a first aluminum source with a flow rate of 100–300 sccm and a flow time of 2–10 s is introduced to form a diffusion-intersoluble structure layer 52. The diffusion-intersoluble structure layer 52 prevents surface atoms from diffusing into the light-emitting layer as impurities, forming non-radiative recombination centers and leakage channels. The inert gas acts as a carrier gas, carrying aluminum atoms from the first aluminum source to form an aluminum layer on the nitride layer 51. Because the aluminum layer and the surface atoms of the nitride layer 51 can form a good diffusion-intersoluble structure layer 52, this diffusion-intersoluble structure layer is formed.

[0089] In one embodiment, the entire aluminum layer formed by the first aluminum source diffuses and dissolves with the surface atoms of the nitride layer 51 to form a mutually soluble structure layer 52. In another embodiment, a portion of the aluminum layer formed by the first aluminum source diffuses and dissolves with the surface atoms of the nitride layer 51 to form a mutually soluble structure layer 52, thereby creating an aluminum layer of a certain thickness above the diffusely soluble structure layer 52.

[0090] For example, the material of the diffusion-mutually soluble structural layer 52 is SiAl. The flow rate of the first aluminum source is 100 sccm, 130 sccm, 160 sccm, 200 sccm, 230 sccm, 260 sccm, or 300 sccm. The introduction time of the first aluminum source is 2 s, 3 s, 4 s, 5 s, 6 s, 7 s, 8 s, 9 s, or 10 s. Because the first aluminum source is introduced under high flow rate conditions, although aluminum atoms can form a uniform distribution, in-plane diffusion of aluminum atoms still occurs due to the surface potential energy difference of the nitride layer 51. However, in the diffusion-mutually soluble structural layer 52 of SiAl material, silicon atoms can be used to effectively restrict the diffusion of aluminum atoms, thereby improving the stability of the aluminum atom distribution.

[0091] The first aluminum source can be an organic compound Al source, including any one or a combination of two or more of trimethylaluminum, triethylaluminum, dimethylalcoaluminum, dimethylaluminum hydride, and aluminum alkyl complexes.

[0092] S133. A second aluminum source is introduced to form an aluminum oxide layer on the diffusion-mutually dissolved structure layer; wherein the flow rate of the first aluminum source is greater than the flow rate of the second aluminum source.

[0093] In one implementation, such as Figure 4 As shown in (e3), under the second condition, a second aluminum source is introduced to form an aluminum layer 53 on the diffusion-intermixed structure layer 52. Figure 4 As shown in (e4), under the third condition, an aluminum oxide layer 54 is formed on the aluminum layer 53. In the resulting epitaxial wafer, the insertion layer 5 includes a nitride layer 51, a diffusion-miscible structure layer 52, an aluminum layer 53, and an aluminum oxide layer 54.

[0094] Optionally, under the second condition, a second aluminum source is introduced to form an aluminum layer 53 on the diffusion-mutually dissolved structure layer 52, including: introducing a second aluminum source with a flow rate of 5 to 100 sccm and a flow time of 5 to 15 s in an inert gas atmosphere to form the aluminum layer 53; the flow rate of the first aluminum source is greater than the flow rate of the second aluminum source.

[0095] For example, the flow rate of the second aluminum source is 5 sccm, 15 sccm, 25 sccm, 35 sccm, 45 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, or 100 sccm. The introduction time of the second aluminum source is 5 s, 6 s, 7 s, 8 s, 9 s, 10 s, 11 s,

[0096] 12s, 13s, 14s, or 15s. The second aluminum source can be an organic compound Al source, including any one or more combinations of trimethylaluminum, triethylaluminum, dimethylalkanedaluminum, dimethylaluminum hydride, and aluminum alkyl complexes.

[0097] In this embodiment, a high Al flow rate process (i.e., introducing a first aluminum source) is first used to rapidly form a nanoscale aluminum layer with a thickness of 1-5 nm on the surface of the nitride layer 51. This avoids uneven distribution of aluminum components caused by differences in surface potential energy of the nitride layer 51, thereby shielding surface defects and improving the uniformity of the aluminum layer distribution. Subsequently, a low Al flow rate process (i.e., introducing a second aluminum source) is used. This allows aluminum atoms to diffuse sufficiently, improving the uniformity of the potential energy of the aluminum atoms distributed on the surface. This reduces the concentrated distribution of aluminum atoms in defect areas, lowers the probability of surface defects being amplified, and prevents surface defects from diffusing into the light-emitting layer in the thickness direction. It also prevents the formation of non-radiative recombination centers and leakage channels that extend into the light-emitting layer. Furthermore, it reduces the incorporation of impurities carried by the second aluminum source during the high Al flow rate process and the C, H, and other impurities formed by the decomposition of the second aluminum source. This prevents surface atoms from diffusing into the light-emitting layer as impurities in the thickness direction, thus avoiding the formation of non-radiative recombination centers and leakage channels.

[0098] Optionally, under the third condition, an aluminide layer 54 is formed on the aluminum layer 53, including: subjecting the aluminum layer 53 to nitrogen heat treatment for 5–20 seconds in an inert gas atmosphere at a temperature of 1000–1200°C to form the aluminide layer 54. Under the nitrogen heat treatment condition, at least a portion of the aluminum layer 53 is nitrided to form an AlN epitaxial layer, which is the aluminide layer 54. The aluminide layer 54 serves to interrupt dislocations and regulate stress, providing a buffer layer growth template, and can be used for the growth of large-size epitaxial wafers.

[0099] For example, the material of the aluminide layer 54 is AlN. The temperature for nitrogen heat treatment of the aluminum layer 53 is 1000℃, 1025℃, 1050℃, 1075℃, 1100℃, 1125℃, 1150℃, 1175℃, or 1200℃. The duration of nitrogen heat treatment of the aluminum layer 53 is 5s, 6s, 7s, 8s, 9s, 10s, 11s, 12s, 13s, 14s, 15s, 16s, 17s, 18s, 19s, or 20s. The nitrogen source for nitrogen heat treatment of the aluminum layer 53 includes any one or a combination of two or more of NH3, organic amine compounds, and trap compounds; the organic amine compounds include alkylamines, alkylamines include tert-butylamine and / or n-propylamine, and trap compounds include dimethyl traps.

[0100] In another embodiment, under the third condition, when at least a portion of the aluminum layer 53 is formed as an aluminide layer 54, all aluminum layers 53 of all thicknesses are reacted away, thereby forming an epitaxial wafer in which the insertion layer 5 includes a nitride layer 51, a diffusion-miscible structure layer 52, and an aluminide layer 54, but does not include the aluminum layer 53.

[0101] The epitaxial wafer fabrication method provided in this embodiment of the invention, based on the above embodiment, grows a nitride layer 51 on the surface of the first sub-buffer layer 3 away from the substrate 1, a portion of the inner wall of the void structure 4, and the groove structure 2. Under first conditions, a first aluminum source is introduced to form a diffusion-intersoluble structure layer 52 on the nitride layer 51. A second aluminum source with a flow rate less than that of the first aluminum source is introduced to form an aluminum compound layer 54 on the diffusion-intersoluble structure layer 52. This embodiment first employs a high Al flow rate process, followed by a low Al flow rate process. Under high Al flow rate conditions, a nanoscale aluminum layer is rapidly distributed on the surface of the nitride layer 51, avoiding uneven aluminum composition distribution caused by differences in surface potential energy of the nitride layer 51. Under low Al flow rate conditions, aluminum atoms can diffuse sufficiently, improving the consistency of the potential energy of the aluminum atoms distributed on the surface, and reducing the concentrated distribution of aluminum atoms in defect areas. This avoids the formation of non-radiative recombination centers and leakage channels.

[0102] Please see Figure 5 and Figure 6 , Figure 5 This is a flowchart of another method for preparing an epitaxial wafer provided by the present invention. Figure 6 This is a schematic diagram of another epitaxial wafer fabrication process provided by the present invention. The epitaxial wafer fabrication method includes:

[0103] S210 provides a base.

[0104] like Figure 6 As shown in (a), a base 1 is provided.

[0105] Substrate 1 is the substrate of the epitaxial wafer, serving to fix and support it. The material of substrate 1 can be sapphire, silicon carbide, silicon, silicon nitride, aluminum nitride, or diamond, etc., and this embodiment does not limit this.

[0106] S220. The substrate is patterned to form multiple groove structures.

[0107] like Figure 6 As shown in (b), the substrate 1 is patterned to form multiple groove structures 2.

[0108] S230. A first sub-buffer layer is grown on the side of the substrate where the groove structure is formed, to form a front buffer layer.

[0109] like Figure 6 As shown in (c), a first sub-buffer layer 3 is grown on substrate 1; specifically, the first sub-buffer layer 3 with a thickness of 0.5 to 1 μm is grown on substrate 1 under the conditions of temperature of 1120 to 1250 °C and pressure of 50 to 150 torr.

[0110] For example, the material of the first sub-buffer layer 3 is a nitride. The growth temperature of the first sub-buffer layer 3 is 1120°C, 1140°C, 1160°C, 1180°C, 1200°C, 1220°C, 1240°C, or 1250°C. The growth pressure of the first sub-buffer layer 3 is 50 torr, 60 torr, 70 torr, 80 torr, 90 torr, 100 torr, 110 torr, 120 torr, 130 torr, 140 torr, or 150 torr. The growth thickness of the first sub-buffer layer 3 is 0.5 μm, 0.6 μm, 0.7 μm, 0.8 μm, 0.9 μm, or 1 μm.

[0111] S240. The portion of the first sub-buffer layer located on the groove structure is etched to form a void structure that penetrates the first sub-buffer layer and is connected to the groove structure.

[0112] like Figure 6 As shown in (d), the first sub-buffer layer 3 is etched to form a void structure 4 that penetrates the first sub-buffer layer 3 and communicates with the groove structure 2.

[0113] S250, an insertion layer is grown on the surface of the first sub-buffer layer away from the substrate, on a portion of the inner wall of the void structure, and on the groove structure.

[0114] like Figure 6 As shown in (e), an insertion layer 5 is grown. The insertion layer 5 may include a nitride layer, a diffusion-mixed structure layer, and an aluminide layer stacked together; or, the insertion layer 5 may include a nitride layer, a diffusion-mixed structure layer, an aluminum layer, and an aluminide layer stacked together.

[0115] S260. Grow a second sub-buffer layer on the insertion layer.

[0116] like Figure 6 As shown in (f), a second sub-buffer layer 6 is grown on the insertion layer 5.

[0117] For example, the second sub-buffer layer 6 is located on the side of the insertion layer 5 away from the substrate 1. The second sub-buffer layer 6 can be grown directly without etching, without changing the size and shape of the void structure 4. This process can improve efficiency and save resources.

[0118] The pre-buffer layer includes a first sub-buffer layer 3 and a second sub-buffer layer 6. The growth temperature of the second sub-buffer layer 6 is lower than that of the first sub-buffer layer 3, and the growth pressure of the second sub-buffer layer 6 is greater than that of the first sub-buffer layer 3. By setting these growth conditions, the longitudinal growth rate of the second sub-buffer layer 6 is increased, which can reduce the layered defects that occur due to excessively rapid lateral growth during grain boundary merging during the growth of the second sub-buffer layer 6, and improve the surface smoothness and thickness uniformity of the second sub-buffer layer 6.

[0119] Optionally, a second sub-buffer layer 6 is grown on the insertion layer 5 under conditions of temperature of 1050–1150 °C and pressure of 200–400 torr.

[0120] For example, the material of the second sub-buffer layer 6 is a nitride. The growth temperature of the second sub-buffer layer 6 is 1050°C, 1060°C, 1070°C, 1080°C, 1090°C, 1100°C, 1110°C, 1120°C, 1130°C, 1140°C, or 1150°C. The growth pressure of the second sub-buffer layer 6 is 200 torr, 220 torr, 240 torr, 260 torr, 280 torr, 300 torr, 320 torr, 340 torr, 360 torr, 380 torr, or 400 torr.

[0121] S270, a buffer layer, an electron-providing layer, a light-emitting layer, and a hole-providing layer are sequentially grown on the second sub-buffer layer.

[0122] like Figure 6 As shown in (g), a buffer layer 7, an electron-providing layer 8, a light-emitting layer 9, and a hole-providing layer 10 are sequentially grown on the second sub-buffer layer 6.

[0123] Optionally, a post-buffer layer 7 with a thickness of 1 to 5 μm is formed on the second sub-buffer layer 6 under conditions of temperature of 1050 to 1150 °C and pressure of 200 to 400 torr.

[0124] For example, the growth pressure of the second sub-buffer layer 6 is 200 torr, 220 torr, 240 torr, 260 torr, 280 torr, 300 torr, 320 torr, 340 torr, 360 torr, 380 torr, or 400 torr. The rear buffer layer 7 is located on the side of the front buffer layer away from the substrate 1, and the growth thickness of the rear buffer layer 7 is 1 μm, 2 μm, 3 μm, 4 μm, or 5 μm; the growth temperature of the rear buffer layer 7 is 1050℃, 1060℃, 1070℃, 1080℃, 1090℃, 1100℃, 1110℃, 1120℃, 1130℃, 1140℃, or 1150℃.

[0125] Optionally, an electron-providing layer 8 is formed on the back buffer layer 7, comprising: growing a layer with a thickness of 2–10 μm and a Si doping concentration of 1 × 10⁻⁶ on the back buffer layer 7 under conditions of a temperature of 1000–1100 °C and a pressure of 100–500 torr. 18 ~8×10 18 cm -3 The electronic layer 8 is provided.

[0126] For example, the electron providing layer 8 can be an n-type nitride layer, and the material of the n-type nitride layer can be any type of n-type nitride or a combination of at least two types. The n-type nitride layer is doped with Si element, and the Si doping concentration is 1×10⁻⁶. 18 ~8×10 18 cm -3 For example, the thickness of electron-providing layer 8 is 2 μm, 4 μm, 6 μm, 8 μm, or 10 μm; the Si doping concentration is 1 × 10⁻⁶. 18 cm -3 2×10 18 cm -3 3×10 18 cm -3 4×10 18 cm -3 5×10 18 cm -3 6×10 18 cm -3 7×10 18 cm -3 Or 8×10 18 cm -3The growth temperature of the electron providing layer 8 is 1000℃, 1010℃, 1020℃, 1030℃, 1040℃, 1050℃, 1060℃, 1070℃, 1080℃, 1090℃, or 1100℃; the growth pressure of the electron providing layer 8 is 100 torr, 140 torr, 180 torr, 220 torr, 260 torr, 300 torr, 340 torr, 380 torr, 420 torr, 460 torr, or 500 torr.

[0127] Optionally, the light-emitting layer 9 is located on the side of the electron-providing layer 8 away from the substrate 1. The light-emitting layer 9 can be a quantum well light-emitting layer, which can be a nitride quantum well light-emitting layer. The nitride quantum well light-emitting layer includes a number of periodically overlapping nitride quantum well layers and nitride quantum barrier layers.

[0128] Further, a light-emitting layer 9 is formed on the electron-providing layer 8, comprising: periodically and repeatedly overlapping growth of a nitride quantum well layer and a nitride quantum barrier layer on the electron-providing layer 8. The overlapping growth period of the nitride quantum well layer and the nitride quantum barrier layer is 2 to 10 cycles, the thickness of the nitride quantum well layer is 1 to 6 nm, and the thickness of the nitride quantum barrier layer is 6 to 25 nm. For example, the number of cycles is 2, 3, 4, 5, 6, 7, 8, 9, or 10; the thickness of the nitride quantum well layer is 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, or 6 nm; and the thickness of the nitride quantum barrier layer is 6 nm, 9 nm, 12 nm, 15 nm, 18 nm, 21 nm, 24 nm, or 25 nm. The growth process of the nitride quantum well layer and the nitride quantum barrier layer is as follows:

[0129] (A1) Nitride quantum well layers were grown at temperatures of 700–1150 °C and pressures of 100–500 torr.

[0130] For example, the growth temperature of the nitride quantum well layer is 700°C, 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C, or 1150°C. The growth pressure of the nitride quantum well layer is 100 torr, 140 torr, 180 torr, 220 torr, 260 torr, 300 torr, 340 torr, 380 torr, 420 torr, 460 torr, or 500 torr.

[0131] (A2) Nitride quantum barrier layers were grown at temperatures of 750–1200 °C and pressures of 100–500 torr.

[0132] For example, the growth temperature of the nitride quantum barrier layer is 750°C, 800°C, 850°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C, 1150°C, or 1200°C. The growth pressure of the nitride quantum barrier layer is 100 torr, 140 torr, 180 torr, 220 torr, 260 torr, 300 torr, 340 torr, 380 torr, 420 torr, 460 torr, or 500 torr.

[0133] Optionally, a hole-providing layer 10 is formed on the light-emitting layer 9, comprising: growing a layer with a thickness of 20–300 nm and a Mg doping concentration of 1 × 10⁻⁶ on the light-emitting layer 9 under conditions of a temperature of 900–1100 °C and a pressure of 100–500 torr. 19 ~1×10 21 cm -3 The cavity provides layer 10.

[0134] For example, the hole-providing layer 10 can be a p-type hole-providing layer, and the material of the p-type hole-providing layer can be any p-type nitride or a combination of at least two types. The p-type hole-providing layer can be doped with Mg, and the Mg doping concentration is 1×10⁻⁶. 19 cm -3 ~1×10 21 cm -3 For example, the hole-providing layer 10 has a thickness of 20 nm, 60 nm, 100 nm, 140 nm, 180 nm, 220 nm, 260 nm, or 300 nm; the Mg doping concentration is 1 × 10⁻⁶. 19 cm -3 5×10 19 cm -3 1×10 20 cm -3 5×10 20 cm -3 Or 1×10 21 cm -3 The growth temperature of the hole-providing layer 10 is 900℃, 925℃, 950℃, 975℃, 1000℃, 1025℃, 1050℃, 1075℃, or 1100℃; the growth pressure of the hole-providing layer 10 is 100 torr, 140 torr, 180 torr, 220 torr, 260 torr, 300 torr, 340 torr, 380 torr, 420 torr, 460 torr, or 500 torr.

[0135] The technical solution provided in this embodiment first etches the first sub-buffer layer 3 to form a void structure 4 that penetrates the first sub-buffer layer 3 and communicates with the groove structure 2; then, an insertion layer 5 is grown on the surface of the first sub-buffer layer 3 away from the substrate 1, part of the inner wall of the void structure 4, and the groove structure 2. Utilizing the hollow structure, on the one hand, the lateral epitaxy of the front buffer layer is increased, improving the crystal quality of the epitaxial layer and reducing the extension of defects into the interior of the light-emitting layer 9; on the other hand, the reflection of light emitted from the light-emitting layer 9 towards the substrate 1 is enhanced at the hollow structure, improving forward light emission, increasing the luminous efficiency of the epitaxial wafer, and improving leakage current performance. The preparation method and process flow are simple. Furthermore, the growth temperature of the second sub-buffer layer 6 is lower than that of the first sub-buffer layer 3, and the growth pressure of the second sub-buffer layer 6 is greater than that of the first sub-buffer layer 3. This helps to increase the longitudinal growth rate of the second sub-buffer layer 6, reducing layered defects that occur due to excessively rapid lateral growth during grain boundary merging during the growth of the second sub-buffer layer 6, and improving the surface smoothness and thickness uniformity of the second sub-buffer layer 6.

[0136] Please see Figure 7 , Figure 7 This is a schematic diagram of the structure of an epitaxial wafer provided by the present invention. The epitaxial wafer includes a substrate 1, a front buffer layer 11, and an insertion layer 5.

[0137] Substrate 1 is the substrate of the epitaxial wafer, serving to fix and support it. Specifically, the material of substrate 1 can be sapphire, silicon carbide, silicon, silicon nitride, aluminum nitride, or diamond, etc., and this embodiment does not limit this.

[0138] Furthermore, such as Figure 7 As shown, a plurality of groove structures 2 are provided on the substrate 1, and the shape of the groove structures 2 can be customized according to requirements. The front buffer layer 11 is located on the side of the substrate 1 where the groove structures 2 are provided. The material of the front buffer layer 11 can be any nitride or a combination of at least two, and this embodiment does not limit this.

[0139] Furthermore, such as Figure 7 As shown, the front buffer layer 11 includes a first sub-buffer layer 3 and multiple void structures 4. Specifically, in a direction perpendicular to the substrate 1, the void structures 4 are disposed on the inner sidewall of the first sub-buffer layer 3, penetrating the first sub-buffer layer 3. The angle α between the void structure 4 and the substrate 1 can be customized according to requirements, and this embodiment of the invention does not impose any limitations on this. It can be understood that the angle α is the angle between the inclined surface of the void structure 4 and the upper surface of the substrate 1. In one embodiment, the angle α between the void structure 4 and the substrate 1 can be an acute angle; in other embodiments, the angle α between the void structure 4 and the substrate 1 is an obtuse angle or a right angle. Each void structure 4 is connected to a corresponding groove structure 2, and the void structure 4 and the groove structure 2 correspond one-to-one. The structure formed by the one-to-one correspondence of the void structure 4 and the groove structure 2 can be referred to as a hollow structure.

[0140] An insertion layer 5 is disposed on the first sub-buffer layer 3. The insertion layer 5 covers the surface of the first sub-buffer layer 3 away from the substrate 1, part of the inner wall of the void structure 4, and the groove structure 2. Specifically, the material of the insertion layer 5 is SiN, and the insertion layer 5 is a nanoporous thin film structure. Epitaxial wafer substrates are generally grown using heteroepitaxial technology. During the growth process, dislocations or defects will be generated between different materials due to lattice constants and thermal mismatches. The insertion layer 5 with a nanoporous thin film structure can, on the one hand, increase the lateral epitaxy of the back buffer layer 6, and on the other hand, interrupt the dislocations from the bottom layer, reduce the extension of defects or dislocations into the interior of the light-emitting layer, and improve the crystal quality of the epitaxial wafer. It can also enhance the reflection of light from the light-emitting layer toward the substrate 1 at the hollow structure, enhance forward light emission, improve the luminous efficiency of the epitaxial wafer, and improve leakage current performance.

[0141] The technical solution provided in this embodiment provides a connecting void structure 4 and groove structure 2 between the substrate 1 and the first sub-buffer layer 3. This increases the lateral epitaxy of the pre-buffer layer 11 during the epitaxial layer growth process, reducing the extension of dislocations or defects into the subsequently grown light-emitting layer and improving crystal quality. Furthermore, by providing a hollow structure, the reflection of light emitted from the light-emitting layer onto the substrate 1 at the hollow structure is enhanced, increasing forward light emission, improving the luminous efficiency of the epitaxial wafer, and improving leakage current performance.

[0142] For example, such as Figure 7 As shown, the projected area of ​​the groove structure 2 on the substrate 1 is equal to the projected area of ​​the void structure 4 on the substrate 1. A first sub-buffer layer 3 with the void structure 4 is epitaxially grown directly on the side of the substrate 1 where the groove structure 2 is located. Through process control of the first sub-buffer layer 3 in the front buffer layer 11, the lateral growth rate of the first sub-buffer layer 3 in the front buffer layer 11 is increased. During the growth of the first sub-buffer layer 3 in the front buffer layer 11, the lateral growth will merge the grooves, ultimately forming the void structure 4. During the lateral growth process, dislocations are fully redirected above the groove structure 2, preventing dislocations from extending into the light-emitting layer, reducing the dislocation channels between the electron-providing layer and the hole-providing layer, thereby improving the radiative recombination efficiency, reducing leakage current through dislocation channels, and improving leakage performance.

[0143] Furthermore, such as Figure 7 As shown, in a plane parallel to the substrate 1, the radial dimension of the groove structure 2 is greater than or equal to 100 nm and less than or equal to 1000 nm; in a direction perpendicular to the substrate 1, the depth of the groove structure 2 is greater than or equal to 500 nm and less than or equal to 1000 nm. The insertion layer 5 has multiple holes, the pore size of which is greater than or equal to 5 nm and less than or equal to 150 nm.

[0144] In this embodiment, the radial dimension of the groove structure 2 is 100–1000 nm, and the depth of the groove structure 2 is 500–1000 nm. The aperture size of the holes in the insertion layer 5 is 5–150 nm. By limiting the size of the groove structure 2 and the holes in the insertion layer 5, the reflection of light emitted from the light-emitting layer onto the substrate 1 at the hollow structure is further enhanced, thereby improving the luminous efficiency of the epitaxial wafer.

[0145] Please see Figure 8 , Figure 8 This is a schematic diagram of another epitaxial wafer structure provided by the present invention. Figure 8 The provided solutions and Figure 7 The provided solutions are similar, and the same parts will not be described again in this embodiment. The difference is that the insertion layer 5 includes a nitride layer 51, a diffusion-miscible structure layer 52, and an aluminum nitride layer 54 stacked sequentially. The nitride layer 51 is located between the diffusion-miscible structure layer 52 and the first sub-buffer layer 3. The diffusion-miscible structure layer 52 is located between the nitride layer 51 and the aluminum nitride layer 54.

[0146] For example, under nitrogen heat treatment conditions, the entire aluminum layer is nitrided to form an aluminide layer 54. The aluminide layer 54 serves to interrupt dislocations and regulate stress, providing a buffer layer growth template that can be used for the growth of large-size epitaxial wafers.

[0147] Please see Figure 9 , Figure 9 This is a schematic diagram of another epitaxial wafer structure provided by the present invention. Figure 9 The provided solutions and Figure 7 The provided solutions are similar, and the same parts will not be described again in this embodiment. The difference is that the insertion layer 5 includes a nitride layer 51, a diffusion-mixed structure layer 52, an aluminum layer 53, and an aluminum nitride layer 54 stacked sequentially. The aluminum layer 53 is located between the diffusion-mixed structure layer 52 and the aluminum nitride layer 54.

[0148] For example, under nitrogen heat treatment conditions, a portion of the aluminum layer is nitrided to form an aluminide layer 54, and the unnitrided portion serves as... Figure 9 The aluminum layer 53 is shown.

[0149] Please see Figure 10 , Figure 10 This is a schematic diagram of another epitaxial wafer structure provided by the present invention. Figure 10 The provided solutions and Figure 7 The provided solutions are similar, and the same parts will not be described again in this embodiment. The difference is that the front buffer layer 11 also includes a second sub-buffer layer 6. The second sub-buffer layer 6 is located on the side of the insertion layer 5 away from the substrate 1.

[0150] In this embodiment, a second sub-buffer layer 6 is provided on the insertion layer 5, which can reduce the lattice mismatch between the epitaxial layer and the substrate 1 and improve the growth quality of the epitaxial layer grown on the substrate 1.

[0151] Please see Figure 11 , Figure 11 This is a schematic diagram of another epitaxial wafer structure provided by the present invention, which is similar to... Figure 10 The epitaxial wafers shown have similar structures, but differ in that the epitaxial wafers also include a back buffer layer 7, an electron providing layer 8, a light-emitting layer 9, and a hole providing layer 10, which are stacked in sequence.

[0152] The rear buffer layer 7 is located on the side of the front buffer layer 11 away from the substrate 1. Specifically, the rear buffer layer 7 is located on the second sub-buffer layer 6, and the thickness of the rear buffer layer 7 is 1 to 5 μm.

[0153] The electron-providing layer 8 is located on the side of the back buffer layer 7 away from the substrate 1. Specifically, the thickness of the electron-providing layer 8 is 2–10 μm. The electron-providing layer 8 can be an n-type nitride layer, and the material of the n-type nitride layer can be any type of n-type nitride or a combination of at least two types. The n-type nitride layer can be doped with Si, and the Si doping concentration can be 1 × 10⁻⁶. 18 ~8×10 18 cm -3 .

[0154] The light-emitting layer 9 is located on the side of the electron-providing layer 8 away from the substrate 1. Specifically, the light-emitting layer 9 can be a quantum well light-emitting layer, which can be a nitride quantum well light-emitting layer. The nitride quantum well light-emitting layer includes several periodically overlapping nitride quantum well layers and nitride quantum barrier layers. The thickness of the nitride quantum well layers is 1-6 nm, and the thickness of the nitride quantum barrier layers is 6-25 nm.

[0155] The hole-providing layer 10 is located on the side of the light-emitting layer 9 away from the substrate 1. Specifically, the hole-providing layer 10 has a thickness of 20–300 nm and can be a p-type hole-providing layer. The material of the p-type hole-providing layer can be any type of p-type nitride or a combination of at least two types. The p-type hole-providing layer can be doped with Mg, with a Mg doping concentration of 1 × 10⁻⁶. 19 cm -3 ~1×10 21 cm -3 .

[0156] Electrons provided by electron providing layer 8 and holes provided by hole providing layer 10 recombine in light-emitting layer 9, thereby emitting light.

[0157] Optionally, in another embodiment, such as Figure 12 As shown, Figure 12 This is a schematic diagram of another epitaxial wafer provided by the present invention, which is similar to... Figure 10 The structures of the epitaxial wafers shown are similar, except that the projected area of ​​the groove structure 2 on the substrate 1 is larger than the projected area of ​​the gap structure 4 on the substrate 1, and the insertion layer 5 is also disposed near the substrate 1 of the first sub-buffer layer 3 and exposes the surface of the groove structure 2.

[0158] The insertion layer 5 includes a first sub-insertion layer to a fourth sub-insertion layer. The first sub-insertion layer covers the upper surface of the first sub-buffer layer 3, the second sub-insertion layer covers the sidewall of the first sub-buffer layer 3 that contacts the gap structure 4, the third sub-insertion layer covers part of the surface of the groove structure 2 that contacts the first sub-buffer layer 3, and the fourth sub-insertion layer covers the inner wall of the groove structure 2.

[0159] In this embodiment, when the projected area of ​​the groove structure 2 on the substrate 1 is greater than the projected area of ​​the void structure 4 on the substrate 1, the insertion layer 5 is also disposed on a portion of the lower surface of the first sub-buffer layer 3 (i.e., a portion of the upper surface in contact with the groove structure 2), ensuring that the insertion layer 5 more closely covers all surfaces in contact with the hollow structure, the substrate 1, and the first sub-buffer layer 3, thereby reducing the impact of changes in the projected area on the quality of the epitaxial layer crystal.

[0160] Optionally, in yet another embodiment, such as Figure 13 As shown, Figure 13 This is a schematic diagram of another epitaxial wafer provided by the present invention, which is similar to... Figure 12 The structures of the epitaxial wafers shown are similar, except that the projected area of ​​the groove structure 2 on the substrate 1 is smaller than the projected area of ​​the gap structure 4 on the substrate 1, and the insertion layer 5 also covers the substrate 1 adjacent to the first sub-buffer layer 3 and exposes the surface of the gap structure 4.

[0161] The insertion layer 5 includes a first sub-insertion layer to a fourth sub-insertion layer. The first sub-insertion layer covers the upper surface of the first sub-buffer layer 3, the second sub-insertion layer covers the sidewall of the first sub-buffer layer 3 that contacts the void structure 4, the third sub-insertion layer covers part of the upper surface of the substrate 1, and the fourth sub-insertion layer covers the inner wall of the groove structure 2.

[0162] In this embodiment, when the projected area of ​​the groove structure 2 on the substrate 1 is smaller than the projected area of ​​the gap structure 4 on the substrate 1, the insertion layer 5 is also disposed on part of the upper surface of the substrate 1. This can better cover the surface of the hollow structure in contact with the substrate 1 and the first sub-buffer layer 3 when the projected areas of the groove structure 2 and the gap structure 4 are different, thereby increasing the lateral extension of the front buffer layer 11.

[0163] In the contact area between the nitride layer 51 and the surface of the substrate 1, and the sidewall of the groove structure 2, the nitride layer 51 exhibits a mixed crystal plane, resulting in poor crystal quality and density. This reduces the mechanical strength of the epitaxial wafer, making it prone to collapse during impacts, compression, and dicing processes. This severely affects the performance stability of the epitaxial wafer and the lifespan of the device. Figure 12 and Figure 13 The structure shown has a groove structure 2 projected onto the substrate 1 with an area that is not equal to the void structure 4 projected onto the substrate 1. This can increase the mechanical properties of the epitaxial wafer and is beneficial to the performance stability and service life of the epitaxial wafer.

[0164] On the other hand, the insertion layer 5 serves to passivate the surface of the substrate 1 and the contact area of ​​the sidewall of the groove structure 2 (i.e., the area where the inner wall of the groove structure 2 contacts the insertion layer 5), reducing charge diffusion caused by high defect distribution in the contact area, improving the insulation performance of the bottom epitaxial layer of the electron providing layer, reducing the probability of leakage current connection, and improving leakage current and brightness performance.

[0165] Example 1

[0166] The epitaxial wafer provided in this embodiment is as follows: Figure 11 As shown, the epitaxial wafer includes a substrate 1, a front buffer layer 11, a rear buffer layer 7, an electron-providing layer 8, a light-emitting layer 9, and a hole-providing layer 10 stacked together. The front buffer layer 11 includes a first sub-buffer layer 3 and a second sub-buffer layer 6, with an insertion layer 5 disposed between the first sub-buffer layer 3 and the second sub-buffer layer 6. The method for fabricating the above epitaxial wafer includes:

[0167] Step S1: Provide substrate 1.

[0168] The substrate 1 is a sapphire substrate or a GaN growth substrate. The radial dimension of the groove structure 2 in the substrate 1 is 100 nm, and the depth of the groove structure 2 is 500 nm.

[0169] Step S2: Under the conditions of temperature of 1120℃ and pressure of 50 torr, a first sub-buffer layer 3 with a thickness of 0.5μm and made of GaN is grown on the substrate 1.

[0170] Step S3: Under the conditions of 1000℃ and 50 torr, a nitride layer 51 with a thickness of 5nm and made of SiN is grown on the first sub-buffer layer 3.

[0171] The pore size in nitride layer 51 is 5 nm.

[0172] Step S4: Under H2 atmosphere, temperature of 1000℃ and pressure of 50 torr, perform a 5s heat annealing treatment on the nitride layer 51.

[0173] Step S5: In an N2 atmosphere, a first aluminum source with a flow rate of 100 sccm and a flow time of 2 s is introduced to form a diffusion-mutually dissolved structure layer 52 of SiAl material.

[0174] Step S6: In an N2 atmosphere, a second aluminum source with a flow rate of 5 sccm and a flow time of 5 s is introduced to form an aluminum layer 53.

[0175] Step S7: Under N2 atmosphere and temperature of 1000℃, the aluminum layer 53 is subjected to nitrogen heat treatment for 5s to form an aluminum oxide layer 54 of AlN material.

[0176] Step S8: Under the conditions of a temperature of 1050℃ and a pressure of 200 torr, a second sub-buffer layer 6 of GaN material is grown on the insertion layer 5.

[0177] Step S9: Under the conditions of a temperature of 1050℃ and a pressure of 100 torr, a post-buffer layer 7 with a thickness of 1μm and made of GaN is formed on the second sub-buffer layer 6.

[0178] Step S10: Under conditions of 1000℃ and 100 torr, grow a 2μm thick Si doping concentration of 1×10⁻⁶ on the back buffer layer 7. 18 cm -3 The electron providing layer 8 is made of n-type GaN.

[0179] Step S11: On the electron-providing layer 8, nitride quantum well layers and nitride quantum barrier layers are periodically and repeatedly overlapped to form the light-emitting layer 9.

[0180] Nitride quantum well layers of InGaN were grown at a temperature of 700℃ and a pressure of 100 torr.

[0181] A nitride quantum barrier layer of GaN was grown at a temperature of 750℃ and a pressure of 100 torr.

[0182] Step S12: Under conditions of 900℃ and 100 torr, a 20nm thick Mg doping concentration of 1×10⁻⁶ is grown on the light-emitting layer 9. 19 cm -3 Hole-providing layer 10 is made of GaN.

[0183] Example 2

[0184] The method for preparing the epitaxial wafer provided in this embodiment includes:

[0185] Step S1: Provide substrate 1.

[0186] The substrate 1 is a sapphire substrate or a GaN growth substrate. The radial dimension of the groove structure 2 in the substrate 1 is 1000 nm, and the depth of the groove structure 2 is 1000 nm.

[0187] Step S2: Under the conditions of temperature of 1250℃ and pressure of 150 torr, a first sub-buffer layer 3 with a thickness of 1μm and made of GaN is grown on the substrate 1.

[0188] Step S3: Under the conditions of temperature of 1200℃ and pressure of 500 torr, a nitride layer 51 with a thickness of 100nm and material of SiN is grown on the first sub-buffer layer 3.

[0189] The pore size in nitride layer 51 is 150 nm.

[0190] Step S4: Under H2 atmosphere, temperature of 1200℃ and pressure of 500 torr, perform 2s of heat annealing on nitride layer 51.

[0191] Step S5: In an N2 atmosphere, a first aluminum source with a flow rate of 300 sccm and a flow time of 10 s is introduced to form a diffusion-mutually dissolved structure layer 52 of SiAl material.

[0192] Step S6: In an N2 atmosphere, a second aluminum source with a flow rate of 100 sccm and a flow time of 15 s is introduced to form an aluminum layer 53.

[0193] Step S7: Under N2 atmosphere and temperature of 1200℃, the aluminum layer 53 is subjected to nitrogen heat treatment for 20s to form an aluminum oxide layer 54 of AlN material.

[0194] Step S8: Under the conditions of a temperature of 1150℃ and a pressure of 400 torr, a second sub-buffer layer 6 of GaN material is grown on the insertion layer 5.

[0195] Step S9: Under the conditions of a temperature of 1150℃ and a pressure of 400 torr, a post-buffer layer 7 with a thickness of 5μm and made of GaN is formed on the second sub-buffer layer 6.

[0196] Step S10: Under conditions of 1100℃ and 500 torr, grow a 10μm thick Si doping concentration of 8×10⁻⁶ on the back buffer layer 7. 18 cm -3 The electron providing layer 8 is made of n-type GaN.

[0197] Step S11: On the electron providing layer 8, nitride quantum well layers and nitride quantum barrier layers are periodically and repeatedly overlapped to form a light-emitting layer 9.

[0198] Nitride quantum well layers of InGaN were grown at a temperature of 1150℃ and a pressure of 500 torr.

[0199] A nitride quantum barrier layer of GaN was grown at a temperature of 1200℃ and a pressure of 500 torr.

[0200] Step S12: Under conditions of 1100℃ and 500 torr, a 300nm thick Mg doping concentration of 1×10⁻⁶ is grown on the light-emitting layer 9. 21 cm -3 Hole-providing layer 10 is made of GaN.

[0201] Example 3

[0202] The method for preparing the epitaxial wafer provided in this embodiment includes:

[0203] Step S1: Provide substrate 1.

[0204] The substrate 1 is a sapphire substrate or a GaN growth substrate. The radial dimension of the groove structure 2 in the substrate 1 is 200 nm, and the depth of the groove structure 2 is 700 nm.

[0205] Step S2: Under the conditions of temperature of 1135℃ and pressure of 80 torr, a first sub-buffer layer 3 with a thickness of 0.7μm and made of GaN is grown on the substrate 1.

[0206] Step S3: Under the conditions of temperature of 1150℃ and pressure of 200 torr, a nitride layer 51 with a thickness of 8nm and made of SiN is grown on the first sub-buffer layer 3.

[0207] The pore size in nitride layer 51 is 50 nm.

[0208] Step S4: Under H2 atmosphere, temperature of 1150℃ and pressure of 200 torr, perform 3s of heat annealing on nitride layer 51.

[0209] Step S5: In an N2 atmosphere, a first aluminum source with a flow rate of 200 sccm and a flow time of 8 s is introduced to form a diffusion-mutually dissolved structure layer 52 of SiAl material.

[0210] Step S6: In an N2 atmosphere, a second aluminum source with a flow rate of 50 sccm and a flow time of 8 s is introduced to form an aluminum layer 53.

[0211] Step S7: Under N2 atmosphere and temperature of 1150℃, the aluminum layer 53 is subjected to nitrogen heat treatment for 10s to form an aluminum oxide layer 54 of AlN material.

[0212] Step S8: Under the conditions of a temperature of 1100℃ and a pressure of 300 torr, a second sub-buffer layer 6 of GaN material is grown on the insertion layer 5.

[0213] Step S9: Under the conditions of a temperature of 1090℃ and a pressure of 200 torr, a post-buffer layer 7 with a thickness of 2.5μm and made of GaN is formed on the second sub-buffer layer 6.

[0214] Step S10: Under conditions of 1080℃ and 150 torr, a 2.5 μm thick Si doping concentration of 5 × 10⁻⁶ is grown on the back buffer layer 7. 18 cm -3 The electron providing layer 8 is made of n-type GaN.

[0215] Step S11: On the electron-providing layer 8, nitride quantum well layers and nitride quantum barrier layers are periodically and repeatedly overlapped to form a light-emitting layer 9.

[0216] Nitride quantum well layers of InGaN were grown at a temperature of 760℃ and a pressure of 300 torr.

[0217] A nitride quantum barrier layer of GaN was grown at a temperature of 860℃ and a pressure of 300 torr.

[0218] Step S12: Under conditions of 965℃ and 400 torr, a 200nm thick Mg doping concentration of 1×10⁻⁶ is grown on the light-emitting layer 9. 20 cm -3 Hole-providing layer 10 is made of GaN.

[0219] Example 4

[0220] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except that the flow rate in step S5 is 50 sccm, and will not be repeated here.

[0221] Example 5

[0222] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except that the flow rate in step S5 is 400 sccm, and will not be repeated here.

[0223] Example 6

[0224] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except that the flow rate in step S6 is 2 sccm, and will not be repeated here.

[0225] Example 7

[0226] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except that the flow rate in step S6 is 150 sccm, and will not be repeated here.

[0227] Example 8

[0228] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except that step S5 is omitted, and will not be repeated here.

[0229] Example 9

[0230] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except that step S6 is omitted, and will not be described again here.

[0231] Example 10

[0232] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except that the temperature in step S7 is 900°C, and will not be repeated here.

[0233] Example 11

[0234] The method for preparing the epitaxial wafer provided in this embodiment is the same as that in Example 3, except that the temperature in step S7 is 1300℃, and will not be repeated here.

[0235] Example 12

[0236] The method for preparing the epitaxial wafer provided in this embodiment is the same as that in Example 3, except for the nitrogen heat treatment for 2 seconds in step S7, and will not be repeated here.

[0237] Example 13

[0238] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except for the nitrogen heat treatment for 25 seconds in step S7, and will not be repeated here.

[0239] Example 14

[0240] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except that step S7 is omitted, and will not be repeated here.

[0241] Example 15

[0242] The method for preparing the epitaxial wafer provided in this embodiment is the same as in Example 3, except that step S4 is omitted, and will not be repeated here.

[0243] Example 16

[0244] The method for preparing the epitaxial wafer provided in this embodiment is the same as that in Embodiment 3, except that steps S4, S5, S6 and S7 are omitted, and will not be described again here.

[0245] Example 17

[0246] In the epitaxial wafer preparation method provided in this embodiment, the following is formed: Figure 12 The epitaxial wafer shown has a larger projected area of ​​groove structure 2 on substrate 1 than that of void structure 4 on substrate 1. The rest is the same as in embodiment 3 and will not be repeated here.

[0247] Example 18

[0248] In the epitaxial wafer preparation method provided in this embodiment, the following is formed: Figure 13 The epitaxial wafer shown has a smaller projected area of ​​groove structure 2 on substrate 1 than that of void structure 4 on substrate 1. The rest is the same as in embodiment 3 and will not be repeated here.

[0249] Comparative Example 1

[0250] In the epitaxial wafer preparation method provided in this embodiment, the insertion layer 5 is not formed. That is, except for omitting steps S3, S4, S5, S6 and S7, the rest is the same as in embodiment 3, and will not be repeated here.

[0251] Comparative Example 2

[0252] In the epitaxial wafer preparation method provided in this embodiment, except that the void structure 4 is not formed in the first sub-buffer layer 3, the rest is the same as that in Comparative Example 1, and will not be described again here.

[0253] The following example demonstrates the effectiveness of the solution provided by this invention by testing the wavelength uniformity, brightness, voltage, and leakage current yield of an LED epitaxial wafer with an emission wavelength of 460nm±1nm on a sapphire substrate. The test data are shown below:

[0254]

[0255]

[0256] Where WLD represents the emission wavelength in nm, and std represents wavelength uniformity in nm. The test data in the table above shows that Examples 1, 2, and 3 exhibit the best photoelectric performance, demonstrating good wavelength uniformity, high brightness, low voltage, and high leakage current yield.

[0257] 1) By comparing Examples 3, 4, and 5, it can be seen that compared with Example 3, the wavelength uniformity of the epitaxial wafer in Examples 4 and 5 is worse (i.e., std is larger), the brightness and leakage yield are reduced, and the voltage is increased. The reason is that if the first aluminum source flow is too large or too small, it will cause the aluminum layer distribution uniformity to be worse. The worse uniformity distribution leads to the thickness consistency being worse, the aluminum layer thickness difference fluctuation is increased, thereby reducing the defect shielding ability and causing a large difference in the thickness of subsequent epitaxial growth. Consequently, there will also be a large difference in the carrier injection uniformity. Finally, the radiative recombination efficiency in the light-emitting layer is low, which reduces the brightness and leakage performance of the epitaxial wafer and increases the voltage of the epitaxial wafer.

[0258] 2) By comparing Examples 3 with Examples 6 and 7, it can be seen that compared with Example 3, the wavelength uniformity of the epitaxial wafer in Examples 6 and 7 is worse (i.e., std is larger), the brightness and leakage yield are reduced, and the voltage is increased. The reason is that when the second aluminum flow rate is too small, aluminum atoms cannot form complete diffusion on the surface. When the second aluminum source flow rate is too large, some aluminum atoms do not have time to diffuse. In short, both excessive and insufficient second aluminum source flow rates will affect the diffusion of aluminum atoms, reduce the consistency of aluminum atom potential energy, and the surface defects are locally amplified and extended into the light-emitting layer, ultimately reducing the brightness and leakage performance of the epitaxial wafer and increasing the voltage of the epitaxial wafer.

[0259] 3) By comparing Examples 3 with Examples 8 and 9, it can be seen that compared with Example 3, the wavelength uniformity of the epitaxial wafer in Examples 8 and 9 is worse (i.e., std is larger), the brightness and leakage yield are reduced, and the voltage is increased. The reasons are the same as those in 1) and 2). It can be determined that the first aluminum source and the second aluminum source process have an impact on the wavelength uniformity, brightness, voltage and leakage yield of the epitaxial wafer. It is necessary to match the corresponding process parameters in order to prepare an epitaxial wafer with better performance.

[0260] 4) By comparing Example 3 with Examples 11, 12, 13, 14, and 15, it can be seen that compared with Example 3, the wavelength uniformity (i.e., std increases), brightness, and leakage current yield of the epitaxial wafers in Examples 11, 12, 13, 14, and 15 decrease, while the voltage increases. This is because when the nitrogen heat treatment temperature is too low or the time is too short, sufficient nitriding effect cannot be provided, and the aluminide layer cannot serve as a growth template for the second sub-buffer layer, resulting in poor thickness uniformity of the subsequently grown epitaxial layer. When the nitrogen heat treatment temperature is too high or the time is too long, the nitriding effect will be overdone, forming more aluminum vacancy defects and increasing the surface roughness after nitriding, affecting the thickness uniformity of the subsequent epitaxial layer. In summary, the nitrogen heat treatment process affects the wavelength uniformity, brightness, voltage, and leakage current yield of the epitaxial wafer, and appropriate process parameters need to be matched to prepare epitaxial wafers with better performance.

[0261] 5) By comparing Example 3 and Example 16, it can be seen that the photoelectric performance of the epitaxial wafer in Example 16 is also reduced to a certain extent compared with Example 3. The wavelength uniformity of the epitaxial wafer deteriorates (i.e., std increases), and the brightness and leakage current yield are slightly reduced. The reason is that omitting the thermal annealing process will cause the surface defect dislocations to extend into the light-emitting layer. In short, the thermal annealing process affects the wavelength uniformity, brightness and leakage current yield of the epitaxial wafer. It is necessary to match the corresponding process parameters in order to prepare an epitaxial wafer with better performance.

[0262] 6) By comparing Example 3 and Example 17, it can be seen that, compared with Example 3, the wavelength uniformity of the epitaxial wafer in Example 17 is worse (i.e., std is larger), the brightness and leakage yield are reduced, and the voltage is increased. This indicates that the process of the present invention improves the crystal quality of the epitaxial layer and reduces the extension of defects into the light-emitting layer. On the other hand, it enhances the reflection of light emitted from the light-emitting layer to the substrate at the hollow structure, enhances the forward light emission, improves the luminous efficiency of the epitaxial wafer, and improves the leakage performance.

[0263] 7) By comparing Example 3 with Examples 18 and 19, it can be seen that the photoelectric properties of the epitaxial wafers in Examples 18 and 19 are comparable to those in Example 3. This indicates that the process of the present invention improves the crystal quality of the epitaxial layer and reduces the extension of defects into the light-emitting layer. On the other hand, it enhances the reflection of light emitted from the light-emitting layer onto the substrate at the hollow structure, enhances forward light emission, improves the luminous efficiency of the epitaxial wafer, and improves the leakage current performance.

[0264] 8) By comparing Example 3 with Comparative Examples 1 and 2, it can be seen that the wavelength uniformity of the epitaxial wafers in Comparative Examples 1 and 2 deteriorates (i.e., std increases), brightness and leakage yield decrease, and voltage increases. This indicates that the embodiments of the present invention improve the brightness of the epitaxial wafer, improve the luminous efficiency of the epitaxial wafer, and improve leakage performance. Comparative Example 2 exhibits relatively superior photoelectric performance compared to Comparative Example 1, which also reflects the positive effect of the insertion layer process in the present invention on improving the photoelectric performance of the epitaxial wafer, improving the crystal quality of the epitaxial layer, and reducing the extension of defects into the light-emitting layer; on the other hand, it enhances the reflection of light emitted from the light-emitting layer to the substrate at the hollow structure, enhances forward light emission, improves the luminous efficiency of the epitaxial wafer, and improves leakage performance.

[0265] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0266] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for preparing an epitaxial wafer, characterized in that, include: The substrate is patterned to form multiple groove structures; A first sub-buffer layer is grown on one side of the substrate where the groove structure is formed to form a front buffer layer; wherein, a void structure is formed on the first sub-buffer layer that penetrates the first sub-buffer layer and communicates with the groove structure; An insertion layer is grown on the surface of the first sub-buffer layer away from the substrate, on a portion of the inner wall of the void structure, and on the groove structure; The insertion layer includes a nitride layer, a diffusion-miscible structure layer, and an aluminide layer. The insertion layer is grown on the surface of the first sub-buffer layer away from the substrate, a portion of the inner wall of the void structure, and the groove structure, including: The nitride layer is grown on the surface of the first sub-buffer layer away from the substrate, on a portion of the inner wall of the void structure, and on the groove structure; Under the first condition, a first aluminum source is introduced to form the diffusion-mutually dissolved structure layer on the nitride layer; A second aluminum source is introduced to form the aluminum compound layer on the diffusion-intersoluble structure layer; the aluminum compound layer is an aluminum nitride layer; The flow rate of the first aluminum source is greater than the flow rate of the second aluminum source.

2. The method for preparing an epitaxial wafer according to claim 1, characterized in that, Introducing a second aluminum source to form the aluminum compound layer on the diffusion-mutually dissolved structure layer includes: Under the second condition, the second aluminum source is introduced to form an aluminum layer on the diffusion-mutually dissolved structure layer; under the third condition, the aluminide layer is formed on the aluminum layer; and / or Before introducing a first aluminum source to form the diffusion-mutually dissolved structure layer on the nitride layer under the first condition, the method further includes: Under the fourth condition, the nitride layer is subjected to thermal annealing.

3. The method for preparing an epitaxial wafer according to claim 2, characterized in that, Under the first condition, a first aluminum source is introduced to form the diffusion-mutually soluble structure layer on the nitride layer, including: In an inert gas atmosphere, a first aluminum source with a flow rate of 100-300 sccm and a flow time of 2-10 s is introduced to form the diffusion-mutually dissolved structure layer. Under the second condition, the second aluminum source is introduced to form an aluminum layer on the diffusion-mutually dissolved structure layer, including: In an inert gas atmosphere, a second aluminum source with a flow rate of 5 to 100 sccm is introduced for a duration of 5 to 15 s to form the aluminum layer.

4. The method for preparing an epitaxial wafer according to claim 2, characterized in that, Under the third condition, the aluminide layer is formed on the aluminum layer, including: The aluminum layer is subjected to nitrogen heat treatment for 5 to 20 seconds in an inert gas atmosphere at a temperature of 1000 to 1200 °C to form the aluminum compound layer. Under the fourth condition, the nitride layer is subjected to thermal annealing, including: The nitride layer is subjected to thermal annealing for 2 to 5 seconds under a reducing gas atmosphere, a temperature of 1000 to 1200 °C, and a pressure of 50 to 500 torr.

5. The method for preparing an epitaxial wafer according to claim 1, characterized in that, The front buffer layer further includes a second sub-buffer layer, which, after the insertion layer is grown on the surface of the first sub-buffer layer away from the substrate, a portion of the inner wall of the void structure, and the groove structure, further includes: A second sub-buffer layer is grown across the void structure on the surface of the insertion layer away from the first sub-buffer layer and the substrate; A post-buffer layer, an electron-providing layer, a light-emitting layer, and a hole-providing layer are sequentially grown on the second sub-buffer layer; The growth temperature of the second sub-buffer layer is lower than that of the first sub-buffer layer, and the growth pressure of the second sub-buffer layer is greater than that of the first sub-buffer layer.

6. The method for preparing an epitaxial wafer according to claim 5, characterized in that, A first sub-buffer layer is grown on the side of the substrate where the groove structure is formed, comprising: Under conditions of temperature of 1120 ~ 1250℃ and pressure of 50 ~ 150 torr, a first sub-buffer layer with a thickness of 0.5 ~ 1 μm is grown on the substrate; Growing the second sub-buffer layer on the insertion layer includes: The second sub-buffer layer is grown on the insertion layer under conditions of temperature of 1050 ~ 1150 ℃ and pressure of 200 ~ 400 torr.

7. An epitaxial wafer prepared by the preparation method according to claim 1, characterized in that, The epitaxial wafer includes: The substrate includes multiple groove structures; A front buffer layer is located on the side of the substrate where the groove structure is provided; wherein, the front buffer layer includes a first sub-buffer layer and a plurality of void structures; in a direction perpendicular to the substrate, the void structures penetrate the first sub-buffer layer; each void structure is connected to a corresponding groove structure; An insertion layer is located on the side of the first sub-buffer layer away from the substrate, covering the surface of the first sub-buffer layer away from the substrate, a portion of the inner wall of the void structure, and the groove structure; the insertion layer includes a nitride layer, a diffusion-miscible structure layer, and an aluminum nitride layer stacked sequentially.

8. The epitaxial wafer according to claim 7, characterized in that, The insertion layer includes an aluminum layer disposed between the diffusion-miscible structure layer and the aluminum nitride layer; The nitride layer is located between the diffusion-miscible structure layer and the first sub-buffer layer.

9. The epitaxial wafer according to claim 7, characterized in that, The projected area of ​​the groove structure on the substrate is larger than the projected area of ​​the void structure on the substrate, and the insertion layer is also disposed adjacent to the first sub-buffer layer and exposes the surface of the groove structure; or The projected area of ​​the groove structure on the substrate is smaller than the projected area of ​​the void structure on the substrate, and the insertion layer also covers the surface of the substrate adjacent to the first sub-buffer layer and exposes the void structure.

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