A method for synthesizing adjacent four-vectors, a common-mode voltage suppression PWM method, device and system

Abstract

The application discloses a method for synthesizing adjacent four vectors, a common-mode voltage suppression PWM method, device and system. The application proposes a switching sequence design method under the rule of adjacent four vector synthesis, and analyzes the control freedom thereof. Through an optimization method for the switching sequence and an adjacent four vector acting time adjustment factor, layer-by-layer optimization of the common-mode voltage volt-second characteristic and output harmonic performance is realized. The application can realize peak value limitation of the common-mode voltage and optimization of the volt-second characteristic, and on the basis, fully utilizes the control freedom to realize optimization of the output harmonic performance.

Description

Technical Field

[0001] This invention belongs to the field of power electronic control, and particularly relates to an adjacent four-vector synthesis method, a common-mode voltage suppression (PWM) method and device, and a system. Background Technology

[0002] With the increasing switching speed and frequency of power electronic devices, the common-mode voltage generated by two-level voltage source inverters has caused some significant negative effects. In photovoltaic power generation, leakage current generated by high-frequency common-mode voltage can cause grid-connected current distortion and even safety issues. In AC motor speed control, the high-frequency shaft voltage and shaft current induced by common-mode voltage at the motor terminals reduce the motor's lifespan. Common-mode voltage is also a source of common-mode electromagnetic interference, affecting the reliable operation of surrounding equipment. Hardware improvements can effectively reduce the negative effects of common-mode voltage, but they increase system cost and size and generate additional losses. Common-mode current can be weakened by adding common-mode chokes, but analysis of the volt-second characteristics of common-mode voltage using existing pulse width modulation strategies shows that current methods easily cause heating and saturation of the common-mode chokes, which is extremely detrimental to suppressing common-mode current. To address this problem, optimizing the control method of power switching devices can mitigate the negative effects of common-mode voltage at a lower cost.

[0003] Traditional pulse width modulation (PWM) strategies primarily employ the nearest three-vector synthesis rule, which selects the three fundamental vectors closest to the reference vector to complete the volt-second equivalent synthesis of the reference vector. The nearest three-vector synthesis rule aims to optimize current ripple, stator flux linkage ripple, and torque pulsation, effectively addressing the main challenge of Si-based inverters operating at switching frequencies below tens of kHz. However, its performance in suppressing common-mode voltage effects is somewhat lacking. With the increase in GaN switching speed and frequency, reaching up to several MHz, the main challenge of the system shifts to the prominent common-mode voltage effect, thus reducing the adaptability of the nearest three-vector synthesis rule. In recent years, some novel switching sequences, distinct from the nearest three-vector approach, have gradually been developed. However, the fundamental theory behind the voltage vector synthesis rules for these novel switching sequences has not yet been established, and the physical significance of these novel switching sequences requires further investigation. Summary of the Invention

[0004] The purpose of this invention is to provide a method for adjacent four-vector synthesis, a common-mode voltage suppression (PWM) method and device, and a system. This invention proposes a switching sequence design method under the adjacent four-vector synthesis rule, solving the problem of lack of control degrees of freedom under the common-mode voltage suppression objective in the nearest three-vector synthesis rule.

[0005] This invention is implemented according to the following technical solution:

[0006] In a first aspect, the present invention provides a method for adjacent four-vector synthesis, the method being applicable to space voltage vector pulse width modulation technology, the method comprising:

[0007] Step S100: In the same sector, select the four vectors corresponding to the vertices of three isosceles trapezoids;

[0008] Step S110: The reference voltage vector exists within a triangular sector contained by two effective voltage vectors, and the triangle is surrounded by three isosceles trapezoids formed by four vectors;

[0009] Step S120: Set the two effective voltage vectors closest to the reference voltage vector as the master voltage vectors.

[0010] Based on the relationship between the angles of the other two selected effective voltage vectors and the main voltage vector, a quadrilateral voltage vector combination is defined; the quadrilateral voltage vector combination includes a leading four-vector combination, a lagging four-vector combination, and a positive four-vector combination;

[0011] Step S130: Using the four effective voltage vectors corresponding to the vertices of the isosceles trapezoid within the sampling period and the duration of the four effective voltage vectors, the equivalent synthesis formula of the reference voltage vector is derived.

[0012] Step S140: For the three synthesis methods of leading quadrilateral voltage vector combination, regular quadrilateral voltage vector combination and lagging quadrilateral voltage vector combination, the equivalent synthesis formula is used to synthesize the reference voltage vector.

[0013] In one embodiment, when the reference voltage vector lies within an isosceles trapezoid formed by four non-zero vectors V1, V2, V3, and V4, the equivalent synthesis formula for the reference voltage vector is:

[0014]

[0015] In the formula, V1, V2, V3, and V4 are the four selected effective voltage vectors, t1', t2', t3', and t4' are the action times of the four selected effective voltage vectors, and T is the effective voltage vector. c Let V1, V2, V3, V4 be the sampling period, and let V1, V2, V3, V4 satisfy 0 ≤ t1', t2', t3', t4' respectively. j '≤T c j = 1, 2, 3, 4.

[0016] Secondly, the present invention provides a common-mode voltage suppression (PWM) method for inverters based on adjacent four vectors, the method comprising the following steps:

[0017] Step S200: The reference voltage vector is synthesized using the above-mentioned adjacent four-vector synthesis method to obtain the synthesized reference voltage vector in three synthesis methods;

[0018] Step S210: Based on the four-vector voltage combination, obtain the switching sequence that conforms to the pulse width modulation synthesis rule, and calculate the effective voltage vector action time of the synthesis reference voltage vector for the three synthesis methods;

[0019] Step S220: Based on the sector position of the reference voltage vector, the DC bus voltage value of the inverter, and the effective voltage vector duration of the synthesized reference voltage vector, establish a constrained mathematical rule model with the goal of minimizing the common-mode voltage volt-second characteristics;

[0020] Step S230: Find the optimal solution for the established constrained mathematical rule model and perform numerical analysis to obtain the optimized switching sequence and optimized action time corresponding to the two synthesis methods with the smallest volt-second characteristic amplitude;

[0021] Step S240: For the optimized switching sequences corresponding to the two synthesis methods that obtain the minimum volt-second characteristic amplitude, calculate the flux linkage ripple of the optimized switching sequences respectively, and select the switching sequence with the minimum flux linkage ripple to optimize the output harmonic performance.

[0022] In one embodiment, calculating the effective voltage vector duration of the synthesized reference voltage vector in the three synthesis methods includes:

[0023] By calculating the duration of action of the two effective voltage vectors and the duration of action of the zero vector when the three most recent vectors are combined, the constraint equation for the duration of action of the voltage vector is obtained.

[0024] Calculate the volt-second characteristics of the four-vector voltage combination, and simultaneously establish the constraint equations for the duration of the voltage vectors to obtain the equation set for the duration of the effective voltage vectors.

[0025] By solving the effective voltage vector action time equations, the action time of the leading quadrilateral voltage vector combination, the regular quadrilateral voltage vector combination, and the lagging quadrilateral voltage vector combination with time adjustment factors are calculated respectively.

[0026] In one embodiment, the constraint equation for the duration of action of the voltage counting vector is:

[0027]

[0028]

[0029] In the formula, t0, t1, and t2 are the action times of the zero vector V0 and the effective voltage vectors V1 and V2 under the recent three-vector synthesis rule, respectively. dref Vqref V ref Voltage components on the d-axis and q-axis, V d1 V q1 These are the voltage components of V1 on the d-axis and q-axis, respectively. d2 V q2 These are the voltage components of V2 on the d-axis and q-axis, respectively, T c The sampling period.

[0030] In one implementation, the constrained mathematical rule model aimed at minimizing the common-mode voltage volt-second characteristic is as follows:

[0031]

[0032] Where t0, t1, and t2 are the application times of the zero vector V0 and the effective voltage vectors V1 and V2 under the recent three-vector synthesis rule, respectively.

[0033] In one implementation, the optimal time adjustment factor Δt under the synthesis method can be obtained by solving the optimal solution through a constrained mathematical rule model. The time adjustment factors for the three synthesis methods are as follows:

[0034] Advanced quadrilateral voltage vector combination:

[0035] Regular quadrilateral voltage vector combination:

[0036] Hysteresis quadrilateral voltage vector combination:

[0037] Wherein, min(V) s_CMV The sign indicates that the common-mode voltage volt-second characteristic value in parentheses takes the smaller value within its respective Δt range.

[0038] In one embodiment, the formula for calculating the flux linkage ripple is:

[0039]

[0040] In the formula, δ is the duty cycle, and λ is the load factor. hn λ is the root mean square value of the flux linkage ripple per unit within one carrier cycle. hn λ is the per-unit value of the flux linkage ripple. hn It can be calculated using the following formula:

[0041]

[0042] In the formula, N is a non-negative integer, and V kh This is the error vector.

[0043] Thirdly, the present invention provides an inverter common-mode voltage suppression (PWM) device based on adjacent four vectors, the device comprising:

[0044] The module for synthesizing a reference voltage vector is used to synthesize a reference voltage vector into three adjacent four-vectors using any of the adjacent four-vector synthesis methods described in claims 1-2, thereby obtaining a synthesized reference voltage vector in three different synthesis methods.

[0045] The effective voltage vector action time calculation module is used to derive a switching sequence that conforms to the pulse width modulation synthesis rule based on the combination of four vector voltages, and to calculate the effective voltage vector action time of the synthesized reference voltage vector for the three synthesis methods.

[0046] The constrained mathematical programming model module is used to establish a constrained mathematical rule model with the goal of minimizing the common-mode voltage volt-second characteristics, based on the sector position of the reference voltage vector, the DC bus voltage value of the inverter, and the effective voltage vector duration of the synthesized reference voltage vector.

[0047] The module for optimizing the switching sequence and optimizing the action time is used to obtain the optimal solution for the established constrained mathematical rule model and perform numerical analysis to obtain the optimized switching sequence and optimized action time corresponding to the two synthesis methods with the smallest volt-second characteristic amplitude.

[0048] The flux linkage ripple optimization module is used to calculate the current ripple of the optimized switching sequence output by the common-mode voltage volt-second characteristic optimization module and select the switching sequence with the minimum flux linkage ripple.

[0049] Thirdly, the present invention provides a gallium nitride inverter control system, the system comprising: the inverter common-mode voltage suppression PWM device based on adjacent four vectors as described in claim 9, a drive circuit module, a gallium nitride inverter module with a common-mode choke, and a load module; the inverter common-mode voltage suppression PWM device based on adjacent four vectors calculates in a digital signal processor to obtain an optimal switching sequence and inputs this switching sequence into the gallium nitride inverter module with a common-mode choke through the drive circuit module, so as to achieve the purpose of controlling the load module.

[0050] Beneficial effects of this invention:

[0051] This invention proposes a switching sequence design method under the adjacent four-vector synthesis rule and analyzes its control degrees of freedom. An optimization method for the switching sequence and the adjustment factor of the adjacent four-vector action time is presented, achieving layer-by-layer optimization of common-mode voltage volt-second characteristics and output harmonic performance. The proposed method can achieve optimization of common-mode voltage peak value limitation and volt-second characteristics, and on this basis, fully utilizes the control degrees of freedom to optimize output harmonic performance. Attached Figure Description

[0052] The accompanying drawings, as part of this invention, are provided to further illustrate the invention. The illustrative embodiments and descriptions of the invention are used to explain the invention, but do not constitute an undue limitation thereof. Clearly, the drawings described below are merely some embodiments, and those skilled in the art can obtain other drawings based on these drawings without any creative effort.

[0053] Figure 1 This is a flowchart of an adjacent four-vector synthesis method provided in an embodiment of the present invention;

[0054] Figure 2 The following is a distribution diagram of four vector combinations in a stationary coordinate system when the reference voltage vector is located in the first sector, provided as an embodiment of the present invention. Figure (a) is a leading quadrilateral voltage vector combination, Figure (b) is a regular quadrilateral voltage vector combination, and (c) is a lagging quadrilateral voltage vector combination.

[0055] Figure 3 This is a flowchart of a common-mode voltage suppression (PWM) method for inverters based on adjacent four vectors, provided in an embodiment of the present invention.

[0056] Figure 4 The present invention provides a switching sequence diagram under the adjacent four-vector synthesis rule of the first sector; wherein Figure (a) is a leading quadrilateral voltage vector combination switching sequence (1), Figure (b) is a leading quadrilateral voltage vector combination switching sequence (2), Figure (c) is a regular quadrilateral voltage vector combination switching sequence (1), Figure (d) is a regular quadrilateral voltage vector combination switching sequence (2), Figure (e) is a lagging quadrilateral voltage vector combination switching sequence (1), and Figure (f) is a lagging quadrilateral voltage vector combination switching sequence (2);

[0057] Figure 5 The figure shows the minimum amplitude analysis of the common-mode voltage volt-second characteristic under three different synthesis methods provided in an embodiment of the present invention, wherein the modulation degree in Figure (a) is 0.6 (m = 0.6) and the modulation degree in Figure (b) is 1.1 (m = 1.1);

[0058] Figure 6 This invention provides an embodiment of the graph, using a modulation depth of 0.8 as an example, to plot λ under different switching sequences. hn Line graph;

[0059] Figure 7 This is a schematic diagram of a common-mode voltage suppression (PWM) device for inverters based on adjacent four vectors, provided in an embodiment of the present invention.

[0060] Figure 8 This is a schematic diagram of a gallium nitride inverter control system according to an embodiment of the present invention;

[0061] Figure 9 The common-mode voltage-volt-second characteristic curves of a gallium nitride inverter using four pulse width modulation methods of the present invention under different modulation indices are provided for an embodiment of the present invention; wherein Figure (a) shows the modulation indices at 0.3 (m = 0.3), Figure (b) shows the modulation indices at 0.7 (m = 0.7), and Figure (c) shows the modulation indices at 1.15 (m = 1.15);

[0062] Figure 10 The following is a simulation comparison of harmonic distortion factors for controlling a resistive-inductive load using a gallium nitride inverter with four pulse width modulation methods of the present invention, provided as an embodiment of the present invention; wherein Figure (a) is a comparison curve of flux linkage ripple for voltage vectors at different angles for the four PWM methods when the modulation degree is 0.7 (m=0.7); and Figure (b) is a comparison of harmonic distortion factors for the three PWM methods under different modulation degrees (m from small to large).

[0063] Figure 11 The common-mode voltage diagram of the present invention using a gallium nitride inverter to control a resistive-inductive load at a modulation degree of 0.3 is provided for one embodiment of the present invention; wherein Figure (a) is an experimental diagram under the space vector pulse width modulation method (SVPWM), Figure (b) is an experimental diagram under the effective zero vector pulse width modulation method (AZSPWM), Figure (c) is an experimental diagram under the common-mode voltage suppression pulse width modulation method with zero-sequence voltage injection (AOZSVI-CMVRPWM), and Figure (d) is an experimental diagram under the adjacent four vector pulse width modulation method (A4V-CMVRPWM) of the present invention;

[0064] Figure 12 The common-mode voltage diagram of the present invention using a gallium nitride inverter to control a resistive-inductive load at a modulation index of 0.7 is provided for one embodiment of the present invention; wherein Figure (a) is an experimental diagram under the space vector pulse width modulation method (SVPWM), Figure (b) is an experimental diagram under the effective zero vector pulse width modulation method (AZSPWM), Figure (c) is an experimental diagram under the common-mode voltage suppression pulse width modulation method with zero-sequence voltage injection (AOZSVI-CMVRPWM), and Figure (d) is an experimental diagram under the adjacent four vector pulse width modulation method (A4V-CMVRPWM) of the present invention;

[0065] Figure 13This document presents a common-mode voltage diagram of a gallium nitride inverter controlling a resistive-inductive load at a modulation depth of 1.15, as provided in one embodiment of the present invention. Figure (a) shows an experimental diagram using the Space Vector Pulse Width Modulation (SVPWM) method, Figure (b) shows an experimental diagram using the Effective Zero Vector Pulse Width Modulation (AZSPWM) method, Figure (c) shows an experimental diagram using the Common-Mode Voltage Suppression Pulse Width Modulation (AOZSVI-CMVRPWM) method with zero-sequence voltage injection, and Figure (d) shows an experimental diagram using the Adjacent Four Vector Pulse Width Modulation (A4V-CMVRPWM) method described in this paper.

[0066] It should be noted that these accompanying drawings and textual descriptions are not intended to limit the scope of the invention in any way, but rather to illustrate the concept of the invention to those skilled in the art by referring to specific embodiments. Detailed Implementation

[0067] Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0068] It should be understood that the described embodiments are merely some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0069] The optional embodiments of this disclosure are described in detail below with reference to the accompanying drawings.

[0070] like Figure 1 As shown, this disclosure provides a method for synthesizing adjacent four vectors, the specific steps of which include:

[0071] Step S100: In the same sector, select the four vectors corresponding to the vertices of three isosceles trapezoids.

[0072] Step S110: The reference voltage vector exists within a triangular sector contained by two effective voltage vectors, and the triangle is surrounded by three isosceles trapezoids formed by the four vectors.

[0073] Specifically, each sector can be contained within three isosceles trapezoids. Taking the reference voltage vector located in the first sector as an example, ... Figure 2 As shown in the figure, based on the arrangement, all the alternative voltage combinations for all six sectors can be written out. Table 1 shows the four-vector combinations that can be selected for the sector containing the voltage vector.

[0074] Table 1

[0075]

[0076]

[0077] Where θ is the angle between the reference voltage vector and V1.

[0078] Step S120: Set the two effective voltage vectors closest to the reference voltage vector as the main voltage vectors. Define a quadrilateral voltage vector combination based on the relationship between the angles of the other two selected effective voltage vectors and the main voltage vectors. The quadrilateral voltage vector combination includes a leading four-vector combination, a lagging four-vector combination, and a positive four-vector combination.

[0079] Specifically, the two effective voltage vectors closest to the reference voltage vector are the main voltage vectors. Based on the relationship between the angles of the other two selected effective voltage vectors and the main voltage vectors, three quadrilateral voltage vector combinations are defined. If the other two selected voltage vectors both lead the main voltage vector, the four-vector voltage combination is defined as a leading quadrilateral voltage vector combination. If the other two selected voltage vectors both lag the main voltage vector, the four-vector voltage combination is defined as a lagging quadrilateral voltage vector combination. If one of the other two selected voltage vectors leads the main voltage vector and the other lags the main voltage vector, the four-vector voltage combination is defined as a regular quadrilateral voltage vector combination.

[0080] Taking the reference voltage vector in the first sector as an example (when θ is between 0 and 60 degrees), the four-vector voltage combinations that can be selected are: 1. V1, V2, V3, V4; 2. V6, V1, V2, V3; 3. V5, V6, V1, V2. The first type of voltage vector combination is defined as a leading quadrilateral voltage vector combination, the second type of voltage vector combination is defined as a regular quadrilateral voltage vector combination, and the third type is defined as a lagging quadrilateral voltage vector combination.

[0081] Step S130: Using the four effective voltage vectors corresponding to the vertices of the isosceles trapezoid within the sampling period and the duration of the four effective voltage vectors, the equivalent synthesis formula of the reference voltage vector is derived.

[0082] by Figure 2 As shown in the isosceles trapezoid, when the reference voltage vector is located in the isosceles trapezoid formed by four non-zero vectors V1, V2, V3 and V4, the reference voltage vector can be equivalently synthesized from V1, V2, V3 and V4 according to the following formula.

[0083]

[0084] In the formula, V1, V2, V3, and V4 are the four selected effective voltage vectors, t1', t2', t3', and t4' are the action times of the four selected effective voltage vectors, and T is the effective voltage vector. cThe sampling period is denoted by t1', t2', t3', and t4', respectively. In the formula, V1, V2, V3, and V4 satisfy the following equation with respect to t1', t2', t3', and t4':

[0085] 0≤t j '≤T c ,j=1,2,3,4 (2)

[0086] The following provides proof of the scientific validity and reference value of the rule for synthesizing adjacent four vectors for the reference sector.

[0087] Case 1: When the reference voltage vector is within the first sector

[0088] According to the quadrilateral rule:

[0089]

[0090] Substituting equation (3) into the equivalent synthesis formula (1), we obtain the following equation:

[0091]

[0092] The formula for calculating the reference voltage vector by combining the three most recent vectors in the first sector is given below:

[0093]

[0094] Where t0, t1, and t2 are the vector action times of the zero vector and the two effective voltage vectors under the most recent three-vector method, respectively.

[0095] Combining equations (4) and (5), we obtain the following equation:

[0096]

[0097] By examining equation (6), it is only necessary to satisfy the following equations to simultaneously satisfy equations (1) and (2), thus proving the effectiveness of the nearest four-vector synthesis rule when the reference voltage is in the first sector.

[0098] 0≤Δt≤min(t0,t2) (7)

[0099] In the formula, Δt is defined as the adjustment factor for the action time of adjacent four vectors.

[0100] Case 2: When the reference voltage vector is within the second sector

[0101] The formula for calculating the reference vector synthesized from the nearest three vectors when the reference voltage vector is within the second sector is given below:

[0102]

[0103] In the formula, t0, t2, and t3 are the action times of the zero vector, V2, and V3 under the recent three-vector synthesis rule, respectively.

[0104] According to the quadrilateral rule, we can obtain:

[0105]

[0106] Combining equations (1) and (9), we obtain the following equation:

[0107]

[0108] Substituting equation (9) into equation (10) and combining them with equation (8) for calculation, we can obtain the solution to the adjacent four-vector synthesis rule in the following equation:

[0109]

[0110] Considering equation (11), if the following equation is satisfied, equations (1) and (2) can be made to hold simultaneously, thus proving the effectiveness of the nearest four-vector synthesis rule when the reference voltage is in the second sector.

[0111]

[0112] Case 3: When the reference voltage vector is within the third sector

[0113] The formula for calculating the reference vector synthesized from the nearest three vectors when the reference voltage vector is within the third sector is given below:

[0114]

[0115] In the formula, t0, t3, and t4 are the action times of the zero vector, V3, and V4 under the recent three-vector synthesis rule, respectively.

[0116] According to the quadrilateral rule, we can obtain:

[0117]

[0118] Substituting equation (14) into equation (1) and combining them with equation (13), we obtain the following equation, which gives the solution to the rule of combining adjacent four vectors:

[0119]

[0120] Examining equation (15), it is only necessary to satisfy the following equation to make equations (1) and (2) hold simultaneously, thus proving the effectiveness of the nearest four-vector synthesis rule when the reference voltage is in the third sector.

[0121] 0≤Δt≤min(t0,t3) (16) Thus, the scientific validity and correctness of the adjacent four-vector composition rule have been effectively proven.

[0122] Step S140: For the three synthesis methods of leading quadrilateral voltage vector combination, regular quadrilateral voltage vector combination and lagging quadrilateral voltage vector combination, the equivalent synthesis formula is used to synthesize the reference voltage vector.

[0123] like Figure 3 As shown, this disclosure provides a common-mode voltage suppression (PWM) method for inverters based on adjacent four vectors. The method includes the following steps:

[0124] Step S200: The reference voltage vector is synthesized using the adjacent four-vector synthesis method described above, resulting in three synthesized reference voltage vectors.

[0125] Step S210: Based on the four-vector voltage combination, obtain the switching sequence that conforms to the pulse width modulation synthesis rule, and calculate the effective voltage vector action time of the synthesis reference voltage vector for the three synthesis methods.

[0126] Taking the first sector as an example, it is easy to see that for a set of four vectors (taking the leading quadrilateral voltage vector combination as an example), there are two types of switching sequences (forward (V1,V2,V3,V4) and reverse (V4,V3,V2,V1)). The selectable four-vector voltage combinations are: 1. V1,V2,V3,V4; 2. V6,V1,V2,V3; 3. V5,V6,V1,V2. The first voltage vector combination is defined as the leading quadrilateral voltage vector combination. The second voltage vector combination is a regular quadrilateral voltage vector combination, and the third is a lagging quadrilateral voltage vector combination. For a sector's reference voltage vector, there are six different switching sequences conforming to the pulse width modulation synthesis rule. The switching sequence diagram under the adjacent four-vector synthesis rule in the first sector is shown below. Figure 4 As shown.

[0127] In this embodiment of the application, the effective voltage vector action time of the synthesized reference voltage vector in the three synthesis methods is calculated, including:

[0128] Step S211: Obtain the constraint equation for the duration of the voltage vector by calculating the duration of action of the two effective voltage vectors and the duration of action of the zero vector when the three-vector synthesis is most recently performed.

[0129] Specifically, the calculation involves the durations (t1, t2) of the two effective voltage vectors (V1, V2) and the duration (t0) of the zero vector (V0) during the three-vector synthesis. The calculation equations are as follows:

[0130]

[0131]

[0132] In the formula, t0, t1, and t2 are the action times of the zero vector V0 and the effective voltage vectors V1 and V2 under the recent three-vector synthesis rule, respectively. dre V qref V ref Voltage components on the d-axis and q-axis, V d1 V q1 These are the voltage components of V1 on the d-axis and q-axis, respectively. d2 V q2 These are the voltage components of V2 on the d-axis and q-axis, respectively, T c The sampling period.

[0133] Step S212: Calculate the volt-second characteristics of the four-vector voltage combination, and simultaneously establish the constraint equations for the action time of the voltage vectors to obtain the equation set for the effective voltage vector action time.

[0134] Step S213: By solving the effective voltage vector action time equation set, calculate the action time of the leading quadrilateral voltage vector combination, the regular quadrilateral voltage vector combination, and the lagging quadrilateral voltage vector combination with time adjustment factors.

[0135] For the leading quadrilateral voltage vector combination (V1, V2, V3, V4), its volt-second characteristics are as follows:

[0136]

[0137] In the formula, t1', t2', t3', and t4' represent the action times of the four effective voltage vectors V1, V2, V3, and V4 selected in the leading quadrilateral voltage vector combination.

[0138] United V ref T c =V1t1+V2t2 gives:

[0139]

[0140] There are three constraint equations for the action time of the voltage vector, and four voltage vector action times need to be calculated. Therefore, there exists a time adjustment factor Δt that makes the above equations valid. This method is applicable to both regular quadrilateral voltage vector combinations and hysteretic quadrilateral voltage vector combinations.

[0141] For a quadrilateral voltage vector combination (V6, V1, V2, V3), its volt-second characteristic is as follows:

[0142] United V ref T c =V1t1+V2t2 gives:

[0143]

[0144] In the formula, t1', t2', t3', and t6' represent the durations of action of the four effective voltage vectors V1, V2, V3, and V6 selected in the quadrilateral voltage vector combination, respectively.

[0145] For the hysteresis quadrilateral voltage vector combination (V5, V6, V1, V2), its volt-second characteristic is as follows:

[0146]

[0147] United V ref T c =V1t1+V2t2 gives:

[0148]

[0149] In the formula, t1', t2', t5', and t6' represent the action times of the four effective voltage vectors V1, V2, V5, and V6 selected in the hysteresis quadrilateral voltage vector combination, respectively.

[0150] Step S220: Based on the sector position of the reference voltage vector, the DC bus voltage value of the inverter, and the effective voltage vector duration of the synthesized reference voltage vector, establish a constrained mathematical model with the goal of minimizing the common-mode voltage volt-second characteristics.

[0151] Without loss of generality, when the reference voltage vector is in the first sector, the common-mode voltage volt-second characteristics of the leading quadrilateral voltage vector combination (V1, V2, V3, V4) are as follows:

[0152]

[0153] The relationship between the action times of each voltage vector in the combined (20) leading quadrilateral voltage vector system is simplified as follows:

[0154]

[0155] The common-mode voltage volt-second characteristics of the quadrilateral voltage vector combination (V6, V1, V2, V3) are shown below:

[0156]

[0157] The relationship between the action times of each voltage vector in the quadrilateral voltage vector group in equation (22) is as follows: Its simplified model is as follows:

[0158]

[0159] The common-mode voltage volt-second characteristics of the hysteresis quadrilateral voltage vector combination (V5, V6, V1, V2) are shown below:

[0160]

[0161] The relationship between the action times of each voltage vector in the combination of hysteretic quadrilateral voltage vectors in equation (24) is as follows: Its simplified model is as follows:

[0162]

[0163] A constrained mathematical regularization model is established with the objective of minimizing the common-mode voltage volt-second characteristic as follows:

[0164]

[0165] Where t0, t1, and t2 represent the zero vector V0 and the effective voltage vector V1 and V2 under the recent three-vector synthesis rule, respectively.

[0166] Step S230: Find the optimal solution for the established constrained mathematical programming model and perform numerical analysis to obtain the optimized switching sequence and optimized action time corresponding to the two synthesis methods with the smallest volt-second characteristic amplitude.

[0167] By obtaining the optimal solution from the constrained mathematical programming model established by equation (31), we can obtain the solution according to... Figure 2 The optimal time adjustment factor Δt under the synthesis method shown in (a) is as follows:

[0168] Advanced quadrilateral voltage vector combination:

[0169] Regular quadrilateral voltage vector combination:

[0170] Hysteresis quadrilateral voltage vector combination:

[0171] min(V s_CMV The sign indicates that the common-mode voltage volt-second characteristic value in parentheses takes the smaller value within its respective Δt range.

[0172] Analysis of the minimum amplitude of common-mode voltage volt-second characteristic under three different synthesis methods is shown in the figure below. Figure 5 As shown. Type 1, 2, and 3 correspond to... Figure 2 The synthesis methods in (a), (b) and (c).

[0173] analyze Figure 5 It is not difficult to conclude that, with a modulation index of 0.6 and θ in the range of 0-30 degrees, Figure 2The minimum common-mode voltage volt-second amplitude corresponding to the synthesis methods in (b) and (c) is close to 0, and their common-mode voltage volt-second characteristics are superior to those in (b) and (c). Figure 2 The synthesis method in (a). When θ is in the range of 30 to 60 degrees. Figure 2 The minimum common-mode voltage volt-second amplitude corresponding to the synthesis methods in (a) and (b) is close to 0, and their common-mode voltage volt-second characteristics are superior. Figure 2 The synthesis method in (c). With a modulation density of 1.1, when θ is in the range of 0 to 30 degrees, Figure 2 The minimum common-mode voltage volt-second amplitude corresponding to the synthesis methods in (b) and (c) is better than Figure 2 The synthesis method in (a). When θ is in the range of 30 to 60 degrees. Figure 2 The common-mode voltage volt-second amplitude corresponding to the synthesis methods in (a) and (b) is better than Figure 2 The synthesis method in (c) is used. Therefore, the optimized switching sequence can be obtained as shown in Table 2.

[0174] Table 2

[0175]

[0176] Substituting the Δt for the optimal solution into the respective application time for each of the three cases, the optimal voltage vector application time for each case is obtained. The calculation process is as follows:

[0177] For the three different voltage vector combinations, there exists an optimal common-mode voltage volt-second characteristic corresponding to Δt. The optimal voltage vector action time for the leading quadrilateral voltage vector combination (V1, V2, V3, V4) is as follows:

[0178]

[0179] Substituting Δt into the expression for the action time containing Δt obtained from equation (20), the action time of each voltage vector can be obtained.

[0180]

[0181] The optimal voltage vector duration for the quadrilateral voltage vector combination (V6, V1, V2, V3):

[0182]

[0183] Substituting Δt into the expression for the action time containing Δt obtained from equation (22), the action time of each voltage vector can be obtained.

[0184]

[0185] The optimal voltage vector action time for the hysteresis quadrilateral voltage vector combination (V5, V6, V1, V2):

[0186]

[0187] Substituting Δt into the expression for the action time containing Δt obtained from equation (24), the action time of each voltage vector can be obtained.

[0188]

[0189] Step S240: For the optimized switching sequences corresponding to the two synthesis methods that obtain the minimum volt-second characteristic amplitude, calculate the flux linkage ripple of the optimized switching sequences respectively, and select the switching sequence with the minimum flux linkage ripple to optimize the output harmonic performance.

[0190] Since the switching sequences obtained in the table above are not unique and produce different output harmonic characteristics, the optimal switching sequence is selected by using the voltage vector combination corresponding to the optimized switching sequences and related information, and by applying the constraint mathematical model in the following formula and the table above. The formula for calculating the flux linkage ripple is as follows:

[0191]

[0192] Where δ is the duty cycle, λ hn λ is the root mean square value of the flux linkage ripple per unit within one carrier cycle. hn λ is the per-unit value of the flux linkage ripple. hn It can be calculated using the following formula:

[0193]

[0194] In the formula, N is a non-negative integer, and V kh This is the error vector.

[0195] Taking a modulation density of 0.8 as an example, the λ values ​​under different switching sequences are plotted. hn Line graph, such as Figure 6 As shown.

[0196] The same analysis yields the optimal switching sequence lists for modulation degrees less than 1 in Table 3 and greater than 1 in Table 4.

[0197] Table 3

[0198]

[0199] Table 4

[0200]

[0201]

[0202] Figure 7 This invention illustrates a common-mode voltage suppression (PWM) device for inverters based on adjacent four vectors, the device comprising:

[0203] The module for synthesizing a reference voltage vector is used to synthesize a reference voltage vector into three adjacent four-vector composites using the above-mentioned adjacent four-vector composite method, thereby obtaining a composite reference voltage vector in three different ways.

[0204] The effective voltage vector action time calculation module is used to derive a switching sequence that conforms to the pulse width modulation synthesis rule based on the combination of four vector voltages, and to calculate the effective voltage vector action time of the synthesized reference voltage vector for the three synthesis methods.

[0205] The constrained mathematical programming model module is used to establish a constrained mathematical programming model with the goal of minimizing the common-mode voltage volt-second characteristics, based on the sector position of the reference voltage vector, the DC bus voltage value of the inverter, and the effective voltage vector duration of the synthesized reference voltage vector.

[0206] The module for optimizing the switching sequence and optimizing the action time is used to obtain the optimal solution for the established constrained mathematical rule model and perform numerical analysis to obtain the optimized switching sequence and optimized action time corresponding to the two synthesis methods with the smallest volt-second characteristic amplitude.

[0207] The flux linkage ripple optimization module is used to calculate the flux linkage ripple of the optimized switching sequence output by the common-mode voltage volt-second characteristic optimization module and select the switching sequence with the minimum flux linkage ripple.

[0208] It should be noted that the inverter common-mode voltage suppression PWM method based on adjacent four vectors provided in the above embodiments is only an example of the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the inverter common-mode voltage suppression PWM device based on adjacent four vectors and the inverter common-mode voltage suppression PWM method embodiment based on adjacent four vectors are based on the same concept. The implementation process is detailed in the inverter common-mode voltage suppression PWM method embodiment based on adjacent four vectors, and will not be repeated here.

[0209] like Figure 8As shown, in one embodiment, a gallium nitride inverter control system is proposed. The system includes: the aforementioned inverter common-mode voltage suppression PWM device based on adjacent four vectors, a drive circuit module, a gallium nitride inverter module with a common-mode choke, and a load module. The inverter common-mode voltage suppression PWM device based on adjacent four vectors calculates in a digital signal processor to obtain an optimal switching sequence and inputs this switching sequence into the gallium nitride inverter module with a common-mode choke through the drive circuit module to achieve the purpose of controlling the load module.

[0210] Figure 9 The graph shows the common-mode voltage volt-second characteristic of using a gallium nitride inverter to control a resistive-inductive load with the four pulse width modulation methods of this invention. Figure 10 Simulation comparison chart of using gallium nitride inverters to control resistive-inductive loads with harmonic distortion factors using the four pulse width modulation methods of this invention.

[0211] Figure 11 Tables 12 and 13 show the common-mode voltage diagrams of gallium nitride inverters controlling resistive-inductive loads using the present invention at modulation depths of 0.3, 0.7, and 1.15, respectively. Tables 5 and 6 below are, in order, the peak value table of common-mode voltage volt-second characteristics and the harmonic factor calculation table.

[0212] Table 5

[0213]

[0214]

[0215] Table 6

[0216]

[0217] By observing Tables 5 and 6, Figures 9 to 13 It can be seen that this technology has better common-mode voltage suppression and harmonic suppression effects compared with existing modulation methods in simulation and experiment. It has achieved layer-by-layer optimization of common-mode voltage volt-second characteristics and output harmonic performance, and on this basis, it has made full use of control degrees of freedom to optimize output harmonic performance.

[0218] Numerous specific details are set forth in the specification provided herein. However, it will be understood that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques have not been shown in detail so as not to obscure the understanding of this specification.

[0219] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features found in other embodiments but not others, combinations of features from different embodiments are also within the scope of protection of this invention and form different embodiments. For example, in the embodiments described above, those skilled in the art can use them in combination based on known technical solutions and the technical problems to be solved by this application.

[0220] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-described technical content to create equivalent embodiments without departing from the scope of the present invention. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the present invention shall still fall within the scope of the present invention.

Claims

1. A common-mode voltage suppression (PWM) method for inverters based on adjacent four vectors, characterized in that, The method includes: A method for synthesizing adjacent four vectors applicable to space voltage vector pulse width modulation technology; the method includes: Step S100: In the same sector, select the four vectors corresponding to the vertices of three isosceles trapezoids; Step S110: The reference voltage vector exists within a triangular sector contained by two effective voltage vectors, and the triangle is surrounded by three isosceles trapezoids formed by four vectors; Step S120: Set the two effective voltage vectors closest to the reference voltage vector as the main voltage vectors. Define a quadrilateral voltage vector combination based on the relationship between the angles of the other two selected effective voltage vectors and the main voltage vectors. The quadrilateral voltage vector combination includes a leading quadrilateral voltage vector combination, a lagging quadrilateral voltage vector combination, and a regular quadrilateral voltage vector combination. A leading quadrilateral voltage vector combination is formed when the other two selected voltage vectors both lead the main voltage vector; a lagging quadrilateral voltage vector combination is formed when the other two selected voltage vectors both lag the main voltage vector; a quadrilateral voltage vector combination is formed when one of the other two selected voltage vectors leads the main voltage vector and the other lags the main voltage vector. Step S130: Using the four effective voltage vectors corresponding to the vertices of the isosceles trapezoid within the sampling period and the duration of the four effective voltage vectors, the equivalent synthesis formula of the reference voltage vector is derived. Step S140: For the three synthesis methods of leading quadrilateral voltage vector combination, regular quadrilateral voltage vector combination and lagging quadrilateral voltage vector combination, the equivalent synthesis formula is used to synthesize the reference voltage vector; Step S200: The adjacent four-vector synthesis method is used to synthesize the reference voltage vector into three synthesized reference voltage vectors. Step S210: Based on the four-vector voltage combination, obtain the switching sequence that conforms to the pulse width modulation synthesis rule, and calculate the effective voltage vector action time of the synthesis reference voltage vector for the three synthesis methods; Step S220: Based on the sector position of the reference voltage vector, the DC bus voltage value of the inverter, and the effective voltage vector duration of the synthesized reference voltage vector, establish a constrained mathematical rule model with the goal of minimizing the common-mode voltage volt-second characteristics; Step S230: Find the optimal solution for the established constrained mathematical rule model and perform numerical analysis to obtain the optimized switching sequence and optimized action time corresponding to the two synthesis methods with the smallest volt-second characteristic amplitude; Step S240: For the optimized switching sequences corresponding to the two synthesis methods that obtain the minimum volt-second characteristic amplitude, calculate the flux linkage ripple of the optimized switching sequences respectively, and select the switching sequence with the minimum flux linkage ripple to optimize the output harmonic performance.

2. The inverter common-mode voltage suppression PWM method based on adjacent four vectors according to claim 1, characterized in that, When the reference voltage vector is in a state consisting of four non-zero vectors and When the reference voltage vector is within the isosceles trapezoid formed by the reference voltage vector, the equivalent synthesis formula is as follows: ， In the formula, These are the four selected effective voltage vectors, These represent the durations of action of the four selected effective voltage vectors. The sampling period is given by the formula. respectively with satisfy: .

3. The inverter common-mode voltage suppression PWM method based on adjacent four vectors according to claim 1, characterized in that, The calculation of the effective voltage vector action time of the synthesized reference voltage vector in the three synthesis methods includes: By calculating the duration of action of the two effective voltage vectors and the duration of action of the zero vector when the three most recent vectors are combined, the constraint equation for the duration of action of the voltage vector is obtained. Calculate the volt-second characteristics of the four-vector voltage combination, and simultaneously establish the constraint equations for the duration of the voltage vectors to obtain the equation set for the duration of the effective voltage vectors. By solving the effective voltage vector action time equations, the action time of the leading quadrilateral voltage vector combination, the regular quadrilateral voltage vector combination, and the lagging quadrilateral voltage vector combination with time adjustment factors are calculated respectively.

4. The inverter common-mode voltage suppression PWM method based on adjacent four vectors according to claim 3, characterized in that, The constraint equation for the duration of action of the voltage vector is: ， ， In the formula, The zero vector under the nearest three-vector composition rule is respectively and effective voltage vector , Duration of action , They are respectively Voltage components on the d-axis and q-axis , They are respectively Voltage components on the d-axis and q-axis , They are respectively Voltage components on the d-axis and q-axis The sampling period.

5. The inverter common-mode voltage suppression PWM method based on adjacent four vectors according to claim 4, characterized in that, The constrained mathematical rule model established with the objective of minimizing the common-mode voltage volt-second characteristic is as follows: ， in, V s_CMV This is a common-mode voltage volt-second characteristic quantity. This is the adjustment factor for the action time of adjacent four vectors.

6. The inverter common-mode voltage suppression PWM method based on adjacent four vectors according to claim 5, characterized in that, The optimal adjustment factor for the action time of adjacent four vectors under the synthesis method can be obtained by finding the optimal solution through a constrained mathematical rule model. The adjustment factors for the adjacent four-vector action time of the three synthesis methods are: ， in, This represents the common-mode voltage volt-second characteristic quantity in parentheses in its respective... Take the smaller value from the range of possible values.

7. The inverter common-mode voltage suppression PWM method based on adjacent four vectors according to claim 6, characterized in that, The formula for calculating the magnetic flux ripple is as follows: ， In the formula, Duty cycle, This represents the root mean square value of the flux linkage ripple per unit within one carrier cycle. This represents the per-unit value of the flux linkage ripple. It can be calculated using the following formula: ， In the formula, N It is a non-negative integer. This is the error vector.

8. A common-mode voltage suppression (PWM) device for inverters based on adjacent four vectors, characterized in that, The apparatus for implementing the inverter common-mode voltage suppression PWM method based on adjacent four vectors as described in any one of claims 1 to 7 includes: The synthesized reference voltage vector module is used to synthesize the reference voltage vector into three adjacent four-vector composites using the adjacent four-vector composite method, resulting in a synthesized reference voltage vector in three different ways. The effective voltage vector action time calculation module is used to derive a switching sequence that conforms to the pulse width modulation synthesis rule based on the combination of four vector voltages, and to calculate the effective voltage vector action time of the synthesized reference voltage vector for the three synthesis methods. The constrained mathematical rule model module is used to establish a constrained mathematical rule model with the goal of minimizing the common-mode voltage volt-second characteristics, based on the sector position of the reference voltage vector, the DC bus voltage value of the inverter, and the effective voltage vector action time of the synthesized reference voltage vector. The module for optimizing the switching sequence and optimizing the action time is used to obtain the optimal solution for the established constrained mathematical rule model and perform numerical analysis to obtain the optimized switching sequence and optimized action time corresponding to the two synthesis methods with the smallest volt-second characteristic amplitude. The flux linkage ripple optimization module is used to calculate the flux linkage ripple of the optimized switching sequence output by the common-mode voltage volt-second characteristic optimization module and select the switching sequence with the minimum flux linkage ripple.

9. A gallium nitride inverter control system, characterized in that, The system includes: the inverter common-mode voltage suppression PWM device based on adjacent four vectors as described in claim 8, a drive circuit module, a gallium nitride inverter module with a common-mode choke, and a load module; the inverter common-mode voltage suppression PWM device based on adjacent four vectors calculates in a digital signal processor to obtain an optimal switching sequence and inputs this switching sequence into the gallium nitride inverter module with a common-mode choke through the drive circuit module to achieve the purpose of controlling the load module.

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