An optical modulator driver and optical transmitter

Abstract

The application discloses an optical modulator driver and an optical transmitter, and relates to the technical fields of optical communication and integrated circuits, and comprises an input impedance matching circuit, a variable gain amplification circuit and a differential output buffer circuit which are connected in sequence; the input impedance matching circuit is used for outputting a differential input signal after impedance matching; the variable gain amplification circuit is used for outputting a signal after gain amplification of the input impedance matching circuit after impedance matching; the differential output buffer circuit comprises a dynamic bias circuit and a common-emitter common-base equalizer circuit; the dynamic bias circuit is used for outputting a dynamic bias voltage required by a signal amplified by the variable gain amplification circuit to the common-emitter common-base equalizer circuit, so that the amplitude of a signal output by the common-emitter common-base equalizer circuit reaches a preset amplitude threshold value. The application can break through the limitation of the transistor breakdown voltage of the existing integrated circuit process, and realize single-ended output of a 2V or above swing signal in a single chip.

Description

Technical Field

[0001] This invention relates to the fields of optical communication technology and integrated circuits, and particularly to an optical modulator driver and an optical transmitter. Background Technology

[0002] Fiber optic communication, a pillar of the communications industry, is the most widely used communication method in our society today. It is an advanced communication technology that uses light waves as the carrier and optical fiber as the transmission medium. As the cornerstone of modern communication systems, it possesses numerous advantages unmatched by other communication systems, such as long-distance transmission, ultra-high speed, and large capacity. A fiber optic communication system mainly consists of three parts: an optical transmitter, an optical fiber channel, and an optical receiver. The optical transmitter primarily comprises an optical modulator and an optical modulator driver. Its function is to amplify electrical signals to drive the optical modulator, modulate the optical signal, and then transmit the resulting optical signal through an optical fiber or cable for transmission. The performance of the optical transmitter directly determines the rate, quality, and transmission distance of the transmitted optical signal.

[0003] As a crucial component of an optical transmitter, the optical modulator driver amplifies electrical signals and then drives the optical modulator to control the intensity of light emitted by the optical module. It is the key component in the conversion of electrical signals into optical signals. The performance of the optical modulator driver determines the performance of the entire optical transmitter. In particular, the output amplitude of the optical modulator driver affects the critical performance parameter of the optical modulator's output power.

[0004] Currently, most integrated circuits in the field of optical communication are based on SiGe or CMOS processes. Due to the shortcomings of CMOS technology in terms of parasitic capacitance, transconductance, and noise, it is mainly used in analog integrated circuits with speeds below 10 Gbps, while SiGe technology is mainly used for complex analog integrated circuits with speeds of 10 Gbps and above. The breakdown voltage of high-speed CMOS devices is generally around 1V, and the breakdown voltage of SiGe devices does not exceed 1.5V. Therefore, due to the limitation of breakdown voltage, it is difficult to achieve single-ended output of a swing signal above 2V. Typically, to obtain sufficient optical power, the output signal swing of the corresponding driver in an optical modulator needs to be as large as possible. Therefore, how to achieve a monolithically integrated optical modulator driver chip with a large swing output that meets the application requirements of optical modulators is a significant challenge and an urgent problem to be solved with current technology. Summary of the Invention

[0005] This invention provides an optical modulator driver and an optical transmitter to solve the technical problem in the related art that it is difficult to meet the requirements of large swing output and monolithic integration application of optical modulator drivers based on existing integrated circuit processes.

[0006] In a first aspect, an optical modulator driver is provided, characterized in that it comprises: an input impedance matching circuit, a variable gain amplifier circuit, and a differential output buffer circuit connected in sequence;

[0007] The input impedance matching circuit is used to output the differential input signal after impedance matching.

[0008] The variable gain amplifier circuit is used to amplify the signal gain after impedance matching by the input impedance matching circuit and then output it.

[0009] The differential output buffer circuit includes a dynamic bias circuit and a common-emitter common-base equalizer circuit. The dynamic bias circuit is used to apply a dynamic bias voltage to the common-emitter common-base equalizer circuit according to the signal output requirements after the gain amplification of the variable gain amplifier circuit, so that the amplitude of the output signal of the common-emitter common-base equalizer circuit reaches a preset amplitude threshold.

[0010] In some embodiments, the dynamic bias circuit includes two symmetrical dynamic bias units, and the common-emitter common-base equalizer circuit includes two symmetrical first equalizer units.

[0011] Each of the aforementioned dynamic bias units includes a symmetrical first transistor, a second transistor, a first resistor, a second resistor, and a first current source, wherein the first resistor and the second resistor are both adjustable resistors;

[0012] The base of the first transistor and the base of the second transistor serve as the input terminals of the dynamic bias unit to receive a differential input signal. The collector of the first transistor is connected to the power supply, the emitter of the first transistor is connected to the first terminal of the first current source and a corresponding first equalizer unit, and the second terminal of the first current source is grounded.

[0013] The first end of the second resistor is connected to the power supply, the second end of the second resistor is connected to the collector of the second transistor and a corresponding first equalizer unit, the emitter of the second transistor is connected to the first end of the first resistor, and the second end of the first resistor is grounded.

[0014] In some embodiments, each of the first equalizer units includes a third transistor, a fourth transistor, a third resistor, and a second current source;

[0015] The base of the third transistor is connected to the emitter of the first transistor, the collector of the third transistor is connected to the emitter of the fourth transistor, the emitter of the third transistor is connected to the first terminal of the second current source, and the second terminal of the second current source is grounded.

[0016] The first end of the third resistor is connected to the power supply, and the second end of the third resistor is connected to the collector of the fourth transistor and serves as the output end of the first equalizer unit.

[0017] The base of the fourth transistor is connected to the collector of the second transistor.

[0018] In some embodiments, the common-emitter common-base equalizer circuit further includes a second capacitor and a fourth resistor, the two ends of which are connected in parallel to the emitters of the two third transistors, respectively.

[0019] In some embodiments, each of the dynamic bias units further includes a first capacitor, a first terminal of which is connected to the collector of the second transistor, and a second terminal of which is grounded.

[0020] In some embodiments, the variable gain amplifier circuit includes a first-stage amplifier circuit, a second-stage amplifier circuit, and a bias control circuit;

[0021] The first-stage amplifier circuit is used to linearly amplify the signal output from the input impedance matching circuit and then output it.

[0022] The second-stage amplifier circuit is used to linearly amplify the signal after it has been linearly amplified by the first-stage amplifier circuit again and output it to the differential output buffer circuit.

[0023] The bias control circuit is used to provide a gain adjustment control voltage to the first-stage amplifier circuit and the second-stage amplifier circuit.

[0024] In some embodiments, the first-stage amplifier circuit includes two symmetrically crossed second equalizer units and two symmetrical first follower units;

[0025] Each of the second equalizer units includes a fifth transistor, a sixth transistor, a seventh transistor, a fifth resistor, a sixth resistor, a seventh resistor, and a third current source;

[0026] The base of the fifth transistor is connected to the input impedance matching circuit as the input terminal of the second equalizer unit. The emitter of the fifth transistor is connected to the first terminal of the third current source. The collector of the fifth transistor is connected to the emitter of the sixth transistor and the emitter of the seventh transistor of another second equalizer unit.

[0027] The base of the sixth transistor is connected to a first control voltage, and the collector of the sixth transistor is connected to the second terminal of the fifth resistor; the first terminal of the fifth resistor is connected to the first terminal of the sixth resistor and the second terminal of the seventh resistor; the first terminal of the seventh resistor is connected to a power supply, and the second terminal of the sixth resistor is connected to the collector of the seventh transistor.

[0028] The base of the seventh transistor is connected to the second control voltage, and the emitter of the seventh transistor is connected to the collector of the fifth transistor of another second equalizer unit.

[0029] Each of the first follower units includes an eighth transistor, a ninth transistor, an eighth resistor, and a fourth current source;

[0030] The first end of the eighth resistor is connected to the power supply, and the second end of the eighth resistor is connected to the collector of the eighth transistor.

[0031] The base of the eighth transistor is connected to the first end of the fifth resistor, and the emitter of the eighth transistor is connected to the collector and base of the ninth transistor.

[0032] The emitter of the ninth transistor is connected to the first terminal of the fourth current source, and the second terminal of the fourth current source is grounded.

[0033] In some embodiments, the second-stage amplifier circuit and the first-stage amplifier circuit have the same circuit structure.

[0034] In some embodiments, the input impedance matching circuit includes an impedance matching unit and a second follower unit;

[0035] The impedance matching unit includes a first MOSFET, a second MOSFET, a third MOSFET, a ninth resistor, a tenth resistor, an operational amplifier, and a fifth current source;

[0036] The drain of the first MOS transistor is connected to the second terminal of the ninth resistor and receives a differential input signal. The first terminal of the ninth resistor is connected to the gate of the first MOS transistor and the drain of the third MOS transistor.

[0037] The drain of the second MOS transistor is connected to the second terminal of the tenth resistor and receives another differential input signal. The first terminal of the tenth resistor is connected to the gate of the second MOS transistor and the drain of the third MOS transistor.

[0038] The source of the first MOSFET and the source of the second MOSFET are both connected to the first terminal of the fifth current source, and the second terminal of the fifth current source is grounded.

[0039] The output terminal of the operational amplifier is connected to the gate of the third MOS transistor, the inverting input terminal of the operational amplifier is connected to the reference voltage, and the source of the third MOS transistor is connected to the power supply.

[0040] The second follower unit includes a thirteenth transistor, an eleventh transistor, an eleventh resistor, a twelfth resistor, a sixth current source, and a seventh current source;

[0041] The base of the thirteenth transistor and the base of the eleventh transistor each receive a differential input signal, and the collectors of the thirteenth transistor and the eleventh transistor are both connected to a power supply.

[0042] The emitter of the thirteenth transistor is connected to the first terminal of the sixth current source as an output terminal of the impedance matching unit, and the second terminal of the sixth current source is grounded.

[0043] The emitter of the eleventh transistor is connected to the first terminal of the seventh current source as another output terminal of the impedance matching unit, and the second terminal of the seventh current source is grounded.

[0044] The two ends of the series connection between the eleventh resistor and the twelfth resistor are respectively connected to the emitter of the thirteenth transistor and the emitter of the eleventh transistor.

[0045] The common terminal of the eleventh resistor and the twelfth resistor connected in series is connected to the non-inverting input terminal of the operational amplifier.

[0046] Secondly, an optical transmitter is provided, including the aforementioned optical modulator driver.

[0047] The beneficial effects of the technical solution provided by this invention include:

[0048] This invention provides an optical modulator driver and an optical transmitter. The optical modulator driver has a differential output buffer circuit with a dynamic bias circuit and a common-emitter / common-base equalizer circuit. This allows the optical modulator driver to achieve single-ended output of a swing signal exceeding 2V, provided that the internal transistors do not exceed the breakdown voltage of the integrated circuit process. In other words, this invention enables the maximum output amplitude of the optical modulator driver to break through the breakdown voltage limitation of existing integrated circuit processes, fulfilling the application requirements of large-swing output and monolithic integration for optical modulator drivers. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0050] Figure 1 A schematic block diagram of an optical modulator driver provided for an embodiment of the present invention;

[0051] Figure 2 A circuit diagram of a differential output buffer circuit provided in an embodiment of the present invention;

[0052] Figure 3 A circuit diagram of the first amplifier circuit provided in an embodiment of the present invention;

[0053] Figure 4 A circuit diagram of the input impedance matching circuit provided in an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram of the simulation results of an optical modulator driver provided in an embodiment of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0056] This invention provides an optical modulator driver that solves the technical problem in the prior art that it is difficult to meet the requirements of large swing output and monolithic integration application of optical modulator drivers based on existing integrated circuit processes.

[0057] See Figure 1 As shown, an embodiment of the present invention provides an optical modulator driver, comprising: an input impedance matching circuit, a variable gain amplifier circuit, and a differential output buffer circuit connected in sequence;

[0058] The input impedance matching circuit is used to output the differential input signal after impedance matching, and the variable gain amplifier circuit is used to amplify the signal gain after impedance matching by the input impedance matching circuit before outputting.

[0059] The differential output buffer circuit includes a dynamic bias circuit and a common-emitter common-base equalizer circuit. The dynamic bias circuit is used to output an adjustable dynamic bias voltage to the common-emitter common-base equalizer circuit according to the signal amplified by the variable gain amplifier circuit, so that the amplitude of the output signal of the common-emitter common-base equalizer circuit reaches a preset amplitude threshold.

[0060] The optical modulator driver in this embodiment of the invention includes a differential output buffer circuit with a dynamic bias circuit and a common-emitter, common-base equalizer circuit. This allows the optical modulator driver to achieve single-ended output of a swing signal of over 2V (differential output of over 4V) while ensuring that the internal transistors do not exceed the breakdown voltage of the integrated circuit process. In other words, this invention enables the maximum output amplitude of the optical modulator driver to break through the breakdown voltage limitation of existing integrated circuit processes, fulfilling the application requirements of large-swing output and monolithic integration for optical modulator drivers.

[0061] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 2 As shown, the dynamic bias circuit includes two symmetrical dynamic bias units, and the common-emitter common-base equalizer circuit includes two symmetrical first equalizer units. Figure 2 The area within the dashed box is the common-emitter, common-base equalizer circuit, while the areas on either side of the dashed box are dynamic bias circuits.

[0062] Each of the aforementioned dynamic bias units includes a symmetrical first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, and a first current source I1, wherein the first resistor R1 and the second resistor R2 are both adjustable resistors. Optionally, the first transistor Q1 and the second transistor Q2 are both NPN transistors.

[0063] The base of the first transistor Q1 and the base of the second transistor Q2 serve as the input terminals of the dynamic bias unit to receive a differential input signal. The collector of the first transistor Q1 is connected to the power supply, and the emitter of the first transistor Q1 is connected to the first terminal of the first current source I1 and a corresponding first equalizer unit. The second terminal of the first current source I1 is grounded.

[0064] The first end of the second resistor R2 is connected to the power supply, the second end of the second resistor R2 is connected to the collector of the second transistor Q2 and a corresponding first equalizer unit, the emitter of the second transistor Q2 is connected to the first end of the first resistor, and the second end of the first resistor R1 is grounded.

[0065] See Figure 2As shown, the second transistor Q2, the first resistor R1, and the second resistor R2 constitute a common-emitter amplifier circuit, which provides dynamic bias voltage for the corresponding first equalizer unit. The differential input terminal InP is connected to the base of the second transistor Q2, and the collector of the second transistor Q2 is the output node A of the common-emitter amplifier circuit. Adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 changes the gain of the common-emitter amplifier circuit, thereby changing the swing of the output signal at node A, which is the magnitude of the dynamic bias of the corresponding first equalizer unit. This allows the maximum output amplitude of the corresponding first equalizer unit to exceed the chip process breakdown voltage limit, achieving single-ended output of a swing signal above 2V, realizing a monolithically integrated optical modulator driver that meets the requirements for large-swing output. Furthermore, the first transistor Q1 and the first current source I1 constitute a follower circuit. The output terminal of the follower circuit, i.e., the emitter of the first transistor Q1, is the input signal terminal of the corresponding first equalizer unit. In addition, a diode D1 can be placed between the collector of the first transistor Q1 and the power supply to consume a certain voltage margin and ensure the reliability of the first transistor Q1.

[0066] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 2 As shown, each of the first equalizer units includes a third transistor Q3, a fourth transistor Q4, a third resistor R3, and a second current source I2.

[0067] The base of the third transistor Q3 is connected to the emitter of the first transistor Q1, the collector of the third transistor Q3 is connected to the emitter of the fourth transistor Q4, the emitter of the third transistor Q3 is connected to the first terminal of the second current source I2, and the second terminal of the second current source I2 is grounded.

[0068] The first end of the third resistor R3 is connected to the power supply, and the second end of the third resistor R3 is connected to the collector of the fourth transistor Q4 and serves as the output terminal of the first equalizer unit. The base of the fourth transistor Q4 is connected to the collector of the second transistor Q2.

[0069] Optionally, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 may be NPN transistors.

[0070] See Figure 2As shown, the third transistor Q3 and the fourth transistor Q4 form a common-emitter, common-base configuration. The second current source I2 is its tail current source, and the third resistor R3 is its load resistor. The collector of the second transistor Q2 in the dynamic bias unit is connected to the base of the fourth transistor Q4 in the first equalizer unit. Adjusting the resistance values ​​of the first resistor R1 and the second resistor R2 can change the swing of the output signal at node A, that is, the magnitude of the dynamic bias voltage of the fourth transistor Q4. This adjusts the magnitude of the voltage at the emitter node A0 of the fourth transistor Q4, which follows the in-phase change of the signal at the output node OutN. In this way, under a large output swing, the common-emitter, common-base configuration can ensure that the Vce voltage of the fourth transistor Q4 does not exceed the breakdown voltage BVceo of its integrated circuit process. At this time, the voltage difference Vce between the collector and emitter of the third transistor Q3 and the fourth transistor Q4 in the common-emitter, common-base circuit does not exceed the process breakdown voltage BVceo. See also Figure 5 As shown, the single-ended output amplitude is close to 2V, while the voltage difference Vce is always less than 1V, meeting the reliability requirements. Furthermore, the dimensions of the second transistor Q2, the fourth transistor Q4, the second resistor R2, and the first capacitor C1 can be adjusted to synchronize the conduction and cutoff of the second transistor Q2 in the dynamic bias unit with the common-emitter, common-base transistors Q3 and Q4 in the first equalizer unit. This reduces the impact of the dynamic bias unit on the output signal quality, ultimately improving the overall performance of the circuit. Additionally, the value of the third resistor R3 is typically between 50 ohms and 60 ohms to meet the impedance matching requirements of the optical modulator.

[0071] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 2 As shown, the common-emitter, common-base equalizer circuit also includes a second capacitor C2 and a fourth resistor R4. The two ends of the parallel connection between the second capacitor C2 and the fourth resistor R4 are respectively connected to the emitters of the two third transistors. This parallel connection generates two poles and one zero, providing a gain peak at high frequencies to compensate for signal attenuation at high frequencies. The bandwidth can be extended by adjusting the values ​​of the second capacitor C2 and the fourth resistor R4 according to the overall circuit specifications.

[0072] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 2As shown, each of the dynamic biasing units further includes a first capacitor C1. The first terminal of the first capacitor C1 is connected to the collector of the second transistor Q2, and the second terminal of the first capacitor C1 is grounded. Each dynamic biasing unit has two signal transmission paths: transmission path one is the path between the second transistor Q2 and the fourth transistor Q4, and transmission path two is the path between the first transistor Q1 and the third transistor Q3. To avoid inconsistent delays of the input signal in the two signal transmission paths, which would lead to a degradation of the output signal quality of the output buffer, the first capacitor C1 is added because the output impedance of the third transistor Q3 in transmission path two is higher than that of the second transistor Q2 in transmission path one, resulting in a longer delay in transmission path two than in transmission path one. This ensures that the delays of the two signal transmission paths are consistent.

[0073] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 1 As shown, the variable gain amplifier circuit includes a first-stage amplifier circuit, a second-stage amplifier circuit, and a bias control circuit.

[0074] The first-stage amplifier circuit linearly amplifies the differential signal output from the input impedance matching circuit before outputting it. Simultaneously, the first-stage amplifier circuit can adjust the control voltage of the variable gain amplifier according to performance requirements to obtain different gain levels.

[0075] The second-stage amplifier circuit is used to linearly amplify the signal after it has been linearly amplified by the first-stage amplifier circuit again and output it to the differential output buffer circuit.

[0076] The bias control circuit is used to provide a gain adjustment control voltage to the first-stage amplifier circuit and the second-stage amplifier circuit.

[0077] Further, see Figure 3 As shown, the first-stage amplifier circuit includes two symmetrically crossed second equalizer units and two symmetrical first follower units. Figure 3 The area within the dashed box contains two symmetrically intersecting second equalizer units, while the areas on either side of the dashed box contain two first follower units.

[0078] Each of the second equalizer units includes a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, and a third current source I3.

[0079] The base of the fifth transistor Q5 is connected to the input impedance matching circuit as the input terminal of the second equalizer unit. The emitter of the fifth transistor Q5 is connected to the first terminal of the third current source I3. The collector of the fifth transistor Q5 is connected to the emitter of the sixth transistor Q6 and the emitter of the seventh transistor Q7 of the other second equalizer unit.

[0080] The base of the sixth transistor Q6 is connected to the first control voltage, and the collector of the sixth transistor Q6 is connected to the second end of the fifth resistor R5; the first end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the second end of the seventh resistor R7; the first end of the seventh resistor R7 is connected to the power supply, and the second end of the sixth resistor R6 is connected to the collector of the seventh transistor Q7.

[0081] The base of the seventh transistor Q7 is connected to the second control voltage, and the emitter of the seventh transistor Q7 is connected to the collector of the fifth transistor Q5 of another second equalizer unit.

[0082] Each of the first follower units includes an eighth transistor Q8, a ninth transistor Q9, an eighth resistor R8, and a fourth current source I4.

[0083] The first terminal of the eighth resistor R8 is connected to a power supply, and the second terminal of the eighth resistor R8 is connected to the collector of the eighth transistor Q8. The base of the eighth transistor Q8 is connected to the first terminal of the fifth resistor R5, and the emitter of the eighth transistor Q8 is connected to both the collector and base of the ninth transistor Q9. The emitter of the ninth transistor Q9 is connected to the first terminal of the fourth current source I4, and the second terminal of the fourth current source I4 is grounded.

[0084] In this configuration, the fifth transistor Q5 and the sixth transistor Q6 form a common-emitter, common-base structure, with the third current source I3 serving as its tail current source, and the fifth resistor R5 as its load resistor. The collectors of the two fifth transistors Q5 are cross-connected to the emitters of the two seventh transistors Q7, respectively. By adjusting the first control voltage Vctrl1 and the second control voltage Vctrl2, the current flowing through the fifth resistor R5 and the sixth resistor R6 in the two resistor branches at the output nodes P and N can be changed, thereby adjusting the gain. Since the two second equalizer units adopt a cross-connection structure, for large |Vctrl1-Vctrl2... ∣All tail currents flow through only one of the two differential pairs at the top, so the gain range can be either the highest positive value or the lowest negative value. For example, for a large Vctrl1-Vctrl2, all tail currents flow through only the two sixth transistors Q6, and the gain is the highest positive value. For a large Vctrl2-Vctrl1, all tail currents flow through only the two seventh transistors Q7, and the gain is the lowest negative value.

[0085] The output nodes P and N are connected to two first follower units, which improves their load-driving capability. The eighth resistor R8 in the first follower unit is used to provide a voltage margin so that the collector-emitter voltage difference Vce of the eighth transistor does not exceed the process limitations, ensuring circuit reliability. The collector and base of the ninth transistor are connected, placing it in the linear amplification region, which increases the potential of the output nodes OutP and OutN to meet the DC bias potential requirements of the input node of the next stage circuit.

[0086] In addition, the first-stage amplifier circuit also includes a ninth resistor R9 and a third capacitor C3. The ninth resistor R9 and the third capacitor C3 are connected in series to the emitters of two fifth transistors, generating two poles ωp1 and ωp2 and a zero ωz, where ωz < ωp1 < ωp2. This provides a gain peak at high frequencies, compensating for signal attenuation at high frequencies. Adjusting the values ​​of the ninth resistor R9 and the third capacitor C3 can extend the bandwidth within a certain frequency range. The first-stage amplifier circuit can also adjust the dimensions of the components to achieve different gain levels according to performance requirements.

[0087] As an optional implementation, in one embodiment of the invention, the second-stage amplifier circuit has the same circuit structure as the first-stage amplifier circuit. The second-stage amplifier circuit further increases the gain of the optical modulator driver while obtaining a wider range of gain adjustment. Similarly, the size of the device can be adjusted according to performance requirements to achieve different gain values ​​and gain adjustment ranges.

[0088] As an optional implementation, in one embodiment of the invention, see [link to relevant documentation]. Figure 4 As shown, the input impedance matching circuit includes an impedance matching unit and a second follower unit. Figure 4 The unit to the left of the dashed line is the impedance matching unit, and the unit to the right of the dashed line is the second follower unit.

[0089] The impedance matching unit includes a first MOSFET M1, a second MOSFET M2, a third MPS transistor M3, a ninth resistor R9, a tenth resistor R10, an operational amplifier AMP1, and a fifth current source I5. The first MOSFET M1 and the second MOSFET M2 are NMOS transistors, and the third MPS transistor M3 is a PMOS transistor.

[0090] The drain of the first MOS transistor M1 is connected to the second terminal of the ninth resistor R9 and receives a differential input signal. The first terminal of the ninth resistor R9 is connected to the gate of the first MOS transistor M1 and the drain of the third MPS transistor M3.

[0091] The drain of the second MOS transistor M2 is connected to the second end of the tenth resistor R10 and receives another differential input signal. The first end of the tenth resistor R10 is connected to the gate of the second MOS transistor M2 and the drain of the third MPS transistor M3.

[0092] The source of the first MOS transistor M1 and the source of the second MOS transistor M2 are both connected to the first terminal of the fifth current source I5, and the second terminal of the fifth current source I5 is grounded.

[0093] The output terminal of the operational amplifier AMP1 is connected to the gate of the third MPS transistor M3, the inverting input terminal of the operational amplifier AMP1 is connected to the reference voltage, and the source of the third MPS transistor M3 is connected to the power supply.

[0094] The second follower unit includes a thirteenth transistor Q10, an eleventh transistor Q11, an eleventh resistor R11, a twelfth resistor R12, a sixth current source I6, and a seventh current source I7.

[0095] The bases of the thirteenth transistor Q10 and the eleventh transistor Q11 each receive a differential input signal. The collectors of both transistors Q10 and Q11 are connected to a power supply. Optionally, a second diode D2 and a third diode D3 are placed between the collector of transistor Q10 and the power supply, and a fourth diode D4 and a fifth diode D5 are placed between the collector of transistor Q11 and the power supply. These diodes supply power to both transistors Q10 and Q11 while consuming a certain voltage margin to prevent the collector-emitter voltage difference Vce between them from becoming too large and exceeding process limitations, thereby improving circuit reliability.

[0096] The emitter of the thirteenth transistor Q10 is connected to the first terminal of the sixth current source I6 as one output terminal of the impedance matching unit, and the second terminal of the sixth current source I6 is grounded. The emitter of the eleventh transistor Q11 is connected to the first terminal of the seventh current source I7 as another output terminal of the impedance matching unit, and the second terminal of the seventh current source I7 is grounded.

[0097] The two ends of the series connection between the eleventh resistor R11 and the twelfth resistor R12 are connected to the emitters of the thirteenth transistor Q10 and the eleventh transistor Q11, respectively. The common terminal of the series connection between the eleventh resistor R11 and the twelfth resistor R12 is connected to the non-inverting input terminal of the operational amplifier AMP1.

[0098] The ninth resistor R9 and the tenth resistor R10 are both 50 ohms. The 50-ohm ninth resistor R9 and tenth resistor R10 are connected to the differential input signals InP and InN, respectively. The drain of the first differential MOS transistor M1 and the drain of the second differential MOS transistor M2 are connected to the second terminals of the ninth resistor R9 and the tenth resistor R10, respectively, to form a differential pair, which improves the anti-interference capability.

[0099] Furthermore, since the on-resistance of the first MOSFET M1 and the second MOSFET M2 is much greater than 50 ohms, the impedance of the first MOSFET M1 and the second MOSFET M2 after being connected to the ninth resistor R9 and the tenth resistor R10 is approximately equal to 50 ohms, thus achieving 50-ohm impedance matching for the differential input signals InP and InN. The tail current source of the first MOSFET M1 and the second MOSFET M2 is the fifth current source I5. The drain of the third MOSFET M3 is connected to the gate of the first MOSFET M1 and the second MOSFET M2, as well as the first end of the ninth resistor R9 and the tenth resistor R10, thus supplying power to the first MOSFET M1 and the second MOSFET M2 while generating a base bias voltage.

[0100] The eleventh resistor R11, the twelfth resistor R12, and the operational amplifier AMP1 form a common-mode negative feedback loop. Its function is as follows: the eleventh resistor R11 and the twelfth resistor R12 are used to detect the common-mode voltage at the output point of the second follower unit and feed it back to the operational amplifier AMP1. The operational amplifier AMP1 compares the common-mode voltage detected by the eleventh resistor R11 and the twelfth resistor R12 with the reference voltage Vref. The output of the operational amplifier AMP1 is connected to the gate of the third MOSFET M3. Based on the comparison result, the gate voltage of the third MOSFET M3 is adjusted to form a common-mode negative feedback loop, so that the output common-mode voltage of the second follower unit is stabilized.

[0101] The input impedance matching circuit achieves 50 ohms input impedance matching, reduces input signal reflection, maximizes the power absorbed by the optical modulator driver, improves signal transmission efficiency, and stabilizes the output common-mode voltage through the common-mode feedback loop.

[0102] This invention also provides an optical transmitter, including the aforementioned optical modulator driver.

[0103] In the description of this invention, it should be noted that the terms "upper," "lower," etc., indicating the orientation or positional relationship are based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Unless otherwise expressly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two elements. For those skilled in the art, the specific meaning of the above terms in this invention can be understood according to the specific circumstances.

[0104] It should be noted that in this invention, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0105] The above description is merely a specific embodiment of the present invention, enabling those skilled in the art to understand or implement the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features of the invention herein.

Claims

1. An optical modulator driver, characterized in that, include: The input impedance matching circuit, the variable gain amplifier circuit, and the differential output buffer circuit are connected in sequence. The input impedance matching circuit is used to output the differential input signal after impedance matching. The variable gain amplifier circuit is used to amplify the signal gain after impedance matching by the input impedance matching circuit and then output it. The differential output buffer circuit includes a dynamic bias circuit and a common-emitter common-base equalizer circuit. The dynamic bias circuit is used to apply a dynamic bias voltage to the common-emitter common-base equalizer circuit according to the signal output requirements after the gain amplification of the variable gain amplifier circuit, so that the amplitude of the output signal of the common-emitter common-base equalizer circuit reaches a preset amplitude threshold. The input impedance matching circuit includes an impedance matching unit and a second follower unit. The impedance matching unit includes a first MOSFET, a second MOSFET, a third MOSFET, a ninth resistor, a tenth resistor, an operational amplifier, and a fifth current source. The drain of the first MOSFET is connected to the second terminal of the ninth resistor and receives a differential input signal. The first terminal of the ninth resistor is connected to the gate of the first MOSFET and the drain of the third MOSFET. The drain of the second MOSFET is connected to the second terminal of the tenth resistor and receives another differential input signal. The first terminal of the tenth resistor is connected to the gate of the second MOSFET and the drain of the third MOSFET. The sources of both the first and second MOSFETs are connected to the first terminal of the fifth current source, and the second terminal of the fifth current source is grounded. The output terminal of the operational amplifier is connected to the gate of the third MOSFET. The inverting input terminal of the operational amplifier is connected to a reference voltage, and the source of the third MOSFET is connected to a power supply. The second follower unit includes a thirteenth transistor, an eleventh transistor, an eleventh resistor, a twelfth resistor, a sixth current source, and a seventh current source. The bases of the thirteenth and eleventh transistors each receive a differential input signal, and the collectors of the thirteenth and eleventh transistors are both connected to a power supply. The emitter of the thirteenth transistor is connected to the first terminal of the sixth current source as one output terminal of the impedance matching unit, and the second terminal of the sixth current source is grounded. The emitter of the eleventh transistor is connected to the first terminal of the seventh current source as another output terminal of the impedance matching unit, and the second terminal of the seventh current source is grounded. The two ends of the eleventh and twelfth resistors connected in series are connected to the emitters of the thirteenth and eleventh transistors, respectively. The common terminal of the eleventh and twelfth resistors connected in series is connected to the non-inverting input terminal of the operational amplifier.

2. The optical modulator driver according to claim 1, characterized in that: The dynamic bias circuit includes two symmetrical dynamic bias units, and the common-emitter common-base equalizer circuit includes two symmetrical first equalizer units. Each of the aforementioned dynamic bias units includes a symmetrical first transistor, a second transistor, a first resistor, a second resistor, and a first current source, wherein the first resistor and the second resistor are both adjustable resistors; The base of the first transistor and the base of the second transistor serve as the input terminals of the dynamic bias unit to receive a differential input signal. The collector of the first transistor is connected to the power supply, the emitter of the first transistor is connected to the first terminal of the first current source and a corresponding first equalizer unit, and the second terminal of the first current source is grounded. The first end of the second resistor is connected to the power supply, the second end of the second resistor is connected to the collector of the second transistor and a corresponding first equalizer unit, the emitter of the second transistor is connected to the first end of the first resistor, and the second end of the first resistor is grounded.

3. The optical modulator driver according to claim 2, characterized in that: Each of the first equalizer units includes a third transistor, a fourth transistor, a third resistor, and a second current source; The base of the third transistor is connected to the emitter of the first transistor, the collector of the third transistor is connected to the emitter of the fourth transistor, the emitter of the third transistor is connected to the first terminal of the second current source, and the second terminal of the second current source is grounded. The first end of the third resistor is connected to the power supply, and the second end of the third resistor is connected to the collector of the fourth transistor and serves as the output end of the first equalizer unit. The base of the fourth transistor is connected to the collector of the second transistor.

4. The optical modulator driver according to claim 3, characterized in that: The common-emitter, common-base equalizer circuit also includes a second capacitor and a fourth resistor, the two ends of which are connected in parallel to the emitters of the two third transistors respectively.

5. The optical modulator driver according to claim 2, characterized in that: Each of the dynamic bias units further includes a first capacitor, the first end of which is connected to the collector of the second transistor, and the second end of which is grounded.

6. The optical modulator driver according to claim 1, characterized in that: The variable gain amplifier circuit includes a first-stage amplifier circuit, a second-stage amplifier circuit, and a bias control circuit. The first-stage amplifier circuit is used to linearly amplify the signal output from the input impedance matching circuit and then output it. The second-stage amplifier circuit is used to linearly amplify the signal after it has been linearly amplified by the first-stage amplifier circuit again and output it to the differential output buffer circuit. The bias control circuit is used to provide a gain adjustment control voltage to the first-stage amplifier circuit and the second-stage amplifier circuit.

7. The optical modulator driver according to claim 6, characterized in that: The first-stage amplifier circuit includes two symmetrically crossed second equalizer units and two symmetrical first follower units; Each of the second equalizer units includes a fifth transistor, a sixth transistor, a seventh transistor, a fifth resistor, a sixth resistor, a seventh resistor, and a third current source; The base of the fifth transistor is connected to the input impedance matching circuit as the input terminal of the second equalizer unit. The emitter of the fifth transistor is connected to the first terminal of the third current source. The collector of the fifth transistor is connected to the emitter of the sixth transistor and the emitter of the seventh transistor of another second equalizer unit. The base of the sixth transistor is connected to a first control voltage, and the collector of the sixth transistor is connected to the second terminal of the fifth resistor; the first terminal of the fifth resistor is connected to the first terminal of the sixth resistor and the second terminal of the seventh resistor; the first terminal of the seventh resistor is connected to a power supply, and the second terminal of the sixth resistor is connected to the collector of the seventh transistor. The base of the seventh transistor is connected to the second control voltage, and the emitter of the seventh transistor is connected to the collector of the fifth transistor of another second equalizer unit. Each of the first follower units includes an eighth transistor, a ninth transistor, an eighth resistor, and a fourth current source; The first end of the eighth resistor is connected to the power supply, and the second end of the eighth resistor is connected to the collector of the eighth transistor. The base of the eighth transistor is connected to the first end of the fifth resistor, and the emitter of the eighth transistor is connected to the collector and base of the ninth transistor. The emitter of the ninth transistor is connected to the first terminal of the fourth current source, and the second terminal of the fourth current source is grounded.

8. The optical modulator driver according to claim 7, characterized in that: The second-stage amplifier circuit has the same circuit structure as the first-stage amplifier circuit.

9. An optical transmitter, characterized in that, Includes the optical modulator driver according to any one of claims 1-8.

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