Method, apparatus, device, medium and program product for redefining layout patterns

Abstract

The present disclosure relates to a method, apparatus, device, medium and program product for redefining a layout pattern. The method comprises determining a plurality of mask patterns corresponding to a layout pattern in a circuit layout, the plurality of mask patterns having different sizes. The method further comprises determining, by photolithography imaging simulation, sizes of a plurality of wafer patterns formed based on the plurality of mask patterns. The method comprises determining, for each wafer pattern in the plurality of wafer patterns, a simulated value of a process parameter for evaluating a process window or imaging quality. The method comprises determining, based at least on the simulated value of the process parameter, a target size from the sizes of the plurality of wafer patterns. The method further comprises setting the layout pattern in the circuit layout to have the target size. In this way, layout pattern redefinition with higher accuracy and wider coverage can be achieved.

Description

Technical Field

[0001] The embodiments of this disclosure primarily relate to the field of integrated circuits. More specifically, the embodiments of this disclosure relate to methods, apparatus, devices, computer-readable storage media, and computer program products for redefining layout graphics. Background Technology

[0002] Photolithography is one of the key processes that determines the linewidth of integrated circuits. In advanced semiconductor process nodes, due to the diffraction and interference effects of light, as well as limitations in light source design, photolithography cannot achieve sufficient lithography windows or produces poor lithographic imaging quality at certain specific sizes or pitches. In the layout, patterns exhibiting these phenomena are called hot spots, which severely impact the overall yield of the photolithography process.

[0003] To address the aforementioned issues, two solutions exist. One solution is to improve overall process yield by adding sub-resolution auxiliary patterning (SRAF). The other solution is to improve overall process yield by redefining the target linewidth value of the pattern. However, in some positive development processes, the improvement effect of SRAF is very limited, and it is prone to generating additional imaging on the wafer. Therefore, the target linewidth redefinition scheme is adopted in most layer lithography processes. Summary of the Invention

[0004] Embodiments of this disclosure provide a scheme for redefining layout graphics.

[0005] In a first aspect of this disclosure, a method for redefining a layout pattern is provided. The method includes: determining multiple mask patterns corresponding to a layout pattern in a circuit layout, the multiple mask patterns having different dimensions. The method further includes: determining the dimensions of multiple wafer patterns formed based on the multiple mask patterns through photolithography imaging simulation. The method includes: for each of the multiple wafer patterns, determining simulated values ​​of process parameters used to evaluate process windows or imaging quality. The method includes: determining a target dimension from the dimensions of the multiple wafer patterns, at least based on the simulated values ​​of the process parameters. The method further includes: setting the layout pattern in the circuit layout to have the target dimension.

[0006] In the embodiments of this disclosure, there is no need to collect and organize large amounts of wafer data, thus reducing the time and material costs of target pattern redefinition, and consequently reducing the time and material costs in the development of lithography and optical proximity correction (OPC) processes. Furthermore, in the embodiments of this disclosure, all patterns in the entire layout can be redefined very quickly and intelligently, and the influence of the surrounding layout environment of each pattern can be fully simulated. In this way, higher accuracy and wider coverage can be achieved, greatly improving the limitations and errors of rule-based target pattern redefinition schemes.

[0007] In one implementation of the first aspect, determining multiple mask patterns includes: in each iteration of a multi-round iteration, determining a subset of the multiple mask patterns by changing the size of the mask patterns within a sampling range for that iteration. The method further includes: in each iteration, determining an intermediate value for a target size based on the subset of the multiple mask patterns; and setting the size of a layout pattern in the circuit layout to the intermediate value for use in the next iteration.

[0008] In this implementation, parallel optimization algorithms can significantly improve computational efficiency. Furthermore, at the start of each iteration (except the first iteration), the surrounding environment of the layout is the environment redefined in the previous iteration. As the number of iterations increases, the degree of overall redefinition decreases until convergence. This approach improves simulation accuracy.

[0009] In another implementation of the first aspect, the method further includes: selecting a predetermined number of mask patterns from the first subset based on simulated values ​​of process parameters corresponding to a first subset of multiple mask patterns, the first subset being determined in a first iteration; and determining a sampling range for a second iteration based on the dimensions of the predetermined number of mask patterns, for determining a second subset of the multiple mask patterns in the second iteration, the second iteration immediately following the first iteration. In this implementation, the sampling range for the next iteration is determined based on the dimensions of the preferred mask patterns from the previous iteration. This approach can accelerate the convergence speed.

[0010] In another implementation of the first aspect, setting the layout graphic in the circuit layout to have a target size includes: obtaining constraints related to design rules for the layout graphic; and, based on the constraints, selectively adding an offset graphic corresponding to the target size to at least one of a first side or a second side of the layout graphic, the second side being opposite to the first side. In this way, the redefined layout can pass the design rule check.

[0011] In another implementation of the first aspect, determining the target size from the dimensions of multiple wafer patterns based at least on simulation values ​​of process parameters includes: for each of the multiple wafer patterns, determining the degree to which a layout pattern set to have the dimensions of the wafer pattern satisfies constraints related to design rules for the layout pattern; and determining the target size from the dimensions of the multiple wafer patterns based on the simulation values ​​of process parameters and the degree to which they are satisfied.

[0012] In another implementation of the first aspect, determining the target size from multiple wafer pattern sizes, based at least on simulated values ​​of process parameters, includes: determining the imaging cost of forming the corresponding wafer pattern based on thresholds, target values, and simulated values ​​for the process parameters; and determining the size of the wafer pattern with the lowest imaging cost as the target size. In this implementation, incorporating design rule checks into the determination of the target size allows for efficient determination, avoiding the need to reselect the target size due to failure to pass design rule checks. This improves the efficiency of pattern redefinition.

[0013] In another implementation of the first aspect, the method further includes: detecting a predetermined type of defect in the circuit layout in response to the layout pattern being set to have a target size; and adding an offset pattern at the detected defect so that the pattern at the detected defect is aligned with the surrounding pattern. In this way, defects can be repaired to avoid negatively impacting subsequent OPC operations.

[0014] In another implementation of the first aspect, the method further includes: identifying the type of a graphic in the circuit layout; and dividing the graphic into multiple layout graphics, including the graphic itself, based on the identified type and the relative position of the graphic to surrounding graphics. Since different parts of the same graphic may be in different environments, a segmentation operation is needed to divide the originally larger graphic in the layout into smaller layout graphics, and then perform a redefinition operation on each of these layout graphics. This approach can improve the accuracy of graphic redefinition.

[0015] In a second aspect of this disclosure, an apparatus for redefining a layout pattern is provided. The apparatus includes: a mask pattern determining unit configured to determine a plurality of mask patterns corresponding to a layout pattern in a circuit layout, the plurality of mask patterns having different sizes. The apparatus includes: a wafer pattern determining unit configured to determine the dimensions of a plurality of wafer patterns formed based on the plurality of mask patterns through photolithography imaging simulation. The apparatus includes: a process parameter determining unit configured to determine, for each of the plurality of wafer patterns, simulated values ​​of process parameters used to evaluate process windows or imaging quality. The apparatus includes: a target size determining unit configured to determine a target size from the dimensions of the plurality of wafer patterns, at least based on the simulated values ​​of the process parameters. The apparatus further includes: a redefining unit configured to set the layout pattern in the circuit layout to have the target size.

[0016] In one implementation of the second aspect, the mask pattern determination unit is further configured to: determine a subset of multiple mask patterns by changing the size of the mask patterns within a sampling range for that iteration in each of the multiple iterations. The target size determination unit is further configured to determine an intermediate value for a target size based on the subset of multiple mask patterns in each iteration. The redefinition unit is further configured to set the size of the layout pattern in the circuit layout to the intermediate value for use in the next iteration.

[0017] In another implementation of the second aspect, the apparatus further includes: a mask pattern selection unit configured to select a predetermined number of mask patterns from the first subset based on simulated values ​​of process parameters corresponding to a first subset of the plurality of mask patterns, the first subset being determined in a first iteration; and a sampling range determination unit configured to determine a sampling range for a second iteration based on the dimensions of the predetermined number of mask patterns, for determining a second subset of the plurality of mask patterns in the second iteration, the second iteration immediately following the first iteration.

[0018] In another implementation of the second aspect, the redefinition unit is further configured to: acquire constraints related to design rules for the layout graphic; and, based on the constraints, selectively add an offset graphic corresponding to the target size to at least one of the first or second sides of the layout graphic, the second side being opposite to the first side.

[0019] In another implementation of the second aspect, the target size determination unit is further configured to: for each of the plurality of wafer patterns, determine the degree to which a layout pattern set to have the size of the wafer pattern satisfies the constraints, the constraints being related to the design rules for the layout pattern; and determine the target size from the sizes of the plurality of wafer patterns based on the simulation values ​​of process parameters and the degree of satisfaction.

[0020] In another implementation of the second aspect, the target size determination unit is further configured to: determine the imaging cost of forming the corresponding wafer pattern based on the threshold, target value and simulation value of the process parameters; and determine the size of the wafer pattern with the lowest imaging cost as the target size.

[0021] In another implementation of the second aspect, the apparatus further includes: a defect detection unit configured to detect a predetermined type of defect in the circuit layout in response to the layout pattern being set to have a target size; and a defect repair unit configured to add an offset pattern at the detected defect so that the pattern at the detected defect is flush with the surrounding pattern.

[0022] In another implementation of the second aspect, the apparatus further includes: a graphic classification unit configured to identify the type of graphic in the circuit layout; and a graphic segmentation unit configured to divide the graphic into a plurality of layout graphics including the layout graphic based on the identified type and the relative position of the graphic with respect to surrounding graphics.

[0023] In a third aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and at least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor. When executed by the at least one processor, the instructions cause the electronic device to perform a method of any implementation of the first aspect.

[0024] In a fourth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the method in any implementation of the first aspect.

[0025] In a fifth aspect of this disclosure, a computer program product is provided, characterized in that it includes computer-executable instructions, wherein the computer-executable instructions, when executed by a processor, implement the method in any implementation of the first aspect.

[0026] It is understood that the apparatus of the second aspect, the electronic device of the third aspect, the computer storage medium of the fourth aspect, or the computer program product of the fifth aspect provided above are all used to perform the method provided in the first aspect. Therefore, the explanations or descriptions regarding the first aspect also apply to the second, third, fourth, and fifth aspects. Furthermore, the beneficial effects achievable by the second, third, fourth, and fifth aspects can be referred to the beneficial effects in the corresponding methods, and will not be repeated here.

[0027] It should be understood that the description in the Summary of the Invention is not intended to limit the key or essential features of the embodiments of this disclosure, nor is it intended to restrict the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0028] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. In the drawings, the same or similar reference numerals denote the same or similar elements, wherein: Figure 1 The test graph used in the rule-based target graph redefinition scheme is shown; Figure 2 A simplified schematic diagram of rule-based target graph redefinition is shown; Figure 3 A block diagram of an example system for model-based target graph redefinition according to embodiments of the present disclosure is shown; Figure 4 Examples of graphical classification according to some embodiments of this disclosure are shown; Figure 5 A schematic diagram showing layout graphics and measurement marks according to some embodiments of the present disclosure is provided; Figure 6 A schematic diagram illustrating the simulation of critical dimensions of a wafer according to some embodiments of the present disclosure is shown; Figure 7 Examples of analysis process windows according to some embodiments of this disclosure are shown; Figure 8A An example of an adjustment function for determining imaging cost according to some embodiments of the present disclosure is shown; Figure 8B Another example of an adjustment function for determining imaging cost according to some embodiments of the present disclosure is shown; Figure 9 A schematic diagram of the sampling range in multiple iterations according to some embodiments of the present disclosure is shown; Figure 10 A schematic diagram of a portion of a redefinition layout according to some embodiments of the present disclosure is shown; Figure 11A A schematic diagram illustrating the repair of example defects according to some embodiments of the present disclosure is shown; Figure 11B A schematic diagram illustrating the repair of another example defect according to some embodiments of the present disclosure is shown; Figure 12 Examples of constraints relating to design rules according to some embodiments of this disclosure are shown; Figure 13 Examples of examined and corrected layouts according to some embodiments of this disclosure are shown; Figure 14 A flowchart illustrating an example method for redefining layout graphics according to some embodiments of this disclosure is shown; Figure 15 A schematic block diagram of an apparatus for redefining layout graphics according to some embodiments of the present disclosure is shown; and Figure 16 A block diagram of a computing device capable of implementing several embodiments of the present disclosure is shown. Detailed Implementation

[0029] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0030] In the description of embodiments of this disclosure, the term "comprising" and similar terms should be understood as open-ended inclusion, i.e., "including but not limited to". The term "based on" should be understood as "at least partially based on". The term "an embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. The term "and / or" indicates at least one of the two items associated therewith. For example, "A and / or B" means A, B, or A and B. Other explicit and implicit definitions may also be included below.

[0031] In embodiments of this disclosure, the term "critical dimension" refers to a physical feature dimension on a layout, mask, or wafer, which is a form of dimension. Throughout this document, the terms "critical dimension" and "dimension" are used interchangeably.

[0032] As mentioned above, target pattern redefinition schemes are used in most layered photolithography processes. Traditional target pattern redefinition schemes are rule-based. In this rule-based scheme, a mask defined by a test pattern with continuously varying linewidths / spacing is used to expose and develop the wafer, and wafer measurement data is collected. Figure 1 An example of a set of test graphs used in a rule-based target graph redefinition scheme is shown. For example... Figure 1 As shown, in the spacing dimension, that is, from test pattern 110 to test pattern 120, the distance between adjacent polygons in the test pattern gradually increases. In the width dimension, that is, from test pattern 110 to test pattern 130, the width of each polygon in the test pattern gradually increases.

[0033] Subsequently, the lithography process evaluation parameters, such as the lithography process window and line width roughness, were observed for each set of test patterns. Taking the lithography process window as an example, its determination method is as follows: the focus depth and exposure dose of the lithography machine are scanned at certain intervals to determine the lithography process conditions under various combinations. Then, the test patterns (e.g., ...) are examined under each lithography process condition. Figure 1 The test pattern shown is exposed and developed. Finally, the photoresist linewidth of the pattern on the wafer is measured, and it is determined whether the photoresist linewidth is within the predetermined range of the target critical dimension (CD) (e.g., ±10%). A curve is plotted with the depth of focus as the x-axis and the exposure dose as the y-axis. The range occupied by the points where the critical dimension changes within the specified range is the photolithography process window.

[0034] Based on all test graphs (e.g., Figure 1 Based on the exposure results of the set of test patterns shown, a table is created. This table is used to indicate whether the common lithography process window of the patterns meets the requirements under different spacing and CD conditions. Specifically, a table like the one described above needs to be created for each type of pattern, with CD in the horizontal row and spacing variation in the vertical column.

[0035] Then, based on the aforementioned table, a selective size adjustment table is established using relevant mathematical formulas. Similarly, a corresponding SSA table needs to be established for each type of graphic to determine the bias that needs to be added to the graphic during the redefinition operation of the target graphic. Then, the relevant layout editing tools are used to add the bias to the relevant graphics in the layout, thereby changing the line width of the graphic. Figure 2 A simplified schematic diagram of rule-based target graph redefinition is shown. For example... Figure 2 As shown, the CD of graphic 210 is 180, and the gap between graphic 210 and graphic 220 is 150. By consulting SSA table 201, the offset can be determined to be -2. Accordingly, an offset of -2 is added to graphic 210.

[0036] While the traditional rule-based target pattern redefinition scheme described above can solve the lithography process window problem, it also has significant drawbacks. For example, it requires additional exposure and the collection of wafer data for evaluating the lithography process window, resulting in high time and material costs. The complete process is lengthy and cumbersome. Rule-based target pattern redefinition has limitations; it cannot be applied to all complex pattern scenarios, and as the number of pattern types increases, a large number of SSA tables need to be generated. Furthermore, this traditional scheme has poor accuracy, adding offsets only based on lookup tables, and cannot fully consider the actual layout environment in which the pattern is located.

[0037] To at least partially address the aforementioned problems and other potential issues, various embodiments of this disclosure provide a scheme for redefining circuit layout patterns. Generally, according to the various embodiments described herein, an offset is added to the circuit layout pattern through simulation of a lithography model to set the pattern to a target size. Therefore, this is a model-based target pattern redefinition scheme. The redefined circuit layout can improve the lithography process window, enhance lithography imaging quality, and repair defects. This also makes subsequent OPC convergence easier, ultimately improving the overall lithography process yield.

[0038] In the embodiments of this disclosure, there is no need to collect and organize large amounts of wafer data, thus significantly reducing the time and material costs of redefining the target pattern, thereby reducing the time and material costs in the lithography and OPC process development. Furthermore, in the embodiments of this disclosure, all patterns in the entire layout can be redefined very quickly and intelligently, and the influence of the surrounding layout environment of each pattern can be fully simulated. In this way, higher accuracy and wider coverage can be achieved, greatly improving the limitations and errors of rule-based target pattern redefinition schemes. Additionally, in the embodiments of this disclosure, the optimal target size of the pattern within a certain range can be found, further improving the overall performance of the lithography process.

[0039] The following is for reference Figures 3 to 16 Various exemplary embodiments of this disclosure are described below.

[0040] Example System Figure 3 A block diagram of an example system 300 for model-based target pattern redefinition according to an embodiment of the present disclosure is shown. Generally, system 300 processes an input circuit layout 301 (also simply referred to as "layout 301") using a lithography model 302 to redefine the patterns in layout 301 and outputs a redefined layout 303. Layout 301 may be provided by the designer. The lithography model 302 may be any known or future-developed model for simulating lithographic imaging, and the scope of this disclosure is not limited in this respect.

[0041] The processing of layout 301 by system 300 can be divided into a preprocessing stage 310 and an optimization stage 320. In the preprocessing stage 310, a series of layout graphics are determined based on the various graphics in layout 301. As used herein, "layout graphics" refers to the graphic unit considered in redefining the target size. Layout graphics can be the original graphics in layout 301, or a part of the original graphics, i.e., obtained by segmenting the original graphics. Each layout graphic is inserted with measurement markers to identify the position of subsequent simulated lithography performance and wafer CD. To achieve this processing, the preprocessing stage 310 can utilize multiple modules, such as... Figure 3 The diagram shows a template module 311, a graphic classification module 312, a segmentation module 313, and a measurement mark insertion module 314. The template module 311 is configured to segment the complete layout 301 into several sub-layouts. In subsequent stages, each sub-layout is processed independently and in parallel to improve overall processing speed. The graphic classification module 312 is configured to identify and classify graphics in the layout 301 (e.g., graphics in each sub-layout) based on predetermined rules. The segmentation module 313 is configured to determine the layout graphics to be processed separately based on the graphic classification; for example, a larger graphic can be divided into several smaller layout graphics. The measurement mark insertion module 314 is configured to determine the measurement positions of the layout graphics and insert measurement marks at those positions. The functions of these modules will be described in detail below.

[0042] In optimization phase 320, a target CD is determined for each layout pattern, and the layout pattern is set to have a target CD. To achieve this process, optimization phase 320 utilizes at least a lithography simulation module 321 and a redefinition module 322. The lithography simulation module 321 is configured to determine the target CD for each layout pattern through lithography imaging simulation. Specifically, the lithography simulation module 321 can determine multiple candidate CDs for each layout pattern through lithography imaging simulation, and select the target CD from the multiple candidate CDs based on the simulation values ​​of process parameters associated with the multiple candidate CDs respectively. In some embodiments, the lithography simulation module 321 may include multiple sub-modules to implement the above process, for example... Figure 1 The process window analysis submodule 331, the lithography performance analysis submodule 332, and the process parameter analysis submodule 333 are shown.

[0043] The redefinition module 322 is configured to set the layout graphic to have a target CD by adding an offset corresponding to the target CD to the layout graphic. In some embodiments, the optimization phase 320 may also utilize the inspection and repair module 323. The inspection and repair module 323 is configured to make the redefined graphic meet constraints related to design rules, and / or repair defects in the redefined graphic. Figure 3As shown, the operations of the lithography simulation module 321, the redefinition module 322, and the optional inspection and repair module 323 can be executed iteratively to continuously optimize, thereby obtaining the final redefined layout 303.

[0044] It should be understood that Figure 3 The division of modules and their functions in system 300 shown is merely illustrative and is not intended to limit the scope of this disclosure. For example, system 300 may include more or fewer modules. Furthermore, the functions of some modules may be combined, or the functions of some modules may be further broken down.

[0045] Preprocessing of the map As referenced above Figure 3 As described, after preprocessing stage 301, multiple layout graphics are determined from layout 301, and each layout graphic is inserted with measurement markers. Specifically, template module 311 cuts the complete layout 301 to divide it into several sub-layouts, such as several sub-layouts of equal size. The size and sampling distance of the sub-layouts can be customized or set based on the size of layout 301 and the processing capability of system 300. Different sub-layouts may overlap or not, and the scope of this disclosure is not limited in this respect. In the optimization stage, each sub-layout can be processed independently and in parallel. In this way, the overall processing speed of layout 301 can be significantly improved.

[0046] The graphic classification module 312 identifies and classifies the graphics in the layout 301 (e.g., graphics in each sub-layout) based on predetermined rules. Figure 4 Examples of graphical classifications according to some embodiments of this disclosure are shown. For example... Figure 4 As shown, the graphics in a portion 400 of the layout are classified as line ends, lines (e.g., line 402), outer corners (e.g., outer corner 403), inner corners (e.g., inner corner 404), gaps (e.g., gaps 405), contacts (e.g., contacts 406), gap ends (e.g., gap ends 407), etc.

[0047] The graphic classification module 312 can identify and classify graphics in layout 301 based on judgment rules for different types. Taking a line end as an example, the following judgment rules can be set: the side length of the line end edge is greater than or equal to the minimum width and less than or equal to the maximum width; the side length of one adjacent edge is greater than or equal to the minimum short edge; and the side length of another adjacent edge is greater than or equal to the minimum long edge. Based on these judgment rules, a line end edge and its adjacent edges can be identified and determined from layout 301 or a sub-layout. By retaining the side lengths of some adjacent edges, a rectangle can be determined as a line end graphic, for example, line end graphic 401. Similarly, graphics of different types can be determined according to their respective judgment rules, such as line graphic 402, exterior corner graphic 403, interior corner graphic 404, gap graphic 405, contact point graphic 406, and gap end graphic 407.

[0048] Figure 4 The graphic classifications shown are merely exemplary and are not intended to limit the scope of this disclosure. Any suitable classification method may also be used. Furthermore, the above-described rules regarding line ends are exemplary. In embodiments of this disclosure, any suitable rules may be applied to different types of graphics.

[0049] The segmentation module 313 divides a graphic into several smaller layout graphics based on the graphic's classification. Specifically, the segmentation module 313 can insert dissection points into the original larger graphic to divide it into smaller sub-graphics. For example, a larger rectangle can be divided into smaller rectangles as layout graphics. The segmentation operation of the graphic is a preparatory stage for the subsequent redefinition operation. Since different parts of the same graphic may be in different environments, it is necessary to use the segmentation operation to divide the original larger graphic into smaller layout graphics, and then perform redefinition operations on these layout graphics separately.

[0050] Figure 5 A schematic diagram of layout graphics and measurement marks according to some embodiments of the present disclosure is shown. Figure 5 The illustration schematically shows how to segment graphic 510 and graphic 520 in a layout to determine multiple layout graphics. Taking graphic 520 as an example, the spacing between its left and right parts is different, meaning they are in different environments. This results in the left and right parts corresponding to different process windows, thus requiring graphic 520 to be segmented.

[0051] As an example, segmentation module 313 can segment larger graphics in the following way. For shorter graphics such as line ends, gap ends, and contacts, segmentation points can be inserted at the four corners of a rectangle. That is, the line end graphics, gap end graphics, and contact graphics themselves will be determined as layout graphics. For areas that have projections with adjacent graphics (such as...) Figure 5(As shown by the dashed lines in the diagram), segmentation points can be inserted at the projected locations within the projection area, such as segmentation points 530 and 535. Simultaneously, segmentation points are inserted at predetermined distances to the left and right along the graphic boundary from these segmentation points, such as segmentation points 531 and 532. For the remaining line or gap areas, segmentation points are inserted at equal intervals according to predetermined step sizes.

[0052] Using the method described above, a large graphic can be divided into several smaller graphic units, each defined by multiple segmentation points. For example, a polygon can be divided into rectangles defined by four segmentation points. Figure 5 In the example, graphics 510 and 520 are divided into 12 layout graphics, namely layout graphics 501-1 to 501-12, which are also collectively or individually referred to as layout graphics 501.

[0053] After the layout pattern is determined, the measurement mark insertion module 314 inserts measurement marks for each layout pattern. The measurement marks are used to identify the measurement positions of the CD in the lithography imaging simulation. For rectangles, the inserted measurement marks are perpendicular to the side length of the rectangle, such as measurement mark 515 and measurement mark 525.

[0054] As an example, for rectangles divided by lines or gaps, the measurement mark can be located on the center line of the rectangle. For example, measurement mark 525 of layout pattern 501-11 is located on the center line of layout pattern 501-11 (which is a rectangle). For rectangles formed by line-end or gap-end patterns, the measurement mark can be located at a distance from the line-end or gap-end edge, which can be 0.9 times the length of the adjacent side or other suitable multiple. For example, measurement mark 515 of layout pattern 501-4 is not located on the center line of layout pattern 501-4, but further away from the line-end edge 550 of layout pattern 501-4. For rectangles formed by contact patterns, the measurement mark can be located at the center of the long side of the rectangle and on the long side.

[0055] It should be understood that the positions of the measurement marks described above are merely exemplary and are not intended to limit the scope of this disclosure. The positions of the measurement marks can be set according to actual needs.

[0056] Model-based photolithography simulation In the optimization phase 320, the lithography simulation module 321 determines the target CD for each layout pattern through lithography imaging simulation. Specifically, the lithography simulation module 321 can determine multiple candidate CDs for each layout pattern through lithography imaging simulation, and select the target CD from the multiple candidate CDs based on the simulation values ​​of process parameters related to the multiple candidate CDs respectively.

[0057] Simulation values ​​of wafer CD and process parameters Candidate CD is the CD at the measurement mark of the pattern formed on the wafer based on the layout pattern through photolithographic imaging simulation. In this paper, the pattern formed on the wafer based on the layout pattern is also referred to as the "wafer pattern". Accordingly, the CD of the wafer pattern is also referred to as the wafer CD. It can be understood that the wafer CD determined by photolithographic imaging simulation corresponds to the simulated value of the linewidth on the photoresist after actual exposure and development. Accordingly, the pattern formed on the mask corresponding to the layout pattern is also referred to as the "mask pattern", and the CD of the mask pattern is also referred to as the mask CD.

[0058] Figure 6 A schematic diagram illustrating a simulation of a wafer CD according to some embodiments of the present disclosure is shown. Figure 6 A mask pattern 601 corresponding to the layout pattern is shown, which has a mask CD 604. A sine wave curve 602 represents the light intensity distribution at the measurement mark obtained based on simulation using a photolithography imaging model. The horizontal dashed line 603 corresponds to the light intensity threshold determined by the photolithography imaging model. The portion of light intensity exceeding the light intensity threshold can be exposed and imaged on the wafer, while the portion of light intensity less than the light intensity threshold cannot be exposed and imaged on the wafer. Therefore, the wafer CD 605 of the wafer pattern can be determined based on the light intensity distribution and the light intensity threshold.

[0059] Under the same lithography conditions, the light intensity distribution is constant, thus the corresponding wafer CD 605 can be determined. In the embodiments of this disclosure, the optimal wafer CD under ideal lithography conditions obtained through subsequent optimization steps can be determined as the target size of the layout pattern, as will be described in detail below. Ideal lithography conditions may refer to the nominal illumination conditions of the lithography machine or the illumination conditions set for the lithography machine.

[0060] Process parameters used to evaluate the lithography process window or imaging quality may include, but are not limited to, depth of focus (DOF), exposure latitude (EL), imaging intensity logarithmic slope (ILS), and mask error enhancement factor (MEEF). For each process parameter, a corresponding target value (tar) and threshold value (tol) can be set. The target value (tar) reflects the ideal imaging value, while the threshold value (tol) reflects the minimum imaging requirements.

[0061] To determine the simulated values ​​of the aforementioned process parameters, the lithography simulation module 321 may include a process window analysis submodule 331 and a lithography performance analysis submodule 332. The process window analysis submodule 331 is used to determine the process window of the layout pattern, i.e., the process window at the measurement mark. As an example, the process window analysis submodule 331 can vary the focus value and exposure dose in fixed steps, with each combination of focus value and exposure dose constituting a lithography condition. Process window models under various lithography conditions can be established sequentially. Then, the wafer CD under the corresponding lithography conditions can be simulated based on the process window model. Using the wafer CD simulated under ideal lithography conditions as the ideal CD, the variation of the wafer CD simulated under other lithography conditions is calculated to see if it falls within a predetermined range (e.g., + / - 10%) of the ideal CD, and this is marked. In this way, the size of the process window at the measurement mark can be calculated.

[0062] Figure 7 Examples of analysis process windows according to some embodiments of this disclosure are shown. Figure 7 As shown, the region between line 701 and line 702 corresponds to a change in wafer CD within a predetermined range. Accordingly, process window 703 and DOF can be determined. The process window analysis submodule 331 can store the value of DOF as part of the process parameters. It can also additionally store the area of ​​process window 703 (i.e., ellipse area), which is a parameter reflecting the size of the process window.

[0063] The operations described above for determining DOF and process window are merely exemplary and are not intended to limit the scope of this disclosure. In embodiments of this disclosure, any suitable method can be used to determine DOF and process window. Furthermore, it is understood that in lithography imaging simulation, the surrounding environment of the layout pattern, i.e., the positional relationship between the layout pattern and adjacent patterns, is considered.

[0064] The lithography performance analysis submodule 332 is used to determine simulated values ​​of other process parameters for the layout pattern. For example, the lithography performance analysis submodule 332 can calculate ILS, MEEF, etc. at measurement marks and store the corresponding simulated values. The lithography performance analysis submodule 332 can use any existing or future-developed method to determine the simulated values ​​of these process parameters, and the scope of this disclosure is not limited in this respect.

[0065] As described below with reference to the optimization algorithm, the CD of the mask pattern can be varied within a sampling range to determine multiple mask CDs. Through photolithography imaging simulation, the wafer CD under ideal conditions corresponding to each mask CD can be determined. In this paper, for illustrative purposes only and without any limitation, the wafer CD under ideal conditions is referred to as the "ideal wafer CD". Thus, multiple ideal wafer CDs and their corresponding simulated values ​​for process parameters can be determined.

[0066] Utilization of process parameters The simulated values ​​of process parameters obtained from the process window analysis submodule 331 and the lithography performance analysis submodule 332 can be used by the process parameter analysis submodule 333 to determine the target CD for the layout pattern. Specifically, the process parameter analysis submodule 333 can select the target CD for the layout pattern from multiple ideal wafer CDs based on the simulated values ​​of the process parameters of each of the multiple understood wafer CDs.

[0067] In some embodiments, the process parameter analysis submodule 333 can determine the target CD based on the imaging cost reflected by the process parameters. For example, the process parameter analysis submodule 333 can determine the imaging cost of forming the corresponding wafer pattern based on the simulated value of the process parameters, the target value tar, and the threshold tol, and determine the CD of the wafer pattern with the lowest imaging cost as the target CD.

[0068] Imaging costs can be represented by a cost function. The cost function is used to evaluate simulation or optimization results. As an example, the cost function corresponding to any process parameter can be calculated using the following formula: Equation (1) in i Indicates measurement markings, weight This indicates the weight of the process parameters. sim This represents the simulated value of the process parameter. f(k) This represents the adjustment function.

[0069] Figure 8A and 8B Examples of adjustment functions for determining imaging costs according to some embodiments of this disclosure are shown. Figure 8A The adjustment function 810 shown can be used for process parameters such as DOF ​​and ILS. Specifically, when the simulated value is less than the threshold tol, the value of the adjustment function... f The value is 10; when the simulated value is greater than or equal to the threshold tol and less than the target value tar, the value of the adjustment function is adjusted. f =1; otherwise f It is 0. Figure 8B The adjustment function 820 shown can be used for process parameters such as MEEF. Specifically, when the simulated value is greater than the threshold tol, the value of the adjustment function... f The value is 10; when the simulated value is greater than or equal to the target value tar and less than the threshold tol, the value of the adjustment function is adjusted. f =1; otherwise f =0. Adjustment function used for ideal wafer CD. f(k) It can be a constant function, such as a constant function with a value of 1.

[0070] When considering multiple process parameters, the process parameter analysis submodule 333 can calculate the imaging cost for each process parameter (e.g., DOF, ILS, MEEF, ideal wafer CD, etc.) separately, and then calculate the total cost of these process parameters. The process parameter analysis submodule 333 can then select the target CD for the layout pattern from these ideal wafer CDs based on the total cost determined for each of the multiple ideal wafers C.

[0071] In this embodiment, imaging cost can be used to comprehensively consider the advantages and disadvantages of process parameters, thereby helping to select the optimal target CD. The imaging cost calculation and adjustment functions described above are merely exemplary and are not intended to limit the scope of this disclosure. In the embodiments of this disclosure, any suitable method can be used to calculate the imaging cost.

[0072] Furthermore, it should be noted that when the initial layout pattern meets the thresholds of process parameters such as DOF, ILS, and MEEF, redefining the layout pattern should be avoided as much as possible. To address this, additional criteria can be added. For example, if the wafer CD obtained from mask CD simulation is close to the initial target CD, and the simulated values ​​of the considered process parameters are greater than their thresholds (e.g., the simulated value of DOF is greater than its threshold, the simulated value of ILS is greater than its threshold, and the simulated value of MEEF is less than its threshold), then the total imaging cost can be set to 0.

[0073] Alternatively, in some embodiments, the process parameter analysis submodule 333 can select a target CD using simulated values ​​of process parameters in ways other than imaging cost. As an example, a target CD can be selected based on the closeness of the simulated values ​​of the process parameters to the target value tar. For instance, for a selected target CD, the simulated value of its corresponding process parameter is closest to the target value tar.

[0074] Examples of optimization algorithms As briefly mentioned earlier, the CD of the mask pattern can be varied within a sampling range to determine multiple mask CDs. The sampling range could be, for example, + / - 40 nm of the initial target CD. Photolithography imaging simulation can determine multiple ideal wafer CDs corresponding to the multiple mask CDs, along with simulated values ​​of the corresponding process parameters. Based on the simulated values ​​of the process parameters, the final target CD can be determined from the multiple ideal wafer CDs. Any suitable optimization algorithm can be used to vary the CD of the mask pattern within the sampling range.

[0075] In some embodiments, a serial optimization algorithm may be employed. For example, a sampling interval may be set, and then samples may be taken at equal intervals within the sampling range from the minimum mask CD to the maximum mask CD. This sampling interval may be set to a small value, or set according to the accuracy requirements of the pattern redefinition, the computing power of system 300, etc. Subsequently, the mask CD of the sampling point is set as the sample value, and the operations described above regarding the process window analysis submodule 331 and the lithography performance submodule 332 are performed to determine the simulated values ​​of the ideal wafer CD and process parameters corresponding to the mask CD. The above operations are repeated for the mask CD of all sampling points, and the value of the mask CD traverses all sampled values ​​within the sampling range.

[0076] After the traversal is complete, the process parameter analysis module 333 selects the target CD from the corresponding ideal wafer CD based on the simulated values ​​of the process parameters for each of the sampled mask CDs. For example, in an embodiment for calculating imaging cost, the total imaging cost for each mask CD can be calculated. Then, the mask CD corresponding to the lowest total imaging cost is determined. The simulated ideal wafer CD corresponding to this mask CD is determined as the target CD for the layout pattern.

[0077] In some embodiments, a parallel optimization algorithm may be employed. In such an embodiment, multiple rounds of iterative sampling can be performed on the mask CD. Each iteration is assigned its own sampling range. In the first iteration, an initial number of parallel samples can be set, followed by sampling at equal intervals within the initial sampling range according to the initial number of parallel samples. In this case, the corresponding sampling interval is related to the initial number of parallel samples and can be a larger value compared to the sampling interval in a serial optimization algorithm. The mask CD is set to these initial sample values ​​respectively. The operations described above with respect to the process window analysis submodule 331 and the lithography performance submodule 332 are performed in parallel (e.g., by different computing cores) for different initial mask CDs to determine the simulated values ​​of the ideal wafer CD and process parameters corresponding to these mask CDs respectively. Then, these initial mask CDs are sorted based on the simulated values ​​of the process parameters, such as the value based on the total imaging cost.

[0078] Based on the sorting results, a predetermined number (e.g., 3) of the top-ranked mask CDs are selected. These selected mask CDs will be used to determine the sampling range for the next iteration. Specifically, a new sampling sub-range can be determined within a certain range to the left and right of each of the selected mask CDs. For example, + / - 6nm of each selected mask CD can be used as a new sampling sub-range. These sampling sub-ranges constitute the sampling range for the next iteration. Then, based on the number of parallel samples for the next iteration, samples are taken at equal intervals within each sampling sub-range. The operations described above regarding the process window analysis submodule 331 and the lithography performance submodule 332 are performed in parallel for the sampled mask CDs to determine the ideal wafer CD and simulated values ​​of the process parameters corresponding to these mask CDs. Then, based on the simulated values ​​of the process parameters, a comprehensive sorting is performed with the mask CDs from the first iteration. This process is repeated for multiple iterations until the optimal ideal wafer CD, for example, the ideal wafer CD corresponding to the lowest imaging cost, is determined based on the simulated values ​​of the process parameters. This ideal wafer CD is determined as the target CD.

[0079] Figure 9 A schematic diagram of the sampling range in multiple iterations according to some embodiments of the present disclosure is shown. Figure 9 In the example, the first iteration has an initial sampling range 910 from the smallest mask CD to the largest mask CD, and the initial number of parallel samples is 7. Accordingly, in the first iteration, the operations described above regarding the process window analysis submodule 331 and the lithography performance submodule 332 are performed in parallel for the 7 initial mask CDs to determine the simulated values ​​of the ideal wafer CD and process parameters corresponding to these 7 mask CDs, respectively. Then, based on the simulated values ​​of the process parameters, such as the value based on the total imaging cost, the 7 initial mask CDs are sorted.

[0080] Based on the sorting results, the masks CD corresponding to sampling points 911, 912, and 913 were selected to determine the sampling range for the second round of iterations. For the second round of iterations, based on the masks CD corresponding to sampling points 911, 912, and 913, sampling sub-ranges 921, 922, and 923 were determined respectively. The union of sampling sub-ranges 921, 922, and 923 is the sampling range for the second round of iterations. In the second round of iterations, the number of parallel samples in each case within sampling sub-ranges 921, 922, and 923 ( Figure 9Example 2) involves equally spaced sampling to determine six mask CDs. The operations described above regarding the process window analysis submodule 331 and the lithography performance submodule 332 are then performed in parallel for these six mask CDs to determine the ideal wafer CD and simulated values ​​of the process parameters corresponding to these six mask CDs. Then, based on the simulated values ​​of the process parameters, a comprehensive ranking is performed with the seven mask CDs from the first iteration. This process is repeated for multiple iterations until the optimal ideal wafer CD, for example, the ideal wafer CD corresponding to the lowest imaging cost, is determined based on the simulated values ​​of the process parameters. This ideal wafer CD is then determined as the target CD.

[0081] It should be understood that Figure 9 The number of parallel samples and the number of mask CDs selected in each iteration shown are merely exemplary and are not intended to limit the scope of this disclosure. In embodiments of this disclosure, these numbers can be set according to actual needs.

[0082] Serial optimization algorithms can be used when the computing power of System 300 is insufficient. When the computing power of System 300 is sufficient, parallel optimization algorithms can greatly improve computational efficiency.

[0083] Furthermore, in the embodiment of the sampling parallel optimization algorithm, the above operation is performed for each layout graphic in layout 301 in each iteration. After each iteration, the size of the layout graphic can be set to the optimal CD determined in that iteration, that is, the layout graphic is redefined as the optimal CD of that iteration. Thus, at the beginning of each iteration except the first iteration, the surrounding environment of the layout graphic is the environment redefined in the previous iteration. As the number of iterations increases, the degree of overall redefinition will become smaller and smaller until convergence. Therefore, the simulation accuracy of the parallel optimization algorithm is also higher than that of the serial optimization algorithm.

[0084] Example of redefining operation Through the operation of the photolithography simulation module 321 described above, a target CD can be determined for each layout pattern. The redefinition module 322 sets the layout pattern to have a target CD. Specifically, the redefinition module 321 can add an offset pattern corresponding to the target CD to the layout pattern, and the offset caused by the offset pattern can be a positive or negative number. The set consisting of the initial pattern and the added offset pattern is the target pattern.

[0085] Figure 10 A schematic diagram of a portion of a redefined layout according to some embodiments of the present disclosure is shown. Layout region 1000 includes graphics 1010, 1020, and 1030. These graphics are further divided into several layout graphics. By adding corresponding offset graphics to these layout graphics, a layout is formed as shown... Figure 10 The redefined graph is shown.

[0086] In an embodiment employing a serial optimization algorithm, a redefinition operation is performed after the target CD is determined based on all mask CDs within the sampling range. In an embodiment employing a parallel optimization algorithm, in each iteration, a redefinition operation is performed based on the intermediate value of the target CD determined in the current iteration (i.e., the value of the optimal ideal wafer CD determined in the current iteration). In this embodiment, after the redefinition operation in each iteration, the measurement markers of the layout pattern need to be processed to align with the boundaries of the redefined layout pattern.

[0087] Furthermore, in some embodiments, the layout may also be additionally inspected and / or repaired to determine the final redefined layout 303. In such embodiments, the operation of the lithography simulation module 321 needs to be combined with inspection and / or repair, and repeated iteratively performed to execute the final redefinition operation.

[0088] Examples of inspection and repair Defect repair The redefined layout may contain defects such as notches and jogs. In some embodiments, these defects can be repaired to avoid negatively impacting subsequent OPC operations. For example, the inspection and repair module 323 can detect defects in the redefined layout, and each defect can have a corresponding detection standard. Offset graphics can be added to the detected defects to make the graphics at the defect level with the surrounding graphics.

[0089] Figure 11A A schematic diagram of a repair notch 1110 according to some embodiments of the present disclosure is shown. Figure 11A In the example, the inspection and repair module 323 detects a notch 1110 because the width 1112 is less than or equal to the threshold width for the notch, and the height 1111 is less than or equal to the threshold height for the notch. An offset graphic 1115 is added to the notch 1110 so that the graphic at the notch 1110 is flush with the surrounding graphic. In this way, the notch defect is repaired.

[0090] Figure 11B A schematic diagram of a repaired cleavage 1120 according to some embodiments of the present disclosure is shown. Figure 11B In the example, because the height 1121 is less than or equal to the threshold height for the cut, the inspection and repair module 323 detects the cut 1120. An offset graphic 1125 is added at the cut 1120 so that the graphic at the cut 1120 is aligned with the surrounding graphic. In this way, the cut defect is repaired.

[0091] Furthermore, since the process window for the patterns at the outer corners cannot be directly evaluated, the aforementioned model-based lithography simulation was not performed on the patterns at the outer corners. Accordingly, a method similar to defect repair can be used to add offset patterns to the outer corners, making them flush with the adjacent line patterns.

[0092] The defects and their remedies described above are merely exemplary and are not intended to limit the scope of this disclosure. Appropriate remedies can be applied to different types of defects.

[0093] Design rule check Every layer of graphics in the layout must meet constraints or limitations related to design rules. Although design rule checks (DRC) are performed on the layout during the initial layout design, the redefined layout may require further DRC checks, such as gap checks between adjacent polygons and correlation checks between different layers.

[0094] Figure 12 Examples of design rule-related constraints according to some embodiments of this disclosure are shown. Since graphics 1210 and 1220 will be split into different masks, a gap check is required on the gap 1201 between graphics 1210 and 1220, for example, to determine whether it satisfies gap constraints under different masks. Since graphics 1210 and 1230 will be split into the same mask, a gap check is required on the gap 1202 between graphics 1220 and 1230, for example, to determine whether it satisfies gap constraints under the same mask. Furthermore, an association check is required between graphics 1240 and graphics 1250 representing vias, for example, to determine whether the enclosure 1203 satisfies constraints.

[0095] In some embodiments, DRC can be implemented as a constraint on the redefinition operation. If the pattern redefinition according to the selected target CD does not meet the constraints related to the design rules, then the target CD will be discarded. A suboptimal wafer CD can be selected from multiple ideal wafer CDs as the target CD to redefine the layout pattern again.

[0096] As an example, in an embodiment employing a parallel optimization algorithm, after each iteration, the layout pattern in the layout is redefined according to the median value of the target CD determined in the current round. If the redefined layout pattern passes the DRC, it does not affect the direction of the iterative optimization. If it fails the DRC, the mask CD selected in that round is discarded, and the remaining mask CDs are reordered.

[0097] In some embodiments, DRC can be implemented as a supplement to the redefinition operation. In the redefinition operation, offset graphics corresponding to the target CD can be selectively added to at least one side of the layout graphic based on constraints related to design rules. For example, if adding an offset graphic to one side does not satisfy the constraints of DRC, the offset added to that side can be reduced, and a larger width offset graphic can be added to the other side to ensure that the total offset satisfies the target CD.

[0098] In some embodiments, the DRC (Design Rule Conformance) can be combined with simulated values ​​of process parameters to determine the target CD (Design Divide). The degree to which the DRC constraints are satisfied when the layout pattern is set to have the corresponding ideal wafer CD can be determined. The target CD is then selected based on this degree of satisfaction and the simulated values ​​of the process parameters. For example, in embodiments that consider imaging costs, a cost item related to the DRC can be added to the total cost. The greater the degree of satisfaction, i.e., the less the design rules are exceeded, the smaller this cost item; conversely, the smaller the degree of satisfaction, i.e., the more the design rules are exceeded, the larger the cost item.

[0099] Figure 13 An example of a layout that has been inspected and repaired according to some embodiments of this disclosure is shown. Layout area 1300 includes graphics 1310, 1320, and 1330. As indicated by arrow 1301, offset graphics are added only on the side of graphics 1310 away from graphics 1320, and the portion of graphics 1320 adjacent to graphics 1310 is not offset. In this way, the redefined layout can pass DRC.

[0100] The above is for reference only. Figures 3 to 13 Example operations of different modules are described. It should be understood that the operations described with respect to different embodiments can be combined. For example, in some embodiments, a parallel optimization algorithm may be employed, and DRC may be implemented as a complement to the redefinition operation. As another example, in some embodiments, a serial optimization algorithm may be employed, and DRC may be implemented as a complement to the redefinition operation. Yet another example, in some embodiments, a parallel optimization algorithm may be employed, and DRC may be combined with simulated values ​​of process parameters.

[0101] Example methods, apparatus, and devices Figure 14 A flowchart of an example method 1400 for redefining a layout drawing according to some embodiments of the present disclosure is shown. Method 1400 can be implemented by any suitable computing device or computing system. It should be understood that method 1400 may also include additional actions not shown and / or actions shown may be omitted. The scope of the present disclosure is not limited in this respect.

[0102] In box 1410, multiple mask patterns corresponding to the layout pattern in the circuit layout are determined. These multiple mask patterns have different dimensions. For example, parallel or serial optimization algorithms can be used to vary the mask CD within the sampling range to determine the multiple mask patterns.

[0103] In some embodiments, to determine multiple mask patterns, a subset of the multiple mask patterns can be determined in each iteration of multiple iterations by changing the size of the mask patterns within a sampling range for that iteration. In this embodiment, method 1400 may further include: in each iteration, determining an intermediate value for a target size based on a subset of the multiple mask patterns; and setting the size of a layout pattern in the circuit layout to the intermediate value for use in the next iteration. For example, a parallel optimization algorithm may be employed.

[0104] In some embodiments, method 1400 may further include: selecting a predetermined number of mask patterns from a first subset based on simulated values ​​of process parameters corresponding to a first subset of a plurality of mask patterns, the first subset being determined in a first iteration; and determining a sampling range for a second iteration based on the dimensions of the predetermined number of mask patterns, for determining a second subset of the plurality of mask patterns in the second iteration, the second iteration immediately following the first iteration. For example, sampling sub-ranges 921, 922, and 923 may be determined based on the mask CDs corresponding to sampling points 911, 912, and 913, respectively. The union of sampling sub-ranges 921, 922, and 923 is the sampling range for the second iteration.

[0105] In box 1420, the dimensions of multiple wafer patterns formed based on multiple mask patterns are determined through photolithography imaging simulation. For example, using a photolithography imaging model, multiple ideal wafer CDs corresponding to multiple mask CDs can be determined. In box 1430, for each of the multiple wafer patterns, simulated values ​​of process parameters used to evaluate process windows or imaging quality are determined. For example, simulated values ​​of parameters such as DOF, ILS, and MEEF can be determined.

[0106] In box 1440, the target dimension is determined from the dimensions of multiple wafer patterns, based at least on simulated values ​​of process parameters. For example, the determined target CD can optimize the process parameters.

[0107] In some embodiments, imaging cost may be considered to determine the target size. The imaging cost for forming the corresponding wafer pattern can be determined based on thresholds, target values, and simulated values ​​for process parameters. The size of the wafer pattern with the lowest imaging cost can be determined as the target size. The ideal wafer CD that minimizes the total cost function can be determined as the target CD.

[0108] In some embodiments, to determine the target size, the DRC can be combined with process parameters. For each of a plurality of wafer patterns, the degree to which a layout pattern configured to have the dimensions of the wafer pattern satisfies constraints can be determined. Constraints are related to design rules for the layout pattern. The target size can be determined from the dimensions of the plurality of wafer patterns based on simulated values ​​of process parameters and the degree of satisfaction. For example, a cost term related to the degree of satisfaction can be added to the total cost function.

[0109] In box 1450, set the layout graphic in the circuit layout to have a target size. For example, you can add an offset graphic to the layout graphic that corresponds to the target size.

[0110] In some embodiments, DRC can be implemented as a complement to the redefinition operation. For example, constraints related to design rules for the layout graphic can be obtained; and based on these constraints, offset graphics corresponding to the target size can be selectively added to at least one of a first side or a second side of the layout graphic. The second side is opposite to the first side.

[0111] In some embodiments, defects can also be repaired. Method 1400 may further include: detecting a predetermined type of defect in the circuit layout in response to the layout pattern being set to have a target size; and adding an offset pattern at the detected defect so that the pattern at the detected defect is aligned with the surrounding pattern.

[0112] In some embodiments, to determine a target size for each layout graphic, the original graphic in the layout may be segmented. Method 1400 may further include: identifying the type of graphic in the circuit layout; and dividing the graphic into a plurality of layout graphics including the layout graphic based on the identified type and the relative position of the graphic to surrounding graphics.

[0113] Figure 15 A schematic block diagram of an apparatus 1500 for redefining layout graphics according to some embodiments of the present disclosure is shown. The apparatus 1500 can be used to implement or be included in a computing device or computing system implementing method 1400. Figure 15As shown, the apparatus 1500 includes a mask pattern determination unit 1510 configured to determine multiple mask patterns corresponding to layout patterns in a circuit layout, the multiple mask patterns having different sizes. The apparatus 1500 also includes a wafer pattern determination unit 1520 configured to determine the sizes of multiple wafer patterns formed based on the multiple mask patterns through photolithography imaging simulation. The apparatus 1500 further includes a process parameter determination unit 1530 configured to determine, for each of the multiple wafer patterns, simulated values ​​of process parameters used to evaluate process windows or imaging quality. The apparatus 1500 also includes a target size determination unit 1540 configured to determine a target size from the sizes of the multiple wafer patterns, at least based on the simulated values ​​of the process parameters. The apparatus 1500 also includes a redefinition unit 1550 configured to set the layout pattern in the circuit layout to have a target size. In some embodiments, the mask pattern determination unit 1510 is further configured to: determine a subset of multiple mask patterns by changing the size of the mask pattern within a sampling range for that iteration in each iteration of multiple iterations, and wherein the target size determination unit 1540 is further configured to determine an intermediate value for a target size based on the subset of multiple mask patterns in each iteration; and the redefinition unit 1550 is further configured to set the size of the layout pattern in the circuit layout to the intermediate value for use in the next iteration.

[0114] In some embodiments, the apparatus 1500 further includes: a mask pattern selection unit configured to select a predetermined number of mask patterns from the first subset based on simulated values ​​of process parameters corresponding to a first subset of a plurality of mask patterns, the first subset being determined in a first iteration; and a sampling range determination unit configured to determine a sampling range for a second iteration based on the dimensions of the predetermined number of mask patterns, for determining a second subset of the plurality of mask patterns in the second iteration, the second iteration immediately following the first iteration.

[0115] In some embodiments, the redefinition unit 1550 is further configured to: acquire constraints related to design rules for the layout graphic; and, based on the constraints, selectively add an offset graphic corresponding to the target size to at least one of a first side or a second side of the layout graphic, the second side being opposite to the first side.

[0116] In some embodiments, the target size determination unit 1540 is further configured to: for each of a plurality of wafer patterns, determine the degree to which a layout pattern set to have the size of the wafer pattern satisfies constraints related to design rules for the layout pattern; and determine a target size from the sizes of the plurality of wafer patterns based on simulation values ​​of process parameters and the degree of satisfaction.

[0117] In some embodiments, the target size determination unit 1540 is further configured to: determine the imaging cost of forming the corresponding wafer pattern based on the threshold, target value and simulation value for the process parameters; and determine the size of the wafer pattern with the lowest imaging cost as the target size.

[0118] In some embodiments, the apparatus 1500 further includes: a defect detection unit configured to detect a predetermined type of defect in a circuit layout in response to a layout pattern being set to have a target size; and a defect repair unit configured to add an offset pattern at the detected defect so that the pattern at the detected defect is flush with the surrounding pattern.

[0119] In some embodiments, the apparatus 1500 further includes: a graphic classification unit configured to identify the type of graphic in a circuit layout; and a graphic segmentation unit configured to divide the graphic into a plurality of layout graphics including the layout graphic based on the identified type and the relative position of the graphic with respect to surrounding graphics.

[0120] Figure 16 A schematic block diagram of a device 1600 capable of implementing various embodiments of the present application is shown. The device 1600 can be used to implement a method for redefining layout graphics according to the present disclosure. As shown, the device 1600 includes a computing unit 1601, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 1602 or loaded from a storage unit 1607 into RAM 1603 and / or ROM 1602. Various programs and data required for the operation of the device 1600 may also be stored in RAM 1603 and / or ROM 1602. The computing unit 1601 and RAM 1603 and / or ROM 1602 are interconnected via a bus 1604. An input / output (I / O) interface 1605 is also connected to the bus 1604.

[0121] Multiple components in device 1600 are connected to I / O interface 1605, including: input unit 1606, such as keyboard, mouse, etc.; output unit 1607, such as various types of monitors, speakers, etc.; storage unit 1608, such as disk, optical disk, etc.; and communication unit 1609, such as network card, modem, wireless transceiver, etc. Communication unit 1609 allows device 1600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0122] The computing unit 1601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 1601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 1601 performs the various methods and processes described above, such as method 1400. For example, in some embodiments, method 1400 may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 1608. In some embodiments, part or all of the computer program may be loaded and / or installed on device 1600 via RAM 1603 and / or ROM 1602 and / or communication unit 1609. When the computer program is loaded into RAM 1603 and / or ROM 1602 and executed by the computing unit 1601, one or more steps of method 1400 described above may be performed. Alternatively, in other embodiments, the computing unit 1601 may be configured to perform method 1400 by any other suitable means (e.g., by means of firmware).

[0123] The program code used to implement the methods of this application may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing device, such that when executed by the processor or controller, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0124] In the context of this application, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. Machine-readable media can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0125] Furthermore, although the operations are described in a specific order, this should be understood as requiring that such operations be performed in the specific order shown or in sequential order, or requiring that all illustrated operations be performed to achieve the desired result. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although several specific implementation details are included in the above discussion, these should not be construed as limiting the scope of this application. Certain features described in the context of individual embodiments may also be implemented in combination in a single implementation. Conversely, various features described in the context of a single implementation may also be implemented individually or in any suitable sub-combination in multiple implementations.

[0126] Although the subject matter has been described using language specific to structural features and / or methodological logic, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are merely illustrative examples of implementing the claims.

Claims

1. A method for redefining a layout graphic, characterized in that, The method includes: Determine multiple mask patterns corresponding to the layout pattern in the circuit layout, wherein the multiple mask patterns have different sizes; The dimensions of the multiple wafer patterns formed on the wafer based on the multiple mask patterns are determined by photolithography imaging simulation. For each of the plurality of wafer patterns, simulated values ​​of process parameters are determined for evaluating process windows or imaging quality; The target size is determined from the dimensions of the plurality of wafer patterns, at least based on the simulated values ​​of the process parameters; and Set the layout graphic in the circuit layout to have the target size.

2. The method according to claim 1, characterized in that, Determining the plurality of mask patterns includes: In each of the multiple iterations, a subset of the multiple mask patterns is determined by changing the size of the mask patterns within the sampling range of that iteration. The method also includes: In each iteration, an intermediate value for the target size is determined based on the subset of the plurality of mask patterns; and The size of the layout graphic in the circuit layout is set to the intermediate value for use in the next iteration.

3. The method according to claim 2, characterized in that, The method further includes: Based on the simulated values ​​of the process parameters corresponding to a first subset of the plurality of mask patterns, a predetermined number of mask patterns are selected from the first subset, which is determined in a first round of iterations; and Based on the dimensions of the predetermined number of mask patterns, a sampling range is determined for the second round of iterations to determine a second subset of the plurality of mask patterns in the second round of iterations, which immediately follows the first round of iterations.

4. The method according to any one of claims 1 to 3, characterized in that, Setting the layout graphic in the circuit layout to have the target size includes: Obtain the constraints related to the design rules for the layout graphic; and Based on the constraints, an offset graphic corresponding to the target size is selectively added to at least one of the first side or the second side of the layout graphic, wherein the second side is opposite to the first side.

5. The method according to any one of claims 1 to 4, characterized in that, Determining the target size from the dimensions of the plurality of wafer patterns based at least on simulated values ​​of the process parameters includes: For each of the plurality of wafer patterns, determine the degree to which the layout pattern, configured to have the dimensions of the wafer pattern, satisfies constraints related to design rules for the layout pattern; and Based on the simulated values ​​of the process parameters and the degree of satisfaction, the target size is determined from the dimensions of the plurality of wafer patterns.

6. The method according to claim 5, characterized in that, Determining the target size from the dimensions of the plurality of wafer patterns based at least on simulated values ​​of the process parameters includes: Based on the threshold values, target values, and simulation values ​​for the process parameters, the imaging cost for forming the corresponding wafer pattern is determined; and The size of the wafer pattern with the lowest imaging cost is determined as the target size.

7. The method according to claim 6, characterized in that, The method further includes: In response to the layout pattern being set to have the target size, a predetermined type of defect is detected in the circuit layout; and An offset graphic is added to the detected defect so that the graphic at the detected defect is aligned with the surrounding graphic.

8. The method according to any one of claims 6 to 7, characterized in that, The method further includes: Identify the type of graphic in the circuit layout; and Based on the identified type and the relative position of the graphic with surrounding graphics, the graphic is divided into multiple layout graphics that include the layout graphic.

9. An apparatus for redefining layout graphics, characterized in that, The device includes: A mask pattern determination unit is configured to determine multiple mask patterns corresponding to a layout pattern in a circuit layout, the multiple mask patterns having different sizes; The wafer pattern determination unit is configured to determine the size of multiple wafer patterns formed on the wafer based on the multiple mask patterns through photolithography imaging simulation; The process parameter determination unit is configured to determine simulated values ​​of process parameters for evaluating process windows or imaging quality for each of the plurality of wafer patterns. A target size determination unit is configured to determine a target size from the dimensions of the plurality of wafer patterns, based at least on simulated values ​​of the process parameters; and The redefinition unit is configured to set the layout graphic in the circuit layout to have the target size.

10. The apparatus according to claim 9, characterized in that, The mask pattern determination unit is further configured to: In each of the multiple iterations, a subset of the multiple mask patterns is determined by changing the size of the mask pattern within the sampling range of that iteration. Furthermore, the target size determination unit is further configured to determine an intermediate value for the target size based on the subset of the plurality of mask patterns in each iteration; and The redefinition unit is further configured to set the size of the layout graphic in the circuit layout to the intermediate value for use in the next iteration.

11. The apparatus according to claim 10, characterized in that, The device further includes: A mask pattern selection unit is configured to select a predetermined number of mask patterns from a first subset of the plurality of mask patterns based on simulated values ​​of the process parameters corresponding to a first subset, the first subset being determined in a first iteration; and A sampling range determination unit is configured to determine a sampling range for a second iteration based on the dimensions of the predetermined number of mask patterns, for determining a second subset of the plurality of mask patterns in the second iteration, which immediately follows the first iteration.

12. The apparatus according to any one of claims 9 to 11, characterized in that, The redefinition unit is further configured as follows: Obtain the constraints related to the design rules for the layout graphic; and Based on the constraints, an offset graphic corresponding to the target size is selectively added to at least one of the first side or the second side of the layout graphic, wherein the second side is opposite to the first side.

13. The apparatus according to claim 12, characterized in that, The target size determination unit is further configured to: For each of the plurality of wafer patterns, determine the degree to which the layout pattern, which is configured to have the size of the wafer pattern, satisfies the constraints related to the design rules for the layout pattern; as well as Based on the simulated values ​​of the process parameters and the degree of satisfaction, the target size is determined from the dimensions of the plurality of wafer patterns.

14. The apparatus according to claim 13, characterized in that, The target size determination unit is further configured to: Based on the threshold values, target values, and simulation values ​​for the process parameters, the imaging cost for forming the corresponding wafer pattern is determined; and The size of the wafer pattern with the lowest imaging cost is determined as the target size.

15. The apparatus according to claim 14, characterized in that, The device further includes: A defect detection unit is configured to detect a predetermined type of defect in the circuit layout in response to the layout pattern being set to have the target size; and The defect repair unit is configured to add an offset graphic at the detected defect so that the graphic at the detected defect is aligned with the surrounding graphic.

16. The apparatus according to any one of claims 13 to 15, characterized in that, The device further includes: A graphic classification unit is configured to identify the type of graphic in the circuit layout; and A graphic segmentation unit is configured to divide the graphic into multiple layout graphics, including the layout graphic, based on the identified type and the relative position of the graphic with surrounding graphics.

17. An electronic device, characterized in that, include: At least one processor; At least one memory coupled to the at least one processor and storing instructions for execution by the at least one processor, the instructions, when executed by the at least one processor, causing the electronic device to perform the method according to any one of claims 1-8.

18. A computer-readable storage medium, characterized in that, It stores a computer program that, when executed by a processor, implements the method according to any one of claims 1-8.

19. A computer program product, characterized in that, Includes computer-executable instructions, wherein the computer-executable instructions, when executed by a processor, implement the method according to any one of claims 1-8.

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