Transmit module and method for transmitting differential signals in a serial bus system

Abstract

The present invention provides a transmitting module (121; 1210) and a method for transmitting differential signals in a serial bus system (1). The transmitting module (121; 1210) has: a first transmitting stage (121A; 121A0) for generating a transmitting current (I1 to In) for a first signal (CAN_H), which can be transmitted to the bus (40) of the bus system (1); a second transmitting stage (121B; 121B0) for generating a transmitting current (I1 to In) for a second signal (CAN_L), which can be transmitted to the bus (40) as a differential signal relative to the first signal (CAN_H); a third transmitting stage (121C; 121C0) for generating a transmitting current (I1 to In) for the first signal (CAN_H); and a fourth transmitting stage (121D; 121D0) for generating a transmitting current (I1 to In) for the second signal (CAN_L), wherein the first transmitting stage to the fourth transmitting stage (121A to 121D; 121A0 to 121D0) are connected in a full bridge, in which The first and fourth transmitting stages (121A, 121D; 121A0, 121D0) are connected in series, and the third and second transmitting stages (121C, 121B; 121C0, 121B0) are connected in series. Each of the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) has at least two current stages (S1 to Sn) connected in parallel with each other. Each of the two current stages (S1 to Sn) has switchable resistors (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn), and the switchable resistors (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of the transmitting stage (121A to 121D; 121A0 to 121D0) have different resistance values.

Description

Technical Field

[0001] The present invention relates to a transmitting module and a method for transmitting differential signals in a serial bus system, which is particularly applicable to CAN XL. Background Technology

[0002] Serial bus systems are used for message or data transmission in technical equipment. For example, they enable communication between sensors and controllers in vehicles or technical production equipment. Different standards or data transmission protocols exist for data transmission. Notably, CAN bus systems, LVDS (Low Voltage Differential Signaling), MSC (Micro-Second Channel), and 10BASE-T1S Ethernet are known.

[0003] In a CAN bus system, messages are transmitted using the CAN protocol and / or CANFD protocol, as described in the ISO-11898-1:2015 standard as a CAN protocol specification with CAN FD. In CAN FD, the transmission on the bus switches between a slow operation in the first communication phase (arbitration phase) and a fast operation in the second communication phase (data phase). In a CAN FD bus system, data transmission rates greater than 1 megabit per second (1 Mbps) can be achieved in the second communication phase. CANFD was initially used in vehicles by most manufacturers with an arbitration bit rate of 500 kbit / s and a data bit rate of 2 Mbit / s.

[0004] To achieve even higher data transfer rates in the second communication phase, successor bus systems for CAN FD exist, such as CAN-SIC and CAN XL. In CAN-SIC, conforming to the CiA 601-4 standard, a data transfer rate of approximately 5 to 8 Mbit / s can be achieved in the second communication phase. CAN XL requires a data transfer rate >10 Mbit / s in the second communication phase, for which the standard (CiA 610-3) is currently defined within the CAN Automation Organization (CiA). In addition to pure data transmission via the CAN bus, CAN XL should also support other functions such as functional safety, data security, and Quality of Service (QoS). These are essential characteristics required for autonomous vehicles.

[0005] In all the CAN-based bus systems mentioned above, the bus signal CAN_H is driven onto the bus independently of the transmit signal TxD, and ideally, the bus signal CAN_L is driven onto the bus simultaneously. Here, the bus state is actively driven at least during the first communication phase of the bus signals CAN_H and CAN_L. Other bus states are not driven and are set by the terminating resistors used for the bus lines, or the bus cores. Due to the different driven states, the signal shapes of the bus signals CAN_H and CAN_L in a real bus system may deviate from the ideal signal shape. This is particularly due to bus system design factors, such as branch lines and switching delays in the switching stages for the bus signals CAN_H and CAN_L. Such mismatches between the two bus signals CAN_H and CAN_L can lead to errors when evaluating the bus signals received by the bus.

[0006] To send and receive bus signals, CAN bus systems for individual communication users typically use transmit / receive devices, also known as CAN transceivers or CAN FD transceivers. CAN transceivers or CAN FD transceivers are not allowed to exceed the limits for vehicle operation in terms of conducted transmission or radiation. Transceivers used for CAN XL must therefore adhere to even stricter limits, defined in the IEC 62228-3 standard. Only in this way can the bus system operate at a predetermined bit rate higher than that in CAN FD and CAN SIC. Adhering to these stringent limits presents a significant challenge, given the available semiconductor technology.

[0007] Compared to CANFD, transceivers used for CAN-SIC or CAN-XL require a third state, the SIC state, in addition to the recessive (rec) and dominant (dom) states, during the arbitration phase, also known as SIC mode or SIC operation. To meet the radiation requirements of the IEC 62228-3 standard, the common-mode voltage of the bus lines for the signals CAN_H and CAN_L must be kept within narrow limits across the three transmission states: recessive, dominant, and SIC. The common-mode voltage occurs at a common-mode choke, which is particularly used in certification measurements to verify compliance with the IEC 62228-3 standard. The common-mode choke is also known as the Common-Mode Choke (CMC). The purpose of the common-mode choke is to allow differential signals (DM = differential mode) to pass through as little as possible without interference and to suppress common-mode signals (CM = common mode) as completely as possible. However, in actual operation, the common-mode choke can generate an unwanted common-mode signal at the output from the differential signal at the input, which has no common-mode share. This is disadvantageous because it is then directly fed into the CAN bus on the bus side and is visible to other CAN modules. Summary of the Invention

[0008] Therefore, the object of the present invention is to provide a transmitting module and a method for transmitting differential signals in a serial bus system, which solves the problems mentioned above. In particular, the transmitting module and method for transmitting differential signals in a serial bus system should be able to compensate for interference parameters acting on the radiation characteristics of the transmitting module.

[0009] This objective is achieved by a transmitting module having the features of claim 1 for transmitting differential signals in a serial bus system. The transmitting module comprises: a first transmitting stage for generating a transmitting current for a first signal capable of being transmitted onto the bus of the bus system; a second transmitting stage for generating a transmitting current for a second signal capable of being transmitted onto the bus as a differential signal relative to the first signal; a third transmitting stage for generating a transmitting current for the first signal; and a fourth transmitting stage for generating a transmitting current for the second signal, wherein the first to fourth transmitting stages are connected in a full-bridge configuration, wherein the first and fourth transmitting stages are connected in series, and the third and second transmitting stages are connected in series, wherein each of the first to fourth transmitting stages has at least two current stages connected in parallel with each other, wherein each of the at least two current stages has a switchable resistor, and wherein the switchable resistors of the transmitting stages have different resistance values.

[0010] The described transmitting module is capable of achieving the required limits on radiation for the transmitting / receiving devices used in CAN XL. Specifically, the transmitting module conforms to the IEC 62228-3 standard, which defines the limits to be followed for bus states dom, sic, and rec.

[0011] The transmitting module, for example, can, in SIC mode, precisely match the impedance between the bus lines used for signals CAN_H and CAN_L to the characteristic ripple resistance, or impedance, of the bus lines used. For the impedance Zw of the bus lines used, Zw = 100 ohms or Zw = 120 ohms is applicable here. Thus, the transmitting module prevents reflections and therefore allows operation at higher bit rates in the bus system.

[0012] The described transmission module allows for a time-staggered and controlled switching process by dividing its four transmission stages into n parts. Access can be implemented according to a Gaussian error function. This enables the setting of soft characteristics during the access process. Furthermore, the potential variation in the time stages during access prevents narrowband frequency lines from appearing in the transmission spectrum.

[0013] Alternatively, the described transmitting module can be used to implement an interleaved and controlled switching process using fixed time steps and varying voltage steps. This also allows the radiation characteristics of the transmitting module to be influenced to conform to predetermined limits.

[0014] Furthermore, the described transmitting module can reduce the effects caused by the asymmetric characteristics of the transmitting stages, which may occur in the transmitting states dom, sic, and rec and worsen radiation. The transmitting module prevents the different characteristics of the components in the transmitting stages A and B of the full bridge (Effect 1), thereby minimizing or preventing the change in common-mode voltage in the dom state compared to the rec state. Moreover, the transmitting module can prevent the different characteristics of the components in the transmitting stages A / D and C / B of the full bridge (Effect 2), thereby minimizing or preventing the change in common-mode voltage in the sic state compared to the rec state. This is particularly advantageous because sufficient radiation results can only be obtained when the common-mode levels in the dom and sic states are matched with the common-mode level in the rec state, starting from the common-mode level in the rec state; however, the causes of the characteristics leading to Effect 1 may be different from those leading to Effect 2.

[0015] Advantageous alternative designs for the transmitting module are described in the dependent claims.

[0016] The output connectors of the full bridge can be configured for connection with terminating resistors on the bus.

[0017] In a feasible manner, the number n of at least two current stages is the same for each of the first to fourth transmitting stages, where n is a natural number greater than 1.

[0018] In one design, each of at least two current stages has a CMOS transistor for switching the resistance of the current stage.

[0019] In one embodiment, the CMOS transistor of the current stage of the first transmitting stage is a PMOS transistor, the CMOS transistor of the current stage of the second transmitting stage is an NMOS transistor, the CMOS transistor of the current stage of the third transmitting stage is a PMOS transistor, and the CMOS transistor of the current stage of the fourth transmitting stage is an NMOS transistor.

[0020] Here, each of the first to fourth transmitting stages is also capable of having a reverse diode to protect against positive feedback in the connector for the bus voltage supply section and negative feedback in the connector for the ground section, and has at least one cascode structure to protect the CMOS transistor.

[0021] In another embodiment, at least two cascode structures are connected in parallel with each other, wherein the number y of cascode structures is the same for each of the first to fourth transmitter stages, wherein y is a natural number greater than 1, and wherein the access resistances of the at least two cascode structures are different.

[0022] The transmitting module may also have at least one first current limiting module as a power supply and at least one second current limiting module as a current sink. The first current limiting module is connected between the connector for the bus voltage supply section and the full bridge, and the second current limiting module is connected between the connector for the ground section and the full bridge.

[0023] According to one embodiment, at least two first current limiting modules are connected in parallel with each other and have different access resistances, wherein at least two second current limiting modules are connected in parallel with each other and have different access resistances, and wherein the number x of the first current limiting modules is equal to the number x of the second current limiting modules, where x is a natural number greater than 1.

[0024] The transmitting module may further include control circuitry for controlling switchable components of the first to fourth transmitting stages according to digitally transmitted signals and an operating mode set for the transmitting module. In a feasible manner, the control circuitry is designed to switch the resistance values ​​of at least two current stages in a time-interleaved and controlled manner.

[0025] The transmitting module described above can be part of a transmitting / receiving device for a user station in a serial bus system, which in turn has a receiving module for receiving signals from the bus.

[0026] The transmitting / receiving device can be part of a user station for a serial bus system, which in turn has a communication control device for controlling communication in the bus system and generating digital transmission signals for controlling the first to fourth transmitting stages.

[0027] In a feasible manner, the user station is designed for communication in a bus system, in which at least temporarily guaranteed dedicated, conflict-free access to the bus of the bus system.

[0028] The aforementioned objective is further achieved by a method for transmitting differential signals in a serial bus system, having the features of claim 15. This method is implemented using a transmitting module, comprising the steps of: generating a transmitting current for a first signal using a first transmitting stage, the first signal being capable of being transmitted onto the bus of the bus system; generating a transmitting current for a second signal using a second transmitting stage, the second signal being capable of being transmitted onto the bus as a differential signal relative to the first signal; generating a transmitting current for the first signal using a third transmitting stage, and generating a transmitting current for the second signal using a fourth transmitting stage, wherein the first to fourth transmitting stages are connected in a full-bridge configuration, in which the first and fourth transmitting stages are connected in series, and the third and second transmitting stages are connected in series, wherein each of the first to fourth transmitting stages has at least two current stages connected in parallel with each other, wherein each of the at least two current stages has a switchable resistor, and wherein the switchable resistors of the transmitting stages have different resistance values.

[0029] This method offers the same advantages as mentioned earlier regarding the sending module.

[0030] Other possible implementations of the invention also include combinations of features or implementations not explicitly mentioned in the foregoing or hereinafter regarding the embodiments. Those skilled in the art will also consider various aspects as improvements or supplements to the corresponding basic form of the invention. Attached Figure Description

[0031] The invention will be described in more detail below with reference to the accompanying drawings and embodiments. Wherein:

[0032] Figure 1 A simplified block diagram of the bus system according to the first embodiment is shown;

[0033] Figure 2A diagram illustrating the structure of a message that can be sent by a user station of a bus system according to a first embodiment is shown.

[0034] Figure 3 Showing the target Figure 1 An example of the ideal time flow of bus signals CAN_H and CAN_L in a bus system;

[0035] Figure 4 The time trend of the differential voltage VDIFF is shown, which is based on the bus of the bus system. Figure 4 It is constructed from bus signals;

[0036] Figure 5 An embodiment is shown for the time trend of a digital transmitted signal, which should be converted into a signal for use during the arbitration phase (SIC operation mode). Figure 1 The bus signals of the bus system are CAN_H and CAN_L;

[0037] Figure 6 This illustrates the timeline of bus signals CAN_H and CAN_L during the transition from a recessive bus state to a dominant bus state and back to a recessive bus state. These bus signals operate based on the arbitration phase (SIC mode). Figure 5 The transmitted signal is sent to the bus;

[0038] Figure 7 An embodiment is shown for the time trend of a digital transmitted signal, which should be converted into a signal for use in the data phase. Figure 1 The bus signals of the bus system are CAN_H and CAN_L;

[0039] Figure 8 The time trends of bus signals CAN_H and CAN_L are shown, which are based on the data phase. Figure 6 The transmitted signal is sent to the bus;

[0040] Figure 9 A circuit diagram of a transmitting module for a user station in a bus system according to the first embodiment is shown;

[0041] Figure 10 against Figure 9 A first specific embodiment of the transmitting module shows timing diagrams illustrating different current levels connected to the transmitting stage;

[0042] Figure 11 against Figure 9 A second specific embodiment of the transmitting module illustrates details of the transmitting stage; and

[0043] Figure 12 A circuit diagram of a transmitting module for a user station in a bus system according to the second embodiment is shown. Detailed Implementation

[0044] In the accompanying drawings, elements that are the same or have the same function are given the same reference numerals, unless otherwise specified.

[0045] Figure 1 A bus system 1 is shown, which can be, for example, at least partially, a CAN bus system, a CAN-FD bus system, etc. Bus system 1 can be used in vehicles, especially motor vehicles, aircraft, etc., or in hospitals, etc.

[0046] exist Figure 1 In this system, bus system 1 has multiple user stations 10, 20, and 30, which are respectively connected to bus 40 or bus lines having a first bus core wire 41 and a second bus core wire 42. For signals on bus 40, bus core wires 41 and 42 can also be referred to as CAN_H and CAN_L. Messages 45, 46, and 47 can be transmitted between the various user stations 10, 20, and 30 in the form of signals via bus 40. User stations 10, 20, and 30 can be, for example, controllers or display devices of a motor vehicle.

[0047] like Figure 1 As shown, user stations 10 and 30 each have a communication control device 11 and a transmitting / receiving device 12. The transmitting / receiving device 12 has a transmitting module 121 and a receiving module 122.

[0048] User station 20 has a communication control device 21 and a transmitting / receiving device 22. The transmitting / receiving device 22 has a transmitting module 221 and a receiving module 222.

[0049] The transmitting / receiving devices 12 of user stations 10 and 30 and the transmitting / receiving device 22 of user station 20 are directly connected to bus 40, even when Figure 1 It is not shown in the text.

[0050] Communication control devices 11 and 21 are respectively used to control the communication between corresponding user stations 10, 20, and 30 and at least one other user station of user station 10, 20, and 30 via bus 40, wherein the other user station is connected to bus 40.

[0051] Communication control unit 11 creates and reads first messages 45 and 47, which are, for example, modified CAN messages 45 and 47. Here, the modified CAN messages 45 and 47 are constructed, for example, according to CAN SIC or CAN XL format. Transmit / receive unit 12 is used to transmit to and receive messages 45 and 47 from the bus. Transmit module 121 receives a digital transmit signal TxD created by communication control unit 11 for one of messages 45 and 47 and converts the digital transmit signal into a signal on bus 40. Receiving module 121 receives the signals corresponding to messages 45 to 47 transmitted on bus 40 and thereby generates a digital receive signal RxD. Receiving module 122 transmits the receive signal RxD to communication control unit 11.

[0052] The communication control unit 21 can be implemented as a conventional CAN controller according to ISO 11898-1:2015, that is, as a classic CAN controller or CANFD controller compatible with CAN FD. The communication control unit 21 creates and reads a second message 46, such as a CANFD message 46. The transmit / receive unit 22 is used to transmit to and receive messages 46 from the bus 40. The transmit module 221 receives the digital transmit signal TxD created by the communication control unit 21 and converts it into a signal for the message 46 on the bus 40. The receive module 221 receives the signals corresponding to messages 45 to 47 transmitted on the bus 40 and thereby generates a digital receive signal RxD. Furthermore, the transmit / receive unit 22 can be implemented as a conventional CAN transceiver.

[0053] To utilize CAN XL or CAN SIC for transmitting messages 45 and 47, empirically proven characteristics responsible for the robustness and user-friendliness of CAN and CAN FD are employed, specifically a frame structure with identifiers and arbitration according to the known CSMA / CR method. The CSMA / CR method necessitates the provision of a so-called recessive state on bus 40, which can be overwritten by other user stations 10, 20, and 30 on bus 40 that have a dominant level or dominant state.

[0054] Using two user stations 10 and 30, it is possible to form and then transmit messages 45 with different CAN formats, especially CANFD, CAN SIC, or CAN XL, and to receive such messages 45, as described in more detail below.

[0055] Figure 2Message 45 illustrates the following frame 450, which is in particular a CAN XL frame, as it is provided by the communication control unit 11 to the transmitting / receiving unit 12 for transmission onto the bus 40. Here, in this embodiment, the communication control unit 11 creates frame 450 in a manner compatible with CANFD. Alternatively, frame 450 is compatible with CAN SIC.

[0056] according to Figure 2 Frame 450 is divided into different communication phases 451 and 452 for CAN communication on bus 40, namely arbitration phase 451 (first communication phase) and data phase 452 (second communication phase). After the start bit SOF, frame 450 has an arbitration field 453, a control field 454, a data field 455, a checksum field 456, and a frame end field 457.

[0057] In arbitration phase 451, user stations 10, 20, and 30 agree bit-by-bit on which user station 10, 20, and 30 wants to send messages 45 and 46 with the highest priority and thus obtain dedicated access to bus 40 of bus system 1 for transmission in the subsequent data phase 452, using identifiers (IDs) such as bits ID28 to ID18 in arbitration field 453. The physical layer is used in arbitration phase 451 as in CAN and CAN-FD. The physical layer corresponds to the bit transport layer or layer 1 of the known OSI model (Open Systems Interconnection Model 1).

[0058] An important point during phase 451 is the use of the known CSMA / CR method, which allows user stations 10, 20, and 30 to access bus 40 simultaneously without disrupting higher-priority messages 45 and 46. This makes it relatively easy to add additional bus user stations 10, 20, and 30 to bus system 1, which is highly advantageous.

[0059] The CSMA / CR method necessitates the introduction of a so-called recessive state on bus 40, which can be overwritten by other user stations 10, 20, and 30 on bus 40 that have a dominant level or dominant state. The recessive state results in high impedance at each user station 10, 20, and 30, which, combined with parasitic phenomena in the bus circuitry, leads to a longer time constant. This limits the maximum bit rate of the current CAN-FD physical layer to approximately 2 megabits per second in practical vehicle applications.

[0060] In data phase 452, in addition to a portion of control field 454, valid data from data field 455, along with checksum field 456, of CAN-XL frame 450, or message 45, is transmitted. Checksum field 456 can include a checksum of the data from data phase 452, including padding bits, which are inserted as reverse bits by the transmitter of message 45 after a predetermined number of identical bits, specifically 10 identical bits. At the end of data phase 452, the system switches back to arbitration phase 451.

[0061] At least one acknowledgment bit can be included in the end field of the frame end phase 457. Furthermore, a sequence of 11 identical bits indicating the end of the CAN XL frame 450 can be present. The at least one acknowledgment bit can be used to notify the receiver whether any errors were found in the received CAN XL frame 450, or message 45.

[0062] The transmitter of message 45 only begins to send bits of data stage 452 onto bus 40 when user station 10 as the transmitter has won the arbitration and therefore has dedicated access to bus 40 of bus system 1 for transmission.

[0063] Therefore, user stations 10 and 30, in the arbitration phase 451 as the first communication phase, partially, and especially up to the FDF bit (inclusive), use a format known from CAN / CAN-FD according to ISO 11898-1:2015. However, compared to CAN or CAN-FD, the net data transmission rate can be increased in the data phase 452 as the second communication phase, especially to more than 10 megabits per second. Furthermore, the size of the effective data per frame can be increased, especially to approximately 2 kilobytes or any other value.

[0064] Figure 3The left side shows user stations 10, 20, and 30 sending signals CAN_H and CAN_L to bus 40 during arbitration phase 451, the signals alternately having at least one dominant state 401 or at least one recessive state 402. After arbitration in arbitration phase 451, one of user stations 10, 20, and 30 is determined as the winner. It is assumed that user station 10 has won the arbitration. Then, the transmit / receive device 12 of user station 10 switches its physical layer from the first operating mode (SLOW) to the second operating mode (FAST_TX) at the end of arbitration phase 451, because user station 10 is the transmitter of message 45 in data phase 452. The transmit module 121 then generates states L0 or L1 for signals CAN_H and CAN_L on bus 40 successively and therefore serially, depending on the transmit signal TxD. The frequencies of signals CAN_H and CAN_L can be increased in data phase 452, as in... Figure 3 As shown on the upper right of the diagram. Therefore, the net data transmission rate is improved in data phase 452 compared to arbitration phase 451. Conversely, the transmitting / receiving device 12 of user station 30 switches its physical layer from the first operating mode (SLOW) to the third operating mode (FAST_RX) at the end of arbitration phase 451 because user station 30 is only a receiver of frame 450 in data phase 452, i.e., not its transmitter. After the end of arbitration phase 451, all transmitting / receiving devices 12 of user stations 10 and 30 switch their operating mode back to the first operating mode (SLOW). Therefore, all transmitting / receiving devices 12 also switch their physical layers.

[0065] according to Figure 4 In arbitration phase 451, ideally, a differential signal VDIFF = CAN_H – CAN_L is formed on bus 40. This differential signal has a value of VDIFF = 2V for dominant state 401 and a value of VDIFF = 0V for recessive state 402. This is in Figure 4 The left side is shown above. Conversely, in data phase 452, a differential signal VDIFF = CAN_H – CAN_L is formed on bus 40, which has states L0 and L1, as shown in... Figure 4As shown on the upper right of the diagram. State L0 has a value of VDIFF = 1V. State L1 has a value of VDIFF = -1V. The receiving module 122 can distinguish between states 401, 402 and L0, L1 respectively using receiving thresholds, which are in the range TH_T1, TH_T2, TH_T3. Here, the receiving module 122 uses at least, for example, a receiving threshold T1 of 0.7V in the arbitration phase 451. The receiving module 122 uses, for example, a receiving threshold T2 of -0.35V, for example, in the arbitration phase 451, and if necessary, also in the data phase 452. In the data phase 452, a receiving threshold T3 of 0.0V is used. (The preceding text is incomplete and requires further context.) Figure 3 When switching between the first operating mode and the third operating mode (SLOW, FAST_TX, FAST_RX), the receiving module 122 switches the receiving threshold respectively.

[0066] Figure 5 An embodiment is shown for a portion of the digital transmission signal TxD, in which the transmission module 121 receives the digital transmission signal from the communication control device 11 during arbitration phase 451 and thereby generates signals CAN_H and CAN_L for bus 40. Figure 5 In the process, the transmitted signal TxD transitions from state LW (low) to state HI (high) and then transitions back to state LW (low).

[0067] As in Figure 6 As shown in more detail below, the sending module 121 is designed for... Figure 5 The transmit signal TxD generates signals CAN_H and CAN_L for bus cores 41 and 42, resulting in an additional state 403 (sic). State 403 (sic) can have different durations, as shown by state 403_0 (sic) during the transition from state 402 (rec) to state 401 (dom), and by state 403_1 (sic) during the transition from state 401 (dom) to state 402 (rec). State 403_0 (sic) is shorter in duration than state 403_1 (sic). To generate according to... Figure 6 The signal transmission module 121 switches to SIC operation mode (SIC mode).

[0068] In CiA610-3, a shorter SIC state 403_0 is not required, and the duration of this state depends on the implementation type. The duration of the "longer" SIC state 403_1 (SIC) is specified as t_sic < 530 ns for both CAN-SIC and SIC operation modes in CAN-XL. Figure 5 The transmission signal begins at the rising edge of TxD.

[0069] Transmitting module 121 should, in the “longer” state 403_1 (sic), match the impedance between bus cores 41 (CANH) and 42 (CANL) as well as possible to the characteristic ripple resistance Zw of the bus lines used. Here, Zw = 100 ohms or 120 ohms applies. This matching prevents reflections and thus allows operation at higher bit rates. For simplicity, state 403 (sic) or sic state 403 will always be referred to below.

[0070] The transmitting module 121 can be used to generate signals for the bus 40 for the following CAN types: CAN-FD, CAN-SIC, and CAN-XL.

[0071]

[0072] Table 1: CAN type for transmitting module 121.

[0073] Therefore, it is possible to generate the transmit module status sic not only in CAN-SIC or CAN-XL (xl_sic), but also in CAN-FD. In CAN-FD, the time required to generate the transmit module status sic is shorter than in CAN-SIC or CAN-XL.

[0074] Figure 7 An embodiment for other portions of the digital transmission signal TxD is shown, in which the transmission module 121 receives the digital transmission signal from the communication control device 11 in the data phase 452 and thereby generates signals CAN_H and CAN_L for the bus 40. Figure 7 In the process, the transmitted signal TxD repeatedly transitions from state HI (High) to state LW (Low) and then back to state HI (High), and so on.

[0075] As in Figure 8 As shown in more detail below, the sending module 121 is designed for... Figure 7 The transmit signal TxD is generated by bus cores 41 and 42, thus generating signals CAN_H and CAN_L, thereby constructing state L0 for state LW (low). Furthermore, state L1 is constructed for state HI (high).

[0076] Figure 9 The basic structure of a transmitting module 121 for one of user stations 10 and 30 is shown. The transmitting module 121 is capable of generating data according to... Figure 5 The signals CAN_H and CAN_L with states 401, 402, and 403, and according to... Figure 8 The signals CAN_H and CAN_L have states L0 and L1, respectively.

[0077] The transmitting module 121 has four transmitting stages: a first transmitting stage 121A, a second transmitting stage 121B, a third transmitting stage 121C, and a fourth transmitting stage 121D. For example... Figure 9 As shown, transmitting stages 121A to 121D are connected as a full bridge. Furthermore, transmitting module 121 has current limiting modules 1211 and 1212. The current limiting modules 1211 and 1212, as well as the components of transmitting stages 121A to 121D (described in more detail below), are controlled by at least one control device 124. At least one control device 124 sends at least one signal to a control connector 125, to which the current limiting modules 1211 and 1212 and / or the components of transmitting stages 121A to 121D are connected. For clarity, in Figure 9 Not all wire connections used for this are shown in the diagram.

[0078] Transmitting module 121 is connected to bus 40, more specifically, to the first bus core 41 of the bus for CAN_H or CAN-XL_H and to the second bus core 42 of the bus for CAN_L or CAN-XL_L. Each of the transmitting stages 121A to 121D is connected to bus 40.

[0079] A voltage supply, typically 5V, is provided through at least one connector 43 to power the first and second bus cores 41 and 42. Connection to ground, or CAN_GND, is achieved via connector 44. The first and second bus cores 41 and 42 are terminated by terminating resistor 49. Terminating resistor 49 is connected as an external load resistor to the full bridge. Resistor 49 is connected to the bridge branch between the connectors for bus cores 41 and 42.

[0080] Figure 9The first transmitting stage 121A has a reverse diode D_A, a transistor HVP_A, and a parallel circuit 121A1 in which the first to nth current stages are connected in parallel, where n is a natural number greater than 1. Additionally, a control circuit T_A is present. The first current stage has a series circuit consisting of a resistor R_A1 and a transistor P_A1. The nth current stage has a series circuit consisting of a resistor R_An and a transistor P_An. The transistor HVP_A can be a CMOS transistor, especially a PMOS transistor. Transistors P_A1 to P_An are CMOS transistors, especially PMOS transistors. The abbreviation "CMOS" stands for Semiconductor Device, in which both p-channel MOSFETs and n-channel MOSFETs are used on a common substrate. The abbreviation CMOS stands for Complementary metal-oxide-semiconductor. The abbreviation "MOSFET" stands for Metal-Oxide-Semiconductor Field-Effect Transistor. The control circuit T_A controls the transistors P_A1 to P_An of the first to nth current levels according to the transmission signal TxD and the operating modes SIC and FAST_TX set by the transmission module 121.

[0081] Figure 9 The second transmitting stage 121B has a reverse diode D_B, a transistor HVN_B, and a parallel circuit 121B1 in which the first to nth current stages are connected in parallel, where n is a natural number greater than 1. Furthermore, a control circuit T_B is present. The first current stage S1 has a series circuit consisting of a resistor R_B1 and a transistor N_B1. The nth current stage has a series circuit consisting of a resistor R_Bn and a transistor N_Bn. The transistor HVN_B can be a CMOS transistor, especially an NMOS transistor. Transistors N_B1 to N_Bn are CMOS transistors, especially NMOS transistors. The control circuit T_B controls the transistors N_B1 to N_Bn of the first to nth current stages according to the transmitting signal TxD and the operating modes SIC and FAST_TX set by the transmitting module 121.

[0082] Figure 9The third transmitting stage 121C has a reverse diode D_C, a transistor HVP_C, and a parallel circuit 121C1 in which the first to nth current stages are connected in parallel, where n is a natural number greater than 1. Furthermore, a control circuit T_C is present. The first current stage has a series circuit consisting of a resistor R_C1 and a transistor P_C1. The nth current stage has a series circuit consisting of a resistor R_An and a transistor P_An. The transistor HVP_C can be a CMOS transistor, especially a PMOS transistor. Transistors P_C1 to P_Cn are CMOS transistors, especially PMOS transistors. The control circuit T_C controls the transistors P_C1 to P_Cn of the first to nth current stages according to the transmitting signal TxD and the operating modes SIC and FAST_TX set by the transmitting module 121.

[0083] Figure 9 The fourth transmitting stage 121D has a reverse diode D_D, a transistor HVN_D, and a parallel circuit 121D1 in which the first to nth current stages are connected in parallel, where n is a natural number greater than 1. Furthermore, a control circuit T_D is present. The first current stage has a series circuit consisting of a resistor R_D1 and a transistor N_D1. The nth current stage has a series circuit consisting of a resistor R_Dn and a transistor P_Dn. The transistor HVP_D can be a CMOS transistor, especially an NMOS transistor. Transistors N_D1 to N_Dn are CMOS transistors, especially NMOS transistors. The control circuit T_D controls the transistors N_D1 to N_Dn of the first to nth current stages according to the transmitting signal TxD and the operating modes SIC and FAST_TX set by the transmitting module 121.

[0084] The current stages S1 to Sn of the transmitting stages 121A to 121D are therefore designed as resistive stages. The resistive stages are set by selecting the corresponding resistance values ​​for the current stages, for example, by selecting resistors R_A1 to R_An for the transmitting stage 121A. The current stages are set based on the resistance values ​​of the resistors. The number n can be arbitrarily selected. Specifically, the number n and therefore the number of resistive or current stages can be selected between 1 and 60. However, alternatively, a number greater than 60 can be selected for n.

[0085] Each of the reverse diodes D_A, D_B, D_C, and D_D protects the associated transmitter stage from positive feedback to connector 44 (CAN-Supply) and negative feedback to connector 43 (CAN_GND). Each of the reverse diodes D_A, D_B, D_C, and D_D can also be referred to as a blocking diode.

[0086] Each stage circuit in the parallel circuits 121A1, 121B1, 121C1, and 121D1, more precisely, the associated control circuits T_A, T_B, T_C, and T_D, sets its resistance value according to the operating mode of the transmitting module 121 (SLOW or SIC, FAST_TX) and the transmitting signal TxD. Therefore, the resistance values ​​of each transmitting stage 121A, 121B, 121C, and 121D can be set according to the operating mode of the transmitting module 121 (SLOW or SIC, FAST_TX) and the transmitting signal TxD. This is further detailed below according to… Figure 10 and Figure 11 And described in Tables 2 and 3.

[0087] Each of transistors HVP_A, HVN_B, HVP_C, and HVN_D is an HV cascode structure and can also be referred to as an HV isolation device. Transistor HVP_A protects the CMOS transistors P_A1 to P_An of the associated parallel circuit 121A1 by absorbing a high voltage drop. Each of transistors HVN_B, HVP_C, and HVN_D has the same function for the CMOS transistors of the associated parallel circuits 121B1, 121C1, and 121D1, respectively. Each of transistors HVP_A, HVN_B, HVP_C, and HVN_D is connected to terminal 125 at its control terminal. Therefore, each of transistors HVP_A, HVN_B, HVP_C, and HVN_D can be controlled by at least one control device 124.

[0088] Current limiting modules 1211 and 1212 are designed as transistors. Current limiting modules 1211 and 1212 are... Figure 9 In the embodiments, they are CMOS transistors. Figure 9 The current limiting module 1211 is a PMOS transistor. Therefore, the current limiting module 1211 forms a power supply. Figure 9 The current limiting module 1212 is an NMOS transistor. Therefore, the current limiting module 1212 forms a current sink (Stromsenke). Current limiting modules 1211 and 1212 are configured to protect the transmitting module 121 and external components, especially other components of the user station 10 and / or bus 40. The arrangement of current limiting modules 1211 and 1212 in the circuit of the transmitting stage 121 is designed for… Figure 6The DOM state 401 is adapted to the SiC state 403. According to design and specifications, twice the current flows in the SiC state in DOM state 401; however, the current in DOM state 401 flows only in one path of the transmitting module 121. Conversely, the current in the SiC state flows in both paths of the transmitting module 121. Both paths are identically designed or configured. Therefore, the same voltage drop occurs at the current limiting modules 1211 and 1212.

[0089] In the transmitting module 121, transmitting stage 121A is connected between connector 43 for the voltage supply section and connector 41 (CANH) for the CAN_H signal. Transmitting stage 121C is connected between connector 43 and connector 42 (CANL) for the voltage supply section and connector 43 or connector 44 (CAN_GND) for the ground section. Transmitting stage 121D is connected between connector 41 (CANH) for the CAN_H signal and connector 43 or connector 44 (CAN_GND) for the ground section. Transmitting stage 121B is connected between connector 42 (CANL) for the CAN_L signal and connector 43 or connector 44 (CAN_GND) for the ground section. Therefore, in the transmitting module 121, on the one hand, transmitting stage 121A is connected to the CANH path. On the other hand, transmitting stage 121D is connected to the CANH path. On the other hand, transmitting stage 121C is connected to the CANL path. On the other hand, transmitting stage 121B is connected to the CANL path.

[0090] Therefore, the transmitting module 121 is composed of a predetermined number of parallel circuits 121A1, 121B1, 121C1, and 121D1 of current stages in the CANH and CANL paths. Each current stage is implemented by a series circuit consisting of CMOS switches and resistors, as described above. All the parallel circuits of the current stages are connected in series in the CANH and CANL paths with the HV cascode structures HVP_A, HVN_B, HVP_C, and HVN_D, as well as the anti-polarity diodes D_A, D_B, D_C, and D_D, as described above. The HV cascode structures HVP_A, HVN_B, HVP_C, and HVN_D can achieve voltages from -27V to +40V at limiting values ​​(maximum rated parameters), such as CANH and CANL.

[0091] Figure 9The functional mode of the circuit depends on the operating mode of the transmitting module 121 and the bus states 401 (dom), 403 (sic), and 402 (rec) in the SIC operating mode (arbitration stage 451), as well as L0 and L1 in the data stage 452, as explained in Table 2 below. Table 2 shows the impedance required according to the state of the transmitting module 121 and the operating modes of stages 451 and 452, as well as the impedances of transmitting stages 121A / 121B and 121C / 121D.

[0092]

[0093] Table 2: Impedance required based on transmission status.

[0094] If the impedance is “infinite”, then the transmitting module 121 or the corresponding transmitting stage 121A, 121B, 121C, 121D is switched off or switched non-conductively.

[0095] Figure 9 The division of each parallel circuit 121A1, 121B1, 121C1, 121D1 into n parts, or n current levels, allows for time-staggered and controlled switching between bus states 401, 402, 403 in the arbitration phase (SIC operation mode) 451 or between bus states L0, L1 in the data phase 452. For this purpose, the resistance values ​​of the resistors for the n current levels are set, such as using... Figure 10 As shown in a specific embodiment.

[0096] Figure 10 An embodiment of the current levels for each switching stage, or current stage S1 to S12, is shown. Therefore, in the illustrated embodiment, twelve current stages S1, S2 to S6 to S12 are used for each of the parallel circuits 121A1, 121B1, 121C1, and 121D1. Thus, n = 12 is applied.

[0097] Current I( Figure 10 The values ​​of the vertical axis (or I1, I2, I6, I12, etc.) are set by selecting the series resistance values ​​of the corresponding current stages S1 to S12. Figure 10 The horizontal axis in the middle has different resistance values.

[0098] In order to generate bus states 401, 402, 403 in the arbitration phase (SIC operation mode) 451 or bus states L0, L1 in the data phase 452, the CMOS transistors of current stages S1 to S12 are connected or turned off in a staggered manner. As a result, a corresponding current I flows in the CANH or CANL path to which the upper-level transmitting stages 121A, 121B, 121C, and 121D are connected.

[0099] A particularly advantageous aspect is that the design of the interleaving (interleaving stage) and resistors of each switching stage, or current stage S1 to S12, ensures that the differential signal VDIFF follows a Gaussian error function. This results in minimal radiation generated analytically.

[0100] For the corresponding Figure 4 Regarding the transition from state 402 (recessive) to state 401 (dominant) at the rising edge of the differential voltage VDIFF, the current in the CANH and CANL paths is gradually increased by sequentially switching on the resistors of parallel circuits 121A1, 121B1, 121C1, and 121D1 to generate a dominant level at bus 40. Corresponding to Figure 4 The transition from state 401 (dominant) to state 402 (recessive) at the falling edge of the differential voltage VDIFF is correspondingly achieved by sequentially turning off the resistors of parallel circuits 121A1, 121B1, 121C1, and 121D1, thereby gradually reducing the current in the CANH and CANL paths. The total current, given by the sum of the currents I1 to I12, or I1 to In, of all current levels S1 to Sn, flows during state 401 (dominant). Here, the total current used to generate the dominant level of nominal VDIFF = 2V, for all current levels S1 to Sn connected to parallel circuits 121A1, 121B1, 121C1, and 121D1, flows through the bus resistor or terminating resistor 49.

[0101] As described above, by setting the resistance value of the current stages' resistors to set and select the current levels of each current stage S1 to S12 in time, it is feasible to adapt the bus signals CAN_H and CAN_L to each other during the transition between states 401 and 402, thereby achieving the desired result. Figure 6 The symmetrical trend of CAN_H and CAN_L. The structure of the transmitting module 121 enables time-staggered access to the various current levels of the parallel circuits 121A1, 121B1, 121C1, and 121D1. Through this time-staggered control, it is possible to adapt to the signal shapes of CAN_H and CAN_L, such as according to... Figure 6As required. It can achieve targeted shaping (formation) of the signal flow for CAN_H and CAN_L. In general, the bus states 401, 402, 403 of the arbitration phase (SIC operation mode) 451 or the bus states L0, L1 of the data phase 452 can be shaped according to presets.

[0102] The resistances of the current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, and 121D1, and therefore their corresponding proportions in the total current, can be selected in different ways to achieve the lowest possible radiation, especially very low radiation, in the transmitting module 121. For lower radiation, it is advantageous to switch a smaller current I (higher resistance value) on or off at the beginning and end of the switching process between bus states 401 and 402, and to switch a larger current (lower resistance value) on or off during the switching process. Therefore, the current in current stages S1 to S12... Figure 10 The settings shown are very advantageous.

[0103] In contrast to the implementation scheme that utilizes the same resistors in the current stages S1 to Sn of the parallel circuits 121A1, 121B1, 121C1, and 121D1, according to Figure 10 The configuration avoids the increase in current during the shutdown process and the transition from state 401 (dominant) to state 402 (recessive).

[0104] The granularity of the time staggering (staggered tuning) used to connect or disconnect the various current stages S1 to S12 is in the range of approximately 2 ns. This small staggering or step size results in lower common-mode interference and a lower negative impact on radiation. Here, the voltage step size set by the resistors or resistor stages of current stages S1, S2 to S6 to S12 remains fixed, while the time staggering varies, thereby setting the softest possible characteristics (according to the Gaussian error function) during connection. The variation in time step size or time stage further prevents narrow-band frequency lines from appearing in the radiation spectrum.

[0105] Alternatively, staggered step size (staggered tuning step size) can be implemented using a fixed time step size and a varying voltage step size.

[0106] The structure shown by the transmitting module 121 enables the transmission of bus signals CAN_H and CAN_L. Figure 6 Symmetrical switching between bus states 401, 402, and 403 in the arbitration phase (SIC operation mode) 451 or between bus states L0 and L1 in the data phase 452 at steep switching edges.

[0107] On the one hand, the structure shown in the transmitting module 121 achieves much steeper switching edges between bus states 401, 402, and 403 in the arbitration phase (SIC operation mode) 451 or between bus states L0 and L1 in the data phase 452 due to the use of fast CMOS switches or CMOS transistors. On the other hand, the symmetry of the time trends of the bus signals CAN_H and CAN_L, necessary to comply with radiation limits, is achieved during the switching process. The characteristic curves are balanced (matched) by selecting or using resistors in the parallel circuits 121A1, 121B1, 121C1, and 121D1. Therefore, the balance (matching) of the characteristic curves depends less on the parameters of the transistors used in the parallel circuits 121A1, 121B1, 121C1, and 121D1.

[0108] The CMOS transistors in the transmit stages 121A1, 121B1, 121C1, and 121D1 operate as switches, meaning they operate at the maximum voltage between the gate and source terminals. The balancing (matching) of each transmit stage 121A1, 121B1, 121C1, and 121D1 therefore depends decisively on the balancing (matching) of resistors R_A1 to R_An, R_B1 to R_Bn, R_C1 to R_Cn, and R_D1 to R_Dn, and no longer depends on the transistors P_A1 to P_An and P_C1 to P_Cn (PMOS) at bus line 41 (CANH) and the transistors N_D1 to N_Dn and N_B1 to N_Bn (NMOS) at bus line 42 (CANL).

[0109] The dominant state 401 (dom) is determined by balancing (matching) the resistors R_A1 to R_An (transmitter stage 121A) and the resistors R_B1 to R_Bn (transmitter stage 121B). Here and also hereinafter, the term "balance" in one feasible embodiment means an active fine-tuning step. In another feasible embodiment, "balance" means that the resistor values ​​match each other as well as possible, which is typically done without a balancing or fine-tuning step.

[0110] The Sic state (Sic) is determined by balancing (matching) resistors R_A1 to R_An (transmitter stage 121A) and resistors R_C1 to R_Cn (transmitter stage 121C), and by balancing (matching) resistors R_D1 to R_Dn (transmitter stage 121D) and resistors R_B1 to R_Bn (transmitter stage 121B).

[0111] In XL-Fast operating mode, state L0 is determined by balancing (matching) resistors R_A1 to R_An (transmitter stage 121A) and resistors R_B1 to R_Bn (transmitter stage 121B). State L1 is determined by balancing (matching) resistors R_C1 to R_Cn (transmitter stage 121C) and resistors R_D1 to R_Dn (transmitter stage 121D). The connection resistance Ron of the corresponding transistors in transmitter stages 121A1, 121B1, 121C1, and 121D1 should be significantly smaller than the respective series-connected resistances of the current stages in transmitter stages 121A1, 121B1, 121C1, and 121D1.

[0112] Figure 11 Showing the target Figure 9 This is a specific embodiment of the structure of the transmitting stage 121B. Therefore, the transmitting stage 121B has three current stages S_I, S_II, and S_III in the parallel circuit 121B1. The first current stage S_I has a resistor R_B1_I and a transistor N_B1_I connected in series. The second current stage S_II has a resistor R_B1_II and a transistor N_B1_II connected in series. The third current stage S_III has a resistor R_B1_III and a transistor N_B1_III connected in series.

[0113] For those with according to Figure 11 Configuration Figure 9 For the purposes of the following description of the circuit, it is assumed that each of the transmitting stages 121A, 121C, and 121D also has, according to, its associated parallel circuits 121A1, 121C1, and 121D1. Figure 11 The embodiment has three current levels S_I, S_II, and S_III.

[0114] Table 3 below shows the control methods that depend on transmitter stages 121A / 121B and transmitter stages 121C and 121D, respectively. Figure 11 The three transistors N_B1_I, N_B1_II, and N_B1_III of the transmitter stage 121B and Figure 9 The corresponding transistors of the transmitting stages 121A, 121C, and 121D.

[0115]

[0116] Table 3: Impedance required based on transmission status.

[0117] In this way, the transmitting module 121 can generate the required steeper edges at the bus signals CAN_H and CAN_L while adhering to radiation limits.

[0118] Alternatively, more than three current stages can be used in the corresponding transmitting stages 121A, 121B, 121C, and 121D, as described above.

[0119] Figure 12 A transmitting module 1210 according to a second embodiment is shown. The transmitting module 1210 is constructed in the same manner as the transmitting module 121 according to the first embodiment, comprising multiple parts. Therefore, only the differences from the first embodiment will be described below.

[0120] Unlike the first embodiment, the transmitting module 1210 according to this embodiment has transmitting stages 121A0, 121B0, 121C0, and 121D0. Transmitting stages 121A0, 121B0, 121C0, and 121D0 are connected as a full bridge. A terminating resistor 49 is connected to a bridge branch between the connectors for the bus cores 41 and 42. Furthermore, instead of current limiting modules 1211 and 1212, the transmitting module 1210 has first to x-th current limiting modules 1211_1 to 1211x and first to x-th current limiting modules 1212_1 to 1212_x. Here, x is a natural number greater than 1.

[0121] Current limiting modules 1211_1 to 1211_x and 1212_1 to 1212_x are each designed as transistors. Current limiting modules 1211_1 to 1211_x and 1212_1 to 1212_x are... Figure 12 In the embodiments, they are CMOS transistors. Figure 12 The current limiting modules 1211_1 to 1211_x are PMOS transistors. Therefore, the current limiting modules 1211_1 to 1211_x respectively form power supplies. Figure 12 The current limiting modules 1212_1 to 1212_x are NMOS transistors. Therefore, the current limiting modules 1212_1 to 1212_x form current sinks respectively.

[0122] Unlike the first embodiment's transmitter stage 121A which has a transistor HVP_A, transmitter stage 121A0 has first to y-th transistors HVP_A1 to HVP_Ay, where y is a natural number greater than 1. Each of the first to y-th transistors HVP_A1 to HVP_Ay is a CMOS transistor, especially a PMOS transistor, as mentioned above regarding transistor HVP_A. Figure 9 As described.

[0123] Unlike the first embodiment's transmitter stage 121B with transistor HVN_B, transmitter stage 121B0 has first to y-th transistors HVN_B1 to HVN_By, where y is a natural number greater than 1. Each of the first to y-th transistors HVN_B1 to HVN_By is a CMOS transistor, especially an NMOS transistor, as previously discussed regarding transistor HVP_B. Figure 9 As described.

[0124] Unlike the transmitter stage 121C of the first embodiment, which has a transistor HVP_C, the transmitter stage 121C0 has first to y-th transistors HVP_C1 to HVP_Cy, where y is a natural number greater than 1. Each of the first to y-th transistors HVP_C1 to HVP_Cy is a CMOS transistor, especially a PMOS transistor, as mentioned above regarding transistor HVP_C. Figure 9 As described.

[0125] Unlike the transmitter stage 121D of the first embodiment, which has a transistor HVN_D, the transmitter stage 121D0 has first to y-th transistors HVN_D1 to HVN_Dy, where y is a natural number greater than 1. Each of the first to y-th transistors HVN_D1 to HVN_Dy is a CMOS transistor, especially an NMOS transistor, as mentioned earlier regarding transistor HVP_D. Figure 9 As described.

[0126] In addition to the functions of the sending module 121 according to the first embodiment, Figure 12 The sending module 1210 also has the following functions.

[0127] Transmitting module 1210, based on its design, can reduce the effects caused by the asymmetric characteristics of the transmitting stage, which may occur in the transmitting states dom (401), sic (403), and rec (402), increasing overshoot and thus worsening radiation. Transmitting module 1210 prevents... Figure 12 The different characteristics of the components in the full-bridge transmitting stages 121A0 and 121B0 (Effect 1) minimize or prevent the change in common-mode voltage in dom state 401 compared to rec state 402.

[0128] To prevent effect 1, the resistance Ron (connection resistance) of the cascode structure in transmitter stages 121A0 and 121B0 can be changed, particularly by manipulation using the respective associated control circuits T_A and T_B. This is achieved by changing up to y parallel-connected transistors HVP_A1 to HVP_Ay and / or up to y parallel-connected transistors HVN_B1 to HVN_By. To maintain the symmetry of the two series circuits of transmitter stages 121A0 and 121D0 and transmitter stages 121C0 and 121B0 in sic state 403, the cascode structure of transmitter stages 121D0 and 121C0 must also undergo the same change. Therefore, up to y parallel-connected transistors HVN_D1 to HVP_Dy and / or up to y parallel-connected transistors HVP_C1 to HVP_Cy also change accordingly. For this purpose, each of transistors HVP_A1 to HVP_Ay, HVN_B1 to HVN_By, HVP_C1 to HVP_Cy, and HVN_D1 to HVP_Dy is connected to junction 125 at its control junction (gate junction). Therefore, each of these transistors can be controlled by at least one control device 124. Intervention for correcting the common-mode level in dom state 401 is achieved by similarly or identically changing HVP_A1 to HVP_Ay and HVP_C1 to HVP_Cy, or by similarly or identically changing HVP_D1 to HVN_Dy and HVP_B1 to HVN_By.

[0129] Furthermore, the transmitting module 1210 can prevent the different characteristics (effect 2) of the components in the transmitting stages 121A0 / 121D0 and 121C0 / 121B0 of the full bridge, thereby minimizing or preventing the change of common-mode voltage in the sic state compared to the rec state 402.

[0130] For this purpose, the resistance Ron (connection resistance) of the current-limiting transistors or current-limiting modules 1211, 1212 can be changed. This is achieved by up to x current-limiting modules 1211_1 to 1211_x connected in parallel and / or up to x current-limiting modules 1212_1 to 1212_x connected in parallel, especially by manipulation performed by at least one control device 124. Intervention for correction of the common-mode level in sic state 403 is achieved by up to x current-limiting modules 1211_1 to 1211_x connected in parallel or up to x current-limiting modules 1212_1 to 1212_x connected in parallel. For example, x = 4 is used. In this case, four different levels of the resistance Ron (connection resistance) of the current-limiting transistors or current-limiting modules 1211, 1212 can be set.

[0131] This prevention of effect 2 is particularly advantageous because sufficient radiation can only be obtained when the common-mode levels in dom state 401 and sic state 403 are matched with the common-mode level of rec state 402, starting from the common-mode level of rec state 402. However, the cause of the characteristics of effect 1 may be different from the cause of effect 2.

[0132] The design of the transmitting module 1210 prevents the common-mode levels in the DOM state 401 from becoming inconsistent due to substrate current losses in the reverse diodes D_A and D_B. In the SIM state, the reverse diodes D_A and D_B are less energized, and all the reverse diodes D_A, D_B, D_C, and D_D of the four transmitting stages 121A0, 121B0, 121C0, and 121D0 are activated. The transmitting module 1210 prevents different common-mode levels in the DOM state and the SIM state. Furthermore, it prevents qualitatively identical effects caused by the different characteristics of the cascode structure.

[0133] Therefore, the transmitting module 1210 can positively influence the effect on the radiation value of the transmitting / receiving device 12, which is decisively affected by the transmitting module 1210.

[0134] The transmitting modules 121 and 1210, transmitting / receiving devices 12 and 22, user stations 10, 20, and 30, bus system 1, and all the foregoing designs of the methods implemented therein, according to the first and second embodiments and their modifications, can be used individually or in all feasible combinations. Additionally, the following modifications are particularly conceivable.

[0135] The bus system 1 described above according to the first and second embodiments is based on a CAN protocol-based bus system. However, the bus system 1 according to the first and / or second embodiments can alternatively be other types of communication networks in which signals are transmitted as differential signals. Advantageously, but not mandatoryly, it is beneficial, in the bus system 1 to ensure dedicated, conflict-free access to the bus 40 for user stations 10, 20, and 30, at least for a defined time period.

[0136] The bus system 1 according to the first embodiment and / or the second embodiment and its modifications is in particular a CAN bus system, a CAN-HS bus system, a CAN FD bus system, a CAN SIC bus system, or a CAN XL bus system. However, the bus system 1 can be other communication networks in which signals are transmitted serially via the bus as differential signals.

[0137] Therefore, the functionality of the embodiments described above can be applied, for example, to the transmitting / receiving devices 12 and 22, which can operate in a CAN bus system or a CAN-HS bus system or a CAN FD bus system or a CAN SIC bus system or a CAN XL bus system.

[0138] It is feasible to, at least temporarily, not use the dominant and recessive bus states for the two bus states 401 and 402, but instead use the first bus state and the second bus state, both of which are driven. An example of such a bus system is the CAN XL bus system.

[0139] The number and arrangement of user stations 10, 20, and 30 in the bus system 1 according to the first embodiment, the second embodiment, and their modifications are arbitrary. In particular, the bus system 1 of the first embodiment or the second embodiment may contain only user station 10 or only user station 30.

Claims

1. A transmitting module (121; 1210) for transmitting differential signals in a serial bus system (1), the transmitting module having: A first transmitting stage (121A; 121A0) is used to generate a transmitting current (I1 to In) for a first signal (CAN_H), which can be transmitted to the bus (40) of the bus system (1). A second transmitting stage (121B; 121B0) is used to generate a transmitting current (I1 to In) for a second signal (CAN_L), which can be transmitted onto the bus (40) as a differential signal relative to the first signal (CAN_H). The third transmitting stage (121C; 121C0) is used to generate a transmitting current (I1 to In) for the first signal (CAN_H), and The fourth transmitter stage (121D; 121D0) is used to generate the transmit current (I1 to In) for the second signal (CAN_L). in, The first to fourth transmitter stages (121A to 121D; 121A0 to 121D0) are connected in a full bridge, in which the first and fourth transmitter stages (121A, 121D; 121A0, 121D0) are connected in series, and the third and second transmitter stages (121C, 121B; 121C0, 121B0) are connected in series. Each of the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) has at least two current stages (S1 to Sn) connected in parallel with each other. Each of the at least two current stages (S1 to Sn) has a switchable resistor (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn), and Among them, the switchable resistors (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of the transmitting stage (121A to 121D; 121A0 to 121D0) have different resistance values.

2. The transmitting module (121; 1210) according to claim 1, wherein, The output connectors (41, 42) of the full bridge are configured to be connected to the terminating resistor (49) of the bus (40).

3. The transmitting module (121; 1210) according to claim 1 or 2, wherein, The number n of the at least two current stages (S1 to Sn) is the same for each of the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0), where n is a natural number greater than 1.

4. The transmitting module (121; 1210) according to any one of the preceding claims, wherein, Each of the at least two current stages (S1 to Sn) has a CMOS transistor for switching the resistors (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of the current stage (S1 to Sn).

5. The transmitting module (121; 1210) according to any one of the preceding claims, in, The CMOS transistors of the current stages (S1 to Sn) of the first transmitting stage (121A; 121A0) are PMOS transistors. In this process, the CMOS transistors of the current stages (S1 to Sn) of the second transmitting stage (121B; 121B0) are NMOS transistors. Wherein, the CMOS transistors of the current stages (S1 to Sn) of the third transmitting stage (121C; 121C0) are PMOS transistors, and Among them, the CMOS transistors of the current stages (S1 to Sn) of the fourth transmitting stage (121D; 121D0) are NMOS transistors.

6. The transmitting module (121; 1210) according to any one of claims 4 or 5, wherein, Each of the first to fourth transmission levels (121A to 121D; 121A0 to 121D0) further has: Reverse diodes (D_A; D_B; D_C; D_D) are used to protect against positive feedback in the connector (43) for the bus voltage supply section and against negative feedback in the connector (44) for the ground section. At least one cascode structure (HVP_A; HVN_B; HVP_C; HVN_D) is used to protect the CMOS transistor.

7. The sending module (1210) according to claim 6, in, At least two common source cascode structures (HVP_A; HVN_B; HVP_C; HVN_D) are connected in parallel with each other. The number y of the common source cascode structure (HVP_A; HVN_B; HVP_C; HVN_D) is the same for each of the first to fourth transmitter stages (121A to 121D; 121A0 to 121D0), where y is a natural number greater than 1. The connection resistances of the at least two common source cascode structures (HVP_A; HVN_B; HVP_C; HVN_D) are different.

8. The transmitting module (121; 1210) according to any one of the preceding claims, further comprising: At least one first current-limiting module (1211) serves as a power supply, connected between the connector (43) for the bus voltage supply section and the full bridge, and As at least one second current limiting module (1212) of the current sink, the second current limiting module is connected between the connector (44) for grounding and the full bridge.

9. The sending module (1210) according to claim 8, in, At least two first current limiting modules (1211_1 to 1211_x) are connected in parallel with each other, and their connection resistors are different. Among them, at least two second current limiting modules (1212_1 to 1211_x) are connected in parallel with each other, and their connection resistors are different. Wherein, the number x of the first current limiting modules (1211_1 to 1211_x) is equal to the number x of the second current limiting modules (1212_1 to 1211_x), where x is a natural number greater than 1.

10. The transmitting module (121; 1210) according to any one of the preceding claims, further comprising: Control circuits (T_A; T_B; T_C; T_D) are used to control the switchable components of the first to fourth transmission stages (121A to 121D; 121A0 to 121D0) according to the digital transmission signal (TxD) and the operating mode (SIC; FAST_TX) set for the transmission modules (121; 1210).

11. The transmitting module (121; 1210) according to claim 10, wherein, The control circuit (T_A; T_B; T_C; T_D) is designed to switch the resistance values ​​of the at least two current levels (S1 to Sn) in a time-interleaved and controlled manner.

12. A transmitting / receiving device (12; 22) for a user station (20) of a serial bus system (1), the transmitting / receiving device having: The transmitting module (121; 1210) according to any one of the preceding claims, and A receiving module (122) for receiving signals from the bus (40).

13. A user station (10; 20; 30) for a serial bus system (1), the user station having: The transmitting / receiving apparatus (12; 22) according to claim 12, and A communication control device (11; 21) is used to control communication in the bus system (1) and to generate digital transmission signals (TxD) for manipulating the first to fourth transmission stages (121A to 121D; 121A0 to 121D0).

14. The user station (10; 20; 30) according to claim 13, wherein, The user stations (10; 20; 30) are designed for communication in the bus system (1), which at least temporarily ensures a user station (10, 20, 30) a dedicated, conflict-free access to the bus (40) of the bus system (1).

15. A method for transmitting differential signals in a serial bus system (1), wherein, The method is implemented using a sending module (121; 1210), and the method includes the following steps: The first transmitting stage (121A; 121A0) generates a transmitting current (I1 to In) for the first signal (CAN_H), which can be transmitted to the bus (40) of the bus system (1). The second transmitting stage (121B; 121B0) generates a transmitting current (I1 to In) for the second signal (CAN_L), which can be transmitted onto the bus (40) as a differential signal relative to the first signal (CAN_H). The third transmitting stage (121C; 121C0) generates a transmitting current (I1 to In) for the first signal (CAN_H), and The fourth transmitting stage (121D; 121D0) generates a transmitting current (I1 to In) for the second signal (CAN_L). The first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) are connected in a full bridge configuration. In this full bridge, the first and fourth transmitting stages (121A, 121D; 121A0, 121D0) are connected in series, and the third and second transmitting stages (121C, 121B; 121C0, 121B0) are connected in series. Each of the first to fourth transmitting stages (121A to 121D; 121A0 to 121D0) has at least two current stages (S1 to Sn) connected in parallel with each other. Each of the at least two current stages (S1 to Sn) has a switchable resistor (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn), and Among them, the switchable resistors (R_A1 to R_An; R_B1 to R_Bn; R_C1 to R_Cn; R_D1 to R_Dn) of the transmitting stage (121A to 121D; 121A0 to 121D0) have different resistance values.

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