Display panel and display device

Abstract

A display panel and a display device, the display panel comprising: a substrate (90), a pixel driving circuit located on one side of the substrate (90), the pixel driving circuit comprising: a driving transistor (T3), a ninth transistor (T9), an eighth transistor (T8), a first transistor (T1), and a second transistor (T2). The first electrode of the ninth transistor (T9) is connected to a third initial signal line (Vinit3), and the second electrode of the ninth transistor (T9) is connected to the first electrode of the driving transistor (T3); the first electrode of the eighth transistor (T8) is connected to the gate electrode of the driving transistor (T3); the first electrode of the first transistor (T1) is connected to a first initial signal line (Vinit1), and the second electrode of the first transistor (T1) is connected to the second electrode of the eighth transistor (T8); the first electrode of the second transistor (T2) is connected to the second electrode of the eighth transistor (T8), and the second electrode of the second transistor (T2) is connected to the second electrode of the driving transistor (T3). The display panel can improve afterimage caused by hysteresis of the driving transistor (T3).

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and more particularly to a display panel and display device. Background Technology

[0002] In related technologies, hysteresis of the driving transistor can cause image retention on the display panel.

[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0004] According to one aspect of this disclosure, a display panel is provided, the display panel comprising: a substrate and a pixel driving circuit. The pixel driving circuit is located on one side of the substrate and includes: a driving transistor, a ninth transistor, an eighth transistor, a first transistor, and a second transistor. The first terminal of the ninth transistor is connected to a third initial signal line, and the second terminal of the ninth transistor is connected to the first terminal of the driving transistor; the first terminal of the eighth transistor is connected to the gate of the driving transistor; the first terminal of the first transistor is connected to the first initial signal line, and the second terminal of the first transistor is connected to the second terminal of the eighth transistor; the first terminal of the second transistor is connected to the second terminal of the eighth transistor, and the second terminal of the second transistor is connected to the second terminal of the driving transistor.

[0005] In an exemplary embodiment of this disclosure, the display panel further includes: a first active layer, a first conductive layer, a second active layer, and a third conductive layer. The first active layer is located on one side of the substrate, and includes a second active portion and a third active portion. The second active portion is used to form a channel region of the second transistor, and the third active portion is used to form a channel region of the driving transistor. The first conductive layer is located on the side of the first active layer opposite to the substrate, and includes a first gate line and a first conductive portion. The orthographic projection of the first gate line on the substrate extends along a first direction and covers the orthographic projection of the second active portion on the substrate. A portion of the structure of the first gate line is used to form the gate of the second transistor. The orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate. The first conductive portion is used to form... The first conductive layer forms the gate of the driving transistor; the second active layer is located on the side of the first conductive layer away from the substrate, the second active layer includes an eighth active portion, the eighth active portion being used to form the channel region of the eighth transistor; the third conductive layer is located on the side of the second active layer away from the substrate, the third conductive layer includes a second gate line, the orthographic projection of the second gate line on the substrate extends along the first direction and covers the orthographic projection of the eighth active portion on the substrate, a portion of the structure of the second gate line being used to form the top gate of the eighth transistor; wherein, the orthographic projection of the first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first conductive portion on the substrate.

[0006] In one exemplary embodiment of this disclosure, the second active portion further includes a twentieth active portion connected to the eighth active portion, the twentieth active portion being connected to the first conductive portion; the projection of the twentieth active portion onto the substrate and the orthographic projection of the first gate line onto the substrate at least partially overlap.

[0007] In one exemplary embodiment of this disclosure, the size of the orthogonal projection of the twentieth active portion onto the substrate in the first direction is greater than the size of the orthogonal projection of the twentieth active portion onto the substrate in the second direction; wherein the first direction and the second direction intersect.

[0008] In an exemplary embodiment of this disclosure, the orthographic projection of the eighth active part onto the substrate in the first direction has a size of L1, and the orthographic projection of the twentieth active part onto the substrate in the first direction has a size of L2; wherein, L2 / L1 is greater than or equal to 2 and less than or equal to 7.

[0009] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes: a fourth transistor, the first terminal of the fourth transistor being connected to a data line, and the second terminal of the fourth transistor being connected to the first terminal of the driving transistor. The display panel further includes: a first active layer and a second active layer, the first active layer including a second active portion and a fourth active portion, the second active portion being used to form a channel region of the second transistor, and the fourth active portion being used to form a channel region of the fourth transistor; the second active layer is located on the side of the first active layer opposite to the substrate, and the second active layer includes an eighth active portion, the eighth active portion being used to form a channel region of the eighth transistor; wherein, in a first direction, the orthographic projection of the eighth active portion on the substrate is located between the orthographic projection of the second active portion on the substrate and the orthographic projection of the fourth active portion on the substrate.

[0010] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is connected to a first electrode of the light-emitting unit. The pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to a second initial signal line, and the second electrode of which is connected to the first electrode of the light-emitting unit. The display panel further includes a first active layer and a first conductive layer. The first active layer is located on one side of the substrate and includes a seventh active portion and a ninth active portion. The seventh active portion is used to form a channel region of the seventh transistor, and the ninth active portion is used to form a channel region of the ninth transistor. The first conductive layer is located on the side of the first active layer away from the substrate and includes a second reset signal line. The orthographic projection of the second reset signal line on the substrate extends along a first direction and covers the orthographic projections of the seventh active portion and the ninth active portion on the substrate. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor, and a portion of the structure of the second reset signal line is used to form the gate of the ninth transistor.

[0011] In an exemplary embodiment of this disclosure, the first active layer further includes: a first active portion, the first active portion being used to form the channel region of the first transistor; the first conductive layer further includes: a first reset signal line and a first conductive portion, the orthographic projection of the first reset signal line on the substrate covering the orthographic projection of the first active portion on the substrate, a portion of the structure of the first reset signal line being used to form the gate of the first transistor, and the first conductive portion being used to form the gate of the driving transistor; wherein, in the same pixel driving circuit, the orthographic projection of the first conductive portion on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the second reset signal line on the substrate; the second reset signal line in the current row of pixel driving circuits is shared as the first reset signal line in the adjacent next row of pixel driving circuits.

[0012] In an exemplary embodiment of this disclosure, the display panel further includes: a first conductive layer, a second conductive layer, and a third conductive layer. The first conductive layer is located on one side of the substrate and includes: a first reset signal line and a first conductive portion. A portion of the first reset signal line is used to form the gate of the first transistor, and the first conductive portion is used to form the gate of the driving transistor. The second conductive layer is located on the side of the first conductive layer away from the substrate and includes the third initial signal line. The third conductive layer is located on the side of the second conductive layer away from the substrate and includes a second gate line. A portion of the second gate line is used to form the top gate of the eighth transistor. In the same pixel driving circuit, the orthographic projection of the first reset signal line on the substrate is located on the side of the orthographic projection of the second gate line on the substrate away from the orthographic projection of the first conductive portion on the substrate. The orthographic projection of the third initial signal line in the adjacent previous row pixel driving circuit is located between the orthographic projection of the first reset signal line on the substrate in the current row pixel driving circuit and the orthographic projection of the second gate line on the substrate in the current row pixel driving circuit.

[0013] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, the pixel driving circuit is connected to the first electrode of the light-emitting unit, and the pixel driving circuit further includes a seventh transistor, the first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode is connected to the first electrode of the light-emitting unit. The display panel further includes: a first conductive layer and a third conductive layer. The first conductive layer is located on one side of the substrate. The first conductive layer includes a first conductive portion, a second reset signal line, and a first gate line. The first conductive portion is used to form the gate of the driving transistor. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor. A portion of the structure of the first gate line is used to form the gate of the second transistor. The third conductive layer is located on the side of the first conductive layer away from the substrate. The third conductive layer includes the first initial signal line. In the same pixel driving circuit, the orthographic projection of the second reset signal line on the substrate is located on the side of the orthographic projection of the first conductive portion on the substrate away from the orthographic projection of the first gate line on the substrate. In the adjacent next row of pixel driving circuits, the orthographic projection of the first initial signal line on the substrate is located between the orthographic projection of the second reset signal line on the substrate in the current row of pixel driving circuits and the orthographic projection of the first conductive portion on the substrate in the current row of pixel driving circuits.

[0014] In one exemplary embodiment of this disclosure, the pixel driving circuit further includes a fifth transistor, the first terminal of which is connected to a power supply line, and the second terminal of which is connected to the first terminal of the driving transistor. The display panel further includes: a first active layer, a first conductive layer, and a third conductive layer. The first active layer is located on one side of the substrate and includes a fifth active portion for forming a channel region of the fifth transistor. The first conductive layer is located on the side of the first active layer away from the substrate and includes an enable signal line. The orthographic projection of the enable signal line on the substrate extends along a first direction and covers the orthographic projection of the fifth active portion on the substrate. A portion of the structure of the enable signal line is used to form the gate of the fifth transistor. The third conductive layer is located on the side of the first conductive layer away from the substrate and includes a first initial signal line. The orthographic projection of the first initial signal line on the substrate in the adjacent next row pixel driving circuit and the orthographic projection of the enable signal line on the substrate in the current row pixel driving circuit at least partially overlap.

[0015] In an exemplary embodiment of this disclosure, in the first unit pixel, the area of ​​the orthographic projection of the first initial signal line in the adjacent next row pixel driving circuit on the substrate is S1; in the first unit pixel, the overlapping area of ​​the orthographic projection of the first initial signal line in the adjacent next row pixel driving circuit on the substrate and the orthographic projection of the enable signal line in the current row pixel driving circuit on the substrate is S2; wherein, S2 / S1 is greater than or equal to 60%.

[0016] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit is connected to a first electrode of the light-emitting unit. The pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to a second initial signal line, and the second electrode of which is connected to the first electrode of the light-emitting unit. The display panel further includes a third conductive layer and a fourth conductive layer. The third conductive layer is located on one side of the substrate; the fourth conductive layer is located on the side of the third conductive layer opposite to the substrate, and the fourth conductive layer includes the second initial signal line, which includes a first sub-initial signal line and / or a second sub-initial signal line. The orthographic projection of the first sub-initial signal line on the substrate extends along a first direction, and the orthographic projection of the second sub-initial signal line on the substrate extends along a second direction, wherein the first direction and the second direction intersect.

[0017] In one exemplary embodiment of this disclosure, when the second initial signal line includes a first sub-initial signal line, the orthographic projection of the first sub-initial signal line on the substrate at least partially overlaps with the orthographic projection of the third initial signal line on the substrate.

[0018] In an exemplary embodiment of this disclosure, in the second unit pixel, the area of ​​the orthographic projection of the first sub-initial signal line on the substrate is S3, the overlapping area of ​​the orthographic projection of the first sub-initial signal line on the substrate and the orthographic projection of the third initial signal line on the substrate is S4, and S4 / S3 is greater than or equal to 50%.

[0019] In one exemplary embodiment of this disclosure, when the second initial signal line includes a first sub-initial signal line and a second sub-initial signal line, the second sub-initial signal line is connected to the first sub-initial signal line that intersects with it.

[0020] In one exemplary embodiment of this disclosure, the display panel includes a plurality of repeating units arrayed along a first direction and a second direction. Each repeating unit includes two pixel driving circuits distributed along the first direction, and the two pixel driving circuits in the same repeating unit are mirror-symmetrically arranged along a mirror symmetry plane. The plurality of repeating units distributed in the second direction form a repeating unit column. When the second initial signal line includes a second sub-initial signal line, at least a portion of the repeating unit column is correspondingly provided with a second sub-initial signal line, and the orthographic projection of the mirror symmetry plane on the substrate is located on the orthographic projection of the second sub-initial signal line on the substrate.

[0021] In one exemplary embodiment of this disclosure, the display panel includes a plurality of repeating units arrayed along a first direction and a second direction. Each repeating unit includes two pixel driving circuits distributed along the first direction. The two pixel driving circuits in the same repeating unit are mirror-symmetrically arranged along a mirror symmetry plane, and the first direction and the second direction intersect. Each pixel driving circuit further includes a fifth transistor, the first electrode of which is connected to a power supply line, and the second electrode of which is connected to the first electrode of the driving transistor. The display panel further includes a first active layer, comprising a third active portion, a fifth active portion, and a thirteenth active portion. The third active portion forms the channel region of the driving transistor, the fifth active portion forms the channel region of the fifth transistor, and the thirteenth active portion is connected to the side of the fifth active portion away from the third active portion. In adjacent repeating units along the first direction, the fifth active portions of two adjacent pixel driving circuits are connected through the same thirteenth active portion, and the thirteenth active portion is connected to the power supply line.

[0022] In one exemplary embodiment of this disclosure, the display panel includes a plurality of repeating units arrayed along a first direction and a second direction. Each repeating unit includes two pixel driving circuits distributed along the first direction. The two pixel driving circuits in the same repeating unit are mirror-symmetrically arranged along a mirror symmetry plane, and the first direction and the second direction intersect. The display panel also includes a light-emitting unit. The pixel driving circuits are connected to a first electrode of the light-emitting unit. The pixel driving circuits further include a sixth transistor and a seventh transistor. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit. The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; the display panel further includes: a first active layer, the first active layer including a sixth active portion, a seventh active portion, and a seventeenth active portion, the sixth active portion being used to form the channel region of the sixth transistor, the seventh active portion being used to form the channel region of the seventh transistor, and the seventeenth active portion being connected to the side of the seventh active portion away from the sixth active portion; in the same repeating unit, the seventh active portions in two adjacent pixel driving circuits are connected through the same seventeenth active portion, and the seventeenth active portion is connected to the second initial signal line.

[0023] In an exemplary embodiment of this disclosure, the display panel further includes: a fourth conductive layer, a fifth conductive layer, an electrode layer, and a pixel definition layer. The fourth conductive layer is located on one side of the substrate; the fifth conductive layer is located on the side of the fourth conductive layer facing away from the substrate, and the fifth conductive layer includes power lines whose orthographic projection on the substrate extends along a second direction; wherein the power lines include a first power line segment, a second power line segment, and a third power line segment, the second power line segment being connected between the first power line segment and the third power line segment; in the same repeating unit, adjacent second power line segments are connected, and the connected second power line segments form a power supply section, and a plurality of power supply sections include a first power supply section and a second power supply section; the electrode layer is located on the side of the fifth conductive layer facing away from the substrate, and the electrode layer includes a plurality of electrode sections, including a first electrode section and a second electrode section, wherein the orthographic projection of the first electrode section on the substrate is smaller than the orthographic projection of the second electrode section on the substrate; the pixel definition layer is located on the side of the electrode layer facing away from the substrate, and a plurality of openings for forming light-emitting units are formed on the pixel definition layer. The opening is correspondingly disposed with respect to the electrode portion, wherein the orthographic projection of the opening on the substrate coincides with the orthographic projection of the corresponding electrode portion on the substrate; wherein the first electrode portion and the first power supply portion are correspondingly disposed, and the second electrode portion and the second power supply portion are correspondingly disposed, wherein the orthographic projection of the first electrode portion on the substrate and the orthographic projection of the corresponding first power supply portion on the substrate at least partially overlap, and the orthographic projection of the second electrode portion on the substrate and the orthographic projection of the corresponding second power supply portion on the substrate at least partially overlap; the area of ​​the orthographic projection of the second power supply portion on the substrate is larger than the orthographic projection of the first power supply portion on the substrate, and the overlapping area of ​​the orthographic projection of the second power supply portion on the substrate and the orthographic projection of the corresponding second electrode portion on the substrate is larger than the overlapping area of ​​the orthographic projection of the first power supply portion on the substrate and the orthographic projection of the corresponding first electrode portion on the substrate.

[0024] In one exemplary embodiment of this disclosure, the display panel further includes a light-emitting unit, and the pixel driving circuit further includes: a fourth transistor, a fifth transistor, a sixth transistor, and a seventh transistor. The first electrode of the fourth transistor is connected to a data line, and the second electrode of the fourth transistor is connected to the first electrode of the driving transistor. The first electrode of the fifth transistor is connected to a power line, and the second electrode of the fifth transistor is connected to the first electrode of the driving transistor. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit. The first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit. The first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are P-type transistors, and the eighth transistor is an N-type transistor.

[0025] According to one aspect of this disclosure, a display device is provided, wherein the display panel described above is included.

[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0027] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0028] Figure 1 This is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel disclosed herein;

[0029] Figure 2 for Figure 1 The timing diagram of the signals at each node in the pixel driving circuit shown;

[0030] Figure 3 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein;

[0031] Figure 4 for Figure 3 Structural layout of the middle shielding layer;

[0032] Figure 5 for Figure 3 Structural layout of the first active layer;

[0033] Figure 6 for Figure 3Structural layout of the first conductive layer;

[0034] Figure 7 for Figure 3 Structural layout of the second conductive layer;

[0035] Figure 8 for Figure 3 Structural layout of the second active layer;

[0036] Figure 9 for Figure 3 Structural layout of the third conductive layer;

[0037] Figure 10 for Figure 3 Structural layout of the fourth conductive layer;

[0038] Figure 11 for Figure 3 The structural layout of the fifth conductive layer;

[0039] Figure 12 for Figure 3 Structural layout of the middle electrode layer;

[0040] Figure 13 for Figure 3 Structural layout of the middle shielding layer and the first active layer;

[0041] Figure 14 for Figure 3 Structural layout of the middle shielding layer, the first active layer, and the first conductive layer;

[0042] Figure 15 for Figure 3 The structural layout of the middle shielding layer, the first active layer, the first conductive layer, and the second conductive layer;

[0043] Figure 16 for Figure 3 The structural layout of the middle shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer;

[0044] Figure 17 for Figure 3 The structural layout of the middle shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer;

[0045] Figure 18 for Figure 3 The structural layout of the middle shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer;

[0046] Figure 19 for Figure 3The structural layout of the middle shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer;

[0047] Figure 20 This is a structural layout of the fifth conductive layer and electrode layer in an exemplary embodiment of the display panel disclosed herein;

[0048] Figure 21 for Figure 20 The structural layout of the fifth conductive layer;

[0049] Figure 22 for Figure 20 Structural layout of the middle electrode layer;

[0050] Figure 23 for Figure 3 The diagram shows a partial cross-sectional view of the display panel cut along the dashed line AA.

[0051] Figure 24 for Figure 1 The timing diagram of the signals at each node in another driving method of the pixel driving circuit shown;

[0052] Figure 25 This is a partial structural layout diagram of another exemplary embodiment of the display panel disclosed herein;

[0053] Figure 26 for Figure 25 The diagram shows the structural layout of the second conductive layer in the display panel. Detailed Implementation

[0054] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0055] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.

[0056] like Figure 1The diagram shown is a schematic diagram of the pixel driving circuit in an exemplary embodiment of the display panel of this disclosure. The pixel driving circuit may include: a first transistor T1, a second transistor T2, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, and a capacitor C. Specifically, the first terminal of the eighth transistor T8 is connected to the gate of the driving transistor T3, and the gate is connected to the second gate driving signal terminal G2; the first terminal of the first transistor T1 is connected to the first initial signal terminal Vinit1, the second terminal is connected to the second terminal of the eighth transistor T8, and the gate is connected to the first reset signal terminal Re1; the first terminal of the second transistor T2 is connected to the second terminal of the eighth transistor T8, the second terminal is connected to the second terminal of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first terminal of the fourth transistor T4 is connected to the data signal terminal Da, the second terminal is connected to the first terminal of the driving transistor T3, and the gate is connected to the first gate driving signal terminal G1; the first terminal of the fifth transistor T5 is connected to… The first power supply terminal is VDD, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM. The first electrode of the sixth transistor T6 is connected to the second electrode of the driving transistor T3, and the gate is connected to the enable signal terminal EM. The first electrode of the seventh transistor T7 is connected to the second initial signal terminal Vinit2, the second electrode is connected to the second electrode of the sixth transistor T6, and the gate is connected to the second reset signal terminal Re2. The first electrode of the ninth transistor T9 is connected to the third initial signal terminal Vinit3, the second electrode is connected to the first electrode of the driving transistor T3, and the gate is connected to the second reset signal terminal Re2. The first electrode of the capacitor is connected to the gate of the driving transistor T3, and the second electrode is connected to the first power supply terminal VDD. This pixel driving circuit can be used to drive the light-emitting unit OLED to emit light. The first electrode of the light-emitting unit OLED is connected to the second electrode of the sixth transistor T6, and the second electrode of the light-emitting unit OLED is connected to the second power supply terminal VSS. Among them, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 can all be P-type transistors, and the eighth transistor T8 can be an N-type transistor.

[0057] like Figure 2 As shown, Figure 1 The diagram shows the timing of signals at each node in the pixel driving circuit. Here, EM represents the timing of the enable signal; G1 represents the timing of the first gate drive signal; G2 represents the timing of the second gate drive signal; Re1 represents the timing of the first reset signal; and Re2 represents the timing of the second reset signal.

[0058] The driving method of the pixel driving circuit in this disclosure may include a reset phase t2, a data writing phase t4, and a light-emitting phase t6. In the reset phase t2: the second gate driving signal terminal G2 outputs a high level, the first reset signal terminal Re1 and the second reset signal terminal Re2 output a low level, the eighth transistor T8, the first transistor T1, the seventh transistor T7, and the ninth transistor T9 are turned on, the first initial signal terminal Vinit1 inputs a first initial signal to the gate of the driving transistor T3 through the first transistor T1 and the eighth transistor T8, the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit through the seventh transistor T7, and the third initial signal terminal Vinit3 inputs a third initial signal to the first electrode of the driving transistor T3 through the ninth transistor T9. In the data writing phase t4: the second gate driving signal terminal G2 outputs a high level, the first gate driving signal terminal G1 outputs a low level signal, the eighth transistor T8, the second transistor T2, and the fourth transistor T4 are turned on, and the data signal terminal Da outputs a data signal to write a compensation voltage Vdata+Vth to the gate of the driving transistor, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. During the light-emitting stage t6: the enable signal terminal EM outputs a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The driving transistor T3, under the influence of its gate voltage Vdata + Vth, drives the OLED unit to emit light. According to the driving transistor output current formula I = (μWCox / 2L)(Vgs - Vth) 2 Where μ is the carrier mobility; Cox is the gate capacitance per unit area; W is the width of the driving transistor channel; L is the length of the driving transistor channel; Vgs is the gate-source voltage difference of the driving transistor; and Vth is the threshold voltage of the driving transistor. In the pixel driving circuit of this disclosure, the output current of the driving transistor I = (μWCox / 2L)(Vdata + Vth - Vdd - Vth) 2 This pixel driving circuit can avoid the influence of the driving transistor threshold on its output current.

[0059] In this exemplary embodiment, the display panel can reset the first terminal of the driving transistor T3 via the ninth transistor T9, and reset the gate of the driving transistor T3 via the eighth transistor T8 and the first transistor T1, thereby restoring the hysteresis of the driving transistor. Furthermore, by adding the eighth transistor T8, the display panel can reduce the leakage current through the first transistor T1 and the second transistor T2 at the gate of the driving transistor T3.

[0060] like Figure 2As shown, the pixel driving circuit driving method further includes a pre-reset stage t1, a hysteresis elimination stage t3, a re-reset stage t5, and a repeated reset stage t7. In the pre-reset stage t1: the second reset signal terminal Re2 outputs a low-level signal, the ninth transistor T9 is turned on, and the third initial signal terminal Vinit3 pre-charges the first electrode of the driving transistor T3 with a third initial signal. This setting can restore the hysteresis of the driving transistor T3 caused by the bias voltage of the previous frame, thereby reducing image retention on the display panel. In the re-reset stage t5: the second reset signal terminal Re2 outputs a low-level signal, the ninth transistor T9 is turned on, and the third initial signal terminal Vinit3 again sends a third initial signal to the first electrode of the driving transistor T3. This setting can also restore the hysteresis of the driving transistor T3. In the repeated reset stage t7: the second reset signal terminal Re2 outputs a low-level signal, the seventh transistor T7 is turned on, and the second initial signal terminal Vinit2 inputs a second initial signal to the first electrode of the light-emitting unit OLED to reset the first electrode of the light-emitting unit OLED. In one frame cycle, the pixel driving circuit driving method may include multiple repeated reset stages t7.

[0061] like Figure 2 As shown, the duration of the pre-reset phase t1 can be 12H; the duration of G2 between the rising edge of the reset phase t2 and the falling edge of G1 in the data write phase t4 can be 8H; the duration of the data write phase t4 can be less than H; and the duration of the repeated reset phase t7 can be 56H. H is the duration of a unit cycle. In other exemplary embodiments, each phase can also have other durations. For example, the duration of the reset phase t2 can be 1 to 3 times the duration of the data write phase t4, such as 1 to 2 times, 2 to 3 times, etc. The duration of the re-reset phase t5 can be 1 to 5 times the duration of the data write phase t4, such as 1 to 2 times, 2 to 3 times, 3 to 4 times, 4 to 5 times, etc. The voltage of the first initial signal can be -2V to -5V, such as -2V, -3V, -4V, -5V. The voltage of the second initial signal can be from -2V to -5V, for example, the voltage of the second initial signal can be -2V, -3V, -4V, or -5V. The voltage of the third initial signal can be from 3V to 7V, for example, the voltage of the third initial signal can be 3V, 4V, 5V, 6V, or 7V.

[0062] This exemplary embodiment also provides a display panel, which may include a substrate, a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, and an electrode layer stacked sequentially, wherein an insulating layer may be disposed between adjacent layers. Figure 3-19 As shown, Figure 3 This is a structural layout diagram of an exemplary embodiment of the display panel disclosed herein. Figure 4 for Figure 3 Structural layout of the middle shading layer, Figure 5 for Figure 3 The structural layout of the first active layer in the middle, Figure 6 for Figure 3 The structural layout of the first conductive layer in the middle, Figure 7 for Figure 3 Layout of the second conductive layer. Figure 8 for Figure 3 The structural layout of the second active layer in the middle. Figure 9 for Figure 3 The structural layout of the third conductive layer in the middle. Figure 10 for Figure 3 The structural layout of the fourth conductive layer in the middle. Figure 11 for Figure 3 Schematic diagram of the fifth conductive layer. Figure 12 for Figure 3 Structural layout of the middle electrode layer, Figure 13 for Figure 3 The structural layout of the middle shielding layer and the first active layer. Figure 14 for Figure 3 The structural layout of the middle shielding layer, the first active layer, and the first conductive layer. Figure 15 for Figure 3 The structural layout of the middle shielding layer, the first active layer, the first conductive layer, and the second conductive layer. Figure 16 for Figure 3 The structural layout of the middle shielding layer, the first active layer, the first conductive layer, the second conductive layer, and the second active layer. Figure 17 for Figure 3 The structural layout of the middle shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, and the third conductive layer. Figure 18 for Figure 3 The structural layout of the middle shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, and the fourth conductive layer. Figure 19 for Figure 3 The structural layout of the middle shielding layer, the first active layer, the first conductive layer, the second conductive layer, the second active layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer. This display panel may include multiple... Figure 1 The pixel driving circuit shown is an example. Figure 19As shown, the multiple pixel driving circuits may include a first pixel driving circuit P1 and a second pixel driving circuit P2 adjacently distributed in the first direction X. The first pixel driving circuit P1 and the second pixel driving circuit P2 may be mirror-symmetrically arranged with a mirror symmetry plane BB. The mirror symmetry plane BB may be perpendicular to the substrate. Furthermore, the orthographic projections of the first pixel driving circuit P1 and the second pixel driving circuit P2 on the substrate may be symmetrically arranged with the intersection of the mirror symmetry plane BB and the substrate as the axis of symmetry. The first pixel driving circuit P1 and the second pixel driving circuit P2 may form a repeating unit. The display panel may include multiple repeating units arrayed in the first direction X and the second direction Y. The second direction Y and the first direction X may intersect; for example, the first direction X may be a row direction, and the second direction Y may be a column direction. The pixel driving circuit may include structures located in a shielding layer, a first active layer, a first conductive layer, a second conductive layer, a second active layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer. The pixel driving circuit does not include structures located in an electrode layer. Furthermore, in this exemplary embodiment, the display panel may have design and manufacturing errors, and the first pixel driving circuit P1 and the second pixel driving circuit P2 may be approximately mirror-symmetrical about the mirror symmetry plane BB.

[0063] like Figure 3 , Figure 4 , Figure 13 As shown, the shielding layer may include a plurality of shielding portions 71, a first extension portion 73, and a second extension portion 72. The orthographic projection of the first extension portion 73 on the substrate extends along the second direction Y and connects adjacent shielding portions 71 in the second direction Y. The orthographic projection of the second extension portion 72 on the substrate extends along the first direction X and connects adjacent shielding portions 71 in the first direction X.

[0064] like Figure 3 , 5As shown in Figures 13 and 14, the first active layer may include a first active portion 61, a second active portion 62, a third active portion 63, a fourth active portion 64, a fifth active portion 65, a sixth active portion 66, a seventh active portion 67, and a ninth active portion 69. Specifically, the first active portion 61 forms the channel region of the first transistor T1, the second active portion 62 forms the channel region of the second transistor T2, the third active portion 63 forms the channel region of the driving transistor T3, the fourth active portion 64 forms the channel region of the fourth transistor T4, the fifth active portion 65 forms the channel region of the fifth transistor T5, the sixth active portion 66 forms the channel region of the sixth transistor T6, the seventh active portion 67 forms the channel region of the seventh transistor T7, and the ninth active portion 69 forms the channel region of the ninth transistor T9. In addition, the first active layer may also include: the tenth active section 610, the eleventh active section 611, the twelfth active section 612, the thirteenth active section 613, the fourteenth active section 614, the fifteenth active section 615, the sixteenth active section 616, the seventeenth active section 617, and the eighteenth active section 618. The tenth active part 610 is connected to the end of the fourth active part 64 away from the third active part 63; the eleventh active part 611 is connected between the first active part 61 and the second active part 62; the twelfth active part 612 is connected between the third active part 63 and the fifth active part 65; the thirteenth active part 613 is connected to the end of the fifth active part 65 away from the third active part 63; the fourteenth active part 614 is connected between the sixth active part 66 and the seventh active part 67; the fifteenth active part 615 and the sixteenth active part 616 are connected to the two ends of the ninth active part 69; the seventeenth active part 617 is connected to the end of the seventh active part 67 away from the sixth active part 66, and in the same repeating unit, the seventh active part 67 in two adjacent pixel driving circuits is connected through the same seventeenth active part 617; the eighteenth active part 618 is connected to the end of the first active part 61 away from the second active part 62. The orthogonal projection of the shielding portion 71 onto the substrate can cover the orthogonal projection of the third active portion 63 onto the substrate. The shielding portion 71 can block light from the third active portion 63 to reduce the impact of light on the driving characteristics of the driving transistor T3. Furthermore, the shielding layer can be made of a conductive material and can also be connected to a stable voltage source to shield the driving transistor T3 from noise. For example, the shielding layer can be connected to the first power supply terminal VDD, the first initial signal terminal Vinit1, the second initial signal terminal Vinit2, and the third initial signal terminal Vinit3. The first active layer can be formed of polycrystalline silicon. Correspondingly, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the ninth transistor T9 can be P-type low-temperature polycrystalline silicon thin-film transistors.

[0065] like Figure 3 ,6 As shown in Figure 14, the first conductive layer may include a first reset signal line Re1, a first gate line G1, an enable signal line EM, a second reset signal line Re2, and a first conductive portion 11. The first reset signal line Re1 can be used to provide... Figure 1 The first reset signal terminal in the first reset signal line Re1. The orthogonal projection of the first reset signal line Re1 on the substrate can cover the orthogonal projection of the first active part 61 on the substrate. A portion of the structure of the first reset signal line Re1 can be used to form the gate of the first transistor T1. The first gate line G1 can be used to provide... Figure 1 The first gate drive signal terminal is located in the first gate line G1. The orthogonal projection of the first gate line G1 onto the substrate can cover the orthogonal projections of the second active portion 62 and the fourth active portion 64 onto the substrate. A portion of the structure of the first gate line G1 can be used to form the gate of the second transistor T2, and another portion of the structure of the first gate line G1 can be used to form the gate of the fourth transistor T4. The enable signal line EM is used to provide... Figure 1 The enable signal terminal, the orthogonal projection of the enable signal line EM on the substrate can extend along the first direction X and cover the orthogonal projections of the fifth active portion 65 and the sixth active portion 66 on the substrate. A portion of the structure of the enable signal line EM can be used to form the gate of the fifth transistor T5, and another portion of the structure of the enable signal line EM can be used to form the gate of the sixth transistor T6. The second reset signal line Re2 is used to provide... Figure 1 The second reset signal terminal is located in the substrate. The orthogonal projection of the second reset signal line Re2 onto the substrate can cover the orthogonal projections of the seventh active part 67 and the ninth active part 69 onto the substrate. A portion of the structure of the second reset signal line Re2 can be used to form the gate of the seventh transistor T7, and another portion of the structure of the second reset signal line segment Re22 can be used to form the gate of the ninth transistor. The orthogonal projection of the first conductive part 11 onto the substrate can cover the orthogonal projection of the third active part 63 onto the substrate. The first conductive part 11 can be used to form the gate of the driving transistor T3 and the first electrode of the capacitor C.

[0066] like Figure 3 , 6As shown in Figure 14, the orthographic projections of the first reset signal line Re1, the first gate line G1, the first conductive portion 11, the enable signal line EM, and the second reset signal line Re2 on the substrate can be sequentially distributed along the second direction Y. The first reset signal line Re1 in the current row pixel driving circuit can be reused as the second reset signal line Re2 in the adjacent previous row pixel driving circuit. This arrangement can improve the integration density of the pixel driving circuit in the second direction Y. Furthermore, the display panel can use the first conductive layer as a mask to perform conductor treatment on the first active layer, that is, the area covered by the first conductive layer in the first active layer can form the channel region of the transistor, and the area not covered by the first conductive layer in the first active layer forms a conductor structure.

[0067] like Figure 3 , 7 As shown in Figure 15, the second conductive layer may include a third gate line 2G2, a third initial signal line Vinit3, and a second conductive portion 22. The orthographic projection of the third initial signal line Vinit3 onto the substrate and the orthographic projection of the third gate line 2G2 onto the substrate can both extend along the first direction X. The third initial signal line Vinit3 is used to provide... Figure 1 The third initial signal terminal, the third gate line 2G2, is used to provide Figure 1 The second gate drive signal terminal in the capacitor. The orthographic projection of the second conductive portion 22 on the substrate can overlap with the orthographic projection of the first conductive portion 11 on the substrate, and the second conductive portion 22 can be used to form the second electrode of the capacitor C. Figure 3 , 7 As shown in Figure 15, the orthographic projection of the third initial signal line Vinit3 in the adjacent previous row pixel driving circuit onto the substrate can be located between the orthographic projection of the third gate line 2G2 in the current row pixel driving circuit onto the substrate and the orthographic projection of the first reset signal line Re1 in the current row pixel driving circuit onto the substrate. This arrangement can further improve the integration of the pixel driving circuit in the second direction Y. The second conductive layer may further include a first connecting portion 23 and a second connecting portion 24. The first connecting portion 23 connects between two adjacent second conductive portions 22 in the same repeating unit. The second connecting portion 24 connects between two adjacent second conductive portions 22 in adjacent repeating units in the first direction X.

[0068] like Figure 3 , 8As shown in Figure 16, the second active layer may include multiple sub-active portions 8, including an eighth active portion 88, a nineteenth active portion 819, and a twentieth active portion 820. The eighth active portion 88 is connected between the nineteenth active portion 819 and the twentieth active portion 820, and is used to form the channel region of the eighth transistor. The orthogonal projection of the third gate line 2G2 on the substrate can cover the orthogonal projection of the eighth active portion 88 on the substrate, and a portion of the structure of the third gate line 2G2 can be used to form the bottom gate of the eighth transistor T8. The second active layer may be formed of indium gallium zinc oxide, and correspondingly, the eighth transistor T8 may be an N-type metal-oxide thin-film transistor.

[0069] like Figure 3 , 9 As shown in Figure 17, the third conductive layer may include: a second gate line 3G2 and a first initial signal line Vinit1. The orthographic projections of the second gate line 3G2 and the first initial signal line Vinit1 on the substrate can both extend along the first direction X. The second gate line 3G2 is used to provide... Figure 1 The second gate driving signal terminal, the orthogonal projection of the second gate line 3G2 on the substrate can cover the orthogonal projection of the eighth active part 88 on the substrate, and part of the structure of the second gate line 3G2 can be used to form the top gate of the eighth transistor T8. The second gate line 3G2 and the third gate line 2G2 in the same row of pixel driving circuits can be connected by vias, and the vias connecting the second gate line 3G2 and the third gate line 2G2 can be located in the edge routing area outside the display area of ​​the display panel. The first initial signal line Vinit1 can be used to provide Figure 1The first initial signal terminal in the image. In this exemplary embodiment, the orthographic projection of the first initial signal line Vinit1 in the adjacent next row pixel driving circuit onto the substrate can be located between the orthographic projection of the first conductive part 11 in the current row pixel driving circuit onto the substrate and the orthographic projection of the second reset signal line Re2 in the current row pixel driving circuit onto the substrate. This arrangement can further improve the integration of the pixel driving circuit in the second direction Y. In addition, the orthographic projection of the first initial signal line Vinit1 in the adjacent next row pixel driving circuit onto the substrate can at least partially overlap with the orthographic projection of the enable signal line EM in the current row pixel driving circuit onto the substrate. This arrangement can improve the transmittance of the display panel to meet the transmittance requirements of the optical under-display fingerprint sensor. Wherein, in the first unit pixel, the area of ​​the orthographic projection of the first initial signal line Vinit1 in the adjacent next row pixel driving circuit onto the substrate is S1, and in the first unit pixel, the overlapping area of ​​the orthographic projection of the first initial signal line Vinit1 in the adjacent next row pixel driving circuit onto the substrate and the orthographic projection of the enable signal line EM in the current row pixel driving circuit onto the substrate is S2. S2 / S1 can be greater than 60%, for example, S2 / S1 can be equal to 60%, 70%, 80%, 90%, 100%, etc. The first unit pixel includes two rows and n columns of pixel driving circuits, where n is a positive integer greater than or equal to 1, and the two rows of pixel driving circuits in the first unit pixel are arranged adjacently. For example, the first unit pixel may include two rows and one column of pixel driving circuits; another example is that the first unit pixel may include two entire rows of pixel driving circuits located in the display area. Furthermore, the display panel can utilize the third conductive layer as a mask to conduct the second active layer, that is, the area in the second active layer covered by the third conductive layer can form the channel region of the transistor, and the area in the second active layer not covered by the third conductive layer forms a conductive structure.

[0070] like Figure 3 , 9 As shown in Figure 17, in the same pixel driving circuit, and in the first direction X, the orthographic projection of the second active portion 62 on the substrate is located on the side where the orthographic projection of the eighth active portion 88 on the substrate is far from the orthographic projection of the first extension 73 on the substrate. This arrangement allows the second active portion 62 to be located away from the first extension 73, thereby avoiding changes in the crystallization state of the first active layer and the risk of tunneling caused by the edge morphology of the first extension 73. It should be understood that in other exemplary embodiments, in the same pixel driving circuit, and in the first direction X, the orthographic projection of the second active portion 62 on the substrate may also be located between the orthographic projection of the eighth active portion 88 on the substrate and the orthographic projection of the first extension 73 on the substrate.

[0071] like Figure 3 , 9As shown in Figure 17, the minimum distance between the orthographic projection of the first active part 61 on the substrate and the orthographic projection of the shielding layer on the substrate is L3, and the size of the orthographic projection of the first active part 61 on the substrate in the first direction X is L4. L3 can be greater than or equal to L4. For example, L3 can be 1, 2, 3, or 4 times L4, etc. The minimum distance between the orthographic projection of the ninth active part 69 on the substrate and the orthographic projection of the shielding layer on the substrate is L5, and the size of the orthographic projection of the ninth active part 69 on the substrate in the first direction X is L6. L5 can be greater than or equal to L6. For example, L5 can be 1, 2, 3, or 4 times L6, etc. The minimum distance between the orthographic projection of the second active part 62 on the substrate and the orthographic projection of the shielding layer on the substrate is L7, and the size of the orthographic projection of the second active part 62 on the substrate in the first direction X is L8. L7 can be greater than or equal to L8. For example, L7 can be 1, 2, 3, or 4 times L8, etc. The minimum distance between the orthographic projection of the fourth active part 64 on the substrate and the orthographic projection of the shielding layer on the substrate is L9, and the dimension of the orthographic projection of the fourth active part 64 on the substrate in the first direction X is L10. L9 can be greater than or equal to L10. For example, L9 can be 1, 2, 3, or 4 times L10. The minimum distance between the orthographic projection of the fifth active part 65 on the substrate and the orthographic projection of the shielding layer on the substrate is L11, and the dimension of the orthographic projection of the fifth active part 65 on the substrate in the first direction X is L12. L11 can be greater than or equal to L12. For example, L11 can be 1, 2, 3, or 4 times L12. The minimum distance between the orthographic projection of the sixth active part 66 on the substrate and the orthographic projection of the shielding layer on the substrate is L13, and the dimension of the orthographic projection of the sixth active part 66 on the substrate in the first direction X is L14. L13 can be greater than or equal to L14. For example, L13 can be 1, 2, 3, or 4 times that of L14. The minimum distance between the orthographic projection of the seventh active part 67 on the substrate and the orthographic projection of the shielding layer on the substrate is L15, and the dimension of the orthographic projection of the seventh active part 67 on the substrate in the first direction X is L16. L15 can be greater than or equal to L16. For example, L15 can be 1, 2, 3, or 4 times that of L16.

[0072] like Figure 3 , 10 As shown in Figure 18, the fourth conductive layer may include: a second initial signal line Vinit2, a first bridging portion 41, a second bridging portion 42, a third bridging portion 43, a fourth bridging portion 44, a fifth bridging portion 45, a sixth bridging portion 46, a seventh bridging portion 47, an eighth bridging portion 48, and a ninth bridging portion 49. The second initial signal line Vinit2 can be used to provide... Figure 1The second initial signal terminal is defined in the diagram. The second initial signal line Vinit2 may include a first sub-initial signal line Vinit21 and a second sub-initial signal line Vinit22. The orthographic projection of the first sub-initial signal line Vinit21 onto the substrate can extend along a first direction X, and the second sub-initial signal line Vinit22 can extend along a second direction Y. Intersecting first and second sub-initial signal lines Vinit21 and Vinit22 are connected. The second initial signal line Vinit2 can be connected to the seventeenth active portion 617 via a via H to connect the first electrode and the second initial signal terminal of the seventh transistor T7. The seventeenth active portion 617 is connected between adjacent seventh active portions 67. This arrangement can improve the integration density of the pixel driving circuit in the first direction while reducing the number of vias. Black squares indicate the positions of the vias. In this exemplary embodiment, each row of pixel driving circuits can be correspondingly provided with a first sub-initial signal line Vinit21, and each column of repeating units can be correspondingly provided with a second sub-initial signal line Vinit22. Multiple first sub-initial signal lines Vinit21 and multiple second sub-initial signal lines Vinit22 can form a grid structure. The second initial signal lines Vinit2 in the grid structure have lower resistance, thereby reducing the voltage difference between the second initial signal terminals at different positions on the display panel. In this exemplary embodiment, as... Figure 19As shown, the orthographic projection of the mirror symmetry plane BB onto the substrate can be located on the orthographic projection of the second sub-initial signal line Vinit22 onto the substrate. It should be understood that in other exemplary embodiments, the second initial signal line Vinit2 can also have other arrangements. For example, a multi-row pixel driving circuit can be correspondingly provided with a first sub-initial signal line Vinit21 and / or a multi-column repeating unit can be correspondingly provided with a second sub-initial signal line Vinit22. For another example, the second initial signal line Vinit2 can include only the first sub-initial signal line Vinit21 or the second sub-initial signal line Vinit22. The first bridging portion 41 can be connected to the thirteenth active portion 613 and the second connecting portion 24 via vias, respectively, to connect the first electrode of the fifth transistor T5 and the second electrode of the capacitor C. In two adjacent repeating units in the first direction X, adjacent pixel driving circuits can share the same first bridging portion 41, and the shared first bridging portion 41 is used to connect the second connecting portion 24 via the same via. Furthermore, in two adjacent repeating units in the first direction X, the fifth active portion 65 in the adjacent pixel driving circuits can be connected through the thirteenth active portion 613. This arrangement can improve the integration of the display panel in the first direction. Simultaneously, the thirteenth active portion 613 can be connected to the first bridging portion 41 through a single via, reducing the number of vias. The second bridging portion 42 can connect the twelfth active portion 612 and the fifteenth active portion 615 through vias, respectively, to connect the second terminal of the ninth transistor T9 and the first terminal of the driving transistor. The third bridging portion 43 can connect the sixteenth active portion 616 and the third initial signal line Vinit3 through vias, respectively, to connect the first terminal of the ninth transistor T9 and the third initial signal terminal. The fourth bridging portion 44 can connect the first conductive portion 11 and the twentieth active portion 820 through vias, respectively, to connect the gate of the driving transistor T3 and the first terminal of the eighth transistor T8. Figure 7 As shown, an opening 221 is formed on the second conductive portion 22. The orthographic projection of the via connecting the first conductive portion 11 and the fourth bridging portion 44 on the substrate is located within the orthographic projection of the opening 221 on the substrate, so that the via connecting the first conductive portion 11 and the fourth bridging portion 44 is insulated from the second conductive portion 22. The fifth bridging portion 45 can be connected to the eighteenth active portion 618 and the first initial signal line Vinit1 through vias, respectively, to connect the first terminal and the first initial signal terminal of the first transistor T1. The sixth bridging portion 46 can be connected to the fourteenth active portion 614 through vias, to connect the second terminal of the sixth transistor T6 and the second terminal of the seventh transistor T7. The eighth bridging portion 48 can be connected to the nineteenth active portion 819 and the eleventh active portion 611 through vias, respectively, to connect the second terminal of the eighth transistor T8 and the second terminal of the first transistor and the first terminal of the second transistor. The ninth bridging portion 49 is connected to the tenth active portion 610 through vias, to connect the first terminal of the fourth transistor.

[0073] like Figure 3 , 8 As shown in Figures 17 and 18, in this exemplary embodiment, the first gate line G1 is disposed between the first conductive portion 11 and the second gate line 3G2, thereby increasing the coupling between the first gate line G1 and the first conductive portion 11. At the end of the data writing phase, the voltage of the first gate line G1 increases, and the first gate line G1 can pull up the voltage of the gate of the driving transistor T3. This arrangement can reduce the voltage of the data signal when the display panel is in black, thereby reducing the power consumption of the display panel. In this exemplary embodiment, the orthographic projection of the twentieth active portion 820 on the substrate and the orthographic projection of the first gate line G1 on the substrate at least partially overlap. At the end of the data writing phase, the first gate line G1 can pull up the voltage of the gate of the driving transistor T3 through the twentieth active portion 820. This arrangement can further reduce the voltage of the data signal when the display panel is in black, thereby reducing the power consumption of the display panel. Figure 8 As shown, the orthographic projection of the twentieth active unit 820 onto the substrate can extend along the first direction X, and the size of the orthographic projection of the twentieth active unit 820 onto the substrate in the first direction X can be greater than the size of the orthographic projection of the twentieth active unit 820 onto the substrate in the second direction Y. In this exemplary embodiment, the size of the orthographic projection of the eighth active unit 88 onto the substrate in the first direction is L1, and the size of the orthographic projection of the twentieth active unit 820 onto the substrate in the first direction is L2; ​​wherein L2 / L1 is greater than or equal to 2 and less than or equal to 7. For example, L2 / L1 can be equal to 2, 3, 4, 5, 6, 7, etc.

[0074] like Figure 3 , 10 As shown in Figure 18, the orthographic projection of the first sub-initial signal line Vinit21 on the substrate can at least partially overlap with the orthographic projection of the third initial signal line Vinit3 on the substrate. This arrangement can improve the transmittance of the display panel. For example, in the second unit pixel, the area of ​​the orthographic projection of the first sub-initial signal line Vinit21 on the substrate can be S3, and the overlapping area of ​​the orthographic projections of the first sub-initial signal line Vinit21 and the third initial signal line Vinit3 on the substrate is S4. S4 / S3 can be greater than or equal to 50%, for example, S4 / S3 can be equal to 50%, 60%, 70%, 80%, 90%, 100%, etc. The second unit pixel includes one row and m columns of pixel driving circuits, where m is a positive integer greater than or equal to 1. For example, the second unit pixel can include one row and one column of pixel driving circuits; or, for another example, the second unit pixel can include an entire row of pixel driving circuits located in the display area.

[0075] like Figure 3 ,11 As shown in Figure 19, the fifth conductive layer may include a data line Da, a power line VDD, and a tenth bridging portion 510. The data line Da can be used to provide... Figure 1 The data signal terminal in the middle, the power line VDD can be used to provide Figure 1 The first power supply terminal is located in the substrate. The orthographic projection of the data line Da on the substrate and the orthographic projection of the power line VDD on the substrate can extend along the second direction Y. The data line Da can be connected to the ninth bridge part 49 through a via to connect the first electrode of the fourth transistor T4 and the data signal terminal. Each column of pixel driving circuit can be provided with a corresponding power line VDD. The power line VDD can be connected to the first bridge part 41 through a via to connect the first power supply terminal and the second electrode of the capacitor C and the first electrode of the fifth transistor T5. In this exemplary embodiment, the power line VDD may include a first power line segment VDD1, a second power line segment VDD2, and a third power line segment VDD3. The second power line segment VDD2 is connected between the first power line segment VDD1 and the third power line segment VDD3. The size of the orthographic projection of the second power line segment VDD2 on the substrate in the first direction X may be larger than the size of the orthographic projection of the first power line segment VDD1 on the substrate in the first direction X, and the size of the orthographic projection of the second power line segment VDD2 on the substrate in the first direction X may be larger than the size of the orthographic projection of the third power line segment VDD3 on the substrate in the first direction X. Furthermore, the orthographic projection of the second power line segment VDD2 on the substrate may also cover the orthographic projection of the eighth active part 88 on the substrate, and the second power line segment VDD2 can reduce the influence of light on the characteristics of the eighth transistor T8. Furthermore, the orthogonal projection of the power line VDD onto the substrate can also cover the orthogonal projections of the twentieth active section 820 and the fourth bridge section 44 onto the substrate. The power line VDD can be used to shield the twentieth active section 820 and the fourth bridge section 44 from noise interference from other signals, thereby improving the stability of the gate voltage of the driving transistor T3. The tenth bridge section 510 can be connected to the sixth bridge section 46 via a via to connect to the second terminal of the sixth transistor T6.

[0076] like Figure 3 , 11 As shown in Figure 19, in this exemplary embodiment, adjacent second power supply segments VDD2 can be interconnected within the same repeating unit. The power supply line VDD and the second conductive portion 22 connected in the first direction X can form a grid structure. The power supply lines of this grid structure have low resistance, thereby reducing the voltage difference between the first power supply terminals at different locations on the display panel and improving the uniformity of the display panel display.

[0077] like Figure 3 , 12 As shown in Figures 20, 21, and 22, Figure 20 This is a structural layout of the fifth conductive layer and electrode layer in an exemplary embodiment of the display panel disclosed herein. Figure 21 for Figure 20 Schematic diagram of the fifth conductive layer. Figure 22 for Figure 20 The structural layout of the middle electrode layer. In this exemplary embodiment, the electrode layer may include multiple electrode portions: a first electrode portion R, a third electrode portion G, and a second electrode portion B. Each electrode portion can be connected to the tenth bridge portion 510 via a via to connect to the second electrode of the sixth transistor T6. The first electrode portion R can be used to form the first electrode of a red light-emitting unit, the second electrode portion B can be used to form the first electrode of a blue light-emitting unit, and the third electrode portion G can be used to form the first electrode of a green light-emitting unit. The multiple electrode portions are arrayed along a first direction X and a second direction Y. The multiple electrode portions distributed along the first direction X form an electrode row, and the multiple electrode portions distributed along the second direction Y form an electrode column. In the same electrode row, the first electrode portion R, the third electrode portion G, the second electrode portion B, and the third electrode portion G are sequentially and alternately distributed along the first direction X. Multiple electrode rows include sequentially adjacent first electrode rows ROW1, second electrode rows ROW2, third electrode rows ROW3, ​​and fourth electrode rows ROW4. First electrode row ROW1 includes first electrode portions R and second electrode portions B alternately distributed in the second direction Y. Second electrode row ROW2 includes multiple third electrode portions G distributed in the second direction Y. Third electrode row ROW3 includes second electrode portions B and first electrode portions R alternately distributed in the second direction Y. Fourth electrode row ROW4 includes multiple third electrode portions G distributed in the second direction Y. The minimum distance K1 between the orthogonal projections of two third electrode portions G located in adjacent electrode rows of the same electrode row on the substrate in the second direction Y is greater than the size K2 of the orthogonal projection of the first electrode portion R on the substrate in the second direction Y, or greater than the size K3 of the orthogonal projection of the second electrode portion B on the substrate in the second direction Y. In this configuration, the orthographic projection of the first electrode portion R on the substrate coincides with the orthographic projection of its corresponding opening on the substrate on the pixel definition layer; the orthographic projection of the second electrode portion B on the substrate coincides with the orthographic projection of its corresponding opening on the substrate on the pixel definition layer; and the orthographic projection of the third electrode portion G on the substrate coincides with the orthographic projection of its corresponding opening on the substrate on the pixel definition layer.

[0078] like Figure 20 , 21As shown in Figure 22, the area of ​​the orthographic projection of the first electrode portion R onto the substrate is larger than the area of ​​the orthographic projection of the third electrode portion G onto the substrate, but smaller than the area of ​​the orthographic projection of the second electrode portion B onto the substrate. In the same repeating unit, two connected second power supply segments VDD2 form a power supply portion. The plurality of power supply portions include: a first power supply portion Vx1 corresponding to the first electrode portion R, and a second power supply portion Vx2 corresponding to the second electrode portion B. The orthographic projections of the first electrode portion R onto the substrate and the corresponding first power supply portion Vx1 onto the substrate at least partially overlap, and the orthographic projections of the second electrode portion B onto the substrate and the corresponding second power supply portion Vx2 onto the substrate at least partially overlap.

[0079] like Figure 20 , 21 As shown in Figure 22, the overlapping area of ​​the orthographic projection of the first electrode portion R on the substrate and the orthographic projection of its corresponding first power supply portion Vx1 on the substrate is B1, and the area of ​​the orthographic projection of the first electrode portion R on the substrate is B2. B1 / B2 can be greater than or equal to 80%, for example, B1 / B2 can be equal to 80%, 90%, 95%, or 100%. When B1 / B2 equals 100%, the orthographic projection of the first electrode portion R on the substrate lies on the orthographic projection of its corresponding first power supply portion Vx1 on the substrate. The overlapping area of ​​the orthographic projection of the second electrode portion B on the substrate and the orthographic projection of its corresponding second power supply portion Vx2 on the substrate is C1, and the area of ​​the orthographic projection of the second electrode portion B on the substrate is C2. C1 / C2 can be greater than or equal to 80%, for example, C1 / C2 can be equal to 80%, 90%, 95%, or 100%. When C1 / C2 equals 100%, the orthogonal projection of the second electrode part B on the substrate is located on the orthogonal projection of the corresponding second power supply part Vx2 on the substrate.

[0080] like Figure 20 , 21As shown in Figure 22, the area of ​​the orthographic projection of the first power supply unit Vx1 corresponding to the first electrode unit R onto the substrate is A1, and the area of ​​the orthographic projection of the second power supply unit Vx2 corresponding to the second electrode unit B onto the substrate is A2, wherein A2 is greater than A1. In this exemplary embodiment, by increasing the area of ​​the second power supply unit Vx2 on the substrate, the orthographic projection of all or most of the structure of the second electrode unit B onto the substrate can be located on the orthographic projection of the second power supply unit Vx2 onto the substrate, thereby improving the flatness of the second electrode unit B and reducing the risk of color shift in the display panel at different viewing angles. In this exemplary embodiment, the overlapping area of ​​the orthographic projection of the second power supply unit Vx2 onto the substrate and the orthographic projection of the corresponding second electrode unit B onto the substrate can be greater than the overlapping area of ​​the orthographic projection of the first power supply unit Vx1 onto the substrate and the orthographic projection of the corresponding first electrode unit R onto the substrate.

[0081] like Figure 20 , 21 As shown in Figure 22, the second power supply unit Vx2 may include a main body Vx21 and two additional parts Vx22, which may be respectively connected to both sides of the main body Vx21 in the second direction Y. The main body Vx21 includes a first side Vx211 on one side of the second direction Y, and the additional parts Vx22 include a second side Vx222 connected to the first side Vx211. The angle between the orthographic projection of the first side Vx211 on the substrate and the orthographic projection of the second side Vx222 on the substrate may be less than 180°.

[0082] It should be noted that, as Figure 3 , 18 As shown in Figures 19 and 20, the black squares drawn on the side of the fourth conductive layer facing away from the substrate represent vias connecting the fourth conductive layer to other layers facing the substrate; the black squares drawn on the side of the fifth conductive layer facing away from the substrate represent vias connecting the fifth conductive layer to other layers facing the substrate; and the black squares drawn on the side of the electrode layer facing away from the substrate represent vias connecting the electrode layer to other layers facing the substrate. These black squares only indicate the location of the vias; different vias represented by black squares at different locations can penetrate different insulating layers.

[0083] like Figure 23 As shown, Figure 3The diagram shows a partial cross-sectional view of the display panel taken along the dashed line AA. The display panel may further include a first insulating layer 91, a second insulating layer 92, a third insulating layer 93, a fourth insulating layer 94, a fifth insulating layer 95, a first dielectric layer 96, a passivation layer 97, a first planarization layer 98, and a second planarization layer 99, wherein the substrate 90, the shielding layer, the first insulating layer 91, the first active layer, the second insulating layer 92, the first conductive layer, the third insulating layer 93, the second conductive layer, the fourth insulating layer 94, the second active layer, the fifth insulating layer 95, the third conductive layer, the first dielectric layer 96, the fourth conductive layer, the passivation layer 97, the first planarization layer 98, the fifth conductive layer, the second planarization layer 99, and the electrode layer are sequentially stacked. The first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be single-layer or multi-layer structures, and the materials of the first insulating layer 91, the second insulating layer 92, the third insulating layer 93, the fourth insulating layer 94, and the fifth insulating layer 95 can be at least one of silicon nitride, silicon oxide, and silicon oxynitride; the first dielectric layer 96 can be a silicon nitride layer; the materials of the first planarization layer 98 and the second planarization layer 99 can be organic materials, such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), silicon-glass bonded structure (SOG), etc. The substrate 90 can include a glass substrate, a barrier layer, and a polyimide layer stacked sequentially, and the barrier layer can be an inorganic material. The passivation layer 97 can be a silicon oxide layer. The materials of the first conductive layer, the second conductive layer, and the third conductive layer can be one of molybdenum, aluminum, copper, titanium, niobium, or an alloy thereof, or a molybdenum / titanium alloy, or a stack thereof. The materials of the fourth and fifth conductive layers can include metallic materials, such as molybdenum, aluminum, copper, titanium, niobium, or alloys thereof, or molybdenum / titanium alloys or stacks, or titanium / aluminum / titanium stacks. The electrode layers can include indium tin oxide layers or silver layers. The sheet resistance of any one of the first, second, and third conductive layers can be greater than the sheet resistance of any one of the fourth and fifth conductive layers.

[0084] It should be noted that the scale of the accompanying drawings in this disclosure can be used as a reference in actual processes, but is not limited thereto. For example, the aspect ratio of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the quantities shown in the figures. The accompanying drawings described in this disclosure are only schematic diagrams of the structure. In addition, the terms "first," "second," etc., are only used to define different structural names and do not have a specific order meaning. In this exemplary embodiment, the orthographic projection of a certain structure on the substrate extends along a certain direction, which can be understood as the orthographic projection of the structure on the substrate extending in a straight line or bending along that direction. A transistor is a device that includes at least three terminals: a gate, a drain, and a source. A transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the drain, the channel region, and the source. In this exemplary embodiment, the channel region refers to the region through which current mainly flows. In this exemplary embodiment, the first electrode can be the drain and the second electrode can be the source, or vice versa. When using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source" and "drain" are sometimes interchanged. Therefore, in this exemplary embodiment, the "source" and "drain" can be interchanged. Additionally, the gate can also be referred to as the control electrode.

[0085] like Figure 24 As shown, Figure 1 The diagram shows the timing diagram of signals at each node in another driving method of the pixel driving circuit shown. Here, EM represents the timing diagram of the signals at the enable signal terminal; G1 represents the timing diagram of the signals at the first gate drive signal terminal; G2 represents the timing diagram of the signals at the second gate drive signal terminal; Re1 represents the timing diagram of the signals at the first reset signal terminal; and Re2 represents the timing diagram of the signals at the second reset signal terminal. This driving method is similar to... Figure 2 The driving method shown may differ only in the timing of the signals at the first reset signal terminal. In this exemplary embodiment, the first reset signal terminal and the second reset signal terminal may be provided with signals by different gate drive circuits. The first reset signal terminal may output a low-level signal only during the reset phase t2.

[0086] like Figure 25-26 As shown, Figure 25 This is a partial structural layout diagram of another exemplary embodiment of the display panel disclosed herein. The display panel is related to… Figure 3 The display panels shown may differ only in the second conductive layer. Figure 26 for Figure 25The diagram shows the structural layout of the second conductive layer in the display panel. This second conductive layer may further include a coupling portion 25, whose orthographic projection on the substrate and the orthographic projection of the first gate line G1 on the substrate at least partially overlap. The twentieth active portion 820 can be connected to the coupling portion 25 via vias. Since the twentieth active portion 820 is an equipotential structure for the gate of the driving transistor T3, at the end of the data writing phase, the first gate line G1 can pull up the voltage of the driving transistor gate through the coupling portion 25. This setting can reduce the black state voltage of the display panel, or reduce the area of ​​the orthographic projection of the twentieth active portion 820 on the substrate while keeping the black state voltage constant.

[0087] This exemplary embodiment also provides a display device, which includes the display panel described above. The display device can be a mobile phone, tablet computer, television, or other display device.

[0088] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.

[0089] The accompanying drawings in this disclosure only illustrate the structures involved in this disclosure; other structures can be referred to with common design. Unless otherwise specified, the embodiments and features described in these embodiments can be combined to obtain new embodiments. Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of this disclosure without departing from the spirit and scope of this disclosure, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

[0090] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.

Claims

1. A display panel, wherein, The display panel includes: Substrate; A pixel driving circuit is located on one side of the substrate, and the pixel driving circuit includes: Drive transistors; The ninth transistor, wherein the first terminal of the ninth transistor is connected to the third initial signal line, and the second terminal of the ninth transistor is connected to the first terminal of the driving transistor; The eighth transistor, wherein the first terminal of the eighth transistor is connected to the gate of the driving transistor; A first transistor, wherein the first terminal of the first transistor is connected to a first initial signal line, and the second terminal of the first transistor is connected to the second terminal of the eighth transistor; The second transistor has its first terminal connected to the second terminal of the eighth transistor, and its second terminal connected to the second terminal of the driving transistor. The display panel further includes a light-emitting unit, and the pixel driving circuit is connected to the first electrode of the light-emitting unit. The pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to a second initial signal line, and the second electrode of which is connected to the first electrode of the light-emitting unit. The display panel also includes: The third conductive layer is located on one side of the substrate. A fourth conductive layer is located on the side of the third conductive layer away from the substrate. The fourth conductive layer includes the second initial signal line, which includes a first sub-initial signal line and a second sub-initial signal line. The first sub-initial signal line extends along a first direction in its orthogonal projection onto the substrate, and the second sub-initial signal line extends along a second direction in its orthogonal projection onto the substrate, wherein the first direction and the second direction intersect. The orthographic projection of the first initial signal line on the substrate at least partially overlaps with the orthographic projection of the third initial signal line on the substrate; The second sub-initial signal line is connected to the first sub-initial signal line that intersects with it; The display panel also includes a power line, and the orthographic projection of the second sub-initial signal line on the substrate and the orthographic projection of the power line on the substrate at least partially overlap.

2. The display panel according to claim 1, wherein, The display panel also includes: A first active layer is located on one side of the substrate. The first active layer includes a second active portion and a third active portion. The second active portion is used to form the channel region of the second transistor, and the third active portion is used to form the channel region of the driving transistor. A first conductive layer is located on the side of the first active layer away from the substrate. The first conductive layer includes a first gate line and a first conductive portion. The orthographic projection of the first gate line on the substrate extends along a first direction and covers the orthographic projection of the second active portion on the substrate. A portion of the structure of the first gate line is used to form the gate of the second transistor. The orthographic projection of the first conductive portion on the substrate covers the orthographic projection of the third active portion on the substrate. The first conductive portion is used to form the gate of the driving transistor. The second active layer is located on the side of the first conductive layer away from the substrate. The second active layer includes an eighth active portion, which is used to form the channel region of the eighth transistor. A third conductive layer is located on the side of the second active layer away from the substrate. The third conductive layer includes a second gate line. The orthographic projection of the second gate line on the substrate extends along the first direction and covers the orthographic projection of the eighth active portion on the substrate. A portion of the structure of the second gate line is used to form the top gate of the eighth transistor. Wherein, the orthographic projection of the first gate line on the substrate is located between the orthographic projection of the second gate line on the substrate and the orthographic projection of the first conductive portion on the substrate.

3. The display panel according to claim 2, wherein, The second active part further includes a twentieth active part connected to the eighth active part, and the twentieth active part is connected to the first conductive part; The projection of the twentieth active portion onto the substrate and the orthographic projection of the first gate line onto the substrate at least partially overlap.

4. The display panel according to claim 3, wherein, The size of the orthographic projection of the twentieth active portion onto the substrate in the first direction is greater than the size of the orthographic projection of the twentieth active portion onto the substrate in the second direction; The first direction and the second direction intersect.

5. The display panel according to claim 3, wherein, The orthographic projection of the eighth active part onto the substrate in the first direction has a size of L1, and the orthographic projection of the twentieth active part onto the substrate in the first direction has a size of L2. Among them, L2 / L1 is greater than or equal to 2 and less than or equal to 7.

6. The display panel according to claim 1, wherein, The pixel driving circuit further includes: a fourth transistor, wherein the first terminal of the fourth transistor is connected to a data line, and the second terminal of the fourth transistor is connected to the first terminal of the driving transistor; The display panel also includes: A first active layer, comprising a second active portion and a fourth active portion, wherein the second active portion is used to form the channel region of the second transistor, and the fourth active portion is used to form the channel region of the fourth transistor; The second active layer is located on the side of the first active layer away from the substrate. The second active layer includes an eighth active portion, which is used to form the channel region of the eighth transistor. In the first direction, the orthographic projection of the eighth active part on the substrate is located between the orthographic projection of the second active part on the substrate and the orthographic projection of the fourth active part on the substrate.

7. The display panel according to claim 1, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit is connected to the first electrode of the light-emitting unit. The pixel driving circuit further includes a seventh transistor, the first electrode of the seventh transistor is connected to a second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit. The display panel also includes: A first active layer is located on one side of the substrate. The first active layer includes a seventh active portion and a ninth active portion. The seventh active portion is used to form the channel region of the seventh transistor, and the ninth active portion is used to form the channel region of the ninth transistor. A first conductive layer is located on the side of the first active layer away from the substrate. The first conductive layer includes a second reset signal line. The orthographic projection of the second reset signal line on the substrate extends along a first direction and covers the orthographic projection of the seventh active portion on the substrate and the orthographic projection of the ninth active portion on the substrate. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor, and a portion of the structure of the second reset signal line is used to form the gate of the ninth transistor.

8. The display panel according to claim 7, wherein, The first active layer further includes: The first active portion is used to form the channel region of the first transistor; The first conductive layer further includes: A first reset signal line, wherein the orthographic projection of the first reset signal line on the substrate covers the orthographic projection of the first active portion on the substrate, and a portion of the structure of the first reset signal line is used to form the gate of the first transistor; A first conductive portion, wherein the first conductive portion is used to form the gate of the driving transistor; In the same pixel driving circuit, the orthographic projection of the first conductive part on the substrate is located between the orthographic projection of the first reset signal line on the substrate and the orthographic projection of the second reset signal line on the substrate. The second reset signal line in the pixel driving circuit of this row is shared as the first reset signal line in the pixel driving circuit of the adjacent next row.

9. The display panel according to claim 1, wherein, The display panel also includes: A first conductive layer is located on one side of the substrate. The first conductive layer includes a first reset signal line and a first conductive portion. A portion of the structure of the first reset signal line is used to form the gate of the first transistor, and the first conductive portion is used to form the gate of the driving transistor. The second conductive layer is located on the side of the first conductive layer away from the substrate, and the second conductive layer includes the third initial signal line; A third conductive layer is located on the side of the second conductive layer away from the substrate. The third conductive layer includes a second gate line, and a portion of the structure of the second gate line is used to form the top gate of the eighth transistor. In the same pixel driving circuit, the orthographic projection of the first reset signal line on the substrate is located on the side where the orthographic projection of the second gate line on the substrate is away from the orthographic projection of the first conductive part on the substrate. The orthographic projection of the third initial signal line in the adjacent previous row pixel driving circuit onto the substrate is located between the orthographic projection of the first reset signal line in the current row pixel driving circuit onto the substrate and the orthographic projection of the second gate line in the current row pixel driving circuit onto the substrate.

10. The display panel according to claim 1, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit is connected to the first electrode of the light-emitting unit. The pixel driving circuit further includes a seventh transistor, the first electrode of which is connected to a second initial signal line, and the second electrode of which is connected to the first electrode of the light-emitting unit. The display panel also includes: A first conductive layer is located on one side of the substrate. The first conductive layer includes a first conductive portion, a second reset signal line, and a first gate line. The first conductive portion is used to form the gate of the driving transistor. A portion of the structure of the second reset signal line is used to form the gate of the seventh transistor. A portion of the structure of the first gate line is used to form the gate of the second transistor. A third conductive layer is located on the side of the first conductive layer away from the substrate, and the third conductive layer includes the first initial signal line; In the same pixel driving circuit, the orthographic projection of the second reset signal line on the substrate is located on the side where the orthographic projection of the first conductive part on the substrate is away from the orthographic projection of the first gate line on the substrate. The orthographic projection of the first initial signal line in the adjacent next row pixel driving circuit onto the substrate is located between the orthographic projection of the second reset signal line in the current row pixel driving circuit onto the substrate and the orthographic projection of the first conductive part in the current row pixel driving circuit onto the substrate.

11. The display panel according to claim 1, wherein, The pixel driving circuit further includes a fifth transistor, the first terminal of which is connected to a power supply line, and the second terminal of which is connected to the first terminal of the driving transistor. The display panel also includes: A first active layer is located on one side of the substrate. The first active layer includes a fifth active portion, which is used to form the channel region of the fifth transistor. A first conductive layer is located on the side of the first active layer away from the substrate. The first conductive layer includes an enable signal line. The orthographic projection of the enable signal line on the substrate extends along a first direction and covers the orthographic projection of the fifth active portion on the substrate. A portion of the structure of the enable signal line is used to form the gate of the fifth transistor. A third conductive layer is located on the side of the first conductive layer away from the substrate, and the third conductive layer includes the first initial signal line; Wherein, the orthographic projection of the first initial signal line in the adjacent next row pixel driving circuit onto the substrate and the orthographic projection of the enable signal line in the current row pixel driving circuit onto the substrate at least partially overlap.

12. The display panel according to claim 11, wherein, In the first unit pixel, the area of ​​the orthogonal projection of the first initial signal line in the adjacent next row pixel driving circuit on the substrate is S1; In the first unit pixel, the overlapping area of ​​the orthographic projection of the first initial signal line in the adjacent next row pixel driving circuit on the substrate and the orthographic projection of the enable signal line in the current row pixel driving circuit on the substrate is S2. Among them, S2 / S1 is greater than or equal to 60%.

13. The display panel according to claim 1, wherein, In the second unit pixel, the area of ​​the orthographic projection of the first sub-initial signal line on the substrate is S3, the overlapping area of ​​the orthographic projection of the first sub-initial signal line on the substrate and the orthographic projection of the third initial signal line on the substrate is S4, and S4 / S3 is greater than or equal to 50%.

14. The display panel according to claim 1, wherein, The display panel includes a plurality of repeating units distributed in an array along the first direction and the second direction. Each repeating unit includes two pixel driving circuits distributed along the first direction. The two pixel driving circuits in the same repeating unit are mirror-symmetrically arranged along a mirror symmetry plane. The plurality of repeating units distributed in the second direction form a repeating unit column, at least a portion of the repeating unit column is provided with a second sub-initial signal line, and the orthographic projection of the mirror symmetry plane on the substrate is located on the orthographic projection of the second sub-initial signal line on the substrate.

15. The display panel according to claim 1, wherein, The display panel includes a plurality of repeating units arranged in an array along a first direction and a second direction. Each repeating unit includes two pixel driving circuits arranged along the first direction. The two pixel driving circuits in the same repeating unit are mirror-symmetrically arranged along a mirror symmetry plane. The first direction and the second direction intersect. The pixel driving circuit further includes a fifth transistor, the first terminal of which is connected to a power supply line, and the second terminal of which is connected to the first terminal of the driving transistor. The display panel also includes: The first active layer includes a third active portion, a fifth active portion, and a thirteenth active portion. The third active portion is used to form the channel region of the driving transistor, the fifth active portion is used to form the channel region of the fifth transistor, and the thirteenth active portion is connected to the side of the fifth active portion away from the third active portion. In the adjacent repeating units in the first direction, the fifth active units in the two adjacent pixel driving circuits are connected through the same thirteenth active unit, and the thirteenth active unit is connected to the power line.

16. The display panel according to claim 1, wherein, The display panel includes a plurality of repeating units arranged in an array along a first direction and a second direction. Each repeating unit includes two pixel driving circuits arranged along the first direction. The two pixel driving circuits in the same repeating unit are mirror-symmetrically arranged along a mirror symmetry plane. The first direction and the second direction intersect. The display panel further includes a light-emitting unit, and the pixel driving circuit is connected to the first electrode of the light-emitting unit. The pixel driving circuit further includes a sixth transistor and a seventh transistor. The first electrode of the sixth transistor is connected to the second electrode of the driving transistor, and the second electrode of the sixth transistor is connected to the first electrode of the light-emitting unit. The first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit. The display panel also includes: The first active layer includes a sixth active portion, a seventh active portion, and a seventeenth active portion. The sixth active portion is used to form the channel region of the sixth transistor, the seventh active portion is used to form the channel region of the seventh transistor, and the seventeenth active portion is connected to the side of the seventh active portion away from the sixth active portion. In the same repeating unit, the seventh active units in two adjacent pixel driving circuits are connected through the same seventeenth active unit, which is connected to the second initial signal line.

17. The display panel according to claim 1, wherein, The display panel also includes: A fourth conductive layer is located on one side of the substrate. A fifth conductive layer is located on the side of the fourth conductive layer opposite to the substrate. The fifth conductive layer includes power lines, and the orthographic projection of the power lines on the substrate extends along a second direction. The power line includes a first power line segment, a second power line segment, and a third power line segment. The second power line segment is connected between the first power line segment and the third power line segment. In the same repeating unit, two adjacent second power line segments are connected to each other. The connected second power line segments form a power supply section. The plurality of power supply sections include a first power supply section and a second power supply section. An electrode layer is located on the side of the fifth conductive layer opposite to the substrate. The electrode layer includes a plurality of electrode portions, among which a first electrode portion and a second electrode portion are included. The orthographic projection of the first electrode portion on the substrate is smaller than the orthographic projection of the second electrode portion on the substrate. A pixel definition layer is located on the side of the electrode layer opposite to the substrate. The pixel definition layer has a plurality of openings for forming light-emitting units. The openings are correspondingly disposed with the electrode portions. The orthographic projection of the openings on the substrate coincides with the orthographic projection of the corresponding electrode portions on the substrate. The first electrode portion and the first power supply portion are respectively disposed in the same manner, and the second electrode portion and the second power supply portion are respectively disposed in the same manner. The orthographic projection of the first electrode portion on the substrate and the orthographic projection of the corresponding first power supply portion on the substrate overlap at least partially, and the orthographic projection of the second electrode portion on the substrate and the orthographic projection of the corresponding second power supply portion on the substrate overlap at least partially. The area of ​​the orthographic projection of the second power supply unit on the substrate is larger than the area of ​​the orthographic projection of the first power supply unit on the substrate, and the overlapping area of ​​the orthographic projection of the second power supply unit on the substrate and the orthographic projection of the corresponding second electrode unit on the substrate is larger than the overlapping area of ​​the orthographic projection of the first power supply unit on the substrate and the orthographic projection of the corresponding first electrode unit on the substrate.

18. The display panel according to claim 1, wherein, The display panel further includes a light-emitting unit, and the pixel driving circuit further includes: A fourth transistor, wherein the first terminal of the fourth transistor is connected to the data line, and the second terminal of the fourth transistor is connected to the first terminal of the driving transistor; The fifth transistor has its first terminal connected to the power supply line and its second terminal connected to the first terminal of the driving transistor. A sixth transistor, wherein the first terminal of the sixth transistor is connected to the second terminal of the driving transistor, and the second terminal of the sixth transistor is connected to the first electrode of the light-emitting unit; A seventh transistor, wherein the first electrode of the seventh transistor is connected to the second initial signal line, and the second electrode of the seventh transistor is connected to the first electrode of the light-emitting unit; The first transistor, the second transistor, the driving transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the ninth transistor are P-type transistors, and the eighth transistor is an N-type transistor.

19. A display device, wherein, Includes the display panel as described in any one of claims 1-18.

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