A digital nuclear pulse signal processor employing a neural network processor architecture

Abstract

The application discloses a digital nuclear pulse signal processor adopting a neural network processor architecture, and relates to the field of radiation detection.The digital nuclear pulse signal processor comprises a radiation detector, a conversion circuit and an FPGA circuit and a SoC circuit.The radiation detector is used for receiving radiation rays and converting the radiation rays into voltage pulse signals.The conversion circuit is used for converting the voltage pulse signals into digital signals.The FPGA circuit is used for extracting pulse waveform data in the digital signals and sending the pulse waveform data to the SoC circuit, receiving a data channel control signal and result data returned by the SoC circuit, selecting target data from the pulse waveform data and the result data, extracting amplitude information and time information of the target data, and transmitting the amplitude information and the time information to the SoC circuit.The result data is pulse waveform data after filtering and noise reduction.The SoC circuit receives the pulse waveform data, the amplitude information and the time information, applies a neural network model loaded by an NPU processor, obtains the result data, determines position information of the radiation rays and corresponding case information, and can realize real-time online processing and analysis of nuclear pulse signals.

Description

Technical Field

[0001] This invention relates to the field of radiation detection, and in particular to a digital nuclear pulse signal processor employing a neural network processor architecture. Background Technology

[0002] In the field of radiation detection, real-time online processing and analysis of nuclear pulse signals is of great significance. Due to the varying objectives of nuclear physics experiments and the different applications of nuclear technology, embedded devices with different functions are often required at the detector backend. These include multichannel analyzers for extracting pulse signal amplitude information for recording and displaying the energy spectrum; pulse width analyzers for measuring the pulse signal width, i.e., pulse duration; and digital storage oscilloscopes for capturing and storing waveform data of high-speed pulse signals. Therefore, it is necessary to develop a high-performance, versatile digital pulse processor capable of comprehensively measuring radiation physics parameters and even fulfilling some complex measurement requirements for different applications.

[0003] With the development of computer technology, artificial neural network technology has been applied to various industries, driving their progress. The rapidly developing SoC (System-on-a-Chip) with neural network processors (NPUs) represents a future trend in artificial neural network technology. Deploying artificial neural network models in embedded systems to process data online in real time is a key development direction. Currently, the method of deploying artificial neural network models in embedded devices for online data processing is mainly used in image processing. No relevant literature on this method has been found in the field of nuclear physics. Therefore, applying this technology to nuclear physics and developing a digital nuclear pulse signal processor based on a neural network processor architecture, using an artificial neural network model deployed in the NPU to process and analyze pulse signals from nuclear physics experiments, is highly significant for the development of nuclear technology. Summary of the Invention

[0004] The purpose of this invention is to provide a digital nuclear pulse signal processor that employs a neural network processor architecture, capable of processing and analyzing nuclear pulse signals in real time online.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A digital nuclear pulse signal processor employing a neural network processor architecture, the processor comprising: a SoC circuit, an FPGA circuit, a radiation detector, and a conversion circuit;

[0007] The radiation detector is used to receive radiation rays and convert the energy of the radiation rays into voltage pulse signals;

[0008] The conversion circuit is connected to the radiation detector; the conversion circuit is used to convert the voltage pulse signal into a digital signal;

[0009] The FPGA circuit is connected to the conversion circuit and the SoC circuit respectively; the FPGA circuit is used to extract pulse waveform data from the digital signal and send the pulse waveform data to the SoC circuit, as well as receive data channel control signals and result data returned by the SoC circuit, select target data from the pulse waveform data and the result data according to the data channel control signals, extract the amplitude information and time information of the target data, and transmit the amplitude information and time information to the SoC circuit.

[0010] The SoC circuit includes an NPU processor; the SoC circuit is used to receive the pulse waveform data, the amplitude information, and the time information, and apply a first neural network model loaded by the NPU processor to filter the pulse waveform data to obtain result data, and apply a second neural network model loaded by the NPU processor to determine the position information of the radiation ray from the result data, and apply a third neural network model loaded by the NPU processor to determine the event information corresponding to the radiation ray based on the result data, and store the position information, the event information, the amplitude information, and the time information.

[0011] Optionally, the conversion circuit includes an analog front-end circuit and an ADC conversion circuit;

[0012] The analog front-end circuit is connected to the radiation detector; the analog front-end circuit is used to filter, amplify, and adjust the bias of the voltage pulse signal to obtain a processed analog signal.

[0013] The ADC conversion circuit is connected to the analog front-end circuit; the ADC conversion circuit is used to convert the processed analog signal into a digital signal.

[0014] Optionally, the FPGA circuit includes a data splicing module, a waveform extraction module, a selection module, and a digital algorithm module;

[0015] The splicing module is connected to the ADC conversion circuit; the splicing module is used to splice the digital signal into data with a length of sixteen bits to obtain spliced ​​data;

[0016] The waveform extraction module is connected to the data splicing module and the SoC circuit respectively; the waveform extraction module is used to extract the pulse waveform data from the spliced ​​data and transmit the pulse waveform data to the SoC circuit.

[0017] The selection module is connected to the SoC circuit and the waveform extraction module respectively; the selection module receives the data channel control signal and the result data returned by the SoC circuit, and selects target data from the pulse waveform data and the result data according to the data channel control signal.

[0018] The digital algorithm module is connected to the selection module; the digital algorithm module is used to extract the amplitude information and time information of the target data, and transmit the amplitude information and time information to the SoC circuit.

[0019] Optionally, the FPGA circuit further includes an output interface;

[0020] The output interface is connected to the digital algorithm module; the output interface is used to output the amplitude information and time information of the target data.

[0021] Optionally, the output interface is a USB 3.0 interface.

[0022] Optionally, the SoC circuit may further include a CPU processor;

[0023] The CPU processor is connected to the NPU processor and the FPGA circuit respectively; the CPU processor is used to transmit the result data to the FPGA circuit, receive the amplitude information and the time information, as well as receive the location information and the event information, and store the location information, the event information, the amplitude information and the time information.

[0024] Optionally, the SoC circuit further includes an output module;

[0025] The output module is connected to the CPU processor; the output module is used to output the position information, the event information, the amplitude information, and the time information.

[0026] Optionally, the output module includes an Ethernet interface and a USB 3.0 interface; the Ethernet interface and the USB 3.0 interface are respectively connected to the CPU processor.

[0027] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0028] The digital core pulse signal processor with a neural network processor architecture proposed in this invention includes: a SoC circuit, an FPGA circuit, a radiation detector, and a conversion circuit; the radiation detector receives radiation rays and converts the energy of the radiation rays into voltage pulse signals; the conversion circuit is connected to the radiation detector; the conversion circuit converts the voltage pulse signals into digital signals; the FPGA circuit is connected to both the conversion circuit and the SoC circuit; the FPGA circuit extracts pulse waveform data from the digital signals and sends the pulse waveform data to the SoC circuit, and receives data channel control signals and result data returned by the SoC circuit; according to the data channel control signals, target data is selected from the pulse waveform data and result data, and the amplitude and time information of the target data are extracted and transmitted to the SoC circuit; finally, the SoC circuit includes an NPU processor; the SoC circuit receives pulse waveform data, amplitude information, and time information, and applies a first neural network model loaded by the NPU processor to filter the pulse waveform data to obtain result data; a second neural network model loaded by the NPU processor determines the position information of the radiation rays from the result data; a third neural network model loaded by the NPU processor determines the event information corresponding to the radiation rays based on the result data; and the position information, event information, amplitude information, and time information are stored. This invention enables real-time online processing and analysis of nuclear pulse signals through SoC circuitry, thereby obtaining real-time information on the location, event, amplitude, and time of radiation rays. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0030] Figure 1 This is a block diagram of the hardware architecture of the nuclear pulse signal processor of the present invention;

[0031] Figure 2 This is a block diagram of the hardware architecture of the core pulse signal processor when the data selector of the present invention selects waveform data 1;

[0032] Figure 3 This is a block diagram of the hardware architecture of the core pulse signal processor when the data selector of the present invention selects waveform data 2;

[0033] Figure 4 This is a schematic diagram illustrating a convolutional neural network (CNN) model of the present invention that predicts event types based on a sequence of pulse signals;

[0034] Figure 5 This is a schematic diagram of the white noise suppression and baseline recovery process of the present invention;

[0035] Figure 6 This is a schematic diagram of the low-frequency noise suppression process of the present invention;

[0036] Figure 7 This is a schematic diagram of the instantaneous noise suppression process of the present invention;

[0037] Figure 8 This is a schematic diagram of the stacked pulse recovery process of the present invention. Detailed Implementation

[0038] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] The purpose of this invention is to provide a digital nuclear pulse signal processor that employs a neural network processor architecture, capable of processing and analyzing nuclear pulse signals in real time online.

[0040] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Example 1

[0042] like Figure 1 As shown, the present invention provides a digital core pulse signal processor employing a neural network processor architecture, the processor comprising: a SoC circuit, an FPGA circuit, a radiation detector, and a conversion circuit.

[0043] The radiation detector is used to receive radiation rays and convert the energy of the radiation rays into voltage pulse signals.

[0044] The conversion circuit is connected to the radiation detector; the conversion circuit is used to convert the voltage pulse signal into a digital signal.

[0045] The FPGA circuit is connected to the conversion circuit and the SoC circuit respectively. The FPGA circuit is used to extract pulse waveform data from the digital signal and send the pulse waveform data to the SoC circuit, as well as receive data channel control signals and result data returned by the SoC circuit. According to the data channel control signals, the FPGA circuit selects target data from the pulse waveform data and the result data, extracts the amplitude information and time information of the target data, and transmits the amplitude information and time information to the SoC circuit.

[0046] The SoC circuit includes an NPU processor; the SoC circuit is used to receive the pulse waveform data, the amplitude information, and the time information, and apply a first neural network model loaded by the NPU processor to filter the pulse waveform data to obtain result data, and apply a second neural network model loaded by the NPU processor to determine the position information of the radiation ray from the result data, and apply a third neural network model loaded by the NPU processor to determine the event information corresponding to the radiation ray based on the result data, and store the position information, the event information, the amplitude information, and the time information.

[0047] Specifically, the conversion circuit includes an analog front-end circuit and an ADC conversion circuit.

[0048] The analog front-end circuit is connected to the radiation detector; the analog front-end circuit is used to filter, amplify and bias the voltage pulse signal to obtain a processed analog signal.

[0049] The ADC conversion circuit is connected to the analog front-end circuit; the ADC conversion circuit is used to convert the processed analog signal into a digital signal.

[0050] Specifically, the FPGA circuit includes a data splicing module, a waveform extraction module, a selection module, and a digital algorithm module.

[0051] The splicing module is connected to the ADC conversion circuit; the splicing module is used to splice the digital signal into data with a length of sixteen bits to obtain spliced ​​data.

[0052] The waveform extraction module is connected to the data splicing module and the SoC circuit respectively; the waveform extraction module is used to extract the pulse waveform data from the spliced ​​data and transmit the pulse waveform data to the SoC circuit.

[0053] The selection module is connected to the SoC circuit and the waveform extraction module respectively; the selection module receives the data channel control signal and the result data returned by the SoC circuit, and selects the target data from the pulse waveform data and the result data according to the data channel control signal.

[0054] The digital algorithm module is connected to the selection module; the digital algorithm module is used to extract the amplitude information and time information of the target data, and transmit the amplitude information and time information to the SoC circuit.

[0055] Furthermore, the FPGA circuit also includes an output interface.

[0056] The output interface is connected to the digital algorithm module; the output interface is used to output the amplitude and time information of the target data. The output interface is a USB 3.0 interface.

[0057] In one specific implementation, the SoC circuit also includes a CPU processor.

[0058] The CPU processor is connected to the NPU processor and the FPGA circuit respectively; the CPU processor is used to transmit the result data to the FPGA circuit, receive the amplitude information and the time information, as well as receive the location information and the event information, and store the location information, the event information, the amplitude information and the time information.

[0059] In one specific implementation, the SoC circuit also includes an output module.

[0060] The output module is connected to the CPU processor; the output module is used to output the position information, the event information, the amplitude information, and the time information.

[0061] Furthermore, the output module includes an Ethernet interface and a USB 3.0 interface; the Ethernet interface and the USB 3.0 interface are respectively connected to the CPU processor.

[0062] like Figure 1 As shown, the NPU-based nuclear pulse signal processor proposed in this invention patent includes a SoC processor, an FPGA circuit, a radiation detector, an analog front-end circuit, and a high-speed ADC circuit.

[0063] Among them, the radiation detector is used to receive radiation rays, such as αβ particles, γ rays, neutrons, etc., and convert the energy of the rays into voltage pulse signals for output.

[0064] The analog front-end circuit mainly filters and adjusts the amplitude and bias of the pulse signal output from the detector, so that the amplitude of the pulse signal input to the high-speed ADC is as close as possible to the full scale of the high-speed ADC circuit, so as to make full use of the resolution of the high-speed ADC and reduce quantization error.

[0065] High-speed ADC circuits perform analog-to-digital conversion on pulse signals, transforming analog signals into digital signals, which are then input to the back-end digital signal processing circuits for calculation and analysis. To obtain more accurate analysis results in subsequent FPGA and NPU operations, the ADC's sampling rate and resolution should be as high as possible to achieve sufficient sampling points and accuracy.

[0066] The FPGA circuit performs data concatenation on the digital signal output from the high-speed ADC, concatenating the ADC's level signals into 16-bit data. Then, it extracts pulse waveform data from the original data. The pulse waveform is identified using a threshold trigger method. When a pulse signal is detected, a fixed number of sampling points are recorded and saved, centered on the maximum value of the pulse signal, both forward and backward. These sampling points cover the entire pulse waveform range. The extracted pulse waveform data serves as input data for subsequent FPGA digital algorithms and the SoC processor. This data is then processed and analyzed to extract useful information. The data selector (MUX) between the waveform extraction module and the digital algorithm provides flexible configuration functionality for the processor. The Ctrl key controls the data channel selected by the data selector. When waveform data 1 is selected as input data for the digital algorithm in the FPGA, the SoC processor and FPGA need to work together. The extracted pulse waveform data is filtered and denoised by a neural network autoencoder deployed in the NPU of the SoC processor before being transmitted back to the FPGA as the raw data for the digital algorithm. The data stitching module stitches together the data input from the ADC; the waveform extraction module extracts pulse waveform data from a large amount of raw sampled data according to a fixed time length; the data selector selects the signal source input to the back-end digital algorithm; the FIFO buffers the data; the shaping algorithm module digitally shapes the raw pulse waveform, and the amplitude extraction module extracts the amplitude of the shaped waveform; the constant ratio timing digitization algorithm and time extraction module extract the count value of the duration of a certain interval of the waveform and convert it into time information. The digital algorithm is not limited to the above two types; the USB 3.0 module transmits the extracted parameter data to the PC host computer via USB 3.0.

[0067] Among them, digital shaping algorithm, amplitude extraction, constant ratio timing digitization algorithm and time extraction are all existing algorithms.

[0068] Specifically, digital shaping algorithms shape pulse waveforms because the original pulse waveform contains superimposed noise, and the waveforms may overlap. Furthermore, the amplitude of the original waveform is a spike, making it difficult to measure accurately. Therefore, it is best to shape the signal using a shaping algorithm before obtaining the pulse signal amplitude. This has the advantages of filtering and suppressing noise, separating stacked signals, and broadening the signal spike to facilitate the extraction of the highest amplitude value. Common shaping algorithms include trapezoidal shaping, Gaussian shaping, and triangular shaping algorithms. The specific implementation processes and principles of these algorithms are existing technologies and will not be elaborated here.

[0069] The amplitude extraction module obtains the highest amplitude value after pulse shaping when the sampling point of the shaped signal exceeds the set threshold and is delayed for a fixed time. Since the shaping parameters are known, the maximum value of the shaped signal is located at the position after a fixed delay after the trigger threshold. By counting from the trigger threshold and delaying for a fixed time, the maximum value after shaping, i.e., the pulse amplitude, can be obtained. The pulse amplitude after shaping is proportional to the original pulse amplitude.

[0070] The constant-ratio timing digitization algorithm counts the number of sampling points within a certain range of pulse signal amplitude. The time extraction module, knowing the sampling frequency, calculates the duration within this range based on the number of sampling points extracted by the constant-ratio timing digitization algorithm. Combining the digital shaping algorithm and the amplitude extraction module allows for the extraction of the pulse signal amplitude; similarly, combining the constant-ratio timing digitization algorithm and the time extraction module allows for the extraction of the duration of the pulse signal amplitude within a certain range. These are all used to extract characteristic parameters from pulse signals.

[0071] The essence of a nuclear pulse signal processor is to obtain characteristic parameters of pulse signals through various methods. These parameters include, but are not limited to, amplitude, signal duration, energy deposition location information, and event type. Amplitude and signal duration are relatively easy to extract and can be obtained using conventional digital algorithms. However, deposition location information and event type identification are often more difficult to accurately identify and analyze, requiring the use of neural network models for analysis and extraction. Therefore, digital algorithms deployed in the FPGA are used to extract simple amplitude and time information, while neural network models deployed in the NPU are used to extract deposition location and event type information. The extraction of characteristic information such as amplitude and duration from pulse signals by digital algorithms in the FPGA is a key function of the nuclear pulse signal processor.

[0072] Ctrl is the control signal for the data selector, determining the channel selected. It can be implemented in hardware or software. Software implementation: In the FPGA program, the Ctrl control interface of the data selector is configured to 0 or 1. After the FPGA is programmed, the data selector is set to select the corresponding channel. Hardware implementation: The Ctrl control interface of the data selector in the FPGA is connected to an FPGA pin. This pin is connected to power or ground via a connector to assign a high or low level to the pin. A high level corresponds to Ctrl being assigned 1, and a low level corresponds to Ctrl being assigned 0, thus controlling the channel selected by the data selector. The control signal of the data selector is mainly configured according to the system's hardware requirements. For example, in some simple applications, only common parameters such as amplitude and rise time of pulse waveforms need to be extracted. This can be achieved using only an FPGA, without the need for a neural network deployed in an NPU for analysis. In this case, to save costs and simplify the system's hardware structure, a SoC processor module is not required. In this case, the Ctrl interface can be configured to 0 through software or hardware configuration. The waveform data 2 output by the waveform extraction module is then used as the input data for the backend FPGA digitization algorithm, simplifying the system as follows: Figure 3 The nuclear pulse signal processor shown is used in some complex environments, such as when the nuclear pulse signal quality is poor, the signal-to-noise ratio is low, or when it is necessary to analyze the energy deposition location and interaction type of the ray in the detector, the FPGA's digital algorithm alone cannot accurately analyze and identify the signal. In such cases, it is necessary to use the neural network model deployed in the NPU of the SoC processor for analysis. The neural network autoencoder can filter and reduce noise in the nuclear pulse signal. At this time, the Ctrl interface is configured to 1, and the nuclear pulse signal after filtering and noise reduction by the neural network autoencoder is selected as the input data of the back-end FPGA digital algorithm. After the nuclear pulse signal is filtered and noise reduced, the FPGA's digital algorithm can extract waveform features such as amplitude and duration more accurately from the nuclear pulse signal.

[0073] The SoC processor employs a heterogeneous architecture, containing an ARM-based CPU processing unit and an NPU processing unit. The CPU runs a C-language application within a Linux environment. This application loads a pre-trained artificial neural network model via the NPU's API interface provided by the chip manufacturer, deploying the model within the NPU. The CPU handles control and data scheduling, sequentially feeding pulse data into the NPU for computation and analysis. By deploying different models, the NPU processing engine gains different functionalities. For example, when a neural network autoencoder is deployed, the pulse waveform data is processed by this model in the NPU, suppressing noise in the waveform data. When a neural network model with position discrimination or event discrimination capabilities is deployed, the data is processed by the model in the NPU, outputting the probability value of the position encoding or the probability value of the event type. After post-processing in the CPU, the position encoding and event type with the highest probability value are selected, thus achieving position discrimination and event discrimination. The pulse processor designed in this invention can be extended based on the functionality of the loaded artificial neural network model, thus possessing strong versatility. Artificial neural network autoencoders are neural network models loaded by the NPU for filtering and noise reduction of waveform data; artificial neural network models for position discrimination and event type discrimination are used to calculate and analyze the position code and event type code of energy deposition based on the input pulse waveform data. The models and functions that the NPU can actually load and implement are not limited to the above three models and functions.

[0074] Position discrimination refers to the location where energy is deposited by particles or rays within the detector. For example, in a high-purity germanium detector, the location of gamma ray energy deposition affects the shape of the output pulse waveform. The location of energy deposition can be deduced from the shape characteristics of the pulse waveform. Similarly, in a long strip scintillator detector, the photons generated by gamma ray energy deposition at different lengths of the detector attenuate at different rates during their transmission to the two electrodes, resulting in different pulse signal amplitudes at the two electrodes. The location of energy deposition can be deduced from the amplitude information of the two signals. The pulse waveform analysis process can be implemented by a neural network model deployed in the NPU, which then infers and outputs the location information of particle or ray energy deposition within the detector. This location information can be obtained by spatially partitioning and encoding the detector; the neural network model determines the spatial information of ray energy deposition within the detector by outputting the encoded values.

[0075] Event identification refers to distinguishing the types of particles, rays, or events interacting with the detector based on the shape characteristics of the pulse waveform output by the detector. For example, alpha, beta, and gamma particles interact with liquid scintillators (liquid scintillators) through different mechanisms, resulting in different pulse waveform shapes and amplitudes. Identification of these three types of particles is achieved based on the differences in waveform shape characteristics. In neutron-gamma identification applications, neutrons and gamma rays interact with the detector through different mechanisms, which is reflected in the falling edge of the detector's output voltage pulse waveform. Identification of neutrons and gamma rays is achieved based on the shape differences of the falling edge. The analysis of waveform characteristics can also be implemented using a neural network model deployed in the NPU to identify event types.

[0076] The above-mentioned waveform feature analysis and reasoning process is quite complex. Conventional PSD (Pulse Shape Discrimination) methods are difficult to accurately identify energy deposition locations and event types. The PSD algorithm deployed in the FPGA cannot be used to achieve the discrimination. Therefore, it is necessary to use an artificial neural network model deployed in the NPU processing engine for analysis to achieve the above discrimination purpose.

[0077] The following is a description of the functions of this invention in two working modes, specifically including:

[0078] When the data selector selects waveform data 1, the system framework of the pulse processor can be simplified to: Figure 2 As shown. When the NPU processing unit is not required, the data selector selects waveform data 2. At this time, the pulse processor becomes a conventional digital pulse signal processor, reducing power consumption and cost. The system framework can be simplified to... Figure 3 Therefore, the pulse processor can be selectively configured according to environmental and functional requirements.

[0079] After configuration of the data selector, the nuclear pulse signal processor can switch between two modes: a SoC processor + FPGA combined operating mode and an FPGA-only operating mode. This increases the flexibility of the nuclear pulse signal processor's functionality, making it more adaptable to changes in the measurement environment and user needs. The two operating modes are described in detail below:

[0080] 1. SoC Processor + FPGA Combined Working Mode: In this mode, the NPU and FPGA work simultaneously. In the FPGA, the data selector (MUX) selects waveform data 1 as the input data for the shaping algorithm and constant ratio timing. After being filtered and denoised by an artificial neural network autoencoder, waveform data 1 has lower noise and a higher signal-to-noise ratio. After processing by the shaping and constant ratio timing algorithms in the FPGA, the extracted pulse amplitude and time information have higher accuracy. In the NPU processing unit, the kernel pulse signal, after being filtered and denoised by the neural network autoencoder, is simultaneously transmitted to the backend artificial neural network models 1 and 2 for energy deposition location identification and event type identification. The probability value corresponding to each location code and event type code is stored in the output structure variable. After post-processing by the CPU processing unit, the location number and event type number with the highest probability value are extracted. The amplitude and timing information of the nuclear pulse signal extracted by the FPGA are transmitted to the memory space allocated by the CPU processing unit of the SoC processor through parallel communication. Finally, under the control of the CPU processing unit, the amplitude, timing information, position code and event type code are cached in the particle event data packet FIFO. Then, the data is transmitted to the data acquisition terminal via Ethernet communication or to the host computer software on the PC via USB 3.0.

[0081] 2. FPGA Standalone Operating Mode: In this mode, only the FPGA operates; the SoC processor is inactive, and the SoC processor core board can even be removed to reduce product costs. The overall system power consumption is also reduced accordingly. The data selector selects waveform data 2 as the signal source for the FPGA's backend digitization algorithm. In this mode, since the neural network model deployed in the NPU processing unit of the SoC processor is not used for kernel pulse signal feature extraction and analysis, the pulse waveform information extracted by the system only comes from the amplitude and time information extracted by the digitization algorithm in the FPGA.

[0082] In this system, since the neural network model needs to analyze and predict based on discrete data of nuclear pulse signals, it is necessary to collect as many sampling points as possible from the nuclear pulse signals to fully capture their shape characteristics. Therefore, a high-speed, high-precision analog-to-digital converter (ADC) is required. Furthermore, the functions of the artificial neural network model include, but are not limited to, filtering and noise reduction, location identification, and event identification. In the field of nuclear physics, other problems that can be solved using artificial neural network technology can have their corresponding models deployed on the NPU hardware platform to expand the functionality and application scope of this architecture.

[0083] The connection relationships, signal flow, and collaborative working process of the nuclear pulse signal processor are described below:

[0084] 1. SoC processor + FPGA combined working mode.

[0085] Radiation deposits energy in a radiation detector, converting it into a voltage pulse signal which is output from the detector. This pulse is then transmitted via a coaxial cable to the analog front-end circuit. After processing by the analog front-end circuit, the nuclear pulse signal is directly transmitted to the high-speed ADC circuit via signal lines on the PCB board. The high-speed ADC circuit performs analog-to-digital conversion on the nuclear pulse signal, converting it into a digital signal which is then transmitted to the FPGA circuit via signal lines on the PCB board. The data splicing module in the FPGA performs bit splicing on the data transmitted from the high-speed ADC, piecing the bits together into a 16-bit half-byte according to the high-speed ADC's communication protocol. The waveform extraction module in the FPGA performs trigger discrimination on the nuclear pulse signal. If the data transmitted into the FPGA is identified as nuclear pulse signal data, a fixed-length portion of the nuclear pulse signal data is extracted and buffered in the transmit FIFO. This buffered data is then transmitted to the SoC processor via parallel communication. Under the control and coordination of the CPU processing unit, the nuclear pulse signal data is loaded into the input structure variable of the neural network model as input data. First, the neural network autoencoder deployed in the NPU performs operations on the nuclear pulse signal data in the input structure variable, achieving filtering and noise reduction. The processed nuclear pulse signal data is then stored in the output structure variable. The CPU processing unit then... The nuclear pulse signal data is extracted from the output structure variable and transmitted in two paths. One path transmits the nuclear pulse signal data back to the receiving FIFO in the FPGA circuit via parallel communication. The digital algorithm deployed in the FPGA reads the nuclear pulse signal data from the receiving FIFO and extracts feature parameters. Through digital algorithms, such as ladder forming algorithm and constant ratio timing digital algorithm, information such as the nuclear pulse signal amplitude and leading edge time is extracted. Then, this parameter information is transmitted to the memory space allocated by the CPU processing unit in the SoC processor via parallel communication. The other path of nuclear pulse signal data is loaded into the next stage of the neural network model under the control of the CPU processing unit. The data is entered into the structure variable as input data for the next-level artificial neural network model deployed in the NPU. When the next-level artificial neural network model deployed in the NPU has the function of energy deposition location identification or particle and event type identification, the model can obtain the radiation ray energy deposition location information or radiation ray type corresponding to the nuclear pulse signal by calculating and reasoning on the nuclear pulse signal data of the input structure variable. The probability value corresponding to the location code or event type code is stored in the output structure variable. The CPU processing unit reads the result data of the output structure variable, and after the program's post-processing, obtains the location code or event type code with the highest probability value.Finally, the nuclear pulse signal amplitude, leading edge time, position encoding, and event type encoding are packaged into particle event data packets, cached in a FIFO, and transmitted to the PC host computer software or data acquisition terminal via USB 3.0 or Ethernet communication.

[0086] 2. The FPGA standalone operating mode specifically includes:

[0087] The main difference between this mode and the SoC processor + FPGA combined working mode is the elimination of the SoC processor circuit. In the FPGA circuit, the waveform data extracted by the waveform extraction module is directly transmitted to the subsequent digitization algorithm of the FPGA for core pulse signal information extraction. Finally, the core pulse signal information extracted by the digitization algorithm in the FPGA is transmitted to the host computer on the PC via USB 3.0. The connection relationship and signal flow of the analog circuit are the same as in the SoC processor + FPGA combined working mode.

[0088] The key features of the nuclear pulse signal processor designed in this invention, based on an NPU hardware platform, for online processing and analysis of nuclear pulse signals are as follows:

[0089] Nuclear pulse signals are characterized by randomness and short waveform duration. In high-radiation source measurement environments, pulse accumulation can occur, and electronic noise can affect threshold triggering, pulse signal shape discrimination, and system energy resolution. Therefore, it is necessary to develop a series of methods to suppress noise, correct aliasing, and achieve event discrimination. Using traditional digital algorithms to solve these problems is not only very difficult to implement and requires significant logic resources, but also yields generally poor results. Artificial neural network (ANN) technology can quickly and efficiently solve these problems. By deploying an ANN model on an NPU hardware platform, it is possible to effectively analyze and process pulse signals obtained from nuclear physics experiments or radiation detection online, as well as perform more complex online particle information measurements. The deployment process mainly involves the following stages: training and validating the ANN model, converting the model file format, optimizing and quantizing the new model file, and finally copying the quantized model file to the relevant system directory for loading by the main program.

[0090] The key aspects are mainly divided into two stages: model training and model deployment. Model training involves creating relevant datasets based on the application requirements to train the built neural network model. The trained model file can then be used for subsequent deployment. The model deployment process follows a standard procedure, which has been briefly introduced in the previous paragraph. Figure 4 This is a schematic diagram of a convolutional neural network (CNN) model predicting event types based on a sequence of pulse signals. The process of signal data processing by the neural network model in an NPU is similar to... Figure 4The process shown is similar. Finally, the trained artificial neural network model is deployed on embedded devices and mobile devices with neural network processors to achieve online analysis and processing of nuclear pulse signals.

[0091] The online processing and analysis process of this invention is as follows:

[0092] The nuclear pulse signal processor performs pulse waveform processing and analysis, which can be divided into three parts based on functionality. The first part consists of a radiation detector, an analog front-end circuit, and a high-speed ADC. It primarily converts radiation energy into an analog voltage signal, and then into a digital signal. In this part, the detector first converts the radiation energy into a voltage pulse signal. After filtering, amplification, and biasing by the analog front-end circuit, a voltage pulse signal of appropriate amplitude is obtained. This signal is then input to the high-speed ADC circuit, which converts the analog signal into a digital signal for input to the next circuit, thus realizing the conversion from radiation to analog voltage signal and then to digital signal. The second part consists of an FPGA circuit, which mainly performs bit splicing of digital signals, extraction of pulse waveform data, and extraction of effective information from the pulse waveform using digital algorithms. Since digital algorithms can only perform some simple operations on waveform data, they can only extract some simple pulse waveform feature information. To achieve more accurate feature recognition of the pulse waveform, the data needs to be transmitted through a FIFO buffer to the NPU processing unit of the SoC processor in the third part, where an artificial neural network model is used to perform more complex calculations and analyses on the pulse waveform data. The third part consists of a SoC circuit integrating an NPU processing engine. The nuclear pulse signal data transmitted from the FPGA is processed by a neural network autoencoder deployed in the NPU. Noise is suppressed while preserving the original waveform characteristics, resulting in new, high-quality waveform data. One path of this data is transmitted back to the FIFO buffer of the FPGA circuit via parallel communication. The other path of nuclear pulse signal data is stored in the input structure variable of the neural network model under the control of the CPU processing unit. The neural network model performs calculations and inferences on the nuclear pulse signal data in the input structure variable, extracting more complex information. Different models can extract different complex information. Finally, the pulse waveform information extracted by the digital algorithm in the FPGA circuit and the pulse waveform information extracted by the artificial neural network model in the NPU circuit are cached in the particle event data packet FIFO under the control of the CPU processing unit in the SoC processor, and then sent to the data acquisition terminal or the host computer on the PC via the communication interface.

[0093] The features and advantages of the NPU processing unit are as follows:

[0094] After deployment, the digital pulse signal is first stored in the model's input structure variable, awaiting loading and computation by the NPU. Through NPU computation, the white noise superimposed on the signal is suppressed to a certain extent. Simultaneously, the NPU is used to perform baseline recovery on the signal, such as... Figure 5 As shown, a high signal-to-noise ratio (SNR) high-quality signal is obtained. The processed signal is then input to the subsequent FPGA for algorithm processing. This eliminates the need to design baseline restorers, digital filters, and other modules within the FPGA, significantly reducing the FPGA's logic resource consumption and development complexity. Simultaneously, it improves the system's energy resolution, reduces the threshold false trigger rate, and enhances system performance. Furthermore, by deploying artificial neural network models from other applications in nuclear physics within the NPU, the functionality and application scope of the nuclear pulse signal processor can be expanded. For low-frequency noise and transient noise superimposed on the signal, such as… Figure 6 and Figure 7 As shown, after processing by the neural network model in the NPU, noise can be filtered out while retaining the signal, thus improving signal quality. For pulse accumulation issues that occur during experiments, an anti-pulse accumulation neural network model can also be deployed in the NPU. The accumulated pulses are expanded into individual independent pulses after NPU processing, such as... Figure 8 As shown.

[0095] This invention has the following advantages:

[0096] 1. This invention designs a NPU-based core pulse signal processor hardware architecture. By deploying different neural network models in the NPU to adapt to different complex particle information measurement applications, it overcomes the shortcomings of traditional FPGA-based core pulse signal processor hardware architectures, such as limited application scenarios and difficulty and complexity in changing functions.

[0097] 2. This invention uses an NPU as the hardware platform for deploying artificial neural network models to perform online processing and analysis of nuclear pulse signals, overcoming the shortcomings of artificial neural network models in nuclear physics experiments and nuclear technology, which can only process pulse data offline due to their large model size and high deployment difficulty.

[0098] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0099] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A digital core pulse signal processor employing a neural network processor architecture, characterized in that, The processor includes: a SoC circuit, an FPGA circuit, a radiation detector, and a conversion circuit; The radiation detector is used to receive radiation rays and convert the energy of the radiation rays into voltage pulse signals; The conversion circuit is connected to the radiation detector; the conversion circuit is used to convert the voltage pulse signal into a digital signal; The FPGA circuit is connected to the conversion circuit and the SoC circuit respectively; the FPGA circuit is used to extract pulse waveform data from the digital signal and send the pulse waveform data to the SoC circuit, as well as receive data channel control signals and result data returned by the SoC circuit, select target data from the pulse waveform data and the result data according to the data channel control signals, extract the amplitude information and time information of the target data, and transmit the amplitude information and time information to the SoC circuit. The SoC circuit includes an NPU processor; the SoC circuit is used to receive the pulse waveform data, the amplitude information, and the time information, and apply a first neural network model loaded by the NPU processor to filter the pulse waveform data to obtain result data, and apply a second neural network model loaded by the NPU processor to determine the position information of the radiation ray from the result data, and apply a third neural network model loaded by the NPU processor to determine the event information corresponding to the radiation ray based on the result data, and store the position information, the event information, the amplitude information, and the time information.

2. The digital core pulse signal processor employing a neural network processor architecture according to claim 1, characterized in that, The conversion circuit includes an analog front-end circuit and an ADC conversion circuit; The analog front-end circuit is connected to the radiation detector; the analog front-end circuit is used to filter, amplify, and adjust the bias of the voltage pulse signal to obtain a processed analog signal. The ADC conversion circuit is connected to the analog front-end circuit; the ADC conversion circuit is used to convert the processed analog signal into a digital signal.

3. The digital core pulse signal processor employing a neural network processor architecture according to claim 2, characterized in that, The FPGA circuit includes a data splicing module, a waveform extraction module, a selection module, and a digital algorithm module; The splicing module is connected to the ADC conversion circuit; the splicing module is used to splice the digital signal into data with a length of sixteen bits to obtain spliced ​​data; The waveform extraction module is connected to the data splicing module and the SoC circuit respectively; the waveform extraction module is used to extract the pulse waveform data from the spliced ​​data and transmit the pulse waveform data to the SoC circuit. The selection module is connected to the SoC circuit and the waveform extraction module respectively; the selection module receives the data channel control signal and the result data returned by the SoC circuit, and selects target data from the pulse waveform data and the result data according to the data channel control signal. The digital algorithm module is connected to the selection module; the digital algorithm module is used to extract the amplitude information and time information of the target data, and transmit the amplitude information and time information to the SoC circuit.

4. The digital core pulse signal processor employing a neural network processor architecture according to claim 3, characterized in that, The FPGA circuit also includes an output interface; The output interface is connected to the digital algorithm module; the output interface is used to output the amplitude information and time information of the target data.

5. The digital core pulse signal processor employing a neural network processor architecture according to claim 4, characterized in that, The output interface is a USB 3.0 interface.

6. The digital core pulse signal processor employing a neural network processor architecture according to claim 1, characterized in that, The SoC circuit also includes a CPU processor; The CPU processor is connected to the NPU processor and the FPGA circuit respectively; the CPU processor is used to transmit the result data to the FPGA circuit, receive the amplitude information and the time information, as well as receive the location information and the event information, and store the location information, the event information, the amplitude information and the time information.

7. The digital core pulse signal processor employing a neural network processor architecture according to claim 6, characterized in that, The SoC circuit also includes an output module; The output module is connected to the CPU processor; the output module is used to output the position information, the event information, the amplitude information, and the time information.

8. The digital core pulse signal processor employing a neural network processor architecture according to claim 7, characterized in that, The output module includes an Ethernet interface and a USB 3.0 interface; the Ethernet interface and the USB 3.0 interface are respectively connected to the CPU processor.

Images