Neural network-based modeling method, device and medium for memristor crossbar array

Abstract

The application relates to a neural network-based modeling method, device, equipment and medium for a memristor cross array, wherein the method comprises the following steps: determining the array position, array size and preset integral time of an analog-to-digital converter of a target memristor cross array, generating an input matrix, an input vector and an actual output vector of the target memristor cross array, and then constructing a training data set; constructing a memristor cross array model based on a full connection layer, a rectified linear unit and an analog-to-digital converter; training the memristor cross array model by using the training data set, generating an intercept parameter vector and a slope parameter vector of the target memristor cross array, and determining the functional relationship between the input matrix and the input vector and the intercept parameter and the slope parameter. Therefore, the problems that the existing linear fitting method cannot handle the change of related parameters, and it is difficult to directly deduce the functional relationship between the corresponding parameters from the theory due to the complex non-ideal characteristics on the memristor cross array are solved.

Description

Technical Field

[0001] This application relates to the field of memristor cross array modeling technology, and in particular to a method, apparatus, device and medium for memristor cross array modeling based on neural networks. Background Technology

[0002] With the development of deep learning technology, artificial intelligence (AI) has broad prospects in industry and scientific research, and computing power is a necessary factor for its development and research. Limited by the traditional von Neumann architecture of chips, the power consumption problem of AI chips is becoming increasingly significant, and high-energy-efficiency, high-computing-power chips have become one of the bottlenecks restricting AI development. Memristor-based in-memory computing architecture chips hold promise for solving this problem. Memristor cross-arrays can perform matrix-vector multiplication, thus enabling the deployment of neural networks. Currently, significant research progress has been made in memristor-related processes, devices, circuits, and architectures.

[0003] However, since memristor cross arrays perform analog calculations, which are different from the binary digital calculations of modern computers, their calculation results have accuracy issues. Furthermore, the non-ideal effects of their devices and circuits further increase noise in the calculation process, which greatly limits the on-chip inference accuracy of neural networks.

[0004] Currently, linear fitting-based modeling methods extract the slope and intercept of linear regression from the matrix-vector multiplication data of memristor cross arrays. The matrix-vector multiplication data for memristor cross arrays includes the input vector... X Input matrix W and output vector Y A linear model was extracted based on the above data. Y 预测 = k WX + b The parameter in (i.e., slope) k and intercept b ,in, This method (representing element-wise multiplication) is used to predict the array output corresponding to any combination of inputs. However, based on the principle of linear fitting, this method actually pre-determines the parameters. k and b The value of and the input vector X Input matrix W Irrelevant. In actual implementation, various non-ideal factors affecting calculation accuracy in the memristor cross array, such as voltage drop and leakage current, are all closely related to the input vector and input matrix. That is to say, the parameters... k and b Not with X ,W Irrelevant constants, but X , W The linear fitting method ignores this fact, and therefore the modeling method of linear fitting often has a large error.

[0005] In summary, existing linear fitting methods cannot handle slope and intercept. b With input vector X Input matrix W The changing conditions and the complex non-ideal characteristics of the memristor cross array make it difficult to directly derive the functional relationship between the corresponding parameters from theory, resulting in a large error in the linear fitting modeling method, which urgently needs to be addressed. Summary of the Invention

[0006] This application provides a method, apparatus, device, and medium for modeling memristor cross arrays based on neural networks, in order to solve the problems that existing linear fitting methods cannot handle changes in relevant parameters, and that due to the complexity of the non-ideal characteristics on the memristor cross array, it is difficult to directly derive the functional relationship between the corresponding parameters from theory.

[0007] The first aspect of this application provides a method for modeling a memristor cross array based on a neural network, comprising the following steps: determining the array position, array size, and a preset integration time of the analog-to-digital converter of the target memristor cross array; generating an input matrix, input vector, and actual output vector of the target memristor cross array based on the array position, array size, and integration time; constructing a training dataset based on the input matrix, input vector, and actual output vector; constructing a memristor cross array model based on a preset fully connected layer, rectified linear unit, and analog-to-digital converter; training the memristor cross array model using the training dataset to generate the intercept parameter vector and slope parameter vector of the target memristor cross array; determining the functional relationship between the input matrix and the input vector and the intercept parameter and slope parameter to obtain the memristor cross array modeling result.

[0008] Optionally, in one embodiment of this application, generating the input matrix, input vector, and actual output vector of the target memristor cross array based on the array position, the array size, and the integration time includes: generating the input matrix and the input vector according to the array position and the array size; mapping the input matrix to the conductance of the target memristor cross array, and simultaneously inputting the input vector to the vector input terminal of the target memristor cross array; and performing a preset matrix-vector multiplication operation based on the integration time, the input matrix, and the input vector to obtain the actual output vector of the target memristor cross array.

[0009] Optionally, in one embodiment of this application, the step of constructing a memristor cross array model based on a preset fully connected layer, rectifier linear unit, and analog-to-digital converter includes: constructing a memristor cross array network through multiple fully connected layers and multiple rectifier linear units; and generating the memristor cross array model based on the memristor cross array network and the analog-to-digital converter.

[0010] Optionally, in one embodiment of this application, generating the intercept parameter vector and slope parameter vector of the target memristor cross array, and determining the functional relationship between the input matrix and the input vector and the intercept parameter and slope parameter, includes: performing a preset matrix-vector multiplication operation on each input matrix and each input vector in the training dataset to obtain a matrix-vector multiplication result; generating the intercept parameter vector and the slope parameter vector based on each input matrix, each input vector, and the memristor cross array network; calculating the output vector prediction value using the analog-to-digital converter based on the intercept parameter vector, the slope parameter vector, and the matrix-vector multiplication result; and determining the functional relationship between the input matrix and the input vector of the target memristor cross array and the intercept parameter and slope parameter according to the output vector prediction value.

[0011] A second aspect of this application provides a neural network-based memristor cross array modeling device, comprising: a first determining module, configured to determine the array position, array size, and preset integration time of a target memristor cross array, and generate an input matrix, input vector, and actual output vector of the target memristor cross array based on the array position, array size, and integration time, and construct a training dataset based on the input matrix, input vector, and actual output vector; a modeling module, configured to construct a memristor cross array model based on a preset fully connected layer, rectifier linear unit, and the analog-to-digital converter; and a second determining module, configured to train the memristor cross array model using the training dataset, generate an intercept parameter vector and a slope parameter vector of the target memristor cross array, and determine the functional relationship between the input matrix and the input vector and the intercept parameter and slope parameter, thereby obtaining a memristor cross array modeling result.

[0012] Optionally, in one embodiment of this application, the first determining module includes: a first generating unit, configured to generate the input matrix and the input vector according to the array position and the array size; a deployment unit, configured to map the input matrix to the conductance of the target memristor cross array, and simultaneously input the input vector to the vector input terminal of the target memristor cross array; and an execution unit, configured to perform a preset matrix-vector multiplication operation based on the integration time, the input matrix, and the input vector to obtain the actual output vector of the target memristor cross array.

[0013] Optionally, in one embodiment of this application, the modeling module includes: a construction unit for constructing a memristor cross array network through multiple fully connected layers and multiple rectified linear units; and a second generation unit for generating the memristor cross array model based on the memristor cross array network and in conjunction with the analog-to-digital converter.

[0014] Optionally, in one embodiment of this application, the second determining module includes: a first calculation unit, configured to perform a preset matrix-vector multiplication operation on each input matrix and each input vector in the training dataset to obtain a matrix-vector multiplication result; a third generation unit, configured to generate the intercept parameter vector and the slope parameter vector based on each input matrix, each input vector, and the memristor cross array network; a second calculation unit, configured to calculate the output vector prediction value using the analog-to-digital converter based on the intercept parameter vector, the slope parameter vector, and the matrix-vector multiplication result; and a result unit, configured to determine the functional relationship between the input matrix and the input vector of the target memristor cross array and the intercept parameter and the slope parameter according to the output vector prediction value.

[0015] A third aspect of this application provides an electronic device, including: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the neural network-based memristor cross array modeling method as described in the above embodiments.

[0016] A fourth aspect of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described neural network-based memristor cross array modeling method.

[0017] Therefore, the embodiments of this application have the following beneficial effects: The embodiments of this application determine the array position, array size, and preset integration time of the analog-to-digital converter (ADC) of the target memristor cross array. Based on the array position, array size, and integration time, the input matrix, input vector, and actual output vector of the target memristor cross array are generated, and a training dataset is constructed based on the input matrix, input vector, and actual output vector. A memristor cross array model is constructed based on preset fully connected layers, rectified linear units, and the ADC. The memristor cross array model is trained using the training dataset to generate the intercept parameter vector and slope parameter vector of the target memristor cross array, and the functional relationship between the input matrix and input vector and the intercept and slope parameters is determined, thus obtaining the memristor cross array modeling result. This application utilizes the learning capability of neural networks to learn the implicit patterns in the dataset, thereby predicting the output result of the memristor cross array based on the input vector and matrix to simulate the behavioral characteristics of the memristor cross array, thereby establishing a more accurate behavioral model. This solves the problems of existing linear fitting methods being unable to handle changes in relevant parameters, and the difficulty in directly deriving the functional relationship between corresponding parameters theoretically due to the complexity of the non-ideal characteristics of the memristor cross array.

[0018] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0019] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a flowchart of a memristor cross array modeling method based on a neural network, according to an embodiment of this application. Figure 2 A schematic diagram of a training dataset construction process is provided for one embodiment of this application; Figure 3 A schematic diagram of a data acquisition process for a memristor cross array matrix-vector multiplication is provided as an embodiment of this application; Figure 4 A schematic diagram of a memristor cross array model architecture is provided for one embodiment of this application; Figure 5 This is an example diagram of a neural network-based memristor cross array modeling device according to an embodiment of this application; Figure 6 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0020] Among them, 10-memristor cross array modeling device based on neural network, 100-first determining module, 200-modeling module, 300-second determining module, 601-memory, 602-processor, and 603-communication interface. Detailed Implementation

[0021] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0022] The following description, with reference to the accompanying drawings, describes a method, apparatus, device, and medium for modeling memristor cross arrays based on neural networks, according to embodiments of this application. Addressing the problems mentioned in the background section, this application provides a method for modeling memristor cross arrays based on neural networks. In this method, the array position, array size, and a preset integration time of the analog-to-digital converter (ADC) of the target memristor cross array are determined. Based on the array position, array size, and integration time, the input matrix, input vector, and actual output vector of the target memristor cross array are generated, and a training dataset is constructed based on the input matrix, input vector, and actual output vector. A memristor cross array model is constructed based on a preset fully connected layer, rectifier linear unit, and ADC. The memristor cross array model is trained using the training dataset to generate the intercept parameter vector and slope parameter vector of the target memristor cross array. The functional relationship between the input matrix and input vector and the intercept and slope parameters is determined, resulting in the memristor cross array modeling result. This application utilizes the learning capabilities of neural networks to learn the implicit patterns in a dataset, thereby predicting the output of a memristor cross array based on input vectors and matrices. This simulates the behavioral characteristics of the memristor cross array, thus establishing a more accurate behavioral model. This solves the problems of existing linear fitting methods being unable to handle variations in relevant parameters, and the difficulty in directly deriving the functional relationships between parameters theoretically due to the complex non-ideal characteristics of the memristor cross array.

[0023] Specifically, Figure 1 This is a flowchart illustrating a neural network-based memristor cross array modeling method provided in an embodiment of this application.

[0024] like Figure 1 As shown, the neural network-based memristor cross array modeling method includes the following steps: In step S101, the array position, array size, and preset integration time of the analog-to-digital converter of the target memristor cross array are determined. Based on the array position, array size, and integration time, the input matrix, input vector, and actual output vector of the target memristor cross array are generated, and a training dataset is constructed based on the input matrix, input vector, and actual output vector.

[0025] The embodiments of this application can calculate the input vector of the target memristor cross array based on the array position, array size, and integration time of the analog-to-digital converter. X Input matrix W and actual output vector Y 实际 The training dataset is constructed based on the calculation results of the memristor cross array, namely the input matrix, input vector and actual output vector, so as to provide reliable data basis for training the memristor cross array model.

[0026] Optionally, in one embodiment of this application, generating the input matrix, input vector, and actual output vector of the target memristor cross array based on the array position, array size, and integration time includes: generating the input matrix and input vector according to the array position and array size; mapping the input matrix to the conductance of the target memristor cross array, and simultaneously inputting the input vector to the vector input terminal of the target memristor cross array; and performing a preset matrix-vector multiplication operation based on the integration time, input matrix, and input vector to obtain the actual output vector of the target memristor cross array.

[0027] Specifically, such as Figure 2 As shown, the process of constructing the training dataset for the target memristor cross array in this application embodiment is as follows: 1. Determine the array location, size, and integration time to be modeled. This application's embodiments can model the entire memristor cross array on the chip, or a partial array. This application's embodiments will use an m x n array as an example for illustration. Furthermore, during matrix multiplication, the output vector calculated from the memristor cross array needs to be integrated and quantized by an analog-to-digital converter (ADC or A / D, a circuit module that converts continuous analog quantities into discrete digital quantities). Figure 3 As shown, the integration time of the analog-to-digital converter can be set manually, and different integration times will produce different outputs. Therefore, a fixed integration time needs to be selected during modeling. t ; 2. Randomly generate an m x n input matrix and input it into the memristor cross array, that is, map the input matrix to the conductance values ​​of the memristor cross array, such as... Figure 3 As shown; 3. Randomly generate p m-dimensional input vectors. These p input vectors actually form a p-row m-column matrix, which is then input into the vector input port of the memristor cross array. 4. The integration time of the analog-to-digital converter is set to... t The system then begins calculating matrix-vector multiplication, collecting the results from the vector output. Since this embodiment requires collecting q input matrix data, q loops are needed to collect data, with each input matrix corresponding to p input vectors, i.e., p output vectors. Y 实际 ; 5. Repeat the above steps, changing to a new input matrix, to obtain matrix-vector multiplication data corresponding to different input matrices.

[0028] The above steps generated q different input matrices and collected corresponding data, resulting in a total of p×q data points, each including an input vector. X Input matrix W and actual output vector Y 实际 The three parts allow the embodiments of this application to use common data processing and deep learning toolkits, such as NumPy (a data analysis and processing toolkit based on the Python language) and PyTorch (a deep learning toolkit based on the Python language), to organize and package the data obtained above, thereby constructing a training dataset.

[0029] In step S102, a memristor cross array model is constructed based on a preset fully connected layer, rectifier linear unit, and analog-to-digital converter.

[0030] After constructing the training dataset, the embodiments of this application can further utilize fully connected layers, rectified linear units, and the aforementioned analog-to-digital converters to construct a memristor cross array model, thereby establishing a behavioral-level model for the memristor cross array. This not only helps to understand the behavioral characteristics of memristor chips under non-ideal conditions, but can also be used as a chip simulator in the off-chip training framework of neural networks, thereby improving the robustness of the model and the on-chip inference accuracy.

[0031] Optionally, in one embodiment of this application, a memristor cross array model is constructed based on a preset fully connected layer, rectifier linear unit, and analog-to-digital converter, including: constructing a memristor cross array network through multiple fully connected layers and multiple rectifier linear units; and generating a memristor cross array model based on the memristor cross array network and the analog-to-digital converter.

[0032] It should be noted that the embodiments of this application can construct a memristor cross array network through multiple FC (Fully-connected) layers and multiple ReLU (Rectifier Linear Unit) activation functions, and combine it with an analog-to-digital converter to build a memristor cross array model, thereby establishing a behavioral-level model for the memristor cross array.

[0033] In step S103, the memristor cross array model is trained using the training dataset to generate the intercept parameter vector and slope parameter vector of the target memristor cross array, and the functional relationship between the input matrix and input vector and the intercept parameter and slope parameter is determined to obtain the memristor cross array modeling result.

[0034] After constructing the memristor cross-array model, the embodiments of this application can further find functions using the memristor cross-array model and the training dataset. Y 预测 = f ( X , W ), to pass Y 预测 To predict Y 实际 .

[0035] Therefore, embodiments of this application can use the calculation results of memristor cross arrays to design datasets, train memristor cross array models, and utilize the learning capabilities of neural networks to learn the implicit patterns in the datasets. This allows for the prediction of the output results of the memristor cross array based on the input vectors and matrices, thereby simulating the behavioral characteristics of the memristor cross array and determining the functional relationship between the input matrix and input vectors and the intercept and slope parameters.

[0036] Optionally, in one embodiment of this application, generating the intercept parameter vector and slope parameter vector of the target memristor cross array, and determining the functional relationship between the input matrix and input vector and the intercept parameter and slope parameter, includes: performing a preset matrix-vector multiplication operation on each input matrix and each input vector in the training dataset to obtain the matrix-vector multiplication result; generating the intercept parameter vector and slope parameter vector based on each input matrix, each input vector, and the memristor cross array network; calculating the output vector prediction value using an analog-to-digital converter based on the intercept parameter vector, slope parameter vector, and matrix-vector multiplication result; and determining the functional relationship between the input matrix and input vector of the target memristor cross array and the intercept parameter and slope parameter according to the output vector prediction value.

[0037] Specifically, such as Figure 4 As shown, embodiments of this application can utilize the input vectors in the training dataset constructed above. X Input matrixW As model input, Y 实际 As model output Y 预测 To determine the target value, the memristor cross-array model is trained using the following steps: 1. Input vector X and input matrix W It is divided into three paths, one of which is for the input vector X and input matrix W Perform the multiplication operation to obtain WX The other two paths are processed by two separate neural networks; 2. The first neural network consists of several fully connected (FC) layers and several ReLU activations. This neural network receives an input vector. X and input matrix W After calculations at each level, an n-dimensional vector is obtained. k ,like Figure 4 As shown, "matrix transformation and connection" is to transform the input vector X and input matrix W Connected together, d in This represents the input dimension of the neural network. d out This represents the output dimension of the neural network (here, it is ). k and b (dimensional n) h 1 and h 2 represents the dimension of the intermediate layer of the neural network; 3. The second neural network also consists of several FC layers and several ReLU activations, and has the same structure as the first neural network. This neural network receives an input vector. X and input matrix W After calculations at each level, an n-dimensional vector is obtained. b ; 4. Regarding the results obtained in step 1 XW The result obtained in step 2 k The result obtained in step 3 b , perform calculations to obtain k WX + b ,in Indicates element-wise multiplication; 5. Regarding the results obtained in step 4 k WX + b After processing by the analog-to-digital converter, the final output is obtained. Y 预测 The settings for the analog-to-digital converter here are related to... Figure 3 The range and accuracy of the analog-to-digital converters in the actual array are consistent. 6. Train the memristor cross-array model using the training dataset, and output the model's data. Y 预测 With target value Y 实际 The mean squared error between the two sides is used as the loss function, and the value of this loss function is backpropagated to learn and update the weights of the neural network model.

[0038] It should be noted that, in addition to the memristor cross array model mentioned above, those skilled in the art may select mainstream deep learning frameworks such as PyTorch or TensorFlow for the definition and training of the above neural network models according to the actual situation, without making any specific restrictions.

[0039] In actual execution, for the input matrix W If the matrix is ​​large, a compression function can be considered. g ( W After compression, g ( W The data size is significantly smaller than the original. W This facilitates neural network processing; subsequently... X , g ( W )and XW Input them together into the neural network model, where XW It directly provides the results of matrix-vector multiplication, while W , g ( W )and XW After being connected by Figure 4 Both sets of neural network processing can obtain the same prediction results. Y 预测 .

[0040] Therefore, the embodiments of this application can learn the data characteristics, i.e., parameters of the memristor cross array by utilizing the learning capability of the memristor cross array model. k and b For parameters W and X By establishing functional relationships, a more accurate behavioral model can be built, effectively improving the accuracy of prediction results.

[0041] The memristor cross array modeling method based on neural networks proposed in this application determines the array position, array size, and preset integration time of the analog-to-digital converter (ADC) of the target memristor cross array. Based on the array position, array size, and integration time, the input matrix, input vector, and actual output vector of the target memristor cross array are generated, and a training dataset is constructed based on the input matrix, input vector, and actual output vector. A memristor cross array model is constructed based on preset fully connected layers, rectifier linear units, and the ADC. The memristor cross array model is trained using the training dataset to generate the intercept parameter vector and slope parameter vector of the target memristor cross array. The functional relationship between the input matrix and input vector and the intercept and slope parameters is determined, resulting in the memristor cross array modeling result. This application utilizes the learning ability of neural networks to learn the implicit patterns in the dataset, thereby predicting the output result of the memristor cross array based on the input vector and matrix, simulating the behavioral characteristics of the memristor cross array, and thus establishing a more accurate behavioral model.

[0042] Secondly, with reference to the accompanying drawings, a neural network-based memristor cross array modeling apparatus according to an embodiment of this application is described.

[0043] Figure 5 This is a block diagram of a neural network-based memristor cross array modeling device according to an embodiment of this application.

[0044] like Figure 5 As shown, the neural network-based memristor cross array modeling device 10 includes: a first determining module 100, a modeling module 200, and a second determining module 300.

[0045] The first determining module 100 is used to determine the array position, array size, and preset integration time of the analog-to-digital converter of the target memristor cross array, and to generate the input matrix, input vector, and actual output vector of the target memristor cross array based on the array position, array size, and integration time, and to construct a training dataset based on the input matrix, input vector, and actual output vector.

[0046] Modeling module 200 is used to construct a memristor cross array model based on a preset fully connected layer, rectifier linear unit and analog-to-digital converter.

[0047] The second determining module 300 is used to train a memristor cross array model using a training dataset, generate the intercept parameter vector and slope parameter vector of the target memristor cross array, and determine the functional relationship between the input matrix and input vector and the intercept parameter and slope parameter to obtain the memristor cross array modeling result.

[0048] Optionally, in one embodiment of this application, the first determining module 100 includes: a first generating unit, a deployment unit, and an execution unit.

[0049] The first generation unit is used to generate the input matrix and input vector according to the array position and array size.

[0050] The deployment unit is used to map the input matrix to the conductance of the target memristor cross array, and simultaneously input the input vector to the vector input terminal of the target memristor cross array.

[0051] The execution unit is used to perform a preset matrix-vector multiplication operation based on the integration time, the input matrix, and the input vector to obtain the actual output vector of the target memristor cross array.

[0052] Optionally, in one embodiment of this application, the modeling module 200 includes: a construction unit and a second generation unit.

[0053] The building unit is used to construct a memristor cross array network through multiple fully connected layers and multiple rectified linear units.

[0054] The second generation unit is used to generate a memristor cross array model based on the memristor cross array network and combined with an analog-to-digital converter.

[0055] Optionally, in one embodiment of this application, the second determining module 300 includes: a first calculation unit, a third generation unit, a second calculation unit, and a result unit.

[0056] The first computing unit is used to perform a preset matrix-vector multiplication operation on each input matrix and each input vector in the training dataset to obtain the matrix-vector multiplication result.

[0057] The third generation unit is used to generate intercept parameter vectors and slope parameter vectors based on each input matrix, each input vector, and the memristor cross array network.

[0058] The second calculation unit is used to calculate the predicted value of the output vector based on the intercept parameter vector, the slope parameter vector, and the matrix-vector multiplication result, using an analog-to-digital converter.

[0059] The result unit is used to determine the input matrix of the target memristor cross array and the functional relationship between the input vector and the intercept and slope parameters based on the output vector prediction values.

[0060] It should be noted that the foregoing explanation of the embodiment of the memristor cross array modeling method based on neural networks also applies to the memristor cross array modeling device based on neural networks in this embodiment, and will not be repeated here.

[0061] According to the neural network-based memristor cross array modeling device proposed in this application, a first determining module is used to determine the array position, array size, and preset integration time of the target memristor cross array, and to generate the input matrix, input vector, and actual output vector of the target memristor cross array based on the array position, array size, and integration time, and to construct a training dataset based on the input matrix, input vector, and actual output vector; a modeling module is used to construct a memristor cross array model based on preset fully connected layers, rectifier linear units, and an analog-to-digital converter; a second determining module is used to train the memristor cross array model using the training dataset, generate the intercept parameter vector and slope parameter vector of the target memristor cross array, and determine the functional relationship between the input matrix and input vector and the intercept and slope parameters to obtain the memristor cross array modeling result. This application utilizes the learning ability of neural networks to learn the implicit patterns in the dataset, thereby predicting the output result of the memristor cross array based on the input vector and matrix, to simulate the behavioral characteristics of the memristor cross array, and thus establish a more accurate behavioral model.

[0062] Figure 6 A schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device may include: The memory 601, the processor 602, and the computer program stored on the memory 601 and capable of running on the processor 602.

[0063] When the processor 602 executes the program, it implements the neural network-based memristor cross array modeling method provided in the above embodiments.

[0064] Furthermore, electronic devices also include: Communication interface 603 is used for communication between memory 601 and processor 602.

[0065] The memory 601 is used to store computer programs that can run on the processor 602.

[0066] The memory 601 may include high-speed RAM memory, and may also include non-volatile memory, such as at least one disk storage device.

[0067] If the memory 601, processor 602, and communication interface 603 are implemented independently, then the communication interface 603, memory 601, and processor 602 can be interconnected via a bus to complete communication between them. The bus can be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. Buses can be categorized as address buses, data buses, control buses, etc. For ease of representation, Figure 6 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0068] Optionally, in a specific implementation, if the memory 601, processor 602, and communication interface 603 are integrated on a single chip, then the memory 601, processor 602, and communication interface 603 can communicate with each other through an internal interface.

[0069] The processor 602 may be a central processing unit (CPU), an application specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of this application.

[0070] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a processor, implements the above-described neural network-based memristor cross array modeling method.

[0071] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0072] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "N" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0073] Any process or method described in the flowchart or otherwise herein can be understood as representing a module, segment, or portion of code comprising one or N executable instructions for implementing custom logic functions or processes, and the scope of the preferred embodiments of this application includes additional implementations in which functions may be performed not in the order shown or discussed, including substantially simultaneously or in reverse order depending on the functions involved, as should be understood by those skilled in the art to which embodiments of this application pertain.

[0074] The logic and / or steps represented in the flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing logical functions, and can be embodied in any computer-readable medium for use by, or in conjunction with, an instruction execution system, apparatus, or device (such as a computer-based system, a processor-included system, or other system that can fetch and execute instructions from, an instruction execution system, apparatus, or device). For the purposes of this specification, "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transmit programs for use by, or in conjunction with, an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of computer-readable media include: an electrical connection having one or more wires (electronic device), a portable computer disk drive (magnetic device), random access memory (RAM), read-only memory (ROM), erasable and editable read-only memory (EPROM or flash memory), fiber optic devices, and portable optical disc read-only memory (CDROM). Alternatively, the computer-readable medium may be paper or other suitable media on which the program can be printed, since the program can be obtained electronically by optically scanning the paper or other medium, followed by editing, interpreting, or otherwise processing as necessary, and then stored in a computer memory.

[0075] It should be understood that the various parts of this application can be implemented using hardware, software, firmware, or a combination thereof. In the above embodiments, the N steps or methods can be implemented using software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, it can be implemented using any one or a combination of the following techniques known in the art: discrete logic circuits having logic gates for implementing logical functions on data signals, application-specific integrated circuits (ASICs) having suitable combinational logic gates, programmable gate arrays (PGAs), field-programmable gate arrays (FPGAs), etc.

[0076] Those skilled in the art will understand that all or part of the steps of the methods in the above embodiments can be implemented by a program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, the program includes one or a combination of the steps of the method embodiments.

[0077] Furthermore, the functional units in the various embodiments of this application can be integrated into a processing module, or each unit can exist physically separately, or two or more units can be integrated into a module. The integrated module can be implemented in hardware or as a software functional module. If the integrated module is implemented as a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0078] The storage medium mentioned above can be a read-only memory, a disk, or an optical disk, etc. Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of this application.

Claims

1. A method for modeling memristor cross arrays based on neural networks, characterized in that, Includes the following steps: The array position, array size, and preset integration time of the analog-to-digital converter of the target memristor cross array are determined. Based on the array position, array size, and integration time, the input matrix, input vector, and actual output vector of the target memristor cross array are generated, and a training dataset is constructed based on the input matrix, the input vector, and the actual output vector. Based on the preset fully connected layer, rectifier linear unit and the analog-to-digital converter, a memristor cross array model is constructed; The memristor cross array model is trained using the training dataset to generate the intercept parameter vector and slope parameter vector of the target memristor cross array. The functional relationship between the input matrix and the input vector and the intercept parameter and slope parameter is determined to obtain the memristor cross array modeling result.

2. The method according to claim 1, characterized in that, The process of generating the input matrix, input vector, and actual output vector of the target memristor cross array based on the array position, the array size, and the integration time includes: The input matrix and the input vector are generated based on the array position and the array size; The input matrix is ​​mapped to the conductance of the target memristor cross array, and the input vector is simultaneously input to the vector input terminal of the target memristor cross array. Based on the integration time, the input matrix, and the input vector, a preset matrix-vector multiplication operation is performed to obtain the actual output vector of the target memristor cross array.

3. The method according to claim 2, characterized in that, The memristor cross-array model, constructed based on a preset fully connected layer, rectifier linear unit, and analog-to-digital converter, includes: A memristor cross array network is constructed using multiple fully connected layers and multiple rectifier linear units; Based on the memristor cross array network, and combined with the analog-to-digital converter, the memristor cross array model is generated.

4. The method according to claim 3, characterized in that, The process of generating the intercept parameter vector and slope parameter vector of the target memristor cross array, and determining the functional relationship between the input matrix and the input vector and the intercept parameters and slope parameters, includes: Perform a preset matrix-vector multiplication operation on each input matrix and each input vector in the training dataset to obtain the matrix-vector multiplication result; Based on each input matrix, each input vector, and the memristor cross array network, the intercept parameter vector and the slope parameter vector are generated. Based on the intercept parameter vector, the slope parameter vector, and the matrix-vector multiplication result, the output vector prediction value is calculated using the analog-to-digital converter. The input matrix of the target memristor cross array and the functional relationship between the input vector and the intercept parameter and the slope parameter are determined based on the predicted output vector value.

5. A memristor cross array modeling device based on neural networks, characterized in that, include: The first determining module is used to determine the array position, array size, and preset integration time of the analog-to-digital converter of the target memristor cross array, and to generate the input matrix, input vector, and actual output vector of the target memristor cross array based on the array position, array size, and integration time, and to construct a training dataset based on the input matrix, input vector, and actual output vector. The modeling module is used to construct a memristor cross array model based on a preset fully connected layer, rectifier linear unit and the analog-to-digital converter; The second determining module is used to train the memristor cross array model using the training dataset, generate the intercept parameter vector and slope parameter vector of the target memristor cross array, and determine the functional relationship between the input matrix and the input vector and the intercept parameter and slope parameter to obtain the memristor cross array modeling result.

6. The apparatus according to claim 5, characterized in that, The first determining module includes: The first generation unit is configured to generate the input matrix and the input vector according to the array position and the array size; The deployment unit is used to map the input matrix to the conductance of the target memristor cross array, and simultaneously input the input vector to the vector input terminal of the target memristor cross array; An execution unit is configured to perform a preset matrix-vector multiplication operation based on the integration time, the input matrix, and the input vector to obtain the actual output vector of the target memristor cross array.

7. The apparatus according to claim 6, characterized in that, The modeling module includes: The building block is used to construct a memristor cross array network through multiple fully connected layers and multiple rectified linear units; The second generation unit is used to generate the memristor cross array model based on the memristor cross array network and in conjunction with the analog-to-digital converter.

8. The apparatus according to claim 7, characterized in that, The second determining module includes: The first computing unit is used to perform a preset matrix-vector multiplication operation on each input matrix and each input vector in the training dataset to obtain the matrix-vector multiplication result; The third generation unit is used to generate the intercept parameter vector and the slope parameter vector based on each input matrix, each input vector and the memristor cross array network; The second calculation unit is used to calculate the predicted value of the output vector based on the intercept parameter vector, the slope parameter vector and the matrix-vector multiplication result, using the analog-to-digital converter. The result unit is used to determine the input matrix of the target memristor cross array and the functional relationship between the input vector and the intercept parameter and the slope parameter based on the output vector prediction value.

9. An electronic device, characterized in that, include: A memory, a processor, and a computer program stored in the memory and executable on the processor, the processor executing the program to implement the neural network-based memristor cross array modeling method as described in any one of claims 1-4.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The program is executed by the processor to implement the neural network-based memristor cross array modeling method as described in any one of claims 1-4.

Images