Display panel, pixel repair method thereof and display device

Abstract

The present disclosure relates to a display panel, a pixel repair method thereof and a display device, wherein the display panel comprises a plurality of pixel driving circuit rows, a plurality of repair data lines and a plurality of repair driving circuits, the plurality of repair driving circuits are arranged along a second direction, at least two repair data lines are correspondingly arranged for one repair driving circuit, and the second direction intersects the first direction; in a direction perpendicular to the plane on which the substrate lies, the first switching structure at least partially overlaps with the at least two repair data lines. The display panel provided by the present disclosure correspondingly arranges at least two repair data lines for one repair driving circuit, so that when one of the repair data lines is occupied by other repair driving circuits, one or more repair data lines can also provide data signals to another repair driving circuit, thereby enabling the display panel to repair more defective pixels when the same number of repair driving circuits are arranged, and improving the pixel fault tolerance of the display panel.

Description

Technical Field

[0001] This disclosure relates to the field of display technology, and in particular to a display panel and a pixel repair method and display device thereof. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are electroluminescent devices that utilize a multilayer organic thin-film structure. They are easy to manufacture and require only low driving voltages. OLED displays are thinner, lighter, brighter, consume less power, have faster response times, higher resolution, greater flexibility, and higher luminous efficiency than traditional LCDs, meeting consumers' evolving demands for display technology. Pixel circuits are required in the display panel to drive the OLED devices. If the pixel circuits are defective, the corresponding OLED devices will not display the correct brightness, resulting in display defects and affecting the display quality. Summary of the Invention

[0003] To address the aforementioned technical problems, this disclosure provides a display panel, a pixel repair method thereof, and a display device.

[0004] This disclosure provides a display panel, comprising: a substrate; a display area and a non-display area, the non-display area at least partially surrounding the display area; a plurality of light-emitting elements and a plurality of pixel driving circuit rows, the display area including the light-emitting elements and the pixel driving circuit rows, each pixel driving circuit row including a plurality of pixel driving circuits arranged along a first direction, one of the pixel driving circuits being electrically connected to at least one light-emitting element; a plurality of repair connection lines, a plurality of repair data lines, and a plurality of repair driving circuits, each pixel driving circuit row correspondingly comprising at least one repair driving circuit and at least one repair connection line; along a direction perpendicular to the plane of the substrate, the pixel driving circuit rows and the repair connection lines are connected to the display area. The repair driving circuit at least partially overlaps with at least one of the repair connection lines; an active layer and a first transition structure, the first transition structure being located on the side of the active layer away from the substrate; the repair driving circuit includes a data writing transistor, the data writing transistor including a channel and a first electrode located in the active layer, the first transition structure being electrically connected to the first electrode of the data writing transistor; a plurality of the repair driving circuits are arranged along a second direction, and each repair driving circuit is correspondingly provided with at least two repair data lines, the second direction intersecting the first direction; along a direction perpendicular to the plane where the substrate is located, the first transition structure at least partially overlaps with at least two of the repair data lines.

[0005] Based on the same inventive concept, this disclosure also provides a pixel repair method for a display panel, applicable to any of the display panels described above, the method comprising: identifying a defective pixel; disconnecting the electrical connection between the light-emitting element of the defective pixel and the pixel driving circuit; and electrically connecting the light-emitting element of the defective pixel to the corresponding repair connection line.

[0006] Based on the same inventive concept, this disclosure also provides a display device, including the display panel described in any of the above claims.

[0007] The display panel provided in this disclosure enables a repair driving circuit to be equipped with at least two repair data lines. When one repair data line is occupied by another repair driving circuit, the other one or more repair driving lines can also provide data signals to another repair driving circuit independently. This allows the display panel to repair more defective pixels when the same number of repair driving circuits are set, thereby improving the pixel fault tolerance rate of the display panel. Attached Figure Description

[0008] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0009] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0010] Figure 1 A partial schematic diagram of a display panel provided in an embodiment of this application;

[0011] Figure 2 This is a partial wiring diagram of a display panel provided in an embodiment of this application;

[0012] Figure 3 A schematic diagram of the circuit principle of a display panel provided in an embodiment of this application;

[0013] Figure 4 This is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of this application;

[0014] Figure 5 A schematic diagram of the active layer structure of a display panel provided in an embodiment of this application;

[0015] Figure 6 This is a schematic diagram of the first metal layer structure of a display panel provided in an embodiment of this application;

[0016] Figure 7 This is a schematic diagram of a capacitor metal layer structure for a display panel provided in an embodiment of this application;

[0017] Figure 8 This is a schematic diagram of the second metal layer structure of a display panel provided in an embodiment of this application;

[0018] Figure 9 A partial cross-sectional schematic diagram of another display panel provided in an embodiment of this application;

[0019] Figure 10 A schematic diagram of the third metal layer structure of the display panel provided in an embodiment of this application;

[0020] Figure 11 This is a schematic diagram of the working timing of a pixel driving circuit provided in an embodiment of this application;

[0021] Figure 12 This is a schematic diagram of the operating timing of another pixel driving circuit provided in an embodiment of this application;

[0022] Figure 13 This is a schematic diagram of the operating timing of another pixel driving circuit provided in an embodiment of this application;

[0023] Figure 14 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0024] Figure 15 A schematic diagram of the circuit principle of another display panel provided in an embodiment of this application;

[0025] Figure 16 A schematic diagram of the circuit principle of another display panel provided in an embodiment of this application;

[0026] Figure 17 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0027] Figure 18 A partial wiring diagram of another display panel provided in an embodiment of this application;

[0028] Figure 19 A schematic diagram of the circuit principle of another display panel provided in an embodiment of this application;

[0029] Figure 20 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0030] Figure 21 A partial wiring diagram of another display panel provided in an embodiment of this application;

[0031] Figure 22A partial schematic diagram of another display panel provided in an embodiment of this application;

[0032] Figure 23 A partial wiring diagram of another display panel provided in an embodiment of this application;

[0033] Figure 24 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0034] Figure 25 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0035] Figure 26 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0036] Figure 27 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0037] Figure 28 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0038] Figure 29 A partial cross-sectional schematic diagram of another display panel provided in an embodiment of this application;

[0039] Figure 30 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0040] Figure 31 This is an overall schematic diagram of a display panel provided in an embodiment of this application;

[0041] Figure 32 A partial schematic diagram of another display panel provided in an embodiment of this application;

[0042] Figure 33 A schematic flowchart illustrating a pixel repair method for a display panel provided in an embodiment of this application;

[0043] Figure 34 This is a schematic diagram of the structure of a display device provided in an embodiment of this application. Detailed Implementation

[0044] To better understand the above-mentioned objectives, features, and advantages of the embodiments of this disclosure, the solutions of the embodiments of this disclosure will be further described below. It should be noted that, unless otherwise specified, the embodiments of this disclosure and the features within them can be combined with each other.

[0045] Numerous specific details are set forth in the following description in order to provide a full understanding of the embodiments of this disclosure, but the embodiments of this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some embodiments of the embodiments of this disclosure, and not all embodiments.

[0046] One embodiment of this disclosure provides a display panel, including a substrate, a display area AA, and a non-display area NA, so as to... Figure 1 For example, the display area AA includes multiple pixel driving circuit rows 310 and multiple light-emitting elements 32. Each pixel driving circuit row 310 includes multiple pixel driving circuits 31 arranged along a first direction h1, and each pixel driving circuit 31 is electrically connected to at least one light-emitting element 32. Specifically, as... Figure 1 As shown, the display panel also includes multiple signal lines, including a first scan line scan1, a second scan line scan2, a third scan line scan3, a horizontal reset voltage line vref-1, a vertical reset voltage line vref-2, an emission control line emit, a pixel data line 15, and a power supply voltage line PVDD. Each pixel driving circuit 31 is connected to the first scan line scan1, the second scan line scan2, the third scan line scan3, the horizontal reset voltage line vref-1, the emission control line emit, the pixel data line 15, and the power supply voltage line PVDD, and drives the corresponding light-emitting element 32 to emit light.

[0047] exist Figure 1 In this design, each pixel driving circuit 31 and repair driving circuit 20 is also connected to the vertical reset voltage line vref-2, and the vertical reset voltage line vref-2 is electrically connected to the horizontal reset voltage line vref-1, forming a grid design to reduce the loading differences among pixels in the display panel. Therefore, in an actual display panel, not every pixel driving circuit 31 and repair driving circuit 20 needs to be directly connected to the vertical reset voltage line vref-2. Figure 1 The above is only an illustration. The connection relationship between the repair drive circuit 20 and the longitudinal reset voltage line vref-2 in the following embodiments is similar and will not be described again.

[0048] It should be noted that in an actual display panel, the pixel driving circuit 31 can be used to implement various driving methods, thus requiring various settings for the number and type of signal lines (such as setting only two scan lines). Therefore, one pixel driving circuit row 310 can also correspond to other signal line settings. Figure 1 The above is for illustrative purposes only and does not limit the actual signal line settings in the display panel.

[0049] The display panel also includes a repair driving circuit 20 and a repair connection line RL. The repair connection line RL extends along a first direction h1 and along a direction h3 perpendicular to the plane of the substrate. The repair driving circuit 20 and the repair connection line RL at least partially overlap. Specifically, when the pixel driving circuit 31 is working normally, the repair connection line RL corresponding to it only overlaps in the direction h3 perpendicular to the plane of the substrate and is not directly electrically connected. It should be noted that, in order to facilitate the subsequent repair of defective pixels appearing in the display area of ​​the display panel, it is preferable that the connection structure between the pixel driving circuit 31 and the light-emitting element 32 and the repair connection line RL at least partially overlap in the thickness direction of the display panel. The connection structure between the pixel driving circuit 31 and the light-emitting element 32 can be a transition structure that is electrically connected to both the transistor in the pixel driving circuit 31 and the light-emitting element 32. It should be noted that, in this invention, defective pixels refer to light-emitting elements that are electrically connected to the pixel driving circuit and cannot display the correct brightness (i.e., cannot emit light normally). For example, under the same grayscale voltage, defective pixels are displayed as brighter (bright spots) or darker (dark spots) than other normal pixels, or defective pixels cannot be lit up at all (bad pixels).

[0050] Each repair drive circuit 20 is connected to the first scan line scan1, the second scan line scan2, the third scan line scan3, the lateral reset voltage line vref-1, the emission control line emit, and the power supply voltage line PVDD, and drives the corresponding light-emitting element 32 to emit light during repair. The display panel also includes multiple repair data lines 14, and, as Figure 1 As shown, multiple repair drive circuits 20 are arranged along the second direction h2, and each repair drive circuit 20 is provided with at least two repair data lines 14. It should be noted that the corresponding arrangement of the repair drive circuits 20 and the repair data lines 14 can be achieved by the adapter structure in the repair drive circuit 20 that is electrically connected to the data writing transistor and the repair data line 14, which at least partially overlaps in the h3 direction; or the data writing transistor in the repair drive circuit 20 can be electrically connected to the repair data line 14 through the adapter structure.

[0051] It is understandable that, such as Figure 1 As shown, the repair driving circuit 20 and the pixel driving circuit 31 in the corresponding pixel driving circuit row 310 are connected to the same first scan line scan1, second scan line scan2, third scan line scan3, lateral reset voltage line vref-1 and light emission control line emit. Therefore, the repair driving circuit 20 can directly use the scan signal, reset signal and control signal of the defective pixel to drive the corresponding light emission element 32 to emit light.

[0052] This disclosure provides a specific embodiment to illustrate the basic principle of the above-described display panel, such as... Figures 2 to 4 As shown, Figure 2 The layout structure of a portion of the display panel is shown. Figure 3 To and Figure 2 The circuit schematic corresponding to the layout structure. Figure 4 It shows Figure 2 The cross-sectional structure of the display panel cut along B1-B1' is shown. Both the pixel driving circuit 31 and the repair driving circuit 20 include multiple transistors T1-T7 and a first storage capacitor C. The repair driving circuit 20 also includes a transistor T8 and a second storage capacitor C'. The display panel includes a substrate 100 and a driving circuit layer. The pixel driving circuit 31 and the repair driving circuit 20 are both located within the driving circuit layer, and the light-emitting elements are located on the side of the driving circuit layer away from the substrate 100. The driving circuit layer specifically includes, in sequence, an active layer S, a first insulating layer 101, a first metal layer M1, a second insulating layer 102, a capacitor metal layer MC, a third insulating layer 103, a second metal layer M2, a fourth insulating layer 104, a third metal layer M3, and a fifth insulating layer 105. The first metal layer M1, the capacitor metal layer MC, the second metal layer M2, and the third metal layer M3 can be collectively referred to as wiring metal layers, used for routing signal lines or transition structures. The active layer S is located on one side of the substrate 100, the first insulating layer 101 is located on the side of the active layer S away from the substrate 100, the first metal layer M1 is located on the side of the first insulating layer 101 away from the active layer S, the second insulating layer 102 is located on the side of the first metal layer M1 away from the active layer S, the capacitor metal layer MC is located on the side of the second insulating layer 102 away from the first metal layer M1, the third insulating layer 103 is located on the side of the capacitor metal layer MC away from the second insulating layer 102, the second metal layer M2 is located on the side of the third insulating layer 103 away from the capacitor metal layer MC, the fourth insulating layer 104 is located on the side of the second metal layer M2 away from the third insulating layer 103, the third metal layer M3 is located on the side of the fourth insulating layer 104 away from the second metal layer M2, and the fifth insulating layer 105 is located on the side of the third metal layer M3 away from the fourth insulating layer 104.

[0053] For example, in combination Figure 2 , Figure 4 and Figure 5 As shown, Figure 5This is a top view schematic diagram of an active layer provided in an embodiment of the present invention. The active layer S includes a first channel region S10, a first doped region S11 and a second doped region S12 located on both sides of the first channel region S10, a second channel region S20, a third doped region S21 and a fourth doped region S22 located on both sides of the second channel region S20, a third channel region S30, a fifth doped region S301 and a sixth doped region S302 located on both sides of the third channel region S30, two fourth channel regions S40, a seventh doped region S41 and an eighth doped region S42 located on both sides of the two fourth channel regions S40 (and two fourth channel regions S40). The active layer S comprises: a doped region between channel regions S40; two fifth channel regions S50; a ninth doped region S51 and a tenth doped region S52 located on either side of the two fifth channel regions S50 (and the doped region between the two fifth channel regions S50); a sixth channel region S60; an eleventh doped region S61 and a twelfth doped region S62 located on either side of the sixth channel region S60; a seventh channel region S70; a thirteenth doped region S71 and a fourteenth doped region S72 located on either side of the seventh channel region S70; an eighth channel region S80; and a fifteenth doped region S81 and a sixteenth doped region S82 located on either side of the ninth channel region S80. One of the two doped regions located on either side of each channel region is the source region, and the other is the drain region. The source and drain regions are doped with impurities. These impurities include P-type or N-type impurities. For example, the active layer S comprises any one or more of low-temperature polycrystalline silicon, amorphous silicon, and oxide active layers.

[0054] like Figure 2 and Figure 5 As shown, the active layer S also includes a lateral reset voltage line vref-1. For example, the lateral reset voltage line vref-1 is connected to the ninth doped region S51 and the fourteenth doped region S72, respectively. This configuration is equivalent to placing the lateral reset voltage line vref-1 in the active layer S, thus avoiding occupying the space of the wiring metal layer on the side of the active layer S away from the substrate, thereby providing sufficient space in the wiring metal layer above it for laying other signal lines or structures.

[0055] Combination Figure 2 and Figure 6 As shown, Figure 6 This is a top view schematic diagram of a first metal layer M1 provided in an embodiment of the present invention. The first metal layer M1 includes the aforementioned light-emitting control line emit, the first electrode C1 of the first storage capacitor C, the first electrode C1' of the second storage capacitor C', the gate G2 of the data writing transistor T2, the gate G4 of the threshold compensation transistor T4, the gate G5 of the first reset transistor T5, and the gate G7 of the second reset transistor T7. The gate G2 of the data writing transistor T2 and the gate G4 of the threshold compensation transistor T4 can be electrically connected.

[0056] Combination Figure 5 and Figure 6 As shown, along the thickness direction h3 of the display panel, the gate G2 of the data writing transistor T2 overlaps with the second channel region S20. The gate G4 of the threshold compensation transistor T4 overlaps with the fourth channel region S40. The gate G5 of the first reset transistor T5 overlaps with the fifth channel region S50. The gate G7 of the second reset transistor T7 overlaps with the seventh channel region S70. The portions of the emit control line that overlap with the first channel region S10, the sixth channel region S60, and the eighth channel region S80 respectively form the gate G1 of the first light-emitting control transistor T1, the gate G6 of the second light-emitting control transistor T6, and the gate G8 of the repair control transistor T8. The portion of the first plate C1 of the first storage capacitor C that overlaps with the third channel region S30 forms the gate G3 of the driving transistor T3.

[0057] Combination Figure 2 and Figure 7 As shown, Figure 7 This is a top view of a capacitor metal layer provided in an embodiment of the present invention. The capacitor metal layer MC includes the second plate C2 of the first storage capacitor C, the second plate C2' of the second storage capacitor C', and the aforementioned repair connection line RL.

[0058] Combination Figure 2 and Figure 8 As shown, Figure 8 This is a top view schematic diagram of a second metal layer provided in an embodiment of the present invention. The second metal layer M2 includes a first scan line scan1, a second scan line scan2, a third scan line scan3, a first adapter structure X1, a second adapter structure X2, a third adapter structure X3, a fourth adapter structure X4, a fifth adapter structure X5, a sixth adapter structure X6, a ninth adapter structure X9, and a tenth adapter structure X10.

[0059] Combination Figure 2 , Figure 5 and Figure 8 As shown, the first adapter structure X1 is electrically connected to the third doped region scan21 of the data writing transistor T2 of the repair drive circuit 20 located in the active layer S through the fourth adapter via K42.

[0060] Combination Figure 2 , Figure 5 and Figure 8As shown, the first scan line scan1 is electrically connected to the gate G5 of the first reset transistor T5 located in the first metal layer M1 through the first via K1. The second scan line scan2 is electrically connected to the gate G4 of the threshold compensation transistor T4 and the gate G2 of the data write transistor T2 located in the first metal layer M1 through the third via K3. The third scan line scan3 is electrically connected to the gate G7 of the second reset transistor T7 located in the first metal layer M1 through the second via K2.

[0061] Combination Figure 2 , Figure 5 , Figure 7 as well as Figure 8 As shown, the fourth adapter structure X4 is electrically connected to the twelfth doped region S62 of the second light-emitting control transistor T6 in the pixel driving circuit located in the active layer S through the first adapter via Kx1, and as shown... Figure 9 As shown ( Figure 9 It shows Figure 2 The cross-sectional structure of the display panel cut along B2-B2', the fourth transition structure X4 and the repair connection line RL located in the capacitor metal layer MC overlap at least partially in the direction h3 perpendicular to the plane where the substrate is located, and form the second parasitic capacitance Q2.

[0062] Combination Figure 2 , Figure 5 , Figure 7 as well as Figure 8 As shown, the second transition structure X2 is electrically connected to the twelfth doped region S62 of the second light-emitting control transistor T6 in the repair driving circuit located in the active layer S through the second transition via Kx2, and simultaneously overlaps at least partially with the repair connection line RL located in the capacitor metal layer MC in the direction h3 perpendicular to the plane of the substrate. Optionally, the second transition structure X2 can be electrically connected to the repair connection line RL located in the capacitor metal layer MC through a via.

[0063] Combination Figure 2 , Figure 5 , Figure 7 as well as Figure 8 As shown, the third transition structure X3 is electrically connected to the fifteenth doped region S81 of the repair control transistor T8 in the repair drive circuit located in the active layer S through the third transition via Kx3. The third transition structure X3 and the repair connection line RL located in the capacitor metal layer MC at least partially overlap in the direction h3 perpendicular to the plane of the substrate.

[0064] Combination Figure 2 , Figure 6 as well as Figure 8 As shown, the third adapter structure X3 is electrically connected to the first plate C1' of the second storage capacitor C' of the repair drive circuit located in the first metal layer M1 through the ninth via K9.

[0065] Combination Figure 2 , Figure 5 , Figure 6 as well as Figure 8 As shown, the fifth transition structure X5 is electrically connected via the seventh via K7 to the tenth doped region S52 of the first reset transistor T5 in the active layer S and the seventh doped region S41 of the threshold compensation transistor T4. The fifth transition structure X5 is also electrically connected via the eighth via K8 to the first plate C1 of the first storage capacitor C in the first metal layer M1.

[0066] Combination Figure 2 and Figure 10 As shown, Figure 10 This is a top view schematic diagram of a third metal layer provided in an embodiment of the present invention. The third metal layer M3 includes pixel data lines 15, multiple repair data lines 14, a vertical reset voltage line vref-2, a power supply voltage line PVDD, a seventh adapter structure X7, and an eighth adapter structure X8. The vertical reset voltage line vref-2 is electrically connected to the aforementioned horizontal reset voltage line vref-1.

[0067] like Figure 2 , Figure 8 , Figure 9 and Figure 10 As shown, the display panel also includes an anode metal layer RE, which is located on the side of the driving circuit layer away from the substrate 100. The anode of the light-emitting element is located on the anode metal layer RE. The anode of the light-emitting element is electrically connected to the active layer S through the seventh transition structure X7 and the fourth transition structure X4. This avoids the anode metal layer RE from being directly electrically connected to the active layer S through a deep hole. That is, by using the second metal layer M2 and the third metal layer M3 as transition structures and flexibly setting the corresponding vias, the display area of ​​the pixels is avoided, which helps to increase the aperture ratio and improve the display brightness. It should be noted that the eighth transition structure X8 can be electrically connected to the second transition structure X2. The setting of the eighth transition structure X8 can make the etching effect of the edge and center positions in the display area AA more consistent, thereby improving the display uniformity of the display panel. It is understood that in some embodiments, the display panel may not include the eighth transition structure X8.

[0068] Combination Figure 2 , Figure 5 as well as Figure 10As shown, the pixel data line 15 is electrically connected to the ninth transition structure X9 located in the second metal layer M2 through a via. The ninth transition structure X9 is electrically connected to the third doped region scan21 of the data writing transistor T2 of the pixel driving circuit 31 located in the active layer S through a via. This enables the pixel data line 15 located in the third metal layer M3 to be electrically connected to the data writing transistor T2 of the pixel driving circuit located in the active layer S through the nine-transition structure X9, so as to transmit data voltage to the source or drain of the data writing transistor T2.

[0069] Combination Figure 2 , Figure 5 , Figure 8 and Figure 10 As shown, multiple repair data lines 14 at least partially overlap with the first transition structure X1 located in the second metal layer M2 along the direction h3 perpendicular to the plane of the substrate. The first transition structure X1 is electrically connected to the third doped region scan21 of the data writing transistor T2 of the repair driving circuit 20 located in the active layer S through a via, thereby enabling the repair data lines 14 to be electrically connected to the data writing transistor T2 of the repair driving circuit 20 located in the active layer S through the first transition structure X1 when they are electrically connected, so as to transmit data voltage to the source or drain of the data writing transistor T2. Specifically, as Figure 2 as well as Figure 3 As shown, a parasitic capacitance Q3 is formed at the intersection of the repair data line 14 and the first adapter structure X1. Specifically, a parasitic capacitance Q3-1 is formed at the intersection of one repair data line 14-1 and the first adapter structure X1, and a parasitic capacitance Q3-2 is formed at the intersection of the other repair data line 14-2 and the first adapter structure X1.

[0070] Figure 10 Two repair data lines 14 are shown in the third metal layer M3. In specific implementations, when one repair driving circuit 20 corresponds to a larger number of repair data lines 14, such as three or more, all repair data lines 14 corresponding to one repair driving circuit 20 can be located entirely in the third metal layer M3, making the etching effect of each repair data line 14 more consistent, thereby improving the display uniformity of the display panel. Furthermore, as... Figure 3 As shown,

[0071] Combination Figure 2 , Figure 5 , Figure 8 and Figure 10As shown, the lateral reset voltage line vref-1 located in the active layer S is electrically connected to the sixth adapter structure X6 through a via. The sixth adapter structure X6 is electrically connected to the longitudinal reset voltage line vref-2 located in the third metal layer M3 through a via. This realizes that the lateral reset voltage line vref-1 located in the active layer S is electrically connected to the longitudinal reset voltage line vref-2 located in the third metal layer M3 through the sixth adapter structure X6, thus realizing the mesh design of the reset voltage line.

[0072] Combination Figure 2 , Figure 5 as well as Figure 10 As shown, the power supply voltage line PVDD is electrically connected to the tenth transition structure X10 located in the second metal layer M2 through a via. The tenth transition structure X10 is electrically connected to the first doped region S11 of the first light-emitting control transistor T1 located in the active layer S through a via. This enables the power supply voltage line PVDD located in the third metal layer M3 to be electrically connected to the first light-emitting control transistor T1 located in the active layer S through the tenth transition structure X10, so as to transmit the power supply voltage to the source or drain of the first light-emitting control transistor T1. It can be understood that when the power supply voltage line PVDD located in the third metal layer M3 is electrically connected to the second plate C2 located in the capacitor metal layer MC, the second metal layer M2 can also be used for transition, which will not be shown in this embodiment.

[0073] Combination Figure 2 , Figure 7 as well as Figure 10 As shown, the power supply voltage line PVDD is electrically connected to the second plate C2 of the first storage capacitor C and the second plate C2' of the second storage capacitor C' located in the capacitor metal layer MC through the tenth via K10, so as to transmit the power supply voltage to the first storage capacitor C and the second storage capacitor.

[0074] like Figure 2 and Figure 3As shown, the pixel driving circuit 31 includes a driving transistor T3, a data writing transistor T2, a first reset transistor T5, a second reset transistor T7, a threshold compensation transistor T4, a first light-emitting control transistor T1, a second light-emitting control transistor T6, and a first storage capacitor C. Specifically: the first terminal of the first light-emitting control transistor T1 is electrically connected to the power supply voltage line PVDD; the second terminal of the first light-emitting control transistor T1 is electrically connected to the first terminal of the driving transistor T3; and the gate of the first light-emitting control transistor is electrically connected to the light-emitting control line emit. The first terminal of the first reset transistor T5 is electrically connected to the reset voltage line vref; the second terminal of the first reset transistor T5 is electrically connected to the gate of the driving transistor T3; and the gate of the first reset transistor T5 is electrically connected to the first scan line scan1. The first terminal of the threshold compensation transistor T4 is electrically connected to the second terminal of the driving transistor T3; the second terminal of the threshold compensation transistor T4 is electrically connected to the gate of the driving transistor T3; and the gate of the threshold compensation transistor T4 is electrically connected to the second scan line scan2. The first terminal of data writing transistor T2 is electrically connected to pixel data line 15, the second terminal of data writing transistor T2 is electrically connected to the first terminal of driving transistor T3, and the gate of data writing transistor T2 is electrically connected to the second scan line scan2. The second plate of the first storage capacitor C is electrically connected to the power supply voltage line PVDD, and the first plate of the first storage capacitor C is electrically connected to the gate of driving transistor T3. The first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of driving transistor T3, the gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line emit, and the second terminal of the second light-emitting control transistor T6 is electrically connected to the anode of light-emitting element 32. The first terminal of the second reset transistor T7 is electrically connected to the reset voltage line vref, the gate of the second reset transistor T7 is electrically connected to the third scan line scan3, and the second terminal of the second reset transistor T7 is electrically connected to the anode of light-emitting element 32.

[0075] When the pixel driving circuit 31 is working, combined with Figure 2 , Figure 3 and Figure 11 As shown, Figure 11 This is a schematic diagram of the working timing of a pixel driving circuit provided in an embodiment of the present invention. The working process of the pixel driving circuit includes a first reset stage t1, a charging stage t2, a second reset stage t3, and a light emission stage t4.

[0076] In the first reset phase t1, the first scan line scan1 controls the first reset transistor T5 to turn on, and the reference voltage provided by the reset voltage line vref resets the first node N1 through the first reset transistor T5. In the charging phase t2, the second scan line scan2 controls the data writing transistor T2 and the threshold compensation transistor T4 to turn on, and the data voltage Vdata provided by the pixel data line 15 is written to the second node N2 through the data writing transistor T2. In this phase, the driving transistor T3 is turned on. The potential of the first node N1 changes continuously until the potential VN1 of the first node N1 changes to VN1 = Vdata - |Vth|, where Vdata is the data voltage provided by the pixel data line 15 and Vth is the threshold voltage of the driving transistor T3. In the second reset phase t2, the third scan line scan3 controls the second reset transistor T7 to turn on, and the reference voltage provided by the reset voltage line vref resets the fourth node N4 through the second reset transistor T7. During the light-emitting stage t4, the first light-emitting control transistor T1, the second light-emitting control transistor T6, and the driving transistor T3 are turned on. Under the action of the first power supply voltage provided by the power supply voltage line PVDD and the second power supply voltage provided by the second power supply voltage line PVEE, the current path between the power supply voltage line PVDD and the second power supply voltage line PVEE is turned on, and the light-emitting element 32, which is electrically connected to the pixel driving circuit 31, is lit.

[0077] Alternatively, when the pixel driving circuit 31 is working, combined with Figure 2 , Figure 3 and Figure 12 As shown, Figure 12 This is a schematic diagram of the working timing of another pixel driving circuit provided in an embodiment of the present invention. The working process of the pixel driving circuit includes a reset stage t1, a charging stage t2, and a light emission stage t3.

[0078] During the reset phase t1, the first scan line scan1 and the third scan line scan3 control the first reset transistor T5 and the second reset transistor T7 to conduct. The reference voltage provided by the reset voltage line vref resets the first node N1 and the fourth node N4 through the first reset transistor T5 and the second reset transistor T7. During the charging phase t2, the second scan line scan2 controls the data writing transistor T2 and the threshold compensation transistor T4 to conduct. The data voltage Vdata provided by the pixel data line 15 is written to the second node N2 through the data writing transistor T2. During this phase, the driving transistor T3 is turned on. The potential of the first node N1 changes continuously until the potential VN1 of the first node N1 changes to VN1 = Vdata - |Vth|, where Vdata is the data voltage provided by the pixel data line 15 and Vth is the threshold voltage of the driving transistor T3. Simultaneously, during the charging phase t2, the third scan line scan3 controls the second reset transistor T7 to conduct, and the reference voltage provided by the reset voltage line vref resets the fourth node N4 through the second reset transistor T7. During the light-emitting stage t3, the first light-emitting control transistor T1, the second light-emitting control transistor T6, and the driving transistor T3 are turned on. Under the action of the first power supply voltage provided by the power supply voltage line PVDD and the second power supply voltage provided by the second power supply voltage line PVEE, the current path between the power supply voltage line PVDD and the second power supply voltage line PVEE is turned on, and the light-emitting element 32, which is electrically connected to the pixel driving circuit 31, is lit.

[0079] Alternatively, when the pixel driving circuit 31 is working, combined with Figure 2 , Figure 3 As shown, Figure 13 This is a schematic diagram illustrating the operating timing of another pixel driving circuit provided in an embodiment of the present invention. The operation of the pixel driving circuit includes a first reset stage t1-1, a first charging stage t1-2, a second reset stage t2-1, a second charging stage t2-2, a third reset stage t3-1, a third charging stage t3-2, a fourth reset stage t4, and a light-emitting stage t5. In the first reset stage t1-1, the reference voltage provided by the reset voltage line vref resets the first node N1 through the first reset transistor T5; in the second reset stages t2-1 and the third reset stages t3-1, the reference voltage provided by the reset voltage line vref resets the first node N1 through the first reset transistor T5, and the reference voltage provided by the reset voltage line vref resets the fourth node N4 through the second reset transistor T7; in the fourth reset stage t4, the reference voltage provided by the reset voltage line vref resets the fourth node N4 through the second reset transistor T7. Figure 11 and Figure 12 compared to, Figure 13In the illustrated timing diagram, by resetting the first node N1 and the fourth node N4 multiple times and writing data to the first node N1 multiple times, the flickering of the display panel at low grayscale can be minimized.

[0080] like Figure 2 and Figure 3 As shown, the repair driving circuit 20 includes a driving transistor T3, a data writing transistor T2, a first reset transistor T5, a second reset transistor T7, a threshold compensation transistor T4, a first light-emitting control transistor T1, a second light-emitting control transistor T6, and a first storage capacitor C. Specifically: the first terminal of the first light-emitting control transistor T1 is electrically connected to the power supply voltage line PVDD; the second terminal of the first light-emitting control transistor T1 is electrically connected to the first terminal of the driving transistor T3; and the gate of the first light-emitting control transistor is electrically connected to the light-emitting control line emit. The first terminal of the first reset transistor T5 is electrically connected to the reset voltage line vref; the second terminal of the first reset transistor T5 is electrically connected to the gate of the driving transistor T3; and the gate of the first reset transistor T5 is electrically connected to the first scan line scan1. The first terminal of the threshold compensation transistor T4 is electrically connected to the second terminal of the driving transistor T3; the second terminal of the threshold compensation transistor T4 is electrically connected to the gate of the driving transistor T3; and the gate of the threshold compensation transistor T4 is electrically connected to the second scan line scan2. When the repair driving circuit 20 participates in pixel repair, the first terminal of the data writing transistor T2 is electrically connected to one of the multiple repair data lines 14, the second terminal of the data writing transistor T2 is electrically connected to the first terminal of the driving transistor T3, and the gate of the data writing transistor T2 is electrically connected to the second scan line scan2. The second plate of the first storage capacitor C is electrically connected to the power supply voltage line PVDD, and the first plate of the first storage capacitor C is electrically connected to the gate of the driving transistor T3. The first terminal of the second light-emitting control transistor T6 is electrically connected to the second terminal of the driving transistor T3, and the gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting control line emit.

[0081] like Figure 2 As shown, in the repair driving circuit 20, the second terminal of the second light-emitting control transistor T6 is electrically connected to the second transition structure X2, and the second transition structure X2 overlaps with the repair connection line RL along the direction h3 perpendicular to the plane of the substrate. In another embodiment, the second transition structure X2 and the repair connection line RL can also be directly electrically connected through a via.

[0082] like Figure 2As shown, in the repair drive circuit 20, the first terminal of the second reset transistor T7 is electrically connected to the lateral reset voltage line vref-1, and the third terminal of the second reset transistor T7 is electrically connected to the third transition structure X3. The third transition structure X3 overlaps with the repair connection line RL along the direction h3 perpendicular to the plane of the substrate, forming the first parasitic capacitance Q1. Furthermore, combined with... Figure 2 and Figure 3 The second parasitic capacitance Q2 is formed at the intersection of the connecting line 14 and the first adapter structure X1. Figure 3 In the process, the intersection of the repair connection line 14 corresponding to the repair driving circuit 20 and the first transition structure X1 in a pixel driving circuit 31-1 forms a second parasitic capacitor Q2-1, and the intersection of the repair connection line 14 corresponding to the repair driving circuit 20 and the first transition structure X1 in another pixel driving circuit 31-2 forms a second parasitic capacitor Q2-2.

[0083] When the repair driving circuit 20 participates in pixel repair, its operating timing is the same as that of the pixel driving circuit 31, and will not be described again.

[0084] like Figure 2 and Figure 3 As shown, the repair drive circuit 20 also includes a second storage capacitor C', the second plate of the second storage capacitor C' is electrically connected to the power supply voltage line PVDD, and the first plate of the second storage capacitor C' is electrically connected to the second electrode of the second reset transistor M7.

[0085] The capacitance of the second storage capacitor C' is typically larger than that of the first storage capacitor C, for example, the second storage capacitor C' is 3-5 times larger than that of the first storage capacitor C. When the repair driving circuit 20 participates in pixel repair, that is, when the repair driving circuit 20 is used to drive the light-emitting element 32 to emit light, the setting of the second storage capacitor C' can make the repaired light-emitting element turn on more slowly than other normal light-emitting elements, thereby suppressing the phenomenon of bright spots in the light-emitting element when displaying at low grayscale.

[0086] like Figure 2 and Figure 3 As shown, the repair drive circuit 20 also includes a repair control transistor M8. The first terminal of the repair control transistor M8 is electrically connected to the second terminal of the second reset transistor M7. The second terminal of the repair control transistor M8 is electrically connected to the second terminal of the second light-emitting control transistor M6 and the repair connection line RL. The gate of the repair control transistor M8 is electrically connected to the light-emitting control line emit.

[0087] The repair control transistor M8 is used to prevent the reference voltage provided by the lateral reset voltage line vref-1 from being repeatedly written into the parasitic capacitance on the repair connection line RL during stages other than the light emission stage when the repair drive circuit 20 does not participate in pixel repair. This avoids repeated charging and discharging of the repair connection line RL and saves power.

[0088] like Figure 14 As shown, combined with Figure 2 and Figure 3 When a pixel driving circuit 31-1 in the display panel malfunctions, causing the corresponding light-emitting element 32-1 to fail to emit light properly, it is necessary to use the repair connection line RL corresponding to the pixel driving circuit 31-1 and the repair driving circuit 20-1 to drive the light-emitting element 32-1 to emit light. Specifically, as follows... Figure 14 As shown, when the pixel driving circuit 31-1 malfunctions, the electrical connection between the light-emitting element 32-1 and the pixel driving circuit 31-1 needs to be disconnected first. Specifically, the electrical connection between the light-emitting element 32-1 and the second light-emitting control transistor T6 needs to be disconnected, and then the repair connection line RL needs to be connected to... Figure 2 The fourth adapter structure X4 shown is fused at its overlapping point, realizing the electrical connection between the repair connection line RL and the light-emitting element 32-1. This enables the repair driving circuit 20-1 to drive the light-emitting element 32-1 to emit light through the repair connection line RL. The circuit schematic diagram of the repair driving circuit 20 participating in pixel repair is shown below. Figure 15 As shown, combined with Figure 2 , Figure 3 and Figure 14 The parasitic capacitances Q1 and Q2-1 formed at the intersection of the repair connection line RL and the pixel driving circuit 20 and the repair driving circuit 31-1 are fused together as wires. The parasitic capacitance Q2-2 still forms at the intersection between the repair connection line RL and several other normal pixel driving circuits 31-2. At this time, if the repair driving circuit 20-1 has already been electrically connected to a repair data line 14-1, the repair driving circuit 20-1 can directly utilize the data signal provided by the repair data line 14-1; if the repair driving circuit 20-1 overlaps with multiple repair data lines 14 in the h3 direction, such as... Figure 2 As shown, the repair drive circuit 20-1 can be electrically connected to one of the repair data lines 14-1, allowing the repair drive circuit 20-1 to utilize the data signal provided by the repair data line 14-1. Thus, when a small number of defective pixels appear in the display panel, repair can be performed directly using the repair drive circuit 20-1 and the electrically connected repair data line 14-1, eliminating the need to fuse the repair drive circuit 20-1 and the repair data line 14-1. This reduces the number of steps in the repair process and improves production efficiency.

[0089] like Figure 2 as well as Figure 14 As shown, when the repair driving circuit 20-1 participates in pixel repair, in addition to electrically connecting the light-emitting element 32-1 to the repair connection line RL, it is also necessary to electrically connect the repair driving circuit 20-1 to the repair connection line RL. That is, it is also necessary to weld the second adapter structure X2 and the third adapter structure X3 at the intersection with the repair connection line RL (in the embodiment where the second adapter structure X2 is already electrically connected to the repair connection line RL, it is only necessary to weld the third adapter structure X3 at the intersection with the repair connection line RL).

[0090] In related technologies, multiple repair driving circuits arranged along a column direction share a single repair data line. When one of the repair driving circuits participates in pixel repair, this repair data line copies the data signal corresponding to the defective pixel (hereinafter referred to as the first defective pixel) and provides this data signal to the participating repair driving circuit, enabling the repair driving circuit to drive the light-emitting element of the first defective pixel to emit light using the corresponding data signal. At this time, multiple repair driving circuits arranged along a column direction receive the same data signal through this repair data line, meaning the repair data line is occupied. When another defective pixel (hereinafter referred to as the second defective pixel) appears in another row of pixel driving circuits, especially when the second defective pixel and the first defective pixel are in different columns, even if the repair driving circuit corresponding to the second defective pixel is not occupied, the second defective pixel cannot be repaired because the data signal received by the repair driving circuit cannot correspond to it.

[0091] In view of this, the display panel provided in this disclosure, by configuring at least two repair data lines for each repair driving circuit, allows one or more repair driving lines to independently provide data signals to another repair driving circuit even when one repair data line is occupied by another repair driving circuit. This enables the display panel to repair more defective pixels with the same number of repair driving circuits, thereby improving the pixel fault tolerance rate of the display panel. Specifically, as... Figure 14 As shown, when the pixel driving circuit 31-1 malfunctions, and the repair driving circuit 20-1 replaces the pixel driving circuit 31-1 to drive the light-emitting element 32-1 to emit light, the repair driving circuit 20-1 is electrically connected to a repair data line 14-1 and receives the data signal corresponding to the pixel driving circuit 31-1 provided by the repair data line 14-1. Simultaneously, if the pixel driving circuit 31-2 in another pixel driving circuit row also malfunctions, the corresponding repair driving circuit 20-2 can be used to replace the pixel driving circuit 31-2 to drive the light-emitting element 32-2 to emit light. The repair driving circuit 20-2 can be electrically connected to another repair data line 14-2 and receive the data signal corresponding to the pixel driving circuit 31-2 provided by the repair data line 14-2. Thus, both defective pixels in the display panel can be repaired.

[0092] It should be noted that, in Figure 14 In the illustrated embodiment, the multiple defective pixel driving circuits 31 are located in different columns. Figure 14 For illustrative purposes only, in a specific implementation of this disclosure, when multiple defective pixel driving circuits 31 are located in the same column, a single repair data line 14 can be used to provide data signals to the light-emitting elements 32 of the multiple pixel driving circuits 31 located in the same column, or multiple data lines 14 can be used to provide data signals to the light-emitting elements 32 of the multiple pixel driving circuits 31 located in the same column respectively.

[0093] Specifically, in Figure 1 and Figure 2 In the embodiment shown, each repair data line 14 overlaps with the repair drive circuit 20 only in the h3 direction. When the repair drive circuit 20 participates in the repair, it needs to be electrically connected to any one of the repair data lines 14.

[0094] It should be noted that, Figures 1 to 14 In this circuit, one repair drive circuit 20 corresponds to two repair data lines 14, but... Figures 1 to 14 For illustrative purposes only, in an actual display panel, one repair drive circuit 20 can correspond to a larger number of repair data lines 14. The same applies to the following embodiments, and will not be described again.

[0095] Figures 1 to 3 In the pixel driving circuit 31 and the repair driving circuit 20 shown, the lateral reset voltage line vref-1 and the vertical reset voltage line vref-2 are electrically connected, so the first reset transistor T5 and the second reset transistor T7 have the same reset voltage. In another embodiment, the lateral reset voltage line vref-1 and the vertical reset voltage line vref-2 can be insulated from each other, thereby transmitting different reset voltages, such as... Figure 16 As shown, the first reset transistor T5 is electrically connected to the first reset voltage line vref1, and the second reset transistor T7 is electrically connected to the second reset voltage line vref2. Those skilled in the art can, without inventive effort, based on other content of this embodiment and... Figure 16 The circuit schematic shown is implemented with the corresponding circuit layout, which will not be elaborated on here.

[0096] Optionally, the first insulating layer 101 comprises an inorganic material, such as at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide.

[0097] Optionally, the second insulating layer 102 comprises an inorganic material, such as at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. In some embodiments, the second insulating layer 102 may comprise multiple inorganic layers.

[0098] Optionally, the third insulating layer 103 comprises an inorganic material, such as at least one of silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide. In some embodiments, the third insulating layer 103 may comprise multiple inorganic layers.

[0099] Optionally, the fourth insulating layer 104 comprises an organic insulating material, such as at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. In some embodiments, the fourth insulating layer 104 may comprise multiple organic layers.

[0100] Optionally, the fifth insulating layer 105 comprises an organic insulating material, such as at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin. In some embodiments, the fifth insulating layer 105 may comprise multiple organic layers.

[0101] In some embodiments, such as Figures 17 to 19 As shown, Figure 17 A schematic diagram of part of the display panel is shown. Figure 18 The layout structure of a portion of the display panel is shown. Figure 19 To and Figure 18 The circuit schematic corresponding to the layout structure. Multiple repair data lines include a first repair data line 141 and a second repair data line 142. The first adapter structure includes a first sub-connection part X11 and a second sub-connection part X12 that are electrically connected. The repair drive circuit 20 is electrically connected to a first repair data line 141 through the first sub-connection part X11, and along the direction h3 perpendicular to the plane where the substrate is located, the second sub-connection part X12 at least partially overlaps with at least one second repair data line 142.

[0102] Specifically, since the repair driving circuit 20 is pre-connected to a repair data line 14, when a first defective pixel appears in one of the multiple pixel driving circuits 31 corresponding to the multiple repair driving circuits 20 arranged along the second direction h2, and the repair driving circuit 20 participates in the repair of the first defective pixel, it is unnecessary to connect the repair data line 14 to the repair driving circuit 20 again, thus simplifying the circuit repair process. When a defective pixel reappears in one of the multiple pixel driving circuits corresponding to the multiple repair driving circuits arranged along the second direction h2, taking the second defective pixel as an example, ... Figure 20 As shown, the repair driving circuit 20-1 corresponding to the light-emitting element 32-1 of the first defective pixel has already occupied the first repair data line 141. Therefore, the repair driving circuit 20-2 corresponding to the light-emitting element 32-2 of the second defective pixel needs to first disconnect its electrical connection with the first repair data line 141. Specifically, it can be done in... Figure 18The electrical connection between the repair drive circuit 20-2 and the first repair data line 141 is disconnected at the first sub-connection part X11 shown in the figure. Then, the repair drive circuit 20-2 corresponding to the second defective pixel is electrically connected to the second repair data line 142. Specifically, the parasitic capacitance Q3 formed at the intersection of the second sub-connection part X12 of the repair drive circuit 20-2 and the second repair data line 142 can be fused into a wire, so that the repair drive circuit 20-2 can receive the data signal provided by the second repair data line 142 and participate in the repair of the second defective pixel.

[0103] Specifically, such as Figure 18 As shown, both the first sub-connection part X11 and the second sub-connection part X12 can be located in the second metal layer M2, and are disposed in a different layer from the first repair data line located in the third metal layer M3 via 141 and the second repair data line 142. The specific connection method between the first sub-connection part X11 and the second sub-connection part X12 and the repair driving circuit 20 can be referred to the connection method between the first adapter structure X1 and the repair driving circuit 20 in the above embodiment, and will not be repeated here.

[0104] In some embodiments, such as Figure 21 As shown, the first sub-connection portion X11 can be located in the second metal layer M2, and the second sub-connection portion X12 can be located in the capacitor metal layer MC. The first sub-connection portion X11 and the second sub-connection portion X12 are disposed in different layers. Specifically, the first adapter structure may further include Figure 21 The third sub-connection portion X13 shown is located in the second metal layer M2. One third sub-connection portion X13 is electrically connected to a second repair data line 142 and overlaps with the second sub-connection portion X12 in the direction h3 perpendicular to the plane of the substrate, so that the second repair data line 142 can be electrically connected to the second sub-connection portion X12 through the third sub-connection portion X13.

[0105] It should be noted that, Figures 17 to 19 In this circuit, a repair drive circuit 20 is provided with a first repair data line 141 and a second repair data line 142. Figure 21 In this circuit, a repair drive circuit 20 is configured with one first repair data line 141 and two second repair data lines 142, but... Figures 17 to 21 For illustrative purposes only, in an actual display panel, one repair drive circuit 20 can correspond to a larger number of second repair data lines 142. The same applies to the following embodiments, and will not be described again.

[0106] In some embodiments, such as Figure 21 as well as Figure 23As shown, the display panel includes multiple repair drive circuit groups 200 arranged along the second direction h2. Each drive circuit group 200 includes at least one repair drive circuit 20. The repair drive circuits 20 within the same repair drive circuit group 200 are electrically connected to the same repair data line 14 through corresponding first adapter structures X1. The repair drive circuits 20 within different repair drive circuit groups 200 are electrically connected to different repair data lines 14 through corresponding first adapter structures X1. Specifically, Figure 22 The first repair drive circuit group 200-1 and the second repair drive circuit group 200-2 are shown. Figure 23 The layout structures of repair drive circuit 20-1 located in the first repair drive circuit group 200-1 and repair drive circuit 20-2 located in the second repair drive circuit group 200-2 are shown.

[0107] Since each repair drive circuit is pre-connected to a repair data line, when a few defective pixels appear in the display panel, the repair drive circuit 20 and the repair data line 14 electrically connected to it can be directly used for repair without having to fuse the repair drive circuit 20 and the repair data line 14. This reduces the number of operation steps in the repair process and improves production efficiency.

[0108] When a second defective pixel appears in the display panel, if the repair driving circuits corresponding to the first defective pixel and the second defective pixel are located in different repair driving circuit groups 200, such as Figure 22 The pixel driving circuit 31-1 for the first defective pixel and the pixel driving circuit 31-2 for the second defective pixel shown are shown. The repair driving circuit 20-2 corresponding to the second defective pixel can directly use the data signal provided by the repair data line 14-2 that is electrically connected to it to participate in pixel repair without performing circuit breaking and welding operations, which further simplifies the circuit repair process.

[0109] If the repair driving circuits corresponding to the first defective pixel and the second defective pixel are located in the same repair driving circuit group, refer to Figures 17 to 21 The circuit repair shown in the embodiment will not be described in detail here.

[0110] In some embodiments, such as Figure 24 As shown, the repair driving circuit 20 is located in the non-display area NA of the display panel. The non-display area NA also includes a virtual pixel driving circuit 40, which is located on the side of the repair driving circuit 20 away from the display area AA.

[0111] During the manufacturing process of a display panel, conductive materials (conductive parts in the pixel structure, such as the gate, source, and drain of transistors, capacitor plates, signal lines, and anodes of light-emitting elements) need to be etched. To improve the consistency of the etching environment at the edges and center of the display area AA, when forming a pixel driving circuit 20 in each display area AA, a virtual pixel driving circuit 40 is simultaneously formed in the non-display area NA adjacent to the display area AA. This makes the etching effect at the edges and center of the display area AA more consistent, thereby improving the display uniformity of the display panel.

[0112] The virtual pixel driving circuit 40 typically cannot drive the light-emitting element to emit light, for various reasons. For example, the display panel may not have a light-emitting element electrically connected to the virtual pixel driving circuit 40; or there may be a light-emitting element, but the pixel definition layer between the anode and cathode of the light-emitting element has not been removed; or the virtual pixel driving circuit 40 may lack certain structures compared to the normal pixel driving circuit 20, preventing it from functioning properly. Understandably, the virtual pixel driving circuit 40 can also be configured to have the exact same structure as the pixel driving circuit, but it will still be unable to drive the light-emitting element to emit light.

[0113] Virtual pixel driving circuits are typically positioned around the display pixels in the display area, and can be arranged in multiple rows or columns, depending on the needs of the display panel. It's understandable that when the repair driving circuit drives the light-emitting elements within the display area, its function is equivalent to that of the display pixel driving circuit. Therefore, the virtual pixel driving circuit can be positioned either closer to the display area or further away from it, depending on the specific requirements. Figure 23 The virtual pixel driving circuit is shown only on the side of the repair driving circuit that is far from the display area.

[0114] It is understandable that when the repair driving circuit is not used to drive the light-emitting elements in the display area to emit light, it can be reused as a virtual pixel driving circuit and achieve the same effect as the virtual pixel driving circuit.

[0115] like Figure 25 As shown, in some embodiments, the repair driving circuit 20 is located in the display area AA of the display panel, and the non-display area NA includes the virtual pixel driving circuit described above.

[0116] The repair drive circuit 20 is located within the display area AA, which can reduce the bezel width of the display panel to some extent. Furthermore, since the display panel provided by this invention can be used in medium-sized products (such as laptops, tablets, and in-vehicle displays), there is ample space in the display area to house the repair drive circuit 20 without affecting the display effect.

[0117] like Figure 26 As shown, the display panel also includes a peripheral driving circuit 50. Along the direction h3 perpendicular to the plane where the substrate is located, each repair data line 14 overlaps at least partially with the peripheral driving circuit 50 and is electrically connected to the adapter cable 140. The adapter cable 140 overlaps at least partially with the repair driving circuit 20 along the direction h3 perpendicular to the plane where the substrate is located, so that the repair driving circuit 20 can be electrically connected to the repair data line 14 through the adapter cable 140, while saving the wiring area of ​​the non-display area NA and reducing the bezel width of the display panel.

[0118] In one embodiment, such as Figure 27 As shown in Figure 28, the peripheral driving circuit specifically includes an emission control circuit 51 connected to the emission control line, a first scan control circuit 52 connected to the first scan line scan1, a second scan control circuit 53 connected to the second scan line scan2, and a third scan control circuit 54 connected to the third scan line scan3. When the non-display area NA includes the repair driving circuit 20, the aforementioned emission control circuit 51, first scan control circuit 52, second scan control circuit 53, and third scan control circuit 54 are all located on the side of the repair driving circuit 20 away from the display area AA.

[0119] In one embodiment, reference Figure 1 and Figure 27 As shown, the light-emitting control circuit 51 receives the input signal in1 and provides a light-emitting control signal to the light-emitting control line emit according to the first input signal in1. The first scan control circuit 52 receives the input signal in2 and provides a first scan control signal to the first scan line scan1 according to the input signal in2. The second scan control circuit 53 receives the input signal in3 and provides a second scan control signal to the second scan line scan2 according to the input signal in3, wherein the input signal in3 received by the second scan control circuit 53 is the first scan control signal output by the first scan control circuit 52. The third scan control circuit 54 receives the input signal in4 and provides a third scan control signal to the third scan line scan3 according to the input signal in4. The signal timing provided by the light-emitting control circuit 51, the first scan control circuit 52, the second scan control circuit 53, and the third scan control circuit 54 can be referenced. Figure 11 , Figure 12 or Figure 13 The peripheral driving circuits corresponding to different pixel circuit driving rows 310 transmit the corresponding input signals through cascading, and provide the corresponding light emission control signal, first scan control signal, second scan control signal and third scan control signal to each pixel circuit driving row 310 in sequence according to the direction of input signal cascading.

[0120] In another embodiment, reference Figure 1 and Figure 28 The light-emitting control circuit 51 receives the input signal in1 and provides a light-emitting control signal to the light-emitting control line emit according to the input signal in1. The first scan control circuit 52 receives the input signal in2 and provides a first scan control signal to the first scan line scan1 according to the input signal in2. The second scan control circuit 53 receives the input signal in3 and provides a second scan control signal to the second scan line scan2 according to the input signal in3. The third scan control circuit 54 receives the input signal in4 and provides a third scan control signal to the third scan line scan3 according to the input signal in4. Figure 27 The difference is that, in Figure 28 In the illustrated embodiment, the input signal in3 received by the second scan control circuit 53 is independent of the second input signal in2 and the first scan control circuit 52. The signals provided by the light emission control circuit 51, the first scan control circuit 52, the second scan control circuit 53, and the third scan control circuit 54 can be referenced. Figure 11 , Figure 12 or Figure 13 The peripheral driving circuits corresponding to different pixel circuit driving rows 310 transmit the corresponding input signals through cascading, and provide the corresponding light emission control signal, first scan control signal, second scan control signal and third scan control signal to each pixel circuit driving row 310 in sequence according to the direction of input signal cascading.

[0121] In some embodiments, such as Figure 29 and Figure 30 As shown ( Figure 30 The pixel driving circuit 31 and the repair driving circuit 20 are shown in a simplified form. For the detailed circuit structure, please refer to [reference needed]. Figure 2 Along the direction h3 perpendicular to the plane where the substrate 100 is located, a repair drive circuit 20 located in the display area AA overlaps at least partially with at least one light-emitting element 32.

[0122] Since the repair driving circuit 20 is located on the driving circuit layer and does not have a directly corresponding light-emitting element, a light-emitting element 32 can be placed above the repair driving circuit 20, such as... Figure 28 As shown, this increases the aperture ratio of the display panel and improves the display effect.

[0123] Specifically, such as Figure 29As shown, the display panel also includes a light-emitting material layer 321 and a cathode metal layer 322. After the light-emitting material layer 321 comes into contact with the anode metal layer RE and the cathode metal layer 322, it can emit light through the current provided by the anode metal layer RE and the cathode metal layer 322. The light-emitting material layer 321, the anode metal layer RE, and the cathode metal layer 322 together constitute the light-emitting element 32. The display panel also includes a sixth insulating layer 106 and an encapsulation layer 107. The sixth insulating layer 106 is located on the side of the anode metal layer RE away from the substrate 100, and the sixth insulating layer 106 is used to define the light-emitting area of ​​the pixel; the encapsulation layer 107 is located on the side of the cathode metal layer 322 away from the substrate 100.

[0124] In some embodiments, the sixth insulating layer 106 comprises an organic insulating material, such as at least one selected from acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin. In some embodiments, the sixth insulating layer 106 may include multiple organic layers. The encapsulation layer 107 typically includes at least one inorganic encapsulation layer and at least one organic layer, and when the encapsulation layer 107 comprises multiple stacked encapsulation layers, an inorganic encapsulation layer closest to the display film layer provides better water and oxygen barrier properties.

[0125] Specifically, such as Figure 30 As shown, the display panel includes a first light-emitting element 32-1, a second light-emitting element 32-2, and a third light-emitting element 32-3. The first light-emitting element 32-1, the second light-emitting element 32-2, and the third light-emitting element 32-3 are blue, green, and red light-emitting elements, respectively, and together they constitute a display pixel.

[0126] It should be noted that, Figure 30 In the process, the pixel driving circuit 31 also overlaps with the light-emitting element 32 at least partially in the h3 direction, but the overlapping portion of the pixel driving circuit 31 and the light-emitting element 32 does not include the pixel driving circuit 31 (specifically, Figure 2 The overlapping portion of the fourth adapter structure X4 shown with the repair connection line RL prevents the light-emitting element 32 in the pixel driving circuit 31 from being unable to be electrically connected to the repair connection line RL during pixel repair.

[0127] In some embodiments, such as Figure 31 as well as Figure 32 As shown, the display panel includes a first region A1. In the first region A1, the number of pixel driving circuits 31 in two adjacent pixel driving circuit rows 310 along the second direction h2 is not equal. Specifically, the cutoff positions of the pixel driving circuit rows 310 may be different in the second direction h2. In the first region A1, the repair driving circuits 20 at least partially overlap along the second h2.

[0128] To accommodate other electronic components, such as cameras, within the display panel, the actual display panel may have an irregular shape. In the irregular area (i.e., the first area A1 mentioned above), the boundary L1 between the display area and the non-display area is diagonal, resulting in an unequal number of pixel driving circuits in adjacent pixel driving circuit rows. However, the repair driving circuit in the irregular area does not need to be adjacent to a pixel driving circuit row. The repair driving circuit in the irregular area can be arranged along the second direction h2, just like the repair driving circuit in the regular area. This simplifies the circuit routing, especially for multiple data repair lines, by allowing them to run in a straight line through the irregular area.

[0129] In some embodiments, the pixel driving circuit 31 and the repair driving circuit 20 have the same projected area along the direction h3 perpendicular to the plane where the substrate 100 is located.

[0130] Specifically, when the repair driving circuit 20 and the pixel driving circuit 31 have the same circuit structure, they can be used to drive the light-emitting element 32 to emit light. In this case, the pixel driving circuit 31 and the repair driving circuit 20 have the same projected area, which facilitates the layout of the circuit in the driving circuit layer and the manufacturing of the display panel. Furthermore, when the pixel driving circuit 31 is located in the display area AA, the identical circuit structure of the repair driving circuit 20 and the pixel driving circuit 31 makes the etching effect of the circuit in the display area AA more consistent, thereby improving the display uniformity of the display panel.

[0131] Based on the same inventive concept, corresponding to the above-described display panel embodiments, one embodiment of this disclosure also provides a pixel repair method for a display panel, such as... Figure 33 As shown, it includes:

[0132] Step 101: Identify defective pixels.

[0133] Specifically, the light-emitting element with abnormal light emission can be identified first, and then the pixel corresponding to the light-emitting element can be identified as the aforementioned defective pixel.

[0134] Step 102: Disconnect the electrical connection between the light-emitting element of the defective pixel and the pixel driving circuit.

[0135] Specifically, such as Figure 14 As shown, when a pixel driving circuit 31-1 in the display panel malfunctions, causing the corresponding light-emitting element 32-1 to fail to emit light normally, it is necessary to use the repair connection line 14-1 and the repair driving circuit 20-1 corresponding to the pixel driving circuit 31-1 to drive the light-emitting element 32-1 to emit light. Specifically, as... Figure 14 As shown, when the pixel driving circuit 31-1 malfunctions, the electrical connection between the light-emitting element 32-1 and the pixel driving circuit 31-1 needs to be disconnected first. Specifically, as shown... Figure 3 As shown, it is necessary to disconnect the electrical connection between the light-emitting element 32 and the sixth transistor, the second light-emitting control transistor T6, while retaining the electrical connection between the light-emitting element 32 and the seventh transistor, the second reset transistor T7, thereby simplifying the process flow during pixel repair.

[0136] Step 103: Connect the light-emitting element of the defective pixel to the corresponding repair connection line.

[0137] Specifically, such as Figure 2 As shown, Step 103 specifically includes fusing the overlap between the repair connection line 14 and the fourth adapter structure X4. Since the fourth adapter structure X4 is electrically connected to the anode RE of the light-emitting element 32, the repair connection line RL can be electrically connected to the anode RE of the light-emitting element 32 through the fourth adapter structure X4. The electrical connection between the two components in the display panel can be achieved through laser welding.

[0138] In one embodiment, the method further includes:

[0139] Step 104: Connect the light-emitting element of the defective pixel to the corresponding repair driving circuit and the corresponding repair connection line.

[0140] like Figure 2 as well as Figure 14 As shown, when the repair driving circuit 20-1 participates in pixel repair, in addition to electrically connecting the light-emitting element 32-1 to the repair connection line RL, it is also necessary to electrically connect the repair driving circuit 20-1 to the repair connection line RL. That is, it is also necessary to weld the second adapter structure X2 and the third adapter structure X3 at the intersection with the repair connection line RL (in the embodiment where the second adapter structure X2 is already electrically connected to the repair connection line RL, it is only necessary to weld the third adapter structure X3 at the intersection with the repair connection line RL).

[0141] Furthermore, since the eighth transistor, the repair control transistor T8, is used to prevent the reference voltage provided by the lateral reset voltage line vref-1 from being repeatedly written into the parasitic capacitance on the repair connection line RL during stages other than the light emission stage when the repair drive circuit 20 does not participate in pixel repair, the eighth transistor, the repair control transistor T8, can not participate in pixel repair. Figure 15 As shown, after the first parasitic capacitor Q1 is fused into a wire, the eighth transistor repair control transistor T8 can be short-circuited, preventing it from participating in pixel repair.

[0142] Specifically, in Figure 1 and Figure 2 In the embodiment shown, when each repair data line 14 corresponding to the repair drive circuit 20 overlaps with it only in the h3 direction, the above method further includes:

[0143] Step 105: Connect the repair drive circuit 20 to a repair data line 14 via the first adapter structure X1, specifically by welding the overlap between the repair data line 14 and the first adapter structure X1.

[0144] In some embodiments, such as Figures 17 to 19 As shown, the multiple repair data lines include a first repair data line 141 and a second repair data line 142. The first adapter structure includes a first sub-connection portion X11 and a second sub-connection portion X12 that are electrically connected. The repair driving circuit 20 is electrically connected to a first repair data line 141 through the first sub-connection portion X11, and along the direction h3 perpendicular to the plane where the substrate is located, the second sub-connection portion X12 at least partially overlaps with at least one second repair data line 142. The above method also includes:

[0145] Step 201: Determine the first defective pixel.

[0146] Step 202: Disconnect the electrical connection between the first defective pixel and the corresponding pixel driving circuit, and connect the first defective pixel to the corresponding repair connection line so that the repair driving circuit corresponding to the first defective pixel receives the data signal provided by the first repair data line.

[0147] Since the repair driving circuit 20 is pre-connected to a first repair data line 141, when the first defective pixel (i.e. the first defective pixel mentioned above) appears in the multiple pixel driving circuits 31 corresponding to the multiple repair driving circuits 20 arranged along the second direction h2, the repair driving circuit 20 participates in the repair of the first defective pixel without having to connect the repair data line to the repair driving circuit, thus simplifying the circuit repair process.

[0148] Step 203: Determine the second defective pixel.

[0149] Step 204: Disconnect the electrical connection between the second defective pixel and the corresponding pixel driving circuit, and then connect the second defective pixel to the corresponding repair connection line.

[0150] Step 205: Disconnect the electrical connection between the repair driving circuit corresponding to the second defective pixel and the first repair data line.

[0151] Step 206: Connect the repair driving circuit corresponding to the second defective pixel to a second repair data line so that the repair driving circuit corresponding to the second defective pixel receives the data signal provided by the second repair data line.

[0152] When a defective pixel reappears in one of the multiple pixel driving circuits 31 corresponding to the multiple repair driving circuits 20 arranged along the second direction h2, and this defective pixel is located in a different column than the first defective pixel, taking the second defective pixel (i.e., the second defective pixel) as an example, Figure 20 As shown, the repair driving circuit 20-1 corresponding to the first defective pixel has already occupied the first repair data line 141. Therefore, the repair driving circuit 20-2 corresponding to the second defective pixel needs to first disconnect its electrical connection with the first repair data line 141. Specifically, this can be done by... Figure 18 The electrical connection between the repair drive circuit 20-2 and the first repair data line 141 is disconnected at the first sub-connection part X11 shown in the figure. Then, the repair drive circuit 20-2 corresponding to the second defective pixel is electrically connected to the second repair data line 142. Specifically, the parasitic capacitance Q3 formed at the intersection of the second sub-connection part X12 of the repair drive circuit 20-2 and the second repair data line 142 can be fused into a wire, so that the repair drive circuit 20-2 can receive the data signal provided by the second repair data line 142 and participate in the repair of the second defective pixel.

[0153] Specifically, the first transition structure may also include Figure 21 The third sub-connection portion X13 shown is located in the second metal layer M2. One third sub-connection portion X13 is electrically connected to a second repair data line 142, and simultaneously overlaps with the second sub-connection portion X12 in a direction h3 perpendicular to the plane of the substrate, allowing the second repair data line 142 to be electrically connected to the second sub-connection portion X12 via the third sub-connection portion X13. Specifically, Step 206 includes: electrically connecting the repair driving circuit 20 corresponding to the second defective pixel to a second repair data line 142 via the second sub-connection portion X2 and the third sub-connection portion X3, so that the repair driving circuit 20 corresponding to the second defective pixel receives the data signal provided by the second repair data line 142.

[0154] It should be noted that the above description describes some embodiments of this disclosure. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0155] Based on the same inventive concept, corresponding to the above-described display panel embodiments, one embodiment of this disclosure also provides a display device, including the display panel in any of the above embodiments.

[0156] In this disclosure, the display device can be any device with a display function, such as a mobile phone, tablet computer, laptop computer, e-reader, television set, or smartwatch. Figure 34 As shown, Figure 34 This is a schematic diagram of a display device provided in an embodiment of the present invention, including the display panel DP in any of the above embodiments. When the display panel is used in vehicles such as automobiles, ships, or airplanes as a transport display screen, it can be an inherent structure independent of the vehicle, or it can be a partial structure integrated with other structural components in the vehicle. For example, the display panel can be integrated with the windshield or with the dashboard surface. The embodiments of the present invention do not limit this.

[0157] The display device provided in this disclosure enables a repair driving circuit to be equipped with at least two repair data lines. When one repair data line is occupied by another repair driving circuit, the other one or more repair driving lines can also provide data signals to another repair driving circuit independently. This allows the display panel to repair more defective pixels when the same number of repair driving circuits are set, thereby improving the pixel fault tolerance rate of the display panel.

[0158] Specifically, the display device in this disclosure embodiment is a medium-sized display device such as a tablet computer, a laptop computer, or an automotive display screen. Since medium-sized display devices have higher resolutions—for example, in related technologies, there is a display panel with a resolution of 3456*2160—it can be roughly understood that it has 3456 pixel circuit driving rows, and each pixel circuit driving row includes 2160 pixel driving circuits. Therefore, for medium-sized display devices, the probability of defective pixels appearing in the display panel is also higher. The display device provided in this disclosure embodiment can improve the pixel fault tolerance rate of the display panel. Furthermore, the display panel of a medium-sized display device can have a larger bezel area (i.e., a non-display area). When the repair driving circuit is located in the bezel area, more repair data lines can be set, further increasing the number of pixels that the repair driving circuit can repair, thus improving the pixel fault tolerance rate of the display panel.

[0159] The apparatus of the above embodiments includes the corresponding display panel in any of the foregoing embodiments and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0160] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes the aforementioned element.

[0161] The foregoing description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described above, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that, include: Substrate; A display area and a non-display area, wherein the non-display area at least partially surrounds the display area; The display area includes the light-emitting elements and the pixel driving circuit rows, and the pixel driving circuit rows include a plurality of pixel driving circuits arranged along a first direction, and one of the pixel driving circuits is electrically connected to at least one light-emitting element. Multiple repair connection lines, multiple repair data lines, and multiple repair driving circuits are provided, with at least one repair driving circuit and at least one repair connection line corresponding to each pixel driving circuit row; Along a direction perpendicular to the plane of the substrate, the pixel driving circuit row and the repair driving circuit at least partially overlap with the same repair connection line; An active layer and a first transition structure, wherein the first transition structure is located on the side of the active layer away from the substrate; The repair driving circuit includes a data writing transistor, the data writing transistor includes a channel and a first electrode located in the active layer, and the first adapter structure is electrically connected to the first electrode of the data writing transistor. The plurality of repair driving circuits are arranged along the second direction, and each repair driving circuit is provided with at least two repair data lines. The second direction intersects the first direction. Along the direction perpendicular to the plane where the substrate is located, the first adapter structure at least partially overlaps with at least two of the repair data lines.

2. The display panel according to claim 1, characterized in that, It also includes multiple scan lines, wherein the pixel driving circuit row and the repair driving circuit at least partially overlap with the same scan line.

3. The display panel according to claim 1, characterized in that, The plurality of repair data lines include a first repair data line and a second repair data line. The first adapter structure includes a first sub-connection portion and a second sub-connection portion that are electrically connected. The repair driving circuit is electrically connected to a first repair data line through the first sub-connection portion. In a direction perpendicular to the plane of the substrate, the second sub-connection portion at least partially overlaps with at least one second repair data line.

4. The display panel according to claim 3, characterized in that, The first sub-connector and the second sub-connector are at least partially separated into different layers.

5. The display panel according to claim 3, characterized in that, The first repair data line is disposed on a different layer from at least one of the first sub-connection portion and the second sub-connection portion, and the second repair data line is disposed on a different layer from at least one of the first sub-connection portion and the second sub-connection portion.

6. The display panel according to claim 1, characterized in that, It includes multiple repair drive circuit groups arranged along the second direction. Each drive circuit group includes at least one repair drive circuit. Repair drive circuits within the same repair drive circuit group are electrically connected to the same repair data line through corresponding first adapter structures. Repair drive circuits within different repair drive circuit groups are electrically connected to different repair data lines through corresponding first adapter structures.

7. The display panel according to claim 1, characterized in that, The non-display area includes the repair driving circuit and the virtual pixel driving circuit; The virtual pixel driving circuit is located on the side of the repair driving circuit away from the pixel driving circuit row.

8. The display panel according to claim 1, characterized in that, The display area also includes the repair driving circuit, and the non-display area includes a virtual pixel driving circuit.

9. The display panel according to claim 8, characterized in that, The device includes a driving circuit layer located on one side of the substrate. The driving circuit layer includes the pixel driving circuit, the repair driving circuit, and the virtual pixel driving circuit. The light-emitting element is located on the side of the driving circuit layer away from the substrate. Along a direction perpendicular to the plane of the substrate, one of the repair driving circuits located in the display area at least partially overlaps with at least one of the light-emitting elements.

10. The display panel according to claim 1, characterized in that, It also includes a peripheral driving circuit, in which each repair data line at least partially overlaps with the peripheral driving circuit along a direction perpendicular to the plane of the substrate.

11. The display panel according to claim 10, characterized in that, The non-display area includes the repair driving circuit and the peripheral driving circuit; The peripheral driving circuit is located on the side of the repair driving circuit away from the pixel driving circuit row.

12. The display panel according to claim 1, comprising a first region, wherein the number of pixel driving circuits in two adjacent rows of pixel driving circuits along the second direction is not equal; In the first region, the repair drive circuits at least partially overlap along the second direction.

13. The display panel according to claim 1, characterized in that, At least two of the repair data lines are located in the same film layer.

14. The display panel according to claim 1, characterized in that, Along a direction perpendicular to the plane of the substrate, the projected area of ​​the pixel driving circuit and the repair driving circuit are the same.

15. The display panel according to claim 1, characterized in that, It also includes light emission control lines, power supply voltage lines, first scan lines, second scan lines, third scan lines, first reset voltage lines, and second reset voltage lines; The repair driving circuit further includes a driving transistor, a first reset transistor, a second reset transistor, a threshold compensation transistor, a first light-emitting control transistor, a second light-emitting control transistor, and a first storage capacitor, wherein: The first terminal of the first light-emitting control transistor is electrically connected to the power supply voltage line, the second terminal of the first light-emitting control transistor is electrically connected to the first terminal of the driving transistor, and the gate of the first light-emitting control transistor is electrically connected to the light-emitting control line. The first terminal of the first reset transistor is electrically connected to the first reset voltage line, the second terminal of the first reset transistor is electrically connected to the gate of the driving transistor, and the gate of the first reset transistor is electrically connected to the first scan line. The first terminal of the threshold compensation transistor is electrically connected to the second terminal of the driving transistor, the second terminal of the threshold compensation transistor is electrically connected to the gate of the driving transistor, and the gate of the threshold compensation transistor is electrically connected to the second scan line. The second terminal of the data writing transistor is electrically connected to the first terminal of the driving transistor, and the gate of the data writing transistor is electrically connected to the second scan line; The second plate of the first storage capacitor is electrically connected to the power supply voltage line, and the first plate of the first storage capacitor is electrically connected to the gate of the driving transistor. The first electrode of the second light-emitting control transistor is electrically connected to the second electrode of the driving transistor, the gate of the second light-emitting control transistor is electrically connected to the light-emitting control line, the second electrode of the second light-emitting control transistor is located in the active layer and is electrically connected to the second transition structure, the second transition structure is located on the side of the active layer away from the substrate, along a direction perpendicular to the plane of the substrate, and the second transition structure at least partially overlaps with the repair connection line. The first terminal of the second reset transistor is electrically connected to the second reset voltage line, the gate of the second reset transistor is electrically connected to the third scan line, the second terminal of the second reset transistor is located in the active layer and is electrically connected to the third transition structure, the third transition structure is located on the side of the active layer away from the substrate, along a direction perpendicular to the plane of the substrate, and the third transition structure at least partially overlaps with the repair connection line.

16. The display panel according to claim 15, characterized in that, The first reset voltage line is electrically connected to the second reset voltage line, or the first reset voltage line is multiplexed as the second reset voltage line.

17. The display panel according to claim 15, characterized in that, The second adapter structure is electrically connected to the repair connection line.

18. The display panel according to claim 15, characterized in that, The repair drive circuit also includes a second storage capacitor, the first plate of which is electrically connected to the power supply voltage line, the first terminal of the second reset transistor is electrically connected, and the second plate of the second storage capacitor is electrically connected to the second terminal of the second reset transistor.

19. The display panel according to claim 15, characterized in that, The repair driving circuit further includes a repair control transistor, the first terminal of which is electrically connected to the second terminal of the second reset transistor, the second terminal of which is electrically connected to the second terminal of the second light-emitting control transistor and the repair connection line, and the gate of which is electrically connected to the light-emitting control line.

20. A pixel repair method for a display panel, characterized in that, The method, applicable to any one of claims 1-19, comprises: Identify defective pixels; Disconnect the electrical connection between the light-emitting element of the defective pixel and the pixel driving circuit; The light-emitting element of the defective pixel is electrically connected to the corresponding repair connection line.

21. The method according to claim 20, characterized in that, The plurality of repair data lines include a first repair data line and a second repair data line. The repair driving circuit is electrically connected to one of the first repair data lines, and along a direction perpendicular to the plane of the substrate, the repair driving circuit at least partially overlaps with one of the second repair data lines. The method further includes: Determine the first defect pixel and the second defect pixel; Disconnect the light-emitting elements of the first defective pixel and the second defective pixel from the corresponding pixel driving circuits, and connect the light-emitting elements of the first defective pixel and the second defective pixel to the corresponding repair connection lines. Disconnect the electrical connection between the repair driving circuit corresponding to the second defective pixel and the first repair data line; The repair driving circuit corresponding to the second defective pixel is electrically connected to a second repair data line, so that the repair driving circuit corresponding to the first defective pixel receives the data signal provided by the first repair data line, and the repair driving circuit corresponding to the second defective pixel receives the data signal provided by the second repair data line.

22. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 19.

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