Delay line with process voltage temperature robustness, linearity and leakage current compensation

Abstract

One aspect relates to an apparatus comprising: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator comprising an input coupled to the first node and an output coupled to the second node.

Description

[0001] Cross-reference to related applications

[0002] This patent application claims priority to pending U.S. non-provisional application No. 17 / 495,608, filed October 6, 2021, which has been assigned to the assignee of this application and is hereby incorporated herein by reference as fully set forth herein and for all applicable purposes. Technical Field

[0003] All aspects of this disclosure relate to signal delay lines in general, and more specifically to signal delay circuits having process voltage-temperature (PVT) robustness, linearity, and leakage current compensation. Background Technology

[0004] Many circuits use delay lines to apply a delay to an input signal (e.g., an input clock) to generate an output signal (e.g., an output clock). For the applied delay to be accurate and predictable, the delay should not vary significantly with process voltage temperature (PVT). It may also be desirable that the delay varies substantially linearly with the delay control signal, so that an accurate and predictable delay can be achieved by properly setting the delay control signal. Additionally, it may be desirable to sense and compensate for leakage current in the delay line circuitry; otherwise, an accurate and predictable delay may not be achievable, especially at certain technology nodes that are sensitive to temperature variations. Summary of the Invention

[0005] The following provides a brief overview of one or more embodiments to offer a basic understanding of such embodiments. This overview is not an exhaustive summary of all anticipated embodiments, nor is it intended to identify key or essential elements of all embodiments, nor to depict the scope of any or all embodiments. Its sole purpose is to introduce some concepts of one or more embodiments in a simplified form as a prelude to the more detailed descriptions that follow.

[0006] One aspect of this disclosure relates to an apparatus. The apparatus includes: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node.

[0007] Another aspect of this disclosure relates to a method. The method includes: generating an oscillating signal based on a first voltage and a first current; controlling the first voltage and the first current such that the ratio of the first voltage to the first current is substantially constant; and delaying an input signal to generate an output signal based on a second voltage associated with the first voltage.

[0008] Another aspect of this disclosure relates to an apparatus. The apparatus includes: a component for generating an oscillating signal based on a first voltage and a first current; a component for controlling the first voltage and the first current such that the ratio of the first voltage to the first current is substantially constant; and a component for delaying an input signal to generate an output signal based on a second voltage associated with the first voltage.

[0009] Another aspect of this disclosure relates to a wireless communication device. The wireless communication device includes one or more baseband signal processing modules; at least one antenna; a transceiver coupled to the at least one antenna and the one or more baseband signal processing modules, wherein the transceiver includes: a ring oscillator coupled between a first node and a first voltage rail; control circuitry coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node.

[0010] To achieve the foregoing and related objectives, one or more embodiments include the features fully described below and specifically pointed out in the claims. The following description and accompanying illustrations set forth certain exemplary aspects of these one or more embodiments in detail. However, these aspects are merely indications of a number of ways in which the principles of the various embodiments may be employed, and the embodiments in this specification are intended to include all such aspects and their equivalents. Attached Figure Description

[0011] Figure 1 A block diagram of an example signal delay circuit according to one aspect of this disclosure is shown.

[0012] Figure 2A A schematic diagram of another example signal delay circuit according to another aspect of this disclosure is shown.

[0013] Figure 2B The illustration shows another aspect according to this disclosure. Figure 2A The example control circuit of the signal delay circuit and the example current / voltage response curve of the ring oscillator are shown in the figure.

[0014] Figure 2C The illustration shows another aspect according to this disclosure. Figure 2A Example control circuits for signal delay circuits and another example current / voltage graph for a ring oscillator.

[0015] Figure 2D The illustration shows another aspect according to this disclosure. Figure 2A A graph showing the example current / voltage response of an example delay line.

[0016] Figure 3 A schematic diagram of an example switched capacitor resistor according to another aspect of this disclosure is illustrated.

[0017] Figure 4 A schematic diagram of an example ring oscillator according to another aspect of this disclosure is shown.

[0018] Figure 5 A block diagram of another example signal delay circuit according to another aspect of this disclosure is shown.

[0019] Figure 6 The illustration shows a schematic diagram of a portion of another example signal delay circuit according to another aspect of this disclosure.

[0020] Figure 7 The illustration shows a schematic diagram of a portion of another example signal delay circuit according to another aspect of this disclosure.

[0021] Figure 8 The illustration shows a schematic diagram of another portion of another example signal delay circuit according to another aspect of this disclosure.

[0022] Figure 9 A schematic diagram of an example leakage current sensor according to another aspect of this disclosure is illustrated.

[0023] Figure 10 A schematic diagram of another example leakage current sensor according to another aspect of this disclosure is illustrated.

[0024] Figure 11 A flowchart illustrating an example method for delaying a signal according to another aspect of this disclosure is shown.

[0025] Figure 12 A block diagram of an example wireless communication device according to another aspect of this disclosure is illustrated. Detailed Implementation

[0026] The specific embodiments described below with reference to the accompanying drawings are intended as descriptions of various configurations and not as representations of the only configurations in which the concepts described herein can be practiced. To provide a comprehensive understanding of the various concepts, specific details are included in the specific embodiments. However, it will be apparent to those skilled in the art that these concepts can be practiced without these specific details. In some instances, well-known structures and components are shown in block diagram form to avoid obscuring these concepts.

[0027] Delay lines are used in many applications. For example, they can be used in phase shifters, time-based analog-to-digital converters (ADCs), multiphase clock generators, digital-to-time converters (DTCs), time-to-digital converters (TDCs), phase-locked loops (PLLs), delay-locked loop (DLL) systems, time measurement systems, and so on. In such applications, controlling these delay lines to provide accurate and predictable delays is often of interest. In this regard, delay lines and associated control circuitry are designed to provide a process voltage-temperature (PVT) settling time delay, a substantially linear delay delivery response to an input delay control signal (e.g., an input code), and to compensate for leakage currents that can affect the achievement of accurate and predictable delays.

[0028] Figure 1 A block diagram of an example signal delay circuit 100 according to one aspect of this disclosure is shown. The signal delay circuit 100 includes a delay line 150 configured to receive an input signal S. IN (e.g., a clock) and generate an output signal S. OUT (For example, a delayed clock), the output signal is the input signal S IN The delayed version. The output signal S is generated by applying delay line 150. OUT Input signal S IN The delay is based on the reference voltage V provided to the delay line 150. REF2 The signal delay circuit 100 includes a delay control circuit 105 configured to generate a reference voltage V at node n2. REF2 Delay line 150 is coupled between node n2 and the lower voltage rail (e.g., ground).

[0029] The signal delay circuit 100 also includes a delay control circuit 105, which includes a control circuit 110 (e.g., controlling the operating point (OP) of a ring oscillator (RO)), a ring oscillator 120, a delay controller 130, and a voltage regulator 140. The control circuit 110 and the ring oscillator 120 are coupled in series between the upper voltage rail VDD and the lower voltage rail (e.g., ground). In some specific embodiments, the control circuit 110 is configured to control the operating point (OP) of the ring oscillator 120. REF1 / I1), which makes it exhibit a substantially linear voltage / current response (e.g., a function with a substantially constant slope). As used herein, the operating point is the target voltage V supplied to the ring oscillator 120. REF1 And current I1. As discussed further herein, the linear voltage / current response is translated into a substantially linear relationship between the PVT steady-state delay applied to the input signal by delay line 150 and the resulting delay applied to the input signal by delay line 150.

[0030] Delay controller 130 is coupled to ring oscillator 120 to provide it with a delay control signal (DCS). As discussed further herein, the delay control signal (DCS) controls the number of inverters enabled in ring oscillator 120, which affects the inherent current / voltage response of ring oscillator 120. That is, the more inverters enabled, the higher the inherent current / voltage response of ring oscillator 120; and the fewer inverters enabled, the lower the inherent current / voltage response of ring oscillator 120.

[0031] Control circuit 110 has a substantially linear inherent voltage-current / voltage response. Control circuit 110 controls the current I1 supplied to ring oscillator 120, such that ring oscillator 120 exhibits a substantially linear current / voltage response to control circuit 110. Therefore, control circuit 110 controls the reference voltage V in response to delay controller 130 controlling ring oscillator 120. REF1 And current I1, so as to linearly current I1 relative to reference voltage V REF1 Maintain the operating point, as discussed. Voltage regulator 140 is based on the reference voltage V. REF1 Generate reference voltage V REF2 (For example, V) REF2 Basically equal to V REF1 ).

[0032] As discussed above, delay line 150 delays the input signal S. IN Based on reference voltage V REF2 (For example, related to the reference voltage V) REF2 Generate output signal S OUT Therefore, if the reference voltage V REF2 If the current I drawn from delay line 150 increases, then... DLY Compared to reference voltage V REF2 It increases non-linearly. This is due to the delay line 150 applied to the input signal S. IN Delay T DLY It can be related to the following relationship: T DLY ~C L ·V REF2 / I DLY Therefore, the delay line 150 is applied to the input signal S. IN The delay varies with the reference voltage V REF2 It decreases as the reference voltage V increases. REF2 If the current I drawn from delay line 150 decreases, then... DLY Compared to the reference voltage V REF2 It decreases less non-linearly. Therefore, according to relation T DLY ~C L ·V REF2 / IDLY The delay line 150 applies to the input signal S. IN The delay varies with the reference voltage V REF2 It increases as it decreases.

[0033] The delay control circuit 105 controls the delay line 150 as follows: If the desired input signal S IN If the delay is smaller, the delay controller 130 tunes (increases) the reference voltage V by generating a delay control signal (DCS). REF1 This allows fewer inverters to be used in the ring oscillator 120. This increases the current I1 and the reference voltage V in the control circuit 110. REF1 In response to the increased reference voltage V REF1 Voltage regulator 140 increases reference voltage V REF2 This reduces the amount of time applied to the input signal S by delay line 150. IN The delay is used to generate the output signal S OUT .

[0034] Conversely, if the desired input signal S IN If the delay is greater, the delay controller 130 tunes (reduces) the reference voltage V by generating a delay control signal (DCS). REF1 This allows more inverters to be enabled in the ring oscillator 120. This causes the control circuit 110 to reduce the current I1 and the reference voltage V. REF1 In response to the decreased reference voltage V REF1 Voltage regulator 140 reduces the reference voltage V REF2 This causes delay line 150 to be increased and applied to the input signal S. IN The delay is used to generate the output signal S OUT .

[0035] Figure 2A A schematic diagram of another example signal delay circuit 200 according to another aspect of this disclosure is illustrated. The signal delay circuit 200 may be a more detailed implementation of the previously discussed signal delay circuit 100. The signal delay circuit 200 includes a delay line 250 and a delay control circuit, which includes a control circuit 210, a ring oscillator 220, a delay controller 230, and a voltage regulator 240.

[0036] Delay line 250 includes a set of M cascaded inverters M 13 / M 14 To M M3 / M M4Where M is an integer. A cascaded inverter refers to inverters connected in series between the input and output terminals; for example, the output of one inverter is coupled to the input of a subsequent inverter. Each inverter in this set of cascaded inverters includes a p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET) coupled in series with an n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) between node n2 and the lower voltage rail (e.g., ground). For example, the first inverter in this set of cascaded inverters includes a p-channel metal-oxide-semiconductor field-effect transistor (PMOS FET) coupled in series with an NMOSFET M. 14 Series-coupled PMOS FET M 13 This includes components coupled together and configured to receive an input signal S. IN (For example, a clock signal) has a gate (inverter input) and a drain coupled together (inverter output). Similarly, the second inverter includes an NMOS FET M... 24 Series-coupled PMOS FET M 23 This includes coupling to the first inverter M 13 / M 14 The gate (input) of the output terminal is coupled together with the drain (output) of the input terminal of the next inverter. This arrangement continues until the last inverter, which includes an NMOS FET M. M4 Series-coupled PMOS FET M M3 This includes the gate (input) coupled to the output of the previous inverter, and the components coupled together and configured to generate the output signal S. OUT (For example, the drain of the output clock) (inverter output).

[0037] Delay line 250 may also include a set of M capacitors C 12 To C M2 The group of M capacitors is coupled to the group of cascaded inverters M. 13 / M 14 To M M3 / M M4 The output terminal is connected to the lower voltage rail (e.g., ground). This group contains M capacitors C. 12 To C M2 Each of these can be implemented as a discrete capacitor, such as a metal-insulator-metal (MIM) capacitor, a metal-oxide-metal (MOM) capacitor, a metal-oxide-semiconductor (MOS) capacitor, etc. Alternatively, the group of M capacitors C 12 To C M2 Each of them can be implemented as a parasitic capacitor of the design.

[0038] The ring oscillator 220 can be configured similarly to the delay line 250, except that the number N of cascaded inverters is an odd integer, and the output of the "last" inverter is coupled to the input of the "first" inverter. More specifically, the ring oscillator 220 includes N cascaded inverters M. 11 / M 12 To M N1 / M N2 The ring. Each inverter in the cascaded inverter ring includes a PMOS FET coupled in series with an NMOS FET between node n1 and the lower voltage rail (e.g., ground). For example, the "first" inverter in the cascaded inverter ring includes a PMOS FET coupled in series with an NMOS FET M. 12 Series-coupled PMOS FET M 11 This includes the PMOS FET M coupled together and coupled to the "last" inverter. N1 The output (drain) and gate (input) of the NMOS FET Mn2. Similarly, the "second" inverter in the cascaded inverter ring includes an NMOS FET Mn2. 22 Series-coupled PMOS FET M 21 This includes the gate (input) coupled to the output of the first inverter, and the drain (output) coupled together to the input of the next inverter. This arrangement continues until the "last" inverter M. N1 / M N2 The ring oscillator 220 can use the same technology (e.g., complementary metal-oxide-semiconductor (CMOS)) and size of the delay line 250.

[0039] The ring oscillator 220 may also include a set of M capacitors C 11 To C N1 The group of M capacitors is coupled to the cascaded inverter M. 11 / M 12 To M N1 / M N2 The output terminal of the ring is connected to the lower voltage rail (e.g., ground). This group contains M capacitors C. 11 To C N1 Each of the M capacitors can be implemented as a discrete capacitor, such as a MIM, MOM, MOS, or other type of capacitor. Alternatively, the group of M capacitors C 11 To C N1 Each of them can be implemented as a parasitic capacitor of the design.

[0040] Control circuit 210 includes a first current source comprising a resistor R1 and a PMOS FET M1 coupled in series with ring oscillator 220 between an upper voltage rail VDD and a lower voltage rail (e.g., ground). Control circuit 210 also includes a second current source comprising a resistor R2 and a PMOS FET M2 coupled in series with resistive device R between the upper voltage rail VDD and the lower voltage rail (e.g., ground). The gates of PMOS FETs M1 and M2 are coupled together to form a current mirror, and their size can be configured to produce a current ratio I1 / I2 of X (e.g., the size of PMOS FET M1 is X times the size of PMOS FET M2). Additionally, the control circuit 210 includes an operational amplifier 212, which includes a first (e.g., negative) input coupled to node n1 between the first current source R1 / M1 and the ring oscillator 220, a second (e.g., positive) input coupled to node n3 between the second current source R2 / M2 and the resistive device R, and an output coupled to the control input (e.g., the gate) of the current sources (e.g., PMOS FETs M1 and M2). The operational amplifier 212 is configured to operate based on the voltage V at node n3. n3 The reference voltage V at node n1 REF1 The difference between them generates the sensing voltage V. SNS .

[0041] The delay controller 230 is configured to generate a delay control signal (DCS). As discussed in more detail herein, this set of cascaded inverters M of the ring oscillator 220... 11 / M 12 To M N1 / M N2 Each of these can include a set of parallel inverters. A delay control signal (DCS) can be configured to enable the set of cascaded inverters M. 11 / M 12 To M N1 / M N2 P (integers greater than zero) inverters from the first subset of the group of parallel inverters in one or more inverters, and enable the group of cascaded inverters M. 11 / M 12 To M N1 / M N2The remaining or second subset of P+1 inverters in one or more of the inverters in the ring oscillator 220. As previously discussed with reference signal delay circuit 100, the current I1 drawn by ring oscillator 220 is related to the total number of all enabled inverters in ring oscillator 220, A*P+B*(P+1), where A is the number of cascaded inverters in the first subset and B is the number of cascaded inverters in the second subset. A plus B equals the number of stages of ring oscillator 220. As previously discussed and further discussed in more detail herein, by controlling the number of enabled inverters A*P+B*(P+1) in ring oscillator 220, the input signal S applied by delay line 250 can be linearly controlled. IN To generate output signal S OUT The delay.

[0042] Voltage regulator 240 can be configured as a low-dropout (LDO) voltage regulator. In this regard, voltage regulator 240 includes operational amplifier 232 and PMOS FET M3. Operational amplifier 232 includes a first (e.g., negative) input coupled to node n1 (e.g., via a filter), a second (e.g., positive) input coupled to node n2, and an output coupled to the gate of PMOS FET M3. PMOS FET M3 is coupled in series with delay line 250 between the upper voltage rail VDD and the lower voltage rail (e.g., ground), with node n2 located between PMOS FET M3 and delay line 250.

[0043] Voltage regulator 240 may include filters for reducing power supply voltage noise, such as: a first low-pass filter (LPF) including a series resistor R3 coupled between node n1 and the first (negative) input of operational amplifier 232, and a shunt capacitor C1 coupled between the negative input of operational amplifier 232 and the lower voltage rail (e.g., ground); and a second LPF including a capacitor C2 and a resistor R4 coupled in parallel between node n2 and the lower voltage rail (e.g., ground).

[0044] Figure 2B The figure illustrates an example of the inherent current versus voltage response of the control circuit 210 and the ring oscillator 220 of the signal delay circuit 200 according to another aspect of this disclosure. The horizontal axis of the graph represents the reference voltage V supplied to the ring oscillator 220. REF1 (At node n1). The vertical axis represents the inherent current / voltage response (labeled "X·I2") relative to control circuit 210 and the inherent current / voltage response (labeled "I1" and "I2") relative to ring oscillator 220 for two different configurations. 1less The current of ”), as discussed further in this paper.

[0045] The inherent current / voltage response X·I2 of the control circuit 210 is the response of current I1 varying with the reference voltage V when the ring oscillator 220 is disconnected from the node n1 REF1 . Similarly, the inherent current / voltage responses I1 and I of the ring oscillator 220 1less are responses of the current of the ring oscillator 220 varying with the reference voltage V when the control circuit 210 is disconnected from the node n1 REF1 .

[0046] As discussed in more detail herein, the control circuit 210 adjusts the operating point of the ring oscillator 220 (e.g., V REF1 and I1) to be on the linear X·I2 response. When this occurs, the following relationship holds:

[0047]

[0048]

[0049] V n3 =V REF1 Equation 3

[0050] where R is the resistance of the resistance device R, and V n3 is the voltage at node n3. In this example, the ring oscillator 220 initially operates at point "A" on the X·I2 line. Furthermore, the initial operating point "A" is on the nonlinear response "I1" of inherent current versus reference voltage V (because the ring oscillator 220 draws I1 current). REF1

[0051] Then, according to this example, the delay controller 230 tunes (increases) the reference voltage V by generating a delay control signal (DCS) REF1 to enable fewer inverters in the ring oscillator 220. Accordingly, the inherent current versus reference voltage V response of the ring oscillator 220 REF1 becomes the nonlinear response "I 1less ", where I 1less <I1. As illustrated, the current of the inherent current versus reference voltage V response I REF1 1less is lower than that of the inherent current versus reference voltage V response I1. Therefore, when fewer inverters are enabled in the ring oscillator 220 by the DCS, the operating point initially changes to point "B", where the current drawn by the ring oscillator 220 is less than the current drawn when operating at point "A"; but the reference voltage V REF1 initially remains the same. Accordingly, the inherent conductance of the ring oscillator 220 decreases. REF1

[0052] ​​​In response to the inherent conductivity of the ring oscillator 220, the reference voltage V REF1 The current I1 supplied by control circuit 210 increases as it charges node n1. Operational amplifier 212 of control circuit 210 now senses voltage V. n3 With reference voltage V REF1 The voltage difference between them reduces the sense voltage V applied to the gates of PMOS FETs M1 and M2. SNS This causes currents I1 and I2 to increase. In response, voltage V... n3 Start with a voltage higher than the reference voltage V REF1 A faster rate of increase. When the voltage V n3 Basically equal to the reference voltage V REF1 When (for example, when Equation 3 is satisfied), the ring oscillator 220 operates at point "C", which is on the linear X·I² response. Therefore, the control circuit 210 responds to the change in the ring oscillator 220 to make its operating point on the linear X·I² response.

[0053] Figure 2C The figure illustrates an example inherent current versus voltage graph of the control circuit 210 and the ring oscillator 220 of the signal delay circuit 200 according to another aspect of this disclosure. The horizontal axis of the graph represents the reference voltage V supplied to the ring oscillator 220. REF1 (At node n1). The vertical axis represents the inherent current / voltage response (labeled "X·I2") relative to control circuit 210 and the inherent current / voltage response (labeled "I1" and "I2") relative to ring oscillator 220 for two different configurations. 1more The current of ”), as discussed further in this paper.

[0054] Similarly, in this example, the ring oscillator 220 initially operates at point "A" on the X·I2 line. Furthermore, the initial operating point "A" is at the point where the inherent current corresponds to the reference voltage V. REF1 The nonlinear response is on "I1" (because the ring oscillator 220 is drawing current from I1). Then, according to this example, the delay controller 230 tunes the reference voltage V by generating a delay control signal (DCS). REF1 This allows for the activation of more inverters in the ring oscillator 220. Therefore, the inherent current of the ring oscillator 220 is related to the reference voltage V. REF1 It becomes a nonlinear response "I" 1more ", where I 1more >I1. As shown in the diagram, the inherent current is related to the reference voltage V. REF1 Response I 1more The current is higher than the inherent current relative to the reference voltage V. REF1Response I1. Therefore, when more inverters are enabled in the ring oscillator 220 by the DCS, the operating point initially changes to point "D", where the current drawn from the ring oscillator 220 is greater than the current drawn when operating at point "A"; however, the reference voltage V REF1 Initially, the same conditions are maintained. Therefore, the inherent conductivity of the ring oscillator 220 increases.

[0055] In response to the increased inherent conductivity of the ring oscillator 220, the reference voltage V REF1 The current I1 is reduced because the control circuit 210 supplies current I1 to the ring oscillator 220. The operational amplifier 212 of the control circuit 210 now senses the voltage V. n3 With reference voltage V REF1 The voltage difference between them increases the sense voltage V applied to the gates of PMOS FETs M1 and M2. SNS This causes currents I1 and I2 to decrease. In response, voltage V... n3 Start with a voltage higher than the reference voltage V REF1 A faster rate of decrease. When voltage V n3 Basically equal to the reference voltage V REF1 When (for example, when Equation 3 is satisfied), the ring oscillator 220 operates at point "E", which is on the linear X·I² response. Therefore, the control circuit 210 responds to the change in the ring oscillator 220 to make the operating point on the linear X·I² response. Figure 2D The figure illustrates an example inherent current / voltage response graph of the delay line 250 of a signal delay circuit 200 according to another aspect of this disclosure. The horizontal axis of the graph represents the reference voltage V supplied to the delay line 250. REF2 (At node n2). The vertical axis represents the current drawn from delay line 250. The following utilizes... Figure 2D The example current / voltage response of the delay line 250 in the plot is used to discuss the reference. Figures 2B to 2C Previous examples discussed.

[0056] The delay line 250 can be controlled as follows: As discussed, the delay control signal (DCS) generated by the delay controller 230 sets the number of inverters enabled in the ring oscillator 220, which is related to the current I1 drawn by the ring oscillator 220. (Reference) Figures 2B to 2C For example, the initial number of inverters enabled by the DCS sets the operating point of the ring oscillator to point "A". Due to V REF2 Basically equal to V REF1 Therefore, the corresponding operating point "A" is plotted on the inherent current / voltage response of delay line 250.

[0057] like Figure 2BAs discussed in the example, if the number of inverters enabled is reduced, the reference voltage V... REF1 Increase. In response, voltage regulator 240 increases the reference voltage V. REF2 Therefore, delay line 250 now follows its inherent current / voltage response I. DLY Operate at point "C". Due to the higher reference voltage V REF2 The delay line 250 reduces the amount applied to the input signal S IN The delay. Similarly, such as Figure 2C As discussed in the example, if the number of inverters enabled increases, the reference voltage V... REF1 Decrease. In response, voltage regulator 240 decreases the reference voltage V. REF2 Therefore, delay line 250 now follows its inherent current / voltage response I. DLY Operate at point "E". Due to the lower reference voltage V REF2 The delay line 250 increases the amount applied to the input signal S IN The delay.

[0058] Mathematically, the period T of the oscillation signal generated by the ring oscillator 220 is... OSC It can be determined by the following equation:

[0059] T OSC =C R ·V REF1 / I1 Equation 4

[0060] Where C R For capacitor C 11 To C N1 The capacitance of each of them. However, according to Equation 1, V REF1 / I1 equals R / X. The resistance R of the resistive device R and the current ratio X of the current mirror M1 / M2 can be configured to be substantially constant over PVT variations. Therefore, the period T of the oscillation signal of the ring oscillator 220 is... OSC It can be given by the following equation:

[0061] T OSC =C R Equation 5 for R / X

[0062] Therefore, if C R R and X can be configured to be substantially constant, then the period T of the ring oscillator 220 OSC It is also essentially constant. Therefore, this property increases the period T. OSC The PVT robustness. As discussed below, the delay line 250 applied to the input signal S IN Delay T DLY With the period T of the ring oscillator 220 OSCRelated. Therefore, extending this further, delay T DLY It is also more robust to PVT.

[0063] As shown in Equation 5, the period T of the oscillation signal generated by the ring oscillator 220 is... OSC It is a function of the R*C time constant, i.e., C R *R. Due to the delay line 250 applied to the input signal S IN Delay and period T OSC This period is related to the R*C time constant, and therefore can be controlled by properly designing the resistor R and capacitor C. 11 To C N1 This controls the PVT variation of the delay applied by the delay line 250. As an example, if a switched capacitor resistor is used as the resistive device R, as discussed further herein, then the delay T... DLY It can be the capacitor ratio C R / C SW The function, where C SW It is a capacitor in a switched capacitor resistor. The resistive device R can also be configured as a thin-film resistor, which can be temperature compensated to reduce delay dependence on PVT changes. The delay line 250 is applied to the input signal S. IN Delay T DLY This can be given by the following relationship:

[0064] T DLY =C L ·V REF2 / I DLY Equation 6

[0065] Where C L For the delay line, capacitor C is 250. 12 To C M2 The capacitance of each of them, and I DLY This is the current drawn from delay line 250.

[0066] Due to voltage regulator 240, reference voltage V REF2 Basically equal to the reference voltage V REF1 The current I drawn from delay line 250 DLY This can be given by the following relationship:

[0067]

[0068] Where Q is the number of parallel inverters in each inverter stage of delay line 250, and P is the average number of enabled parallel inverters in each stage of ring oscillator 220. Substituting Equation 7 into Equation 6, we get I... DLY The delay line 250 is applied to the input signal S. IN Delay T DLYThis can be given by the following relationship:

[0069]

[0070] Due to capacitor C 12 To C M2 Capacitor C L It can be controlled to be substantially constant with respect to PVT, and as previously discussed, V REF1 / I1 equals R / X, which can also be controlled to be essentially constant with respect to PVT, and when set hour, / Q is a constant, therefore for delay T DLY PVT can also be achieved

[0071] Robustness. Furthermore, the average number of inverters enabled. It can be given by the following equation:

[0072]

[0073] Where A is the number of inverter stages in the ring oscillator 220 with P enabled inverters, B is the number of inverter stages in the ring oscillator 220 with P+1 enabled inverters, and N is the number of cascaded stages of the ring oscillator 220 (A+B=N). [A·P+B·(P+1)] can be controlled by the DCS signal from the delay controller 230. Therefore, by changing the DCS, a linear delay T can be achieved. DLY For the DCS transfer function, and the delay T DLY High-resolution ΔT for each enabled inverter DLY (For example, by substituting 1 / N in Equation 8) To obtain C L ·V REF1 / I1·1 / (N·Q) resolution).

[0074] Figure 3 A schematic diagram of an example switched capacitor resistor 300 according to another aspect of this disclosure is illustrated. As previously mentioned, the resistive device R of the signal delay circuit 200 can be implemented as the switched capacitor resistor 300.

[0075] Specifically, the switched capacitor resistor 300 includes a first switching device SW1, a capacitor C3, and a second switching device SW2. The first switching device SW1 and capacitor C3 are coupled in series between node n3 and the lower voltage rail (e.g., ground). The second switching device SW2 is coupled in parallel with capacitor C3. The open / closed state of the first switching device SW1 is controlled by a first clock signal CLK1, and the open / closed state of the second switching device SW2 is controlled by a second clock signal CLK2. In an exemplary embodiment, the first clock signal CLK1 and the second clock signal CLK2 may be based on the input signal S to the delay line 250. IN .

[0076] During operation, in the first phase of switching operation of the first switching device SW1 and the second switching device SW2, the first switching device SW1 is closed and the second switching device SW2 is open. Therefore, in this phase, current I2 charges capacitor C3. In the second phase of switching operation of the first switching device SW1 and the second switching device SW2, the first switching device SW1 is open and the second switching device SW2 is closed. Therefore, in this phase, the charge stored in capacitor C3 during the first phase flows to the lower voltage rail (e.g., ground) via the second switching device SW2. By alternating the open / closed states of the first switching device SW1 and the second switching device SW2 at a frequency f, the switched capacitor resistor 300 has a resistance R given by the following relationship: R = 1 / (C SW *f), where C SW Let C3 be the capacitance.

[0077] Figure 4 A schematic diagram of an example ring oscillator 400 according to another aspect of this disclosure is illustrated. The ring oscillator 400 may be an example of a more detailed implementation of the previously discussed ring oscillator 220.

[0078] The ring oscillator 400 includes a set of N inverter stages 410-1 to 410-N. Each inverter stage includes a set of parallel inverters. For example, the first inverter stage 410-1 includes a first set of parallel inverters I11 to IS1; the second inverter stage 410-2 includes a second set of parallel inverters I12 to IS2; the third inverter stage 410-3 includes a third set of parallel inverters I13 to IS3; and so on, up to the Nth inverter stage 410-N, which includes an Nth set of parallel inverters I1N to ISN, where N is an odd integer as previously discussed, and S is an integer. Therefore, in this example, there are S×N inverters. The inputs of the parallel inverters in each stage are coupled together and coupled to the coupled outputs of the parallel inverters of the previous inverter stage (including the input of the first inverter stage 410-1, which is coupled to the output of the last inverter stage 410-N). Similarly, the outputs of the parallel inverters in each stage are coupled together and coupled to the coupled inputs of the parallel inverters in the next inverter stage (including the output of the last inverter stage 410-N, which is coupled to the input of the first inverter stage 410-1).

[0079] In this example, some inverters in the inverter array may be always on or enabled. The inverters that are always enabled are inverters I11 to I1N. That is, at least one row of inverters may include always enabled inverters, such that the ring oscillator 400 oscillates without involving the delay controller 450. Other inverters may be selectively enabled inverters. In this example, the selectively enabled inverters are inverters I21 to ISN. Each of the selectively enabled inverters includes a first switching device coupled between node n1 and the inverter PMOS FET, and a second switching device coupled between the inverter NMOS FET and the lower voltage rail (e.g., ground). The delay controller 450 is coupled to the control inputs of the first and second switching devices of each of the selectively enabled inverters to control the on / off state of the switching devices via a delay control signal (DCS).

[0080] Figure 5 A block diagram of another example signal delay circuit 500 according to another aspect of this disclosure is shown. The signal delay circuit 500 is similar to the previously discussed signal delay circuit 100 and includes many similar elements identified by the same reference numerals, except that the most significant digit in the signal delay circuit 500 is "5" compared to "1" in the signal delay circuit 100.

[0081] The difference between signal delay circuit 500 and signal delay circuit 100 is that signal delay circuit 500 also includes leakage current I. LKG Compensation circuit 560, the leakage current compensation circuit is configured to compensate current ICOMP Injected into the ring oscillator 520 to compensate for leakage current in the ring oscillator 520. Specifically, at certain technology nodes (e.g., 7 nanometer (nm) FINFET and more or different advanced technology nodes) and at relatively high temperatures, the ring oscillator 520 may experience significant current leakage.

[0082] To compensate for the current leakage of the ring oscillator 520, the leakage current I LKG The compensation circuit 560 includes leakage current I LKG Sensor 562 and Compensation Current I COMP Injector 564. Leakage current I LKG Sensor 562 is configured to generate a leakage current I that occurs in ring oscillator 520. LKG The associated (e.g., proportional to its estimate) sense current I SNS Compensation current I COMP Injector 564 is configured to be based on sensed current I SNS Generate compensation current I COMP And inject it into the ring oscillator 520. Compensation current I COMP This should be related to the leakage current I that occurs in the ring oscillator 520. LKG They are basically the same or within the defined tolerance of the leakage current.

[0083] Figure 6 The illustration shows a schematic diagram of a portion of another example signal delay circuit 600 according to another aspect of this disclosure. The signal delay circuit 600 may be a more detailed implementation of a portion of the previously discussed signal delay circuit 200, wherein a leakage current I is added. LKG Compensation circuit. The common components of signal delay circuits 600 and 200 are a ring oscillator 620 and a control circuit 610 including an operational amplifier 612. It should be understood that, as in signal delay circuit 200, signal delay circuit 600 may also include a delay controller, a voltage regulator, and a delay line.

[0084] As mentioned, the signal delay circuit 600 includes a leakage current I. LKG Compensation circuit 660. Leakage current I LKG The compensation circuit 660 includes a leakage current sensor 662 and a compensation current I in the form of a current mirror. COMP Injector 664. Leakage current I LKG Sensor 662 is represented as a current source, which is configured to generate a sensing current I. SNS The sensed current is the estimated leakage current I that appears in the ring oscillator 620. LKG A scaled-down (1 / K) version, where 1 / K is the scaling factor.

[0085] Compensation current I COMP Injector 664 includes leakage current I LKG Sensor 662 is connected in series with PMOS FET M4 between the upper voltage rail VDD and the lower voltage rail (e.g., ground). Compensation current I... COMP Injector 664 includes a PMOS FET M5 coupled between the upper voltage rail VDD and node n1. The gates of PMOS FETs M5 and M4 are coupled together and to the drain of PMOS FET M4 to form a current mirror. The sizes of PMOS FETs M5 and M4 can be configured to provide a current mirror ratio K to compensate for the sensed current I. SNS The scaled version of the estimated leakage current in [the original text]. Therefore, the compensation current I [is...]. COMP Injector 664 is configured to generate compensation current I COMP The compensation current is the sensing current I. SNS K times. Compensation current I COMP It is supplied to the ring oscillator 620 via node n1.

[0086] Figure 7 A schematic diagram of a portion of another example signal delay circuit 700 according to another aspect of this disclosure is illustrated. Signal delay circuit 700 is a variation of signal delay circuit 600, having many of the same elements identified by the same reference numerals, except that the most significant digit in the case of signal delay circuit 700 is "7". The difference between signal delay circuit 700 and signal delay circuit 800 is that the compensation current I... COMP The injector 764 also includes a current input error amplifier to force the voltages at nodes n1 and n4 to be substantially the same or within a specific percentage difference (e.g., 20%) (i.e., correlated with each other). In other words, the current input error amplifier is configured to control a first voltage across the leakage current sensor 762 to correlate it with a second voltage at the first node n1. At fast corners, the voltage difference at nodes n1 and n4 may result in a compensation current I. COMP The difference between this current and the sensed leakage current that occurs in the ring oscillator 720. Additionally, the current input error amplifier improves the power supply rejection ratio (PSRR) and suppresses the impact of power supply variations on the compensation current I. COMP The impact of this is significant. In this example, the current input error amplifier includes NMOS FETs M7 and M6, respectively, coupled between PMOS FETs M5 and M4 and nodes n1 and n4. The gates of NMOS FETs M7 and M6 are coupled to the drain of NMOS FET M7.

[0087] Figure 8The illustration shows a portion of another example signal delay circuit 800 according to another aspect of this disclosure. The signal delay circuit 800 may be a more detailed implementation of a portion of the previously discussed signal delay circuit 200, wherein a leakage current I is added. LKG Compensation circuit. The common components of signal delay circuits 800 and 200 are a ring oscillator 820 and a control circuit 810 including an operational amplifier 812. It should be understood that, as in signal delay circuit 200, signal delay circuit 800 may also include a delay controller, a voltage regulator, and a delay line.

[0088] As mentioned, the signal delay circuit 800 includes a leakage current I. LKG The compensation circuit 862 includes a leakage current compensation circuit comprising a leakage current sensor (e.g., denoted as a current source) coupled in parallel with the resistive device R of the control circuit 810. The leakage current sensor 862 is configured to generate a sensing current I. SNS The sensed current is essentially equal to 1 / X multiplied by the estimated leakage current I that occurs in the ring oscillator 820. LKG Where X is the current ratio of the current mirror formed by PMOS FETs M1 and M2, as previously discussed. Therefore, the current mirror will sense the current I. SNS Amplification current ratio X to generate compensation current I COMP The compensation current is essentially equal to the leakage current I that occurs in the ring oscillator 820. LKG The estimate (e.g., within the defined tolerance of the leakage current). Compensation current I COMP The current flows into the ring oscillator 820 to compensate for leakage current I. LKG Therefore, in this specific implementation, the compensation current I COMP It is supplied to the ring oscillator 820 via the control circuit 810.

[0089] Figure 9 A schematic diagram of an example leakage current sensor 900 according to another aspect of this disclosure is illustrated. The leakage current sensor 900 may be an example of any of leakage current sensors 662, 762, and 862, implemented in more detail. The leakage current sensor 900 includes a set of virtual (non-operating) inverters M. 15 / M 16 To M T5 / M T6Inverters are virtual or non-operating because their inputs (gates) are attached to node n4 as in signal delay circuits 600 and 700, or to node n3 as in signal delay circuit 800, or to a lower voltage rail (e.g., ground). As an example, essentially half of the inverters may have their inputs attached to a lower voltage rail (e.g., ground), and essentially the other half may have their inputs attached to either node n4 or n3.

[0090] The number of inverters in the leakage current sensor 900 should be approximately a scaling factor (e.g., 1 / K or 1 / X) of the number of enabled inverters in the corresponding ring oscillator. Since the number of enabled inverters in the corresponding ring oscillator can vary depending on the desired delay of the delay line, the number of inverters in the leakage current sensor 900 can be set to an average or intermediate value of the number of enabled inverters in the corresponding ring oscillator. The current drawn by the leakage current sensor 900 is the sensing current I discussed earlier. SNS .

[0091] Figure 10 A schematic diagram of another example leakage current sensor 1000 according to another aspect of this disclosure is illustrated. The leakage current sensor 1000 may be an example of a more detailed implementation of any of leakage current sensors 662, 762, and 862. The leakage current sensor 1000 includes a set of always-enabled virtual (non-operating) inverters M. 16 / M 17 To M U6 / M U7 and a set of selectively enabled virtual (non-operational) inverters M 18 / M 19 To M V8 / M V9 The group of selectively enabled virtual (non-operating) inverters M 18 / M 19 To M V8 / M V9 Also includes switchgear SW 18 / SW 19 To SW V8 / SW V9 These switching devices can be controlled by a delay control signal (DCS) generated by a corresponding delay controller. That is, the delay controller, via the delay control signal (DCS), enables the number of selectively activated inverters in the leakage current sensor 1000 to be substantially a proportional factor (e.g., 1 / K or 1 / X) to the number of activated inverters in the corresponding ring oscillator. The current drawn by the leakage current sensor 1000 is the sensing current I discussed earlier. SNS .

[0092] Figure 11 A flowchart illustrating an example method 1100 for delaying a signal according to another aspect of this disclosure is shown. Method 1100 includes generating an oscillating signal based on a first voltage and a first current (block 1110). Examples of components for generating the oscillating signal based on the first voltage and the first current include any of the ring oscillators described herein.

[0093] Method 1100 further includes controlling the first voltage and the first current such that the ratio of the first voltage to the first current is substantially constant (block 1120). Examples of components for controlling the first voltage and the first current such that the ratio of the first voltage to the first current is substantially constant include any of the control circuits described herein.

[0094] Additionally, method 1100 includes delaying the input signal to generate an output signal based on a second voltage associated with the first voltage (block 1130). Examples of components for delaying the input signal to generate an output signal based on a second voltage associated with the first voltage include any of the delay lines described herein.

[0095] Controlling the first voltage and the first current may include generating a second current associated with the first current, routing the second current through a resistive device to generate a third voltage, and controlling the first and second currents based on the difference between the third voltage and the first voltage, wherein the first voltage is based on the first current. Examples of components for generating the second current associated with the first current include any of a current mirror (including PMOS FETs M1 and M2). Examples of components for routing the second current through a resistive device to generate the third voltage include any coupling from the current mirror to the resistive device R. Examples of components for controlling the first and second currents based on the difference between the third voltage and the first voltage include any of operational amplifiers 212, 812, 912, and 1012.

[0096] The method may further include tuning a first voltage, including selectively enabling one or more parallel inverters in a ring of cascaded parallel inverters. Examples of components for enabling one or more parallel inverters in a ring of cascaded parallel inverters include any of the delay controllers described herein. The method may further include sensing a leakage current in a ring oscillator and providing a compensation current to the ring oscillator based on the sensed leakage current. Examples of components for sensing a leakage current in a ring oscillator include any of the leakage current sensors described herein. Examples of components for providing a compensation current to the ring oscillator based on the sensed leakage current include the compensation current I described herein. COMPAny of the injectors. Providing a compensation current to the ring oscillator may include providing the compensation current to the ring oscillator via control circuitry for controlling a first voltage. Examples of components used to provide the compensation current to the ring oscillator via the control circuitry may include the coupling of the leakage current sensor 862 described herein to the control circuitry.

[0097] Figure 12 A block diagram of an example wireless communication device 1200 according to another aspect of this disclosure is illustrated. The wireless communication device 1200 includes an integrated circuit (IC) 1210, which may be implemented as a system-on-a-chip (SOC). The SOC 1210 includes one or more baseband signal processing modules 1220.

[0098] The wireless communication device 1200 also includes a transceiver (Tx / Rx) 1230 coupled to one or more baseband signal processing modules 1220 to receive a baseband transmit signal BB_TX from it and provide it with a baseband receive signal BB_RX. The transceiver (Tx / Rx) 1230 may include a baseband amplifier 1232, an up-conversion mixer 1234, a radio frequency (RF) filter 1236, and a power amplifier 1238. These devices 1232, 1234, 1236, and 1238, cascaded together (where mixer 1234 is coupled to a local oscillator (LO) 1240), are configured to convert the baseband transmit signal BB_TX to an RF transmit signal RF_TX. The transceiver (Tx / Rx) 1230 also includes a low-noise amplifier (LNA) 1242, a down-conversion mixer 1244, a baseband filter 1246, and a baseband amplifier 1248. These cascaded devices 1242, 1244, 1246, and 1248 (where mixer 1244 is coupled to local oscillator (LO) 1240) are configured to convert the RF received signal RF_RX into the baseband received signal BB_RX.

[0099] The wireless communication device 1200 also includes an antenna interface 1250 and at least one antenna 1260. A transceiver 1230 is coupled to at least one antenna 1260 via the antenna interface 1250. The antenna interface 1250 is configured to route an RF transmit signal RF_TX to at least one antenna 1260 for its wireless transmission. The antenna interface 1250 is also configured to route an RF receive signal RF_RX wirelessly received via at least one antenna 1260 to the transceiver 1230. The local oscillator (LO) 1240 may include a delay-locked loop (DLL) or a phase-locked loop (PLL), including any of the signal delay circuits described herein.

[0100] The following provides an overview of the various aspects of this disclosure:

[0101] Aspect 1: An apparatus comprising: a ring oscillator coupled between a first node and a first voltage rail; a control circuit coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node.

[0102] Aspect 2: The apparatus according to Aspect 1, wherein the control circuit comprises: a resistive device; a first current source, the first current source being coupled in series with the resistive device between a second voltage rail and the first voltage rail; a second current source, the second current source being coupled between the second voltage rail and the first node; and an operational amplifier, the operational amplifier including a first input coupled to a third node between the first current source and the resistive device, a second input coupled to the first node, and an output coupled to control inputs of the first current source and the second current source, respectively.

[0103] Aspect 3: The apparatus according to aspect 2, wherein the resistive device includes a switched capacitor resistor or a thin film resistor.

[0104] Aspect 4: The apparatus according to any one of Aspects 2 to 3 further includes a leakage current compensation circuit coupled between the third node and the first voltage rail.

[0105] Aspect 5: The apparatus according to aspect 4, wherein the leakage current compensation circuit includes a leakage current sensor.

[0106] Aspect 6: The apparatus according to aspect 5, wherein the leakage current sensor includes a set of virtual inverters.

[0107] Aspect 7: The apparatus according to aspect 5 or 6 further includes a delay controller coupled to the ring oscillator and the leakage current sensor.

[0108] Aspect 8: The apparatus according to any one of aspects 1 to 7, wherein the control circuit is configured to control the operating point of the ring oscillator.

[0109] Aspect 9: The apparatus according to any one of aspects 1 to 7 further includes a delay controller coupled to the ring oscillator.

[0110] Aspect 10: The apparatus according to any one of Aspects 1 to 9, wherein the ring oscillator comprises: a ring of a cascaded inverter coupled between the first node and the first voltage rail; and a set of capacitors coupled between the output of the ring of the cascaded inverter and the first voltage rail.

[0111] Aspect 11: The apparatus according to aspect 10, wherein each cascaded inverter of the ring oscillator comprises a set of selectable parallel inverters.

[0112] Aspect 12: The apparatus according to aspect 11 further includes a delay controller coupled to select the input of the set of selectable parallel inverters.

[0113] Aspect 13: The apparatus according to any one of Aspects 1 to 12, wherein the delay line comprises: a set of cascaded inverters coupled between the second node and the first voltage rail, wherein the set of cascaded inverters includes an input configured to receive an input signal and an output configured to generate an output signal, the output signal being a delayed version of the input signal; and a set of capacitors coupled between the outputs of the set of cascaded inverters and the first voltage rail.

[0114] Aspect 14: The apparatus according to any one of Aspects 1 to 13, wherein the voltage regulator includes a low dropout (LDO) regulator.

[0115] Aspect 15: An apparatus according to any one of Aspects 1 to 13, wherein the voltage regulator comprises: a field-effect transistor (FET) coupled between a second voltage rail and a second node; and an operational amplifier including a first input coupled to the first node, a second input coupled to the second node, and an output coupled to the gate of the FET.

[0116] Aspect 16: The apparatus according to any one of aspects 1 to 15 further includes a low-pass filter (LPF) coupled to the first node or the second node.

[0117] Aspect 17: The apparatus according to any one of aspects 1 to 4 and 9 to 16 further includes a leakage current compensation circuit coupled to the first node.

[0118] Aspect 18: The apparatus according to aspect 17, wherein the leakage current compensation circuit includes: a leakage current sensor; and a current mirror coupled to the leakage current sensor and the first node.

[0119] Aspect 19: The apparatus according to aspect 18, wherein the leakage current compensation circuit includes a current input error amplifier configured to control a first voltage across the leakage current sensor to correlate it with a second voltage at the first node.

[0120] Aspect 20: A method comprising: generating an oscillating signal based on a first voltage and a first current; controlling the first voltage and the first current such that the ratio of the first voltage to the first current is substantially constant; and delaying an input signal to generate an output signal based on a second voltage associated with the first voltage.

[0121] Aspect 21: The method according to aspect 20, wherein controlling the first voltage and the first current includes: generating a second current associated with the first current; routing the second current through a resistive device to generate a third voltage; and controlling the first current and the second current based on the difference between the third voltage and the first voltage, wherein the first voltage is based on the first current.

[0122] Aspect 22: The method according to aspect 20 or 21 further includes tuning the first voltage, the tuning of the first voltage including selectively enabling one or more parallel inverters in a ring of cascaded parallel inverters.

[0123] Aspect 23: The method according to any one of aspects 20 to 22 further includes: sensing a leakage current in the ring oscillator; and providing a compensation current to the ring oscillator based on the sensed leakage current.

[0124] Aspect 24: According to the method of aspect 23, providing the compensation current to the ring oscillator includes providing the compensation current to the ring oscillator via a control circuit for controlling the first voltage and the first current.

[0125] Aspect 25: An apparatus comprising: means for generating an oscillating signal based on a first voltage and a first current; means for controlling the first voltage and the first current such that the ratio of the first voltage to the first current is substantially constant; and means for delaying an input signal to generate an output signal based on a second voltage associated with the first voltage.

[0126] Aspect 26: The apparatus according to aspect 25 further includes a component for tuning the first voltage, including a component for selectively activating one or more parallel inverters in a ring of cascaded parallel inverters.

[0127] Aspect 27: The apparatus according to aspect 25 or 26, wherein the component for generating the oscillation signal comprises: a component for sensing leakage current in the ring oscillator; and a component for providing a compensation current to the ring oscillator based on the sensed leakage current.

[0128] Aspect 28: A wireless communication device comprising: one or more baseband signal processing modules; at least one antenna; a transceiver coupled to the at least one antenna and the one or more baseband signal processing modules, wherein the transceiver includes: a ring oscillator coupled between a first node and a first voltage rail; control circuitry coupled to the first node; a delay line coupled between a second node and the first voltage rail; and a voltage regulator including an input coupled to the first node and an output coupled to the second node.

[0129] Aspect 29: The wireless communication device according to aspect 28, wherein the ring oscillator includes a ring of cascaded inverters coupled between the first node and the first voltage rail, wherein each cascaded inverter includes a set of selectable parallel inverters; and further includes a delay controller coupled to the set of selectable parallel inverters of each cascaded inverter.

[0130] Aspect 30: The wireless communication device according to aspect 28 or 29 further includes a leakage current compensation circuit coupled to the first node or the control circuit.

[0131] The prior description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the spirit or scope of this disclosure. Thus, this disclosure is not intended to be limited to the examples described herein, but should be accorded the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: A ring oscillator coupled between a first node and a first voltage rail; Control circuit, the control circuit being coupled to the first node; A delay line, which is coupled between the second node and the first voltage rail; and A voltage regulator, the voltage regulator including an input terminal coupled to the first node and an output terminal coupled to the second node, wherein the voltage regulator includes: A field-effect transistor (FET) coupled between a second voltage rail and a second node; and An operational amplifier, the operational amplifier including a first input terminal coupled to the first node, a second input terminal coupled to the second node, and an output terminal coupled to the gate of the FET.

2. The apparatus according to claim 1, wherein the control circuit comprises: Resistive devices; A first current source, wherein the first current source is coupled in series with the resistive device between the second voltage rail and the first voltage rail; A second current source is coupled between the second voltage rail and the first node; and An operational amplifier, comprising a first input terminal coupled to a third node between the first current source and the resistive device, a second input terminal coupled to the first node, and an output terminal coupled to control input terminals of the first current source and the second current source, respectively.

3. The apparatus of claim 2, wherein the resistive device comprises a switched capacitor resistor or a thin film resistor.

4. The apparatus according to claim 2 further includes a leakage current compensation circuit, the leakage current compensation circuit being coupled between the third node and the first voltage rail.

5. The apparatus of claim 4, wherein the leakage current compensation circuit includes a leakage current sensor.

6. The apparatus of claim 5, wherein the leakage current sensor comprises a set of virtual inverters.

7. The apparatus of claim 5 further includes a delay controller coupled to the ring oscillator and the leakage current sensor.

8. The apparatus of claim 1, wherein the control circuit is configured to control the operating point of the ring oscillator.

9. The apparatus of claim 1, further comprising a delay controller coupled to the ring oscillator.

10. The apparatus of claim 1, wherein the ring oscillator comprises: A cascaded inverter loop, wherein the cascaded inverter loop is coupled between the first node and the first voltage rail; and A set of capacitors, wherein the set of capacitors is respectively coupled between the output terminal of the loop of the cascaded inverter and the first voltage rail.

11. The apparatus of claim 10, wherein each cascaded inverter of the ring oscillator comprises a set of selectable parallel inverters.

12. The apparatus of claim 11, further comprising a delay controller coupled to enable the inputs of the set of selectable parallel inverters.

13. The apparatus of claim 1, wherein the delay line comprises: A set of cascaded inverters coupled between the second node and the first voltage rail, wherein the set of cascaded inverters includes an input configured to receive an input signal and an output configured to generate an output signal, the output signal being a delayed version of the input signal; and A set of capacitors, wherein the set of capacitors is respectively coupled between the output terminal of the set of cascaded inverters and the first voltage rail.

14. The apparatus of claim 1, wherein the voltage regulator comprises a low-dropout (LDO) regulator.

15. The apparatus of claim 1, further comprising a low-pass filter (LPF) coupled to at least one of the first node or the second node.

16. The apparatus of claim 1 further includes a leakage current compensation circuit coupled to the first node.

17. The apparatus of claim 16, wherein the leakage current compensation circuit comprises: Leakage current sensor; and A current mirror, which is coupled to the leakage current sensor and the first node.

18. The apparatus of claim 17, wherein the leakage current compensation circuit includes a current input error amplifier configured to control a first voltage across the leakage current sensor to correlate it with a second voltage at the first node.

19. A method for a signal delay circuit, comprising: An oscillation signal is generated based on the first voltage and the first current; The first voltage and the first current are controlled such that the ratio of the first voltage to the first current is substantially constant. as well as The input signal is delayed to generate an output signal based on a second voltage related to the first voltage, wherein controlling the first voltage and the first current includes: Generate a second current related to the first current; The second current is routed through a resistive device to generate a third voltage; and The first current and the second current are controlled based on the difference between the third voltage and the first voltage, wherein the first voltage is based on the first current.

20. The method of claim 19, wherein the signal delay circuit includes a loop of cascaded parallel inverters, the loop of cascaded parallel inverters including one or more parallel inverters, the method further comprising tuning the first voltage, tuning the first voltage including selectively enabling the one or more parallel inverters.

21. The method of claim 19, wherein the signal delay circuit comprises a ring oscillator, and the method further comprises: Sensing the leakage current in the ring oscillator; as well as A compensation current is provided to the ring oscillator based on the sensed leakage current.

22. The method of claim 21, wherein providing the compensation current to the ring oscillator comprises providing the compensation current to the ring oscillator via a control circuit for controlling the first voltage and the first current.

23. An apparatus for a signal delay circuit, comprising: A component for generating an oscillation signal based on a first voltage and a first current; A component for controlling the first voltage and the first current such that the ratio of the first voltage to the first current is substantially constant. and A component for delaying an input signal to generate an output signal based on a second voltage related to the first voltage. The components used to control the first voltage and the first current include: A component used to generate a second current associated with the first current; A component for routing the second current through a resistive device to generate a third voltage; and a component for controlling the first current and the second current based on the difference between the third voltage and the first voltage, wherein the first voltage is based on the first current.

24. The apparatus of claim 23, wherein the signal delay circuit includes a loop of cascaded parallel inverters, the loop of cascaded parallel inverters including one or more parallel inverters, the apparatus further including a component for tuning the first voltage, the component including a component for selectively enabling the one or more parallel inverters.

25. The apparatus of claim 23, wherein the signal delay circuit comprises a ring oscillator, and the apparatus further comprises: Components used to sense leakage current in the ring oscillator; and A component for providing compensation current to the ring oscillator based on the sensed leakage current.

26. A wireless communication device, comprising: One or more baseband signal processing modules; At least one antenna; A transceiver coupled to the at least one antenna and the one or more baseband signal processing modules, wherein the transceiver includes: A ring oscillator coupled between a first node and a first voltage rail; Control circuit, the control circuit being coupled to the first node; Delay line, the delay line being coupled between the second node and the first voltage rail; and A voltage regulator, the voltage regulator including an input terminal coupled to the first node and an output terminal coupled to the second node, wherein the voltage regulator includes: Field-effect transistor (FET), the field-effect transistor (FET) being coupled between a second voltage rail and a second node; and An operational amplifier, the operational amplifier including a first input terminal coupled to the first node, a second input terminal coupled to the second node, and an output terminal coupled to the gate of the FET.

27. The wireless communication device of claim 26, wherein the ring oscillator comprises a ring of cascaded inverters coupled between the first node and the first voltage rail, wherein each cascaded inverter comprises a set of selectable parallel inverters; and further comprises a delay controller coupled to the set of selectable parallel inverters of each cascaded inverter.

28. The wireless communication device according to claim 26 further includes a leakage current compensation circuit, the leakage current compensation circuit being coupled to the first node or the control circuit.

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