Array substrate and display panel

Abstract

The application discloses an array substrate and a display panel. The array substrate comprises a substrate, a common electrode line, a data line, a pixel electrode and a data line shielding electrode. The shielding line comprises a plurality of first shielding lines and a plurality of second shielding lines which are alternately connected in the extension direction of the data line. The first shielding line is arranged in the same layer as the pixel electrode. The second shielding line is arranged between the first shielding line and the data line. The orthogonal projection of the first shielding line and the second shielding line on the substrate covers the orthogonal projection of the data line on the substrate. While the transmittance is considered, the parasitic capacitance between the data line and the shielding line is reduced, the charging efficiency is improved, and the power of the data line is reduced.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to an array substrate and a display panel. Background Technology

[0002] In current Liquid Crystal Display (LCD) panels, to improve pixel electrode transmittance, related technologies use transparent storage capacity and shielding (TSS) located between the data lines and pixel electrodes to replace the data shielding (DBS) placed on the same layer as the pixel electrodes, achieving the same function of shielding the data lines. Because the transparent electrode is transparent and not on the same layer as the pixel electrodes, there is no gap between the transparent electrode and the pixel electrodes to prevent short circuits or crosstalk, which helps to increase the area of ​​the pixel electrode's light-emitting region and improve pixel electrode transmittance. However, with this method, the distance between the transparent electrode and the data lines is larger than the distance between the shielding lines and the data lines, leading to an increase in the parasitic capacitance between the transparent electrode and the data lines. This results in an increased capacitive load on the data lines and a decrease in charging efficiency.

[0003] Therefore, there is an urgent need to provide an array substrate and display panel to solve the above-mentioned technical problems. Summary of the Invention

[0004] This invention provides an array substrate and a display panel to solve the technical problem that existing transparent electrode lines replace shielding lines to shield data lines, resulting in increased parasitic capacitance between the second shielding line and the data line, thereby increasing the capacitive load on the data line and reducing charging efficiency.

[0005] To solve the above problems, the technical solution provided by the present invention is as follows:

[0006] This invention provides an array substrate, comprising:

[0007] Substrate;

[0008] A common electrode line is disposed on the substrate;

[0009] The data cable is located on the common electrode line;

[0010] A pixel electrode is disposed on the data line, and the pixel electrode is insulated from the data line; and

[0011] A masking line is disposed on the data line, including multiple first masking lines and multiple second masking lines alternately connected in a first direction. The first masking lines are disposed on the same layer as the pixel electrode, and the second masking lines are disposed between the first masking lines and the data line.

[0012] Wherein, the orthogonal projections of the first and second shielding lines on the substrate cover the orthogonal projection of the data line on the substrate; the first direction is the extension direction of the data line.

[0013] According to the array substrate provided by the present invention, the array substrate includes a plurality of pixel electrode regions and a plurality of first wiring regions and a plurality of second wiring regions disposed on one side of the pixel electrode regions. The plurality of first wiring regions extend along a first direction and are arranged along a second direction. The plurality of second wiring regions extend along the second direction and are arranged along the first direction. The pixel electrode is located in the pixel electrode region, and the masking line is located in the first wiring region.

[0014] In a top-down view, the first masking line is located on one side of the second trace area, and the second masking line is located at least on one side of the pixel electrode area; the second direction is perpendicular to the first direction.

[0015] According to the array substrate provided by the present invention, in a top view, there are multiple overlapping portions between the multiple first shielding lines and the multiple second shielding lines, and the orthographic projection of the multiple overlapping portions on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate.

[0016] According to the array substrate provided by the present invention, the overlapping portion is located on one side of the second trace area.

[0017] According to the array substrate provided by the present invention, the array substrate includes a plurality of sub-pixel units of different colors arranged sequentially in the second direction, each of the overlapping portions being located on one side of a corresponding sub-pixel unit, and the plurality of overlapping portions being flush with the side of the pixel electrode region of the corresponding sub-pixel unit.

[0018] According to the array substrate provided by the present invention, the plurality of sub-pixel units include a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit arranged in the second direction, and the plurality of overlapping portions include a first overlapping portion, a second overlapping portion, and a third overlapping portion arranged in the second direction. The first overlapping portion is located on the side of the first sub-pixel unit away from the second sub-pixel unit, the second overlapping portion is located on the side of the second sub-pixel unit away from the third sub-pixel unit, and the third overlapping portion is located on the side of the third sub-pixel unit close to the second sub-pixel unit.

[0019] In the first direction, the distance between the first overlapping portion and the pixel electrode region of the first sub-pixel unit is d1, the distance between the second overlapping portion and the pixel electrode region of the second sub-pixel unit is d2, and the distance between the third overlapping portion and the pixel electrode region of the first sub-pixel unit is d3; d1 is greater than d2 and d3.

[0020] According to the array substrate provided by the present invention, in the second direction, the width of the second shielding line is greater than the width of the first shielding line.

[0021] According to the array substrate provided by the present invention, the orthogonal projection of the pixel electrode on the substrate overlaps with the orthogonal projection of the data line on the substrate.

[0022] According to the array substrate provided by the present invention, the array substrate further includes:

[0023] A gate insulating layer covers the side of the common electrode line away from the substrate, and the data line is disposed on the side of the gate insulating layer away from the substrate;

[0024] An insulating dielectric layer covers the side of the data line away from the substrate, and a second shielding line is disposed on the side of the insulating dielectric layer away from the substrate; and

[0025] A leveling layer covers the side of the second masking line away from the substrate, wherein the first masking line and the pixel electrode are disposed on the side of the leveling layer away from the data line;

[0026] The first shielding line is electrically connected to the common electrode line through a first via penetrating the gate insulating layer, the insulating dielectric layer, and the leveling layer, and the second shielding line is electrically connected to the common electrode line through a second via penetrating the gate insulating layer and the insulating dielectric layer.

[0027] According to the array substrate provided by the present invention, the insulating dielectric layer includes a passivation layer and a color resist layer, the passivation layer covers the side of the data line away from the substrate, and the color resist layer is disposed on the side of the passivation layer away from the substrate;

[0028] The color resist layer includes a color resist opening disposed in the second trace area, and the first via and the second via are located within the color resist opening.

[0029] This invention provides a display panel, including the array substrate described above;

[0030] Opposing substrate, disposed opposite to the array substrate; and

[0031] A liquid crystal layer is disposed between the array substrate and the opposing substrate.

[0032] The beneficial effects of this invention are as follows: The array substrate and display panel provided by this invention are constructed by using a first shielding line and a second shielding line disposed in different layers for shielding data lines. The first shielding line is insulated from the pixel electrode in the same layer and located on one side of the second wiring area. The second shielding line is located between the data line and the first shielding line and is at least located on one side of the pixel electrode area. Since the second shielding line is transparent and disposed in a different layer from the pixel electrode, there is no gap limitation between the auxiliary electrode and the pixel electrode, thereby increasing the light-emitting area of ​​the pixel electrode and improving transmittance. While taking into account transmittance, since no pixel electrode is disposed in the second wiring area, the use of a first shielding line disposed in the same layer as the pixel electrode on one side of the second wiring area helps to reduce the parasitic capacitance between the data line and the shielding line, which helps to improve charging efficiency, reduce the power of the data line, and improve the serious heat generation problem of the flip-chip film. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a schematic diagram of a planar structure of an array substrate provided in an embodiment of the present invention;

[0035] Figure 2 It is along Figure 1 A schematic diagram of the cross-sectional structure of A-A' in the diagram;

[0036] Figure 3 This is a schematic diagram of another planar structure of an array substrate provided in an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the planar structure of the shielding line provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of a cross-sectional structure of a display panel provided in an embodiment of the present invention.

[0039] Explanation of reference numerals in the attached figures:

[0040] 100, Sub-pixel unit; 100a, Pixel electrode area; 100b, First trace area; 100c, Second trace area;

[0041] 1001, First sub-pixel unit; 1002, Second sub-pixel unit; 1003, Third sub-pixel unit;

[0042] 101. Substrate; 102. Common electrode line; 103. Gate insulating layer; 104. Active layer; 105. Data line; 106. Insulating dielectric layer; 1061. Passivation layer; 1062. Color resist layer; 1062a. Color resist opening; 107. Masking line; 1071. First masking line; 1072. Second masking line; 107a. Overlapping portion; 108. Pixel electrode; 109. Leveling layer; 110. Thin film transistor; 111. Connecting line; 112. First via; 113. Pixel via;

[0043] 1. Array substrate; 2. Opposing substrate; 3. Liquid crystal layer;

[0044] D1, second direction; D2, first direction. Detailed Implementation

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Furthermore, it should be understood that the specific embodiments described herein are only for illustration and explanation of the present invention and are not intended to limit the present invention. In the present invention, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0046] Please see Figure 1 and Figure 2 This invention provides an array substrate 1, which includes a plurality of sub-pixel units 100. Each sub-pixel unit 100 includes a pixel electrode region 100a, a first wiring region 100b, and a second wiring region 100c. The first wiring region 100b is disposed adjacent to the pixel electrode region 100a and the second wiring region 100c in a second direction D1, and the second wiring region 100c is disposed adjacent to the pixel electrode region 100a in a first direction D2. The first direction D2 is the extension direction of the data line 105, and the second direction D1 is perpendicular to the first direction D2.

[0047] The array substrate 1 includes a substrate 101, a common electrode line 102, a data line 105, a pixel electrode 108, and a masking line 107. The common electrode line 102 is disposed on the substrate 101; the data line 105 is disposed on the common electrode line 102 and located in the first trace area 100b, and the data line 105 is insulated from the common electrode line 102; the pixel electrode 108 is disposed on the data line 105 and located in the pixel electrode area 100a, and the pixel electrode 108 is insulated from the data line 105; the masking line 107 is disposed on the data line 105 and located in the first trace area 100b, and the masking line 107 includes a first masking line 1071 and a second masking line 1072. The first masking line 1071 is insulated from the pixel electrode 108 in the same layer, and the second masking line 1072 is disposed between the first masking line 1071 and the data line 105.

[0048] In this embodiment of the invention, the first masking line 1071 is located on one side of the second trace area 100c, and the second masking line 1072 is located on one side of the pixel electrode area 100a. The orthogonal projections of the first masking line 1071 and the second masking line 1072 on the substrate 101 cover the orthogonal projection of the data line 105 on the substrate 101.

[0049] It should be noted that the principle of using DBS technology to control the liquid crystal potential to achieve light blocking is as follows: the shielding line 107 and the CF common electrode of the CF (Color Film) substrate located on the opposite side of the array substrate 1 are applied to the same common potential, and there is no voltage difference between them. Therefore, no matter what voltage signal is applied to the pixel electrode 108, the liquid crystal sandwiched between the shielding line 107 and the CF common electrode will not rotate. The liquid crystal not rotating means that the phase of the polarized light does not change. In a normally black liquid crystal display, polarized light passing through the first polarizer cannot pass through the second polarizer. Therefore, the shielding line 107 can act as a black matrix, replacing the black matrix for light blocking. Furthermore, this design has the advantage that the shielding line 107 is located on the array substrate 1. When the display panel is made into a curved display and bends, even if the upper and lower substrates are misaligned, the position of the shielding line 107 relative to the data line 105 will not change. Therefore, there is no light leakage problem, which helps to avoid Mura (display defects).

[0050] It is understood that the present invention constructs the shielding line 107 used to shield the data line 105 by using a first shielding line 1071 and a second shielding line 1072 disposed in different layers, with the second shielding line 1072 located on one side of the pixel electrode region 100a. Since the second shielding line 1072 is transparent and disposed in a different layer from the pixel electrode 108, there is no need to consider the possibility of a short circuit between the second shielding line 1072 and the pixel electrode 108. There is no gap limitation between them, and the pixel electrode 108 can extend closer to the data line 105, increasing the area of ​​the light-emitting region of the pixel electrode region 100a, which is beneficial for improving transmittance.

[0051] Meanwhile, the first masking line 1071 is located on one side of the second routing area 100c. This arrangement is due to two reasons: First, since the pixel electrode 108 is not located in the second routing area 100c, the pixel electrode 108 cannot extend into the second routing area 100c. Therefore, the portion of the masking line 107 located on one side of the second routing area 100c does not need to be routed on the same layer as the second masking line 1072. Second, since the second masking line 1072 is located between the first masking line 1071 and the data line 105, the vertical interlayer distance between the second masking line 1072 and the data line 105 in the thickness direction of the array substrate 1 is smaller than the vertical interlayer distance between the first masking line 1071 and the data line 105.

[0052] Regarding the second aspect, it should be noted that, according to the capacitance calculation formula: c = εs / 4πkd, ε is the dielectric constant of the intermediate medium, s is the effective facing area of ​​the two plates, π and k are constants, and d is the distance between the two plates. It is known that the capacitance value is usually related to the effective facing area between the two plates, the distance between the two plates, and the dielectric constant of the medium between the two plates. Among them, the capacitance value is positively correlated with the effective facing area between the two plates and negatively correlated with the distance between the two plates. Therefore, when other parameters are fixed, the smaller the distance d between the two plates, the larger the capacitance value. That is, the capacitance between the second shielding line 1072 and the data line 105 is greater than the capacitance between the first shielding line 1071 and the data line 105. This means that if the second shielding line 1072 is used to completely replace the electrode lines disposed on the same layer as the pixel electrode 108, the increased capacitance between the shielding line 107 and the data line 105 will increase the capacitive load of the data line 105, which is not conducive to improving charging efficiency. The increased power of the data line 105 will cause the chip-on-film (COF) used to provide data signals to the data line 105 to overheat severely, and may even cause it to burn out.

[0053] In this invention, the masking line 107 is formed by alternating the first masking line 1071 and the second masking line 1072. Compared to the scheme where the second masking line 1072 completely replaces the electrode line disposed on the same layer as the pixel electrode 108, this method is beneficial for improving the capacitance degradation between the masking line 107 and the data line 105, thereby improving charging efficiency and reducing the power of the data line 105. Therefore, in this embodiment of the invention, the masking line 107 is neither entirely composed of electrode lines disposed on the same layer as the pixel electrode 108, nor entirely composed of the second masking line 1072, thus simultaneously meeting the requirements of both the transmittance of the pixel electrode 108 and the capacitive load of the data line 105.

[0054] Specifically, the materials of the first masking line 1071 and the pixel electrode 108 include any one of ITO (Indium-Tin-Oxide), IGZO (Indium gallium zinc oxide), and ITO / Ag / ITO stacked materials. It is known that the materials of the first masking line 1071 and the pixel electrode 108 include transparent conductive materials commonly used in the art.

[0055] Specifically, the material of the second shielding line 1072 includes any one of ITO (Indium-Tin-Oxide), IGZO (Indium gallium zinc oxide), and ITO / Ag / ITO stacked materials. It is known that the material of the second shielding line 1072 also includes transparent conductive materials commonly used in the art.

[0056] In this embodiment, the array substrate 1 further includes a thin-film transistor 110 and a gate line located in the second wiring region 100c. The gate line extends along the second direction D1, and the gate line and the data line 105 intersect to define the pixel electrode region 100a. The common electrode line 102 is disposed in the same layer as the gate and gate line of the thin-film transistor 110, both located in the first metal layer. The data line 105 is located in the second metal layer, and the data line 105 is disposed in the same layer as the source and drain of the thin-film transistor 110.

[0057] It should be noted that the common electrode line 102 is subjected to the same voltage signal as the CF common electrode. In order to achieve the same common potential between the shielding line 107 and the CF common electrode, the shielding line 107 in this embodiment is electrically connected to the common electrode line 102. Specifically, in one embodiment, the first shielding line 1071 is electrically connected to the common electrode line 102, and the second shielding line 1072 is connected to an external voltage signal, the voltage of which is the same as the voltage of the common electrode line 102; in another embodiment, both the first shielding line 1071 and the second shielding line 1072 are electrically connected to the common electrode line 102; in yet another embodiment, the first shielding line 1071 is electrically connected to the common electrode line 102, and the first shielding line 1071 is also electrically connected to the second shielding line 1072.

[0058] Considering process errors and precision, from a top-down view, it is difficult to manufacture the first shielding line 1071 near the end of the second shielding line 1072, which is precisely joined to the second shielding line 1072 near the end of the first shielding line 1071. Therefore, in order to ensure that the data line 105 is completely covered by the first shielding line 1071 and the second shielding line 1072, in this embodiment, from a top-down view, there is an overlap portion 107a between the first shielding line 1071 and the second shielding line 1072.

[0059] Furthermore, since the pixel electrode 108 in this embodiment extends towards the data line 105, the edge of the pixel electrode region 100a may be located in the first trace region 100b. Since the pixel electrode 108 and the first masking line 1071 are disposed in the same layer and fabricated through the same process, the spacing of the film patterns, especially the safe distance between different electrodes in the same layer, needs to be ensured during the process to prevent interference between the first masking line 1071 and the pixel electrode 108, which could lead to contact and short circuits or crosstalk. Therefore, in this embodiment, a certain distance needs to be set between the first masking line 1071 and the pixel electrode 108 in the first direction D2. Thus, in this embodiment, in the second direction D1, the orthographic projection of the overlapping portion 107a on the substrate 101 does not overlap with the orthographic projection of the pixel electrode 108 on the substrate 101, to avoid interference from the first masking line 1071 to the pixel electrode 108, which could cause defects.

[0060] Furthermore, the overlapping portion 107a is located on one side of the second trace area 100c, and in the first direction D2, the distance from the overlapping portion 107a to the pixel electrode area 100a is greater than 0.

[0061] In this embodiment, the size of the overlapping portion 107a in the first direction D2 cannot be too large or too small. This is because if the size is too large, the area of ​​the second shielding line 1072 on one side of the second trace area 100c will be large, which is detrimental to improving the parasitic capacitance between the shielding line 107 and the data line 105. If the size is too small, the existing process precision cannot be achieved, resulting in the shielding line 107 not being able to completely cover the data line 105. For example, the inventors of this patent have experimentally determined that the size of the overlapping portion 107a in the first direction D2 is 2-3 micrometers. For instance, the size of the overlapping portion 107a in the first direction D2 can be any one of 2 micrometers, 2.2 micrometers, 2.4 micrometers, 2.6 micrometers, 2.8 micrometers, and 3 micrometers. Of course, the size of the overlapping portion 107a in the first direction D2 should be adaptively set according to the actual situation, and this embodiment of the invention does not impose any limitations on this.

[0062] In this embodiment, the orthographic projection of the pixel electrode 108 on the substrate 101 overlaps with the orthographic projection of the data line 105 on the substrate 101, but the orthographic projection of the pixel electrode 108 on the substrate 101 does not overlap with the orthographic projection of the data line 105 of the adjacent sub-pixel unit 100 on the substrate 101. Further, the orthographic projection of the pixel electrode 108 on the substrate 101 coincides with the orthographic projection of the data line 105 on the substrate 101.

[0063] Please see Figure 3 In this embodiment, the width of the second shielding line 1072 is greater than the width of the first shielding line 1071 in the second direction D1. The reason for this setting is that, as can be seen from the above analysis of the factors affecting the capacitance value, the capacitance value is positively correlated with the effective facing area between the two plates. Furthermore, since the pixel electrode 108 extends to overlap with the second shielding line 1072 in the top view, this embodiment increases the width of the second shielding line 1072 in the second direction D1, thereby increasing the facing area between the second shielding line 1072 and the pixel electrode 108. This increases the storage capacitance between the second shielding line 1072 and the pixel electrode 108, which in turn increases the charging efficiency.

[0064] Please see Figure 4In this embodiment, the plurality of sub-pixel units 100 include sub-pixel units 100 of different colors arranged sequentially in the second direction D1. In the second direction D1, the overlapping portion 107a of the plurality of sub-pixel units is kept flush on the side near the pixel electrode region 100a to reduce the difficulty of fabricating the first masking line 1071 and the second masking line 1072.

[0065] Further, the plurality of sub-pixel units 100 includes a first sub-pixel unit 1001, a second sub-pixel unit 1002, and a third sub-pixel unit 1003 arranged in the second direction D1. The area of ​​the pixel electrode region 100a of the first sub-pixel unit 1001 is smaller than the area of ​​the pixel electrode region 100a of the second sub-pixel unit 1002 and the third sub-pixel unit 1003. The area of ​​the pixel electrode region 100a of the second sub-pixel unit 1002 is equal to the area of ​​the pixel electrode region 100a of the third sub-pixel unit 1003. In the first direction D2, the first sub-pixel unit 1001 is farther away from the corresponding pixel electrode region 100a than the second sub-pixel unit 1002 and the third sub-pixel unit 1003.

[0066] Specifically, in this embodiment, the first sub-pixel unit 1001 can be a blue sub-pixel unit, the second sub-pixel unit 1002 can be one of a red sub-pixel unit and a green sub-pixel unit, and the third sub-pixel unit 1003 can be the other of a red sub-pixel unit and a green sub-pixel unit. Taking the first sub-pixel unit 1001 as a blue sub-pixel unit, the second sub-pixel unit 1002 as a red sub-pixel unit, and the third sub-pixel unit 1003 as a green sub-pixel unit as an example, since the blue sub-pixel unit has lower luminous efficiency and shorter lifespan compared to the red and green sub-pixel units, in order to improve the uniformity of luminous efficiency of sub-pixel units of different colors, the pixel electrode area of ​​the blue sub-pixel unit in this embodiment is larger than the pixel electrode area of ​​the red and green sub-pixel units. That is, the edge of the pixel electrode area of ​​the blue sub-pixel unit near the corresponding second wiring area protrudes upwards beyond the edge of the pixel electrode area of ​​the other two colors near the corresponding second wiring area. Considering the manufacturing difficulty, the overlapping portion 107a of each color pixel unit must be fabricated on the same horizontal line on the side closest to the corresponding pixel electrode area. Therefore, in this embodiment of the invention, the overlapping portion 107a of the blue sub-pixel unit is closer to the corresponding pixel electrode area 100a than the overlapping portions 107a of the red and green sub-pixel units. Specifically, in the first direction D2, the distance from the overlapping portion 107a of the blue sub-pixel unit to the pixel electrode area 100a is d1, the distance from the overlapping portion 107a of the red sub-pixel unit to the pixel electrode area 100a is d2, and the distance from the overlapping portion 107a of the blue sub-pixel unit to the pixel electrode area 100a is d3, so d1 > d2 = d3.

[0067] Please continue reading. Figure 1 and Figure 2 In this embodiment, the array substrate 1 further includes an insulating dielectric layer 106 and a leveling layer 109. The insulating dielectric layer 106 covers the side of the data line 105 away from the substrate 101, and the second shielding line 1072 is disposed on the side of the insulating dielectric layer 106 away from the substrate 101. The leveling layer 109 covers the side of the second shielding line 1072 away from the substrate 101. The first shielding line 1071 and the pixel electrode 108 are disposed on the side of the leveling layer 109 away from the data line 105. The first shielding line 1071 is electrically connected to the common electrode line 102 through a first via 112 penetrating the gate insulating layer 103, the insulating dielectric layer 106, and the leveling layer 109. The second shielding line 1072 is electrically connected to the common electrode line 102 through a second via penetrating the gate insulating layer 103 and the insulating dielectric layer 106.

[0068] Furthermore, the array substrate 1 also includes a connecting line 111 disposed on the same layer as the pixel electrode 108. The connecting line 111 is used to connect the two first shielding lines 1071 located on opposite sides of the second trace area 100c. The present invention does not limit the specific arrangement of the connecting line 111, as long as the first shielding line 1071 is effectively connected and does not interfere with other traces.

[0069] Further, the insulating dielectric layer 106 includes a passivation layer 1061 and a color resist layer 1062. The passivation layer 1061 covers the side of the data line 105 away from the substrate 101, and the color resist layer 1062 is disposed on the side of the passivation layer 1061 away from the substrate 101. The color resist layer 1062 includes a color resist opening 1062a disposed in the second trace area 100c, and the first via 112 and the second via are located within the color resist opening 1062a.

[0070] Accordingly, the color resist layer 1062 includes a plurality of color resist units, each of which is correspondingly disposed with one of the sub-pixel units 100 for emitting light of the corresponding color. The plurality of color resist units may include red color resist units, green color resist units, and blue color resist units. In this embodiment, the array substrate 1 is a COA (Color on Array) array substrate, that is, the color resist units are formed on the array substrate 1, which helps to reduce the color resist offset caused by the misalignment of the upper and lower substrates. In addition, it can also simplify the fabrication process of the CF substrate.

[0071] Specifically, the leveling layer 109 is a flexible organic layer (PFA), and the passivation layer 1061 is an inorganic layer.

[0072] It should be noted that the array substrate 1 further includes a gate insulating layer 103 and an active layer 104. The gate insulating layer 103 covers the common electrode line 102, the gate, and the gate line. The active layer 104 is disposed on the side of the gate insulating layer 103 away from the substrate 101. The material of the gate insulating layer 103 includes any one or more combinations of silicon nitride, silicon oxide, and silicon oxynitride. The gate, the active layer 104, the source, and the drain constitute the thin-film transistor 110. The source is electrically connected to the data line 105, and the drain is electrically connected to the pixel electrode 108 through a pixel via 113. This is prior art and will not be described in detail here.

[0073] Please see Figure 5The present invention also provides a display panel, which is a liquid crystal display panel. The display panel includes the array substrate 1 in the above embodiments, the opposing substrate 2 disposed opposite to the array substrate 1, and the liquid crystal layer 3 disposed between the array substrate 1 and the opposing substrate 2.

[0074] Specifically, the opposing substrate 2 is a color filter substrate, and a common CF electrode is disposed on the opposing substrate 2. There is a voltage difference between the common CF electrode and the pixel electrode 108 on the array substrate 1. This voltage difference can drive the liquid crystal molecules in the liquid crystal layer 3 to rotate, thereby realizing image display. A black matrix is ​​also disposed on the opposing substrate 2. Of course, the black matrix can also be disposed on the array substrate 1.

[0075] The beneficial effects are as follows: The array substrate and display panel provided by the present invention are constructed by using a first shielding line and a second shielding line disposed in different layers for shielding the data lines. The first shielding line is insulated from the pixel electrode in the same layer and located on one side of the second wiring area. The second shielding line is located between the data line and the first shielding line and is at least located on one side of the pixel electrode area. Since the second shielding line is transparent and disposed in a different layer from the pixel electrode, there is no gap limitation between the auxiliary electrode and the pixel electrode, thereby increasing the light-emitting area of ​​the pixel electrode and improving transmittance. While taking into account transmittance, since no pixel electrode is disposed in the second wiring area, the use of a first shielding line disposed in the same layer as the pixel electrode on one side of the second wiring area helps to reduce the parasitic capacitance between the data line and the shielding line, which helps to improve charging efficiency and reduce the power of the data line.

[0076] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. An array substrate, characterized in that, include: Substrate; A common electrode line is disposed on the substrate; The data cable is located on the common electrode line; A pixel electrode is disposed on the data line, and the pixel electrode is insulated from the data line; and A masking line is disposed on the data line, including multiple first masking lines and multiple second masking lines alternately connected in a first direction. The first masking lines are disposed on the same layer as the pixel electrode, and the second masking lines are disposed between the first masking lines and the data line. Wherein, the orthographic projections of the first and second shielding lines on the substrate cover the orthographic projection of the data line on the substrate; the first direction is the extension direction of the data line; Both the first and second shielding wires are made of transparent conductive materials.

2. The array substrate according to claim 1, characterized in that, The array substrate includes a plurality of pixel electrode regions and a plurality of first trace regions and a plurality of second trace regions disposed on one side of the pixel electrode regions. The plurality of first trace regions extend along a first direction and are arranged along a second direction. The plurality of second trace regions extend along the second direction and are arranged along the first direction. The pixel electrode is located in the pixel electrode region, and the masking line is located in the first trace region. In a top-down view, the first masking line is located on one side of the second trace area, and the second masking line is located at least on one side of the pixel electrode area; the second direction is perpendicular to the first direction.

3. The array substrate according to claim 2, characterized in that, From a top-down view, there are multiple overlapping portions between the multiple first masking lines and the multiple second masking lines, and the orthographic projection of the multiple overlapping portions on the substrate does not overlap with the orthographic projection of the pixel electrode on the substrate.

4. The array substrate according to claim 3, characterized in that, The overlapping portion is located on one side of the second wiring area.

5. The array substrate according to claim 4, characterized in that, The array substrate includes a plurality of sub-pixel units of different colors arranged sequentially in the second direction. Each overlapping portion is located on one side of a corresponding sub-pixel unit, and the plurality of overlapping portions are flush with the side of the pixel electrode region of the corresponding sub-pixel unit.

6. The array substrate according to claim 5, characterized in that, The plurality of sub-pixel units include a first sub-pixel unit, a second sub-pixel unit, and a third sub-pixel unit arranged in the second direction, and the plurality of overlapping portions include a first overlapping portion, a second overlapping portion, and a third overlapping portion arranged in the second direction. The first overlapping portion is located on the side of the first sub-pixel unit away from the second sub-pixel unit, the second overlapping portion is located on the side of the second sub-pixel unit away from the third sub-pixel unit, and the third overlapping portion is located on the side of the third sub-pixel unit closer to the second sub-pixel unit. In the first direction, the distance between the first overlapping portion and the pixel electrode region of the first sub-pixel unit is d1, the distance between the second overlapping portion and the pixel electrode region of the second sub-pixel unit is d2, and the distance between the third overlapping portion and the pixel electrode region of the first sub-pixel unit is d3; d1 is greater than d2 and d3.

7. The array substrate according to claim 2, characterized in that, In the second direction, the width of the second shielding line is greater than the width of the first shielding line.

8. The array substrate according to claim 7, characterized in that, The orthographic projection of the pixel electrode on the substrate overlaps with the orthographic projection of the data line on the substrate.

9. The array substrate according to claim 2, characterized in that, The array substrate further includes: A gate insulating layer covers the side of the common electrode line away from the substrate, and the data line is disposed on the side of the gate insulating layer away from the substrate; An insulating dielectric layer covers the side of the data line away from the substrate, and a second shielding line is disposed on the side of the insulating dielectric layer away from the substrate; and A leveling layer covers the side of the second masking line away from the substrate, wherein the first masking line and the pixel electrode are disposed on the side of the leveling layer away from the data line; The first shielding line is electrically connected to the common electrode line through a first via penetrating the gate insulating layer, the insulating dielectric layer, and the leveling layer, and the second shielding line is electrically connected to the common electrode line through a second via penetrating the gate insulating layer and the insulating dielectric layer.

10. The array substrate according to claim 9, characterized in that, The insulating dielectric layer includes a passivation layer and a color resist layer. The passivation layer covers the side of the data line away from the substrate, and the color resist layer is disposed on the side of the passivation layer away from the substrate. The color resist layer includes a color resist opening disposed in the second trace area, and the first via and the second via are located within the color resist opening.

11. A display panel, characterized in that, Includes the array substrate according to any one of claims 1-10; The opposing substrate is disposed opposite to the array substrate; as well as A liquid crystal layer is disposed between the array substrate and the opposing substrate.

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