Array substrate, manufacturing method thereof and display panel

Abstract

The application discloses an array substrate, a manufacturing method thereof and a display panel. The array substrate comprises scan lines and gate electrodes arranged on a substrate; a gate insulating layer covering the scan lines and the gate electrodes; a first active layer, a data line, a source electrode and a drain electrode arranged above the gate insulating layer; a first insulating layer arranged above the gate insulating layer; a common electrode, a second insulating layer and a pixel electrode arranged above the first insulating layer, wherein the pixel electrode is electrically connected with the drain electrode; a bonding pad is arranged in a bonding area at the edge of the substrate, wherein the bonding pad comprises a first bonding pad layer and a second bonding pad layer which are arranged in sequence, the first bonding pad layer is formed by a metal layer, and the second bonding pad layer is formed by a metal oxide semiconductor layer arranged above the substrate after a conductorization treatment. The second bonding pad layer formed by the metal oxide semiconductor layer after the conductorization treatment is arranged above the first bonding pad layer of the metal, so that the first bonding pad layer of the metal can be protected, and the corrosion resistance of the bonding pad is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, its manufacturing method, and a display panel. Background Technology

[0002] With the development of display technology, thin and light display panels are increasingly favored by consumers, especially thin and light display panels (liquid crystal display, LCD). An existing display device includes a thin film transistor array substrate (TFT array substrate), a color filter substrate (CF substrate), and liquid crystal molecules filled between the TFT array substrate and the color filter substrate. When the display device is in operation, driving voltages are applied to the pixel electrodes of the TFT array substrate and the common electrode of the color filter substrate, or to the common electrode and pixel electrodes of the TFT array substrate, respectively. This controls the rotation direction of the liquid crystal molecules between the two substrates, refracting the backlight provided by the backlight module of the display device to display an image.

[0003] After fabrication, thin-film transistor array substrates typically undergo performance testing to determine their quality. The bonding pads in the bonding region are made of a low-resistance metal (such as copper) and need to be exposed for easy bonding. However, during salt spray testing of the TFT array substrate, the exposed bonding pads are prone to corrosion, leading to poor contact after bonding.

[0004] Furthermore, with the rapid development of display technology, touch display panels have become widely accepted and used, such as in smartphones and tablets. Touch display panels utilize embedded touch technology to combine the touch panel and LCD panel into one unit, embedding the touch panel functionality into the LCD panel, thus enabling the LCD panel to simultaneously display and sense touch input.

[0005] In-cell touchscreens integrate touch functionality within the display screen, effectively reducing the overall thickness of the display and simplifying the manufacturing process, resulting in thinner, lighter products with lower production costs, thus gaining widespread popularity. Currently, in-cell touchscreens typically have the touchscreen structure directly mounted on a thin-film transistor array (TFT-LCD) substrate. This involves multiplexing some structural components used for transmitting display signals as touch electrodes within the TFT-LCD substrate; a common approach is to reuse common electrode blocks as touch electrodes. The TFT-LCD substrate needs to be configured not only with scan lines and data lines but also with touch traces, which then transmit common signals and touch signals to the common electrode blocks. Because the actual signal transmission lengths of the touch traces electrically connected to each common electrode block are unequal—that is, the resistance of the portion of the touch trace involved in signal transmission differs—the delay on the common electrode blocks farther from and closer to the touch chip is different, resulting in poor touch performance. Summary of the Invention

[0006] In order to overcome the shortcomings and deficiencies of the prior art, the present invention aims to provide an array substrate and its manufacturing method, as well as a display panel, to solve the problem that the pads of the film transistor array substrate are easily corroded during salt spray testing in the prior art.

[0007] The objective of this invention is achieved through the following technical solution:

[0008] This invention provides an array substrate, comprising:

[0009] Substrate;

[0010] A first metal layer is disposed above the substrate, the first metal layer including a scan line and a gate, the gate being electrically connected to the scan line;

[0011] A gate insulating layer covering the first metal layer;

[0012] A first metal oxide semiconductor layer and a second metal layer are sequentially disposed above the gate insulating layer. The first metal oxide semiconductor layer includes a first active layer, and the second metal layer includes a data line, a source, and a drain. The source is electrically connected to the data line, and the source and the drain are connected through the first active layer.

[0013] A first insulating layer is disposed above the gate insulating layer, the first insulating layer covering the data line, the source, the drain and the first active layer;

[0014] A common electrode, a second insulating layer, and a pixel electrode are disposed above the first insulating layer. The second insulating layer is located between the common electrode and the pixel electrode and insulates and separates the common electrode and the pixel electrode from each other. The pixel electrode is conductively connected to the drain electrode.

[0015] A pad is provided in the bonding area at the edge of the substrate. The pad includes a first pad layer and a second pad layer stacked in sequence. The first pad layer is formed by the first metal layer, and the second pad layer is formed by a metal oxide semiconductor layer disposed above the substrate after being conductiveized.

[0016] Furthermore, the array substrate includes a first transparent electrode layer and a second transparent electrode layer disposed above the first insulating layer, the second insulating layer being located between the first transparent electrode layer and the second transparent electrode layer, the first transparent electrode layer including the common electrode, the second transparent electrode layer including the pixel electrode, and the first transparent electrode layer being located below or above the second transparent electrode layer;

[0017] And / or, the pads include a third pad layer covering the upper surface of the second pad layer, and the first transparent electrode layer or the second transparent electrode layer includes the third pad layer;

[0018] And / or, the pads include a fourth pad layer located between the first pad layer and the second pad layer, and the second metal layer includes the fourth pad layer;

[0019] And / or, the first metal oxide semiconductor layer includes the second pad layer.

[0020] Furthermore, the array substrate includes a second metal oxide semiconductor layer disposed above the second metal layer;

[0021] The second metal oxide semiconductor layer includes the second pad layer;

[0022] And / or, the second metal oxide semiconductor layer includes a conductive protective layer located on the upper surfaces of the data line, the source, and the drain;

[0023] And / or, the second metal-oxide-semiconductor layer includes the pixel electrode or the common electrode;

[0024] And / or, the second metal oxide semiconductor layer includes a second active layer located on the upper surface of the first active layer, and the source and the drain are connected through the first active layer and the second active layer.

[0025] Furthermore, the second metal layer includes touch traces parallel to the data line, the touch traces include a first touch trace and a second touch trace, and the upper surface of the first touch trace is covered with the protective layer;

[0026] The common electrode includes a first common electrode block away from the touch chip and a second common electrode block near the touch chip. The first common electrode block is conductively connected to the corresponding first touch trace, and the second common electrode block is conductively connected to the corresponding second touch trace. Alternatively, the common electrode includes a first common electrode block away from the touch chip, a second common electrode block near the touch chip, and a third common electrode block located between the first common electrode block and the second common electrode block. Both the first common electrode block and the second common electrode block are conductively connected to the corresponding second touch trace. The number of second touch traces connected to each first common electrode block is greater than the number of second touch traces connected to each second common electrode block. The third common electrode block is conductively connected to the corresponding first touch trace.

[0027] Furthermore, the second metal oxide semiconductor layer is located on the upper or lower surface of the first insulating layer and is in contact with the surface of the first insulating layer.

[0028] This application also provides a method for fabricating an array substrate, including:

[0029] Provide substrate;

[0030] A first metal layer is formed on top of the substrate, and the first metal layer is etched to form patterned scan lines and gates, wherein the gates are electrically connected to the scan lines;

[0031] A gate insulating layer covering the first metal layer is formed on the substrate;

[0032] A first metal oxide semiconductor layer is formed above the gate insulating layer, and the first metal oxide semiconductor layer is etched to form a patterned first active layer;

[0033] A second metal layer covering the first metal oxide semiconductor layer is formed above the gate insulating layer. The second metal layer is etched to form patterned data lines, source and drain. The source is electrically connected to the data line. The source and drain are connected through the first active layer.

[0034] A first insulating layer is formed above the gate insulating layer, and the first insulating layer covers the data line, the source, the drain, and the first active layer;

[0035] A common electrode, a second insulating layer, and a pixel electrode are formed above the first insulating layer. The second insulating layer is located between the common electrode and the pixel electrode and insulates and separates the common electrode and the pixel electrode from each other. The pixel electrode is conductively connected to the drain electrode.

[0036] A pad is formed in the bonding area at the edge of the substrate. The pad includes a first pad layer and a second pad layer stacked in sequence. The first pad layer is formed by etching the first metal layer, and the second pad layer is formed by etching and conductor-forming a metal oxide semiconductor layer disposed above the substrate.

[0037] Furthermore, a first transparent electrode layer and a second transparent electrode layer are formed above the first insulating layer, the second insulating layer is located between the first transparent electrode layer and the second transparent electrode layer, the first transparent electrode layer is located below or above the second transparent electrode layer, the first transparent electrode layer is etched to form the patterned common electrode, and the second transparent electrode layer is etched to form the patterned pixel electrode.

[0038] And / or, the pads include a third pad layer covering the upper surface of the second pad layer, and the patterned third pad layer is formed when the first transparent electrode layer or the second transparent electrode layer is etched;

[0039] And / or, the pads include a fourth pad layer located between the first pad layer and the second pad layer, and the patterned fourth pad layer is formed when the second metal layer is etched;

[0040] And / or, when etching the first metal oxide semiconductor layer, a patterned second pad layer is formed.

[0041] Further, it includes: forming a second metal oxide semiconductor layer over the second metal layer;

[0042] The second pad layer is formed by etching and conductor-forming the second metal oxide semiconductor layer;

[0043] And / or, after etching and conductor-forming the second metal oxide semiconductor layer, a protective layer is formed, the protective layer being located on the upper surfaces of the data line, the source, and the drain;

[0044] And / or, the pixel electrode or the common electrode is formed by etching and conductor-forming the second metal oxide semiconductor layer;

[0045] And / or, after etching and conductor-forming the second metal oxide semiconductor layer, a second active layer is formed on the upper surface of the first active layer, and the source and the drain are connected through the first active layer and the second active layer.

[0046] Furthermore, when etching the second metal layer, patterned touch traces are formed. The extension direction of the touch traces is parallel to that of the data lines. The touch traces include a first touch trace and a second touch trace. The upper surface of the first touch trace is covered with the protective layer.

[0047] The common electrode includes a first common electrode block away from the touch chip and a second common electrode block near the touch chip. The first common electrode block is conductively connected to the corresponding first touch trace, and the second common electrode block is conductively connected to the corresponding second touch trace. Alternatively, the common electrode includes a first common electrode block away from the touch chip, a second common electrode block near the touch chip, and a third common electrode block located between the first common electrode block and the second common electrode block. Both the first common electrode block and the second common electrode block are conductively connected to the corresponding second touch trace. The number of second touch traces connected to each first common electrode block is greater than the number of second touch traces connected to each second common electrode block. The third common electrode block is conductively connected to the corresponding first touch trace.

[0048] This application also provides a display panel, including the array substrate described above.

[0049] The beneficial effects of this invention are as follows: by covering the first metal pad layer with a second pad layer formed by conductive treatment of a metal oxide semiconductor layer, the first metal pad layer can be protected, improving the corrosion resistance of the pads and preventing corrosion of the pads during salt spray testing of the array substrate. The second pad layer can be formed by etching the same metal oxide semiconductor layer as the first active layer, reducing manufacturing processes; simultaneously, the data lines, source, and drain are formed by etching a metal layer, ensuring the conductivity of the data lines, source, and drain. Attached Figure Description

[0050] Figure 1 This is a schematic diagram of the array substrate structure in Embodiment 1 of the present invention;

[0051] Figures 2a-2e This is a schematic flowchart of the method for fabricating the array substrate in Embodiment 1 of the present invention;

[0052] Figure 3 This is a schematic diagram of the array substrate structure in Embodiment 2 of the present invention;

[0053] Figures 4a-4e This is a schematic flowchart of the method for fabricating the array substrate in Embodiment 2 of the present invention;

[0054] Figure 5 This is a schematic diagram of the array substrate structure in Embodiment 3 of the present invention;

[0055] Figures 6a-6d This is a schematic flowchart of the method for fabricating the array substrate in Embodiment 3 of the present invention;

[0056] Figure 7 This is a schematic diagram of the array substrate structure in Embodiment 4 of the present invention;

[0057] Figures 8a-8c This is a schematic flowchart of the method for fabricating the array substrate in Embodiment 4 of the present invention;

[0058] Figure 9 This is one of the planar structural schematic diagrams of the array substrate in Embodiment 5 of the present invention;

[0059] Figure 10 This is a schematic diagram of the cross-sectional structure of the array substrate at the first common electrode block in Embodiment 5 of the present invention;

[0060] Figure 11 This is a schematic cross-sectional view of the array substrate at the second common electrode block in Embodiment 5 of the present invention;

[0061] Figure 12 This is the second schematic diagram of the planar structure of the array substrate in Embodiment 5 of the present invention;

[0062] Figure 13 This is a schematic diagram of the planar structure of the array substrate in Embodiment Six of the present invention;

[0063] Figure 14 This is a schematic diagram of the display device in the dark state according to the present invention;

[0064] Figure 15 This is a schematic diagram of the display device in the bright state in this invention. Detailed Implementation

[0065] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation methods, structures, features, and effects of the array substrate and its manufacturing method, and the display panel proposed according to the present invention:

[0066] [Example 1]

[0067] Figure 1 This is a schematic diagram of the array substrate in Embodiment 1 of the present invention. Figure 1 As shown, an array substrate provided in Embodiment 1 of the present invention includes:

[0068] Substrate 10 may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. Substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0069] The first metal layer 11 disposed above the substrate 10 Figure 2a The first metal layer 11 includes scan lines and a gate 111, with the gate 111 electrically connected to the scan lines. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo.

[0070] A gate insulating layer 101 covers the first metal layer 11. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0071] The first metal oxide semiconductor layer 12 is sequentially disposed above the gate insulating layer 101. Figure 2b ) and the second metal layer 13 ( Figure 2c The first metal-oxide-semiconductor layer 12 includes a first active layer 121. The second metal layer 13 includes a data line 131, a source 132, and a drain 133. The source 132 is electrically connected to the data line 131, and the source 132 and the drain 133 are connected through the first active layer 121. Multiple scan lines and multiple data lines 131 are mutually insulated and intersecting to form multiple pixel units. The gate 111, the first active layer 121, the source 132, and the drain 133 together form a thin-film transistor. The first metal-oxide-semiconductor layer 12 is preferably made of a transparent metal-oxide-semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO). The second metal layer 13 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo, Cu / Mo, etc.

[0072] A first insulating layer 102 is disposed above the gate insulating layer 101, and the first insulating layer 102 covers the data line 131, the source 132, the drain 133, and the first active layer 121. The material of the first insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of the two.

[0073] A common electrode 141, a second insulating layer 103, and a pixel electrode 151 are disposed above the first insulating layer 102. The second insulating layer 103 is located between the common electrode 141 and the pixel electrode 151, insulating and separating the common electrode 141 and the pixel electrode 151 from each other. The pixel electrode 151 is electrically connected to the drain electrode 133. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0074] A bonding pad is provided in the bonding area at the edge of the substrate 10. The bonding pad includes a first bonding pad layer 171 and a second bonding pad layer 172 stacked sequentially. The first bonding pad layer 171 is formed by a first metal layer 11, and the second bonding pad layer 172 is formed by a conductor-enhancing treatment of a metal oxide semiconductor layer disposed above the substrate 10. In this embodiment, the second bonding pad layer 172 is formed by a conductor-enhancing treatment of the first metal oxide semiconductor layer 12 disposed above the substrate 10. That is, both the first active layer 121 and the second bonding pad layer 172 are formed by etching the first metal oxide semiconductor layer 12, but the second bonding pad layer 172 needs to undergo a conductor-enhancing treatment to make the second bonding pad layer 172 a conductor, thereby increasing its conductivity.

[0075] In this embodiment, the array substrate includes a first transparent electrode layer 14 disposed above the first insulating layer 102. Figure 2d ) and the second transparent electrode layer 15 ( Figure 2eThe second insulating layer 103 is located between the first transparent electrode layer 14 and the second transparent electrode layer 15. The first transparent electrode layer 14 includes a common electrode 141, and the second transparent electrode layer 15 includes a pixel electrode 151. The first transparent electrode layer 14 is located below the second transparent electrode layer 15, meaning the common electrode 141 is located below the pixel electrode 151. Therefore, the first insulating layer 102 and the second insulating layer 103 need to have contact holes in the areas corresponding to the drain electrode 133 to expose the drain electrode 133, thereby facilitating contact with the pixel electrode 151. Alternatively, the first transparent electrode layer 14 can also be located above the second transparent electrode layer 15, meaning the common electrode 141 is located above the pixel electrode 151. The first transparent conductive layer 14 and the second transparent conductive layer 15 are made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0076] Furthermore, the pads include a third pad layer 173 covering the upper surface of the second pad layer 172, and the second transparent electrode layer 15 includes the third pad layer 173. That is, both the third pad layer 173 and the pixel electrode 151 are etched from the second transparent electrode layer 15, thereby raising the pads for easier bonding. Of course, the first transparent electrode layer 14 may also include the third pad layer 173, that is, both the third pad layer 173 and the common electrode 141 are etched from the first transparent electrode layer 14.

[0077] Figures 2a-2e This is a schematic flowchart of the method for fabricating the array substrate in Embodiment 1 of the present invention. Figures 2a-2e As shown, this embodiment also provides a method for fabricating an array substrate, used to fabricate the array substrate described above. The fabrication method includes:

[0078] like Figure 2a As shown, a substrate 10 is provided, which may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0079] A first metal layer 11 is formed above the substrate 10. The first metal layer 11 is etched to form patterned scan lines, a gate 111, and a first pad layer 171. The gate 111 is electrically connected to the scan lines, and the first pad layer 171 is located in the bonding region at the edge of the substrate 10. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo.

[0080] A gate insulating layer 101 covering the first metal layer 11 is formed on the substrate 10, and the gate insulating layer 101 is etched to form an opening in the region corresponding to the first pad layer 171, thereby exposing the first pad layer 171. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0081] like Figure 2b As shown, a first metal oxide semiconductor layer 12 is formed above the gate insulating layer 101. The first metal oxide semiconductor layer 12 is etched to form a patterned first active layer 121 and a second pad layer 172. The second pad layer 172 is in contact with the first pad layer 171, and the second pad layer 172 is not initially subjected to a conductor treatment. The first metal oxide semiconductor layer 12 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0082] like Figure 2c As shown, a second metal layer 13 covering the first metal-oxide-semiconductor layer 12 is formed above the gate insulating layer 101. The second metal layer 13 is etched to form patterned data lines 131, sources 132, and drains 133. The sources 132 are electrically connected to the data lines 131, and the sources 132 and drains 133 are connected through the first active layer 121. Multiple scan lines and multiple data lines 131 are mutually insulated and intersecting to form multiple pixel units. The gate 111, the first active layer 121, the sources 132, and the drains 133 together form a thin-film transistor. The second metal layer 13 can be made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or combinations of the above metals, such as Al / Mo, Cu / Mo, etc.

[0083] A first insulating layer 102 is formed above the gate insulating layer 101, and the first insulating layer 102 covers the data line 131, the source 132, the drain 133, the first active layer 121, and the second pad layer 172. The material of the first insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0084] like Figure 2d and 2e As shown, a common electrode 141, a second insulating layer 103, and a pixel electrode 151 are formed above the first insulating layer 102. The second insulating layer 103 is located between the common electrode 141 and the pixel electrode 151, insulating and separating the common electrode 141 and the pixel electrode 151 from each other. The pixel electrode 151 is electrically connected to the drain electrode 133. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0085] Specifically, such as Figure 2d As shown, a first transparent electrode layer 14 is formed above the first insulating layer 102. The first transparent electrode layer 14 is etched to form a patterned common electrode 141. The first transparent conductive layer 14 is made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0086] A second insulating layer 103 is formed above the first insulating layer 102 to cover the common electrode 141. The first insulating layer 102 and the second insulating layer 103 are etched simultaneously, so that the first insulating layer 102 and the second insulating layer 103 form contact holes in the region corresponding to the drain 133 and open holes in the region corresponding to the second pad layer 172, so as to expose the drain 133 and the second pad layer 172.

[0087] Using the second insulating layer 103 as a shield, the second pad layer 172 is made conductive, for example by plasma treatment, ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping, thereby making the second pad layer 172 a conductor. By using the second insulating layer 103 as a shield to make the second pad layer 172 conductive, one masking process can be reduced.

[0088] like Figure 2eAs shown, a second transparent electrode layer 15 is formed above the second insulating layer 103. The second transparent electrode layer 15 is etched to form patterned pixel electrodes 151 and a third pad layer 173. The pixel electrodes 151 are electrically connected to the drain 133 through contact holes, and the third pad layer 173 is in conductive contact with the second pad layer 172. The second transparent conductive layer 15 is made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO). Of course, in other embodiments, the third pad layer 173 can also be formed by etching the first transparent electrode layer 14.

[0089] The first pad layer 171, the second pad layer 172, and the third pad layer 173 are sequentially stacked in the bonding area at the edge of the substrate 10 to form a pad.

[0090] [Example 2]

[0091] Figure 3 This is a schematic diagram of the array substrate in Embodiment 2 of the present invention. Figure 3 As shown, the array substrate and its fabrication method provided in Embodiment 2 of the present invention are the same as those in Embodiment 1. Figure 1 The array substrate and its fabrication method are basically the same as those in this embodiment, except that:

[0092] The pads include a fourth pad layer 174 located between the first pad layer 171 and the second pad layer 172. The second metal layer 13 includes the fourth pad layer 174. That is, the fourth pad layer 174, the data line 131, the source 132 and the drain 133 are all etched by the second metal layer 13, thereby raising the pads and making them easier to bond.

[0093] Further, the array substrate includes a second metal oxide semiconductor layer 16 disposed above the second metal layer 13. The second metal oxide semiconductor layer 16 includes a second pad layer 172, which covers the upper surface of the fourth pad layer 174. That is, in this embodiment, the second pad layer 172 is formed by etching and conductive processing of the second metal oxide semiconductor layer 16 disposed above the second metal layer 13. After etching the first metal oxide semiconductor layer 12, only the first active layer 121 is formed. The second metal oxide semiconductor layer 16 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0094] The second metal-oxide-semiconductor layer 16 further includes a conductive protective layer 161. The protective layer 161 is located on the upper surfaces of the data line 131, source 132, and drain 133, and is in direct contact with these surfaces. This reduces the impedance of the data line 131, source 132, and drain 133, thereby increasing their conductivity. Simultaneously, it also provides some protection to the data line 131, source 132, and drain 133, reducing the risk of scratches. Due to the protective effect of the protective layer 161, the thickness of the second insulating layer 103 can be reduced, decreasing the distance between the common electrode 141 and the pixel electrode 151 to meet the application requirements of high-frequency switching.

[0095] In this embodiment, the second metal oxide semiconductor layer 16 is located on the lower surface of the first insulating layer 102 and the upper surface of the second metal layer 13, and is in contact with the surfaces of the first insulating layer 102 and the second metal layer 13.

[0096] In another embodiment, the second metal oxide semiconductor layer 16 may further include a pixel electrode 151 or a common electrode 141, thereby reducing the fabrication and etching of a transparent conductive layer to simplify the process.

[0097] Figures 4a-4e This is a schematic flowchart of the method for fabricating the array substrate in Embodiment 2 of the present invention. Figures 4a-4e As shown, this embodiment also provides a method for fabricating an array substrate, used to fabricate the array substrate described above. The fabrication method includes:

[0098] like Figure 4aAs shown, a substrate 10 is provided, which may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0099] A first metal layer 11 is formed above the substrate 10. The first metal layer 11 is etched to form patterned scan lines, a gate 111, and a first pad layer 171. The gate 111 is electrically connected to the scan lines, and the first pad layer 171 is located in the bonding region at the edge of the substrate 10. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo.

[0100] A gate insulating layer 101 covering the first metal layer 11 is formed on the substrate 10, and the gate insulating layer 101 is etched to form an opening in the region corresponding to the first pad layer 171, thereby exposing the first pad layer 171. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0101] A first metal-oxide-semiconductor layer 12 is formed above the gate insulating layer 101. The first metal-oxide-semiconductor layer 12 is etched to form a patterned first active layer 121. In this embodiment, the second pad layer 172 is not formed after etching the first metal-oxide-semiconductor layer 12. The first metal-oxide-semiconductor layer 12 is preferably made of a transparent metal-oxide-semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0102] like Figure 4bAs shown, a second metal layer 13 and a second metal oxide semiconductor layer 16 are sequentially formed above the gate insulating layer 101. The second metal layer 13 can be made of a metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or a combination of the above metals, such as Al / Mo or Cu / Mo. The second metal oxide semiconductor layer 16 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0103] like Figure 4c As shown, the entire second metal oxide semiconductor layer 16 is subjected to a conductor-making process, such as plasma treatment, ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping, thereby making the entire second metal oxide semiconductor layer 16 a conductor.

[0104] like Figure 4d As shown, the second metal layer 13 and the second metal oxide semiconductor layer 16 are etched simultaneously. The second metal layer 13 forms patterned data lines 131, source 132, drain 133, and a fourth pad layer 174. The source 132 is electrically connected to the data line 131, and the source 132 and drain 133 are connected through a first active layer 121. The fourth pad layer 174 is located in the bonding region at the edge of the substrate 10 and is in contact with the surface of the first pad layer 171. The second metal oxide semiconductor layer 16 forms patterned second pad layer 172 and a protective layer 161. The second pad layer 172 is located in the bonding region at the edge of the substrate 10 and is in contact with the surface of the fourth pad layer 174. The protective layer 161 is located on the upper surface of the data line 131, source 132, and drain 133. Multiple scan lines and multiple data lines 131 are mutually insulated and intersected to form multiple pixel units, and the gate 111, the first active layer 121, the source 132 and the drain 133 together form a thin film transistor.

[0105] like Figure 4e As shown, a first insulating layer 102 is formed above the gate insulating layer 101, and the first insulating layer 102 covers the protective layer 161, the first active layer 121, and the second pad layer 172. The material of the first insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0106] Please refer to Figure 2d and 2eAs shown, a common electrode 141, a second insulating layer 103, and a pixel electrode 151 are formed above the first insulating layer 102. The second insulating layer 103 is located between the common electrode 141 and the pixel electrode 151, insulating and separating the common electrode 141 and the pixel electrode 151 from each other. The pixel electrode 151 is electrically connected to the drain electrode 133. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0107] Please refer to Figure 2d As shown, a first transparent electrode layer 14 is formed above the first insulating layer 102. The first transparent electrode layer 14 is etched to form a patterned common electrode 141. The first transparent conductive layer 14 is made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0108] A second insulating layer 103 covering the common electrode 141 is formed above the first insulating layer 102. The first insulating layer 102 and the second insulating layer 103 are etched simultaneously, so that the first insulating layer 102 and the second insulating layer 103 form contact holes in the region corresponding to the drain 133 and open holes in the region corresponding to the second pad layer 172, so as to expose the protective layer 161 at the second pad layer 172 and the drain 133.

[0109] Please refer to Figure 2e As shown, a second transparent electrode layer 15 is formed above the second insulating layer 103. The second transparent electrode layer 15 is etched to form patterned pixel electrodes 151 and a third pad layer 173. The pixel electrodes 151 are electrically connected to the drain electrode 133 through contact holes, and the third pad layer 173 is electrically connected to the second pad layer 172. The second transparent conductive layer 15 is made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0110] The first pad layer 171, the fourth pad layer 174, the second pad layer 172 and the third pad layer 173 are stacked sequentially in the bonding area at the edge of the substrate 10 to form a pad.

[0111] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0112] [Example 3]

[0113] Figure 5 This is a schematic diagram of the array substrate in Embodiment 3 of the present invention. Figure 5 As shown, the array substrate and its fabrication method provided in Embodiment 3 of the present invention are similar to those in Embodiment 2. Figures 3 to 4e The array substrate and its fabrication method are basically the same as those in this embodiment, except that:

[0114] The array substrate includes a second metal oxide semiconductor layer 16 disposed above the second metal layer 13. The second metal oxide semiconductor layer 16 includes a second pad layer 172, which covers the upper surface of the fourth pad layer 174. In this embodiment, the second pad layer 172 is formed by etching and conductive treatment of the second metal oxide semiconductor layer 16 disposed above the second metal layer 13. After etching the first metal oxide semiconductor layer 12, only the first active layer 121 is formed. The second metal oxide semiconductor layer 16 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0115] The second metal-oxide-semiconductor layer 16 further includes a conductive protective layer 161. The protective layer 161 is located on the upper surface of the data line 131, the source 132, and the drain 133, thereby reducing the impedance of the data line 131, the source 132, and the drain 133 and increasing their conductivity. At the same time, it also provides some protection for the data line 131, the source 132, and the drain 133.

[0116] The second metal-oxide-semiconductor layer 16 includes a second active layer 162 located on the upper surface of the first active layer 121. The second active layer 162 is in direct contact with the upper surface of the first active layer 121. The source 132 and the drain 133 are connected through the first active layer 121 and the second active layer 162. The gate 111, the first active layer 121, the second active layer 162, the source 132, and the drain 133 together form a thin-film transistor. By connecting the source 132 and the drain 133 through the first active layer 121 and the second active layer 162, the conduction performance of the thin-film transistor can be increased.

[0117] In another embodiment, the second metal oxide semiconductor layer 16 may further include a pixel electrode 151 or a common electrode 141, thereby reducing the fabrication and etching of a transparent conductive layer to simplify the process.

[0118] Figures 6a-6d This is a schematic flowchart of the fabrication method of the array substrate in Embodiment 3 of the present invention. Figures 6a-6d As shown, this embodiment also provides a method for fabricating an array substrate, used to fabricate the array substrate described above. The fabrication method includes:

[0119] like Figure 6a As shown, a substrate 10 is provided, which may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0120] A first metal layer 11 is formed above the substrate 10. The first metal layer 11 is etched to form patterned scan lines, a gate 111, and a first pad layer 171. The gate 111 is electrically connected to the scan lines, and the first pad layer 171 is located in the bonding region at the edge of the substrate 10. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo.

[0121] A gate insulating layer 101 covering the first metal layer 11 is formed on the substrate 10, and the gate insulating layer 101 is etched to form an opening in the region corresponding to the first pad layer 171, thereby exposing the first pad layer 171. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0122] A first metal-oxide-semiconductor layer 12 is formed above the gate insulating layer 101. The first metal-oxide-semiconductor layer 12 is etched to form a patterned first active layer 121. In this embodiment, the second pad layer 172 is not formed after etching the first metal-oxide-semiconductor layer 12. The first metal-oxide-semiconductor layer 12 is preferably made of a transparent metal-oxide-semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0123] A second metal layer 13 is formed above the gate insulating layer 101. The second metal layer 13 is etched to form patterned data lines 131, a source 132, a drain 133, and a fourth pad layer 174. The source 132 is electrically connected to the data line 131, and the source 132 and the drain 133 are connected through a first active layer 121. The fourth pad layer 174 is located in the bonding region at the edge of the substrate 10 and is in contact with the surface of the first pad layer 171. Multiple scan lines and multiple data lines 131 are mutually insulated and intersected to form multiple pixel units. The second metal layer 13 can be made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals, such as Al / Mo or Cu / Mo.

[0124] like Figure 6b As shown, a second metal oxide semiconductor layer 16 covering the second metal layer 13 is formed above the gate insulating layer 101. The second metal oxide semiconductor layer 16 is etched to form a patterned second pad layer 172, a protective layer 161, and a second active layer 162. The second pad layer 172 is located in the bonding region at the edge of the substrate 10 and is in contact with the surface of the fourth pad layer 174. The protective layer 161 is located on the upper surface of the data line 131, the source 132, and the drain 133. The second active layer 162 is located on the upper surface of the first active layer 121 and is in contact with the surface of the first active layer 121. The gate 111, the first active layer 121, the second active layer 162, the source 132, and the drain 133 together form a thin film transistor.

[0125] like Figure 6cAs shown, the second pad layer 172 and the protective layer 161 are made conductive, for example, by plasma treatment, ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping, thereby making the second pad layer 172 and the protective layer 161 conductive, while the second active layer 162 retains semiconductor properties. Specifically, a photoresist layer covering the second pad layer 172, the protective layer 161, and the second active layer 162 is formed above the gate insulating layer 101. The photoresist layer is patterned, retaining the photoresist at the second active layer 162, and then the second pad layer 172 and the protective layer 161 are made conductive using the patterned photoresist layer as a mask. The mask used for patterning the photoresist layer can be the same mask used for etching the first active layer 121; alternatively, an additional mask can be used, but this would increase manufacturing costs.

[0126] like Figure 6d As shown, a first insulating layer 102 is formed above the gate insulating layer 101, and the first insulating layer 102 covers the protective layer 161, the first active layer 121, the second pad layer 172, and the second active layer 162. The material of the first insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0127] Please refer to Figure 2d and 2e As shown, a common electrode 141, a second insulating layer 103, and a pixel electrode 151 are formed above the first insulating layer 102. The second insulating layer 103 is located between the common electrode 141 and the pixel electrode 151, insulating and separating the common electrode 141 and the pixel electrode 151 from each other. The pixel electrode 151 is electrically connected to the drain electrode 133. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0128] Please refer to Figure 2d As shown, a first transparent electrode layer 14 is formed above the first insulating layer 102, and the first transparent electrode layer 14 is etched to form a patterned common electrode 141. The first transparent conductive layer 14 is made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0129] A second insulating layer 103 covering the common electrode 141 is formed above the first insulating layer 102. The first insulating layer 102 and the second insulating layer 103 are etched simultaneously, so that the first insulating layer 102 and the second insulating layer 103 form contact holes in the region corresponding to the drain 133 and open holes in the region corresponding to the second pad layer 172, so as to expose the protective layer 161 at the second pad layer 172 and the drain 133.

[0130] Please refer to Figure 2e As shown, a second transparent electrode layer 15 is formed above the second insulating layer 103. The second transparent electrode layer 15 is etched to form patterned pixel electrodes 151 and a third pad layer 173. The pixel electrodes 151 are electrically connected to the drain electrode 133 through contact holes, and the third pad layer 173 is electrically connected to the second pad layer 172. The second transparent conductive layer 15 is made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0131] The first pad layer 171, the fourth pad layer 174, the second pad layer 172 and the third pad layer 173 are stacked sequentially in the bonding area at the edge of the substrate 10 to form a pad.

[0132] Those skilled in the art should understand that the remaining structure and working principle of this embodiment are the same as those of Embodiment 2, and will not be repeated here.

[0133] [Example 4]

[0134] Figure 7 This is a schematic diagram of the array substrate in Embodiment 4 of the present invention. Figure 7 As shown, the array substrate and its fabrication method provided in Embodiment 4 of the present invention are the same as those in Embodiment 1. Figures 1 to 2e The array substrate and its fabrication method are basically the same as those in this embodiment, except that:

[0135] The pads include a fourth pad layer 174 located between the first pad layer 171 and the second pad layer 172. The second metal layer 13 includes the fourth pad layer 174. That is, the fourth pad layer 174, the data line 131, the source 132 and the drain 133 are all etched by the second metal layer 13, thereby raising the pads and making them easier to bond.

[0136] Further, the array substrate includes a second metal oxide semiconductor layer 16 disposed above the second metal layer 13. The second metal oxide semiconductor layer 16 includes a second pad layer 172, which covers the upper surface of the fourth pad layer 174. That is, in this embodiment, the second pad layer 172 is formed by etching and conductive processing of the second metal oxide semiconductor layer 16 disposed above the second metal layer 13. After etching the first metal oxide semiconductor layer 12, only the first active layer 121 is formed. The second metal oxide semiconductor layer 16 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0137] The second metal-oxide-semiconductor layer 16 includes a pixel electrode 151, meaning that the pixel electrode 151 and the second pad layer 172 are formed by etching the second metal-oxide-semiconductor layer 16 together. Of course, in other embodiments, the common electrode 141 and the second pad layer 172 may also be formed by etching the second metal-oxide-semiconductor layer 16 together.

[0138] In this embodiment, the second metal oxide semiconductor layer 16 is located on the upper surface of the first insulating layer 102 and the lower surface of the second insulating layer 103, and is in contact with the surfaces of the first insulating layer 102 and the second insulating layer 103.

[0139] In another embodiment, the second metal-oxide-semiconductor layer 16 may further include a protective layer 161, which covers the upper surfaces of the data line 131, the source 132, and the drain 133. This reduces the impedance of the data line 131, the source 132, and the drain 133, thereby increasing their conductivity; simultaneously, it also provides some protection for the data line 131, the source 132, and the drain 133.

[0140] Figures 8a-8c This is a schematic flowchart of the fabrication method of the array substrate in Embodiment 4 of the present invention. Figures 8a-8c As shown, this embodiment also provides a method for fabricating an array substrate, used to fabricate the array substrate described above. The fabrication method includes:

[0141] like Figure 8aAs shown, a substrate 10 is provided, which may be made of materials such as glass, quartz, silicon, acrylic or polycarbonate. The substrate 10 may also be a flexible substrate. Suitable materials for flexible substrates include, for example, polyethersulfone (PES), polyethylene naphthalate (PEN), polyethylene (PE), polyimide (PI), polyvinyl chloride (PVC), polyethylene terephthalate (PET) or combinations thereof.

[0142] A first metal layer 11 is formed above the substrate 10. The first metal layer 11 is etched to form patterned scan lines, a gate 111, and a first pad layer 171. The gate 111 is electrically connected to the scan lines, and the first pad layer 171 is located in the bonding region at the edge of the substrate 10. The first metal layer 11 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo or Cu / Mo.

[0143] A gate insulating layer 101 covering the first metal layer 11 is formed on the substrate 10, and the gate insulating layer 101 is etched to form an opening in the region corresponding to the first pad layer 171, thereby exposing the first pad layer 171. The first insulating layer 101 is a gate insulating layer, and the material of the first insulating layer 101 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0144] A first metal-oxide-semiconductor layer 12 is formed above the gate insulating layer 101. The first metal-oxide-semiconductor layer 12 is etched to form a patterned first active layer 121. In this embodiment, the second pad layer 172 is not formed after etching the first metal-oxide-semiconductor layer 12. The first metal-oxide-semiconductor layer 12 is preferably made of a transparent metal-oxide-semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0145] A second metal layer 13 is formed above the gate insulating layer 101. The second metal layer 13 is etched to form patterned data lines 131, a source 132, a drain 133, and a fourth pad layer 174. The source 132 is electrically connected to the data line 131, and the source 132 and the drain 133 are connected through a first active layer 121. The fourth pad layer 174 is located in the bonding region at the edge of the substrate 10 and is in contact with the surface of the first pad layer 171. Multiple scan lines and multiple data lines 131 are mutually insulated and intersected to form multiple pixel units. The gate 111, the first active layer 121, the source 132, and the drain 133 together form a thin-film transistor. The second metal layer 13 can be made of metal, such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), etc., or a combination of the above metals, such as Al / Mo, Cu / Mo, etc.

[0146] A first insulating layer 102 is formed above the gate insulating layer 101, covering the data line 131, source 132, drain 133, first active layer 121, and fourth pad layer 174. The first insulating layer 102 is etched to form contact holes in the region corresponding to the drain 133 and openings in the region corresponding to the fourth pad layer 174, thereby exposing the fourth pad layer 174 and the drain 133. The material of the first insulating layer 102 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0147] A second metal oxide semiconductor layer 16 is formed above the first insulating layer 102. The second metal oxide semiconductor layer 16 is etched to form a patterned second pad layer 172 and a pixel electrode 151. The second pad layer 172 is located in the bonding area at the edge of the substrate 10 and is in contact with the surface of the fourth pad layer 174. The pixel electrode 151 is electrically connected to the drain 133 through a contact hole on the first insulating layer 102.

[0148] like Figure 8b As shown, the second pad layer 172 and pixel electrode 151 are made conductive, for example by plasma treatment, ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping, thereby making the second pad layer 172 and pixel electrode 151 conductive. Of course, in other embodiments, the second metal oxide semiconductor layer 16 can be made conductive first and then etched.

[0149] like Figure 8cAs shown, a second insulating layer 103 covering the pixel electrode 151 is formed above the first insulating layer 102. The second insulating layer 103 is simultaneously etched to form an opening in the region corresponding to the second pad layer 172, thereby exposing the second pad layer 172. The material of the second insulating layer 103 is silicon oxide (SiOx), silicon nitride (SiNx), or a combination of both.

[0150] A first transparent electrode layer 14 is formed above the second insulating layer 103. The first transparent electrode layer 14 is etched to form a patterned common electrode 141 and a third pad layer 173. The third pad layer 173 makes conductive contact with the second pad layer 172. The first transparent conductive layer 14 is made of indium tin oxide (ITO), indium zinc oxide (IZO), cadmium tin oxide (CTO), aluminum zinc oxide (AZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), cadmium oxide (CdO), hafnium oxide (HfO), indium gallium zinc oxide (InGaZnO), indium gallium zinc magnesium oxide (InGaZnMgO), indium gallium magnesium oxide (InGaMgO), or indium gallium aluminum oxide (InGaAlO).

[0151] The first pad layer 171, the fourth pad layer 174, the second pad layer 172 and the third pad layer 173 are stacked sequentially in the bonding area at the edge of the substrate 10 to form a pad.

[0152] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0153] [Example 5]

[0154] Figure 9 This is one of the schematic diagrams of the planar structure of the array substrate in Embodiment 5 of the present invention. Figure 10 This is a schematic diagram of the cross-sectional structure of the array substrate at the first common electrode block in Embodiment 5 of the present invention. Figure 11 This is a schematic diagram of the cross-sectional structure of the array substrate at the second common electrode block in Embodiment 5 of the present invention. Figure 12 This is the second schematic diagram of the planar structure of the array substrate in Embodiment 5 of the present invention. For example... Figures 9-12 As shown, the array substrate and its fabrication method provided in Embodiment 5 of the present invention are similar to those in Embodiment 2. Figures 3 to 4e Example 3 Figures 5 to 6d Example 4 Figures 7 to 8c The array substrate and its fabrication method are basically the same as those in this embodiment, except that:

[0155] The pads include a fourth pad layer 174 located between the first pad layer 171 and the second pad layer 172. The second metal layer 13 includes the fourth pad layer 174. That is, the fourth pad layer 174, the data line 131, the source 132, and the drain 133 are all etched from the second metal layer 13, thereby raising the pads for easy bonding. Of course, in other embodiments, the fourth pad layer 174 may not be provided.

[0156] The array substrate includes a second metal oxide semiconductor layer 16 disposed above the second metal layer 13. The second metal oxide semiconductor layer 16 includes a second pad layer 172, which covers the upper surface of the fourth pad layer 174. In this embodiment, the second pad layer 172 is formed by etching and conductive treatment of the second metal oxide semiconductor layer 16 disposed above the second metal layer 13. After etching the first metal oxide semiconductor layer 12, only the first active layer 121 is formed. The second metal oxide semiconductor layer 16 is preferably made of a transparent metal oxide semiconductor material, such as indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), zinc tin oxide (ZnSnO), gallium tin oxide (GaSnO), gallium zinc oxide (GaZnO), indium gallium zinc oxide (IGZO), or indium gallium zinc tin oxide (IGZTO).

[0157] In this embodiment, the second metal layer 13 includes touch traces 134 parallel to the data line 131. The touch traces 134 include a first touch trace 134a and a second touch trace 134b. The common electrode 141 includes a first common electrode block 141a at the end away from the touch chip 100 and a second common electrode block 141b at the end closer to the touch chip 100. The first common electrode block 141a is electrically connected to the corresponding first touch trace 134a, and the second common electrode block 141b is electrically connected to the corresponding second touch trace 134b. The common electrode 141 can be electrically connected to the corresponding touch trace 134 through contact holes in the first insulating layer 102 and the second insulating layer 103. The touch trace 134 can apply a common voltage signal to the common electrode 141 during the display phase to achieve normal screen display; it can also apply a touch signal to the common electrode 141 during the touch phase to achieve normal touch functionality.

[0158] The second metal-oxide-semiconductor layer 16 further includes a conductive protective layer 161. The protective layer 161 is located on the upper surface of the data line 131, source 132, drain 133, and first touch trace 134a, thereby reducing the impedance of the data line 131, source 132, drain 133, and first touch trace 134a, and increasing their conductivity. Simultaneously, it also provides some protection for the data line 131, source 132, drain 133, and first touch trace 134a. The upper surface of the second touch trace 134b does not require the protective layer 161.

[0159] Since the first touch trace 134a is provided with a protective layer 161, and the upper surface of the second touch trace 134b is not provided with a protective layer 161, the resistance difference between the first touch trace 134a and the second touch trace 134b participating in the signal transmission is reduced, and the delay difference between the common electrode blocks (first common electrode block 141a and second common electrode block 141b) far away from and near the touch chip 100 is reduced, thereby increasing the touch effect.

[0160] Furthermore, in the common electrode 141, the N / 2 rows away from the touch chip 100 are the first common electrode block 141a, and the N / 2 rows closer to the touch chip 100 are the second common electrode block 141b, where N is the total number of rows of the common electrode 141.

[0161] In this embodiment, the second metal-oxide-semiconductor layer 16 is located on the upper surface of the first insulating layer 102 and the lower surface of the second insulating layer 103, and is in contact with the surfaces of the first insulating layer 102 and the second insulating layer 103. When etching the first insulating layer 102, the data line 131, source 132, drain 133, fourth pad layer 174, and first touch trace 134a need to be exposed. Of course, in other embodiments, the second metal-oxide-semiconductor layer 16 may also be located on the lower surface of the first insulating layer 102 and the upper surface of the second metal layer 13, and be in contact with the surfaces of the first insulating layer 102 and the second metal layer 13.

[0162] Furthermore, the second metal-oxide-semiconductor layer 16 includes a pixel electrode 151, meaning that the pixel electrode 151 and the second pad layer 172 are etched together by the second metal-oxide-semiconductor layer 16. Alternatively, in other embodiments, the common electrode 141 and the second pad layer 172 may also be etched together by the second metal-oxide-semiconductor layer 16. In other embodiments, the protective layer 161 may not be provided on the surfaces of the data line 131, source 132, and drain 133; instead, it may only be provided on the upper surface of the first touch trace 134a; and / or, the pixel electrode 151 may not be provided at all.

[0163] like Figure 9 As shown, each touch trace 134 is of equal length and extends from the far end of the touch chip 100 to its electrical connection with the touch chip 100. That is, each touch trace 134 passes through the entire row of common electrode blocks, meaning each touch trace 134 crosses the same number of common electrode blocks. This method is called a through-type method. Figure 10 As shown, in each column of common electrode blocks, the touch traces 134 electrically connected to each common electrode block are of unequal length. Specifically, the touch traces 134 gradually shorten from left to right, meaning the number of common electrode blocks crossed by the touch traces 134 gradually decreases from left to right. This method is called a non-through method. In the non-through method, the metal traces 135 that are cut off between two adjacent common electrode blocks are electrically connected to the corresponding common electrode block through contact holes, thereby reducing the parasitic capacitance between the common electrode blocks and avoiding affecting the touch function and screen display function.

[0164] The method for fabricating the array substrate provided in Embodiment 2 is the same as that in Embodiment 4. Figures 7 to 8c The manufacturing method is basically the same as that in the previous embodiment, except that in this embodiment:

[0165] The second metal layer 13 is etched to form patterned data lines 131, source 132, drain 133, a fourth pad layer 174, and touch traces 134. The source 132 is electrically connected to the data line 131, and the source 132 and drain 133 are connected through a first active layer 121. The fourth pad layer 174 is located within the bonding area at the edge of the substrate 10 and contacts the surface of the first pad layer 171. The extension directions of the touch traces 134 and the data lines 131 are parallel to each other. Multiple scan lines and multiple data lines 131 are mutually insulated and intersecting to form multiple pixel units. The gate 111, the first active layer 121, the source 132, and the drain 133 together form a thin-film transistor. The second metal layer 13 can be made of metals such as copper (Cu), silver (Ag), chromium (Cr), molybdenum (Mo), aluminum (Al), titanium (Ti), manganese (Mn), nickel (Ni), or combinations of the above metals such as Al / Mo, Cu / Mo, etc.

[0166] The second metal oxide semiconductor layer 16 is etched to form a patterned second pad layer 172, a pixel electrode 151, and a protective layer 161. The second pad layer 172 is located in the bonding area at the edge of the substrate 10 and is in contact with the surface of the fourth pad layer 174. The pixel electrode 151 is electrically connected to the drain electrode 133 through a contact hole on the first insulating layer 102. The touch trace 134 includes a first touch trace 134a and a second touch trace 134b. The protective layer 161 covers the data line 131, the source 132, the drain 133, and the upper surface of the first touch trace 134a, thereby reducing the impedance of the data line 131, the source 132, the drain 133, and the first touch trace 134a, and increasing the conductivity of the data line 131, the source 132, the drain 133, and the first touch trace 134a; at the same time, it can also provide a certain degree of protection for the data line 131, the source 132, the drain 133, and the first touch trace 134a.

[0167] The second pad layer 172, pixel electrode 151, and protective layer 161 are made conductive, for example, by plasma treatment, ion bombardment, hydrogen (H2) doping, helium (He) doping, and argon (Ar) doping, thereby making the second pad layer 172, pixel electrode 151, and protective layer 161 conductive. Preferably, the second metal oxide semiconductor layer 16 can be made conductive first and then etched, thereby reducing the masking process during the conductive treatment.

[0168] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiments 2, 3, and 4, and will not be repeated here.

[0169] [Example 6]

[0170] Figure 13 This is a schematic diagram of the planar structure of the array substrate in Embodiment Six of the present invention. Figure 13 As shown, the array substrate and its fabrication method provided in Embodiment Six of the present invention are similar to those in Embodiment Five. Figures 9 to 12 The array substrate and its fabrication method are basically the same as those in this embodiment, except that:

[0171] The common electrode 141 includes a first common electrode block 141a away from the touch chip 100, a second common electrode block 141b close to the touch chip 100, and a third common electrode block 141c located between the first common electrode block 141a and the second common electrode block 141b. The first common electrode block 141a and the second common electrode block 141b are both electrically connected to the corresponding second touch traces 134b. The number of second touch traces 134b connected to each first common electrode block 141a is greater than the number of second touch traces 134b connected to each second common electrode block 141b. The third common electrode block 141c is electrically connected to the corresponding first touch trace 134a. The number of second touch traces 134b connected to each second common electrode block 141b is the same as the number of first touch traces 134a connected to each third common electrode block 141c. In this embodiment, each first common electrode block 141a is connected to two second touch lines 134b, each second common electrode block 141b is connected to one second touch line 134b, and each third common electrode block 141c is connected to one first touch line 134a.

[0172] Because the first touch trace 134a has a protective layer 161, the upper surface of the second touch trace 134b does not have a protective layer 161, and the number of first common electrode blocks 141a connected to the second touch traces 134b is greater than the number of second common electrode blocks 141b connected to the second touch traces 134b, the delay difference on the common electrode blocks (first common electrode block 141a, second common electrode block 141b, and third common electrode block 141c) that are far from and close to the touch chip 100 is further reduced, thereby increasing the touch effect.

[0173] Furthermore, the N / 3 rows of the common electrode 141 furthest from the touch chip 100 are the first common electrode block 141a, the N / 3 rows of the common electrode 141 furthest from the touch chip 100 are the second common electrode block 141b, and the N / 3 rows between the first common electrode block 141a and the second common electrode block 141b are the third common electrode block 141c, where N is the total number of rows of the common electrode 141.

[0174] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 5, and will not be repeated here.

[0175] Figure 14 This is a schematic diagram of the display device in the dark state in this invention. Figure 15 This is a schematic diagram of the display device in the present invention in the illuminated state. (See attached diagram.) Figure 14 and Figure 15 As shown, this application also provides a display device, including a display panel and a backlight module 50, wherein the backlight module 50 is located below the display panel and is used to provide a backlight source for the display panel.

[0176] The display panel includes an array substrate, a color filter substrate 20 disposed opposite to the array substrate, and a liquid crystal layer 30 located between the array substrate and the color filter substrate 20. The array substrate is the array substrate described in Embodiments 1 to 6. The liquid crystal layer 30 uses positive liquid crystal molecules, i.e., liquid crystal molecules with positive dielectric anisotropy, such as… Figure 14 As shown, in the initial state, the positive liquid crystal molecules in the liquid crystal layer 30 are aligned parallel to the color filter substrate 20 and the array substrate, and the alignment direction of the positive liquid crystal molecules on the side closer to the color filter substrate 20 is parallel to that of the positive liquid crystal molecules on the side closer to the array substrate.

[0177] The color filter substrate 20 has multiple color resist layers 22 corresponding to pixel units on the side facing the liquid crystal layer 30, and black matrices (BM) 21 that space the multiple color resist layers 22 apart from each other. A black matrix 21 is provided between any two adjacent columns and two adjacent rows of pixel units. The color resist layers 22 include red (R), green (G), and blue (B) color resist materials, respectively forming red, green, and blue pixel units. The black matrices 21 are located between the red, green, and blue pixel units, separating adjacent pixel units from each other. An upper polarizer 41 is provided on the side of the color filter substrate 20 away from the liquid crystal layer 30, and a lower polarizer 42 is provided on the side of the array substrate away from the liquid crystal layer 30. The transmission axis of the upper polarizer 41 and the transmission axis of the lower polarizer 42 are perpendicular to each other.

[0178] The backlight module 50 can be an edge-lit backlight module or a direct-lit backlight module. Preferably, the backlight module 50 adopts a collimated backlight (CBL) mode, which can collect light and ensure display effect. The backlight module 50 includes a backlight source 51 and a privacy layer 53, which is used to reduce the range of light emission angle. A brightness enhancement film 52 is also provided between the backlight source 51 and the privacy layer 53, which increases the brightness of the backlight module 50. The privacy layer 53 is essentially a miniature venetian blind structure, which can block light with a large incident angle and allow light with a small incident angle to pass through, thus reducing the range of light angles passing through the privacy layer 53. The privacy layer 53 includes multiple parallel light-blocking walls and light-transmitting holes located between two adjacent light-blocking walls, and light-absorbing materials are provided on both sides of the light-blocking walls. Of course, the backlight 51 can also be a light-concentrating backlight, thus eliminating the need for a privacy screen 53, but light-concentrating backlights are more expensive than conventional backlights.

[0179] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0180] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. An array substrate, characterized in that, include: Substrate (10); A first metal layer (11) is disposed above the substrate (10), the first metal layer (11) includes a scan line and a gate (111), the gate (111) being electrically connected to the scan line; A gate insulating layer (101) covering the first metal layer (11); A first metal-oxide-semiconductor layer (12) and a second metal layer (13) are sequentially disposed above the gate insulating layer (101). The first metal-oxide-semiconductor layer (12) includes a first active layer (121). The second metal layer (13) includes a data line (131), a source (132), a drain (133), and a touch trace (134) parallel to the data line (131). The source (132) is electrically connected to the data line (131). The source (132) and the drain (133) are connected through the first active layer (121). The touch trace (134) includes a first touch trace (134a) and a second touch trace (134b). A second metal oxide semiconductor layer (16) is disposed above the second metal layer (13). The second metal oxide semiconductor layer (16) includes a conductive protective layer (161). The upper surface of the first touch trace (134a) is covered by the protective layer (161), and the upper surface of the second touch trace (134b) is not covered by the protective layer (161). A first insulating layer (102) is disposed above the gate insulating layer (101), and the first insulating layer (102) covers the data line (131), the source (132), the drain (133) and the first active layer (121); A common electrode (141), a second insulating layer (103), and a pixel electrode (151) are disposed above the first insulating layer (102). The second insulating layer (103) is located between the common electrode (141) and the pixel electrode (151) and insulates and separates the common electrode (141) and the pixel electrode (151) from each other. The pixel electrode (151) is electrically connected to the drain electrode (133). The common electrode (141) includes a first common electrode block (141a) at the end away from the touch chip (100) and a second common electrode block (141b) at the end close to the touch chip (100). The first common electrode block (141a) is electrically connected to the corresponding first touch trace (134a), and the second common electrode block (141b) is electrically connected to the corresponding second touch trace (134b); or, the common electrode (141) includes a first common electrode block (141a) at the end away from the touch chip (100) and a second common electrode block (141b) at the end close to the touch chip (100). The first common electrode block (141a) and the second common electrode block (141b) are located between the first common electrode block (141a) and the second common electrode block (141b). The first common electrode block (141a) and the second common electrode block (141b) are both electrically connected to the corresponding second touch trace (134b). The number of second touch traces (134b) connected to each first common electrode block (141a) is greater than the number of second touch traces (134b) connected to each second common electrode block (141b). The third common electrode block (141c) is electrically connected to the corresponding first touch trace (134a). A pad is provided in the bonding area at the edge of the substrate (10). The pad includes a first pad layer (171) and a second pad layer (172) stacked in sequence. The first pad layer (171) is formed by the first metal layer (11), and the second pad layer (172) is formed by the second metal oxide semiconductor layer (16) disposed above the substrate (10) after being conductiveized.

2. The array substrate according to claim 1, characterized in that, The array substrate includes a first transparent electrode layer (14) and a second transparent electrode layer (15) disposed above the first insulating layer (102), the second insulating layer (103) is located between the first transparent electrode layer (14) and the second transparent electrode layer (15), the first transparent electrode layer (14) includes the common electrode (141), the second transparent electrode layer (15) includes the pixel electrode (151), and the first transparent electrode layer (14) is located below or above the second transparent electrode layer (15). And / or, the pads include a third pad layer (173) covering the upper surface of the second pad layer (172), and the first transparent electrode layer (14) or the second transparent electrode layer (15) includes the third pad layer (173); And / or, the pads include a fourth pad layer (174) located between the first pad layer (171) and the second pad layer (172), and the second metal layer (13) includes the fourth pad layer (174).

3. The array substrate according to claim 1, characterized in that, The protective layer (161) is located on the upper surfaces of the data line (131), the source (132), and the drain (133); And / or, the second metal oxide semiconductor layer (16) includes the pixel electrode (151); And / or, the second metal oxide semiconductor layer (16) includes a second active layer (162) located on the upper surface of the first active layer (121), and the source (132) and the drain (133) are connected through the first active layer (121) and the second active layer (162).

4. The array substrate according to claim 3, characterized in that, The second metal oxide semiconductor layer (16) is located on the upper surface of the first insulating layer (102) and is in contact with the surface of the first insulating layer (102).

5. A method for fabricating an array substrate, characterized in that, include: Provide substrate (10); A first metal layer (11) is formed above the substrate (10), and the first metal layer (11) is etched to form patterned scan lines and gates (111), wherein the gates (111) are electrically connected to the scan lines. A gate insulating layer (101) covering the first metal layer (11) is formed on the substrate (10); A first metal oxide semiconductor layer (12) is formed above the gate insulating layer (101), and the first metal oxide semiconductor layer (12) is etched to form a patterned first active layer (121); A second metal layer (13) covering the first metal oxide semiconductor layer (12) is formed above the gate insulating layer (101). The second metal layer (13) is etched to form patterned data lines (131), source (132), drain (133) and patterned touch traces (134). The extension direction of the touch traces (134) is parallel to that of the data lines (131). The source (132) is electrically connected to the data lines (131). The source (132) and the drain (133) are connected through the first active layer (121). The touch traces (134) include a first touch trace (134a) and a second touch trace (134b). A second metal oxide semiconductor layer (16) is formed above the second metal layer (13). After etching and conductor treatment of the second metal oxide semiconductor layer (16), a protective layer (161) is formed. The upper surface of the first touch trace (134a) is covered by the protective layer (161), and the upper surface of the second touch trace (134b) is not covered by the protective layer (161). A first insulating layer (102) is formed above the gate insulating layer (101), and the first insulating layer (102) covers the data line (131), the source (132), the drain (133) and the first active layer (121); A common electrode (141), a second insulating layer (103), and a pixel electrode (151) are formed above the first insulating layer (102). The second insulating layer (103) is located between the common electrode (141) and the pixel electrode (151) and insulates and separates the common electrode (141) and the pixel electrode (151) from each other. The pixel electrode (151) is electrically connected to the drain (133). The common electrode (141) includes a first common electrode block (141a) at the end away from the touch chip (100) and a second common electrode block (141b) at the end close to the touch chip (100). The first common electrode block (141a) is electrically connected to the corresponding first touch trace (134a), and the second common electrode block (141b) is electrically connected to the corresponding second touch trace (134b); or, the common electrode (141) includes a first common electrode block (141a) at the end away from the touch chip (100) and a second common electrode block (141b) at the end close to the touch chip (100). The first common electrode block (141a) and the second common electrode block (141b) are located between the first common electrode block (141a) and the second common electrode block (141b). The first common electrode block (141a) and the second common electrode block (141b) are both electrically connected to the corresponding second touch trace (134b). The number of second touch traces (134b) connected to each first common electrode block (141a) is greater than the number of second touch traces (134b) connected to each second common electrode block (141b). The third common electrode block (141c) is electrically connected to the corresponding first touch trace (134a). A pad is formed in the bonding area at the edge of the substrate (10). The pad includes a first pad layer (171) and a second pad layer (172) stacked in sequence. The first pad layer (171) is formed by etching the first metal layer (11). The second pad layer (172) is formed by etching and conductor treatment of the second metal oxide semiconductor layer (16) disposed above the substrate (10).

6. The method for fabricating an array substrate according to claim 5, characterized in that, A first transparent electrode layer (14) and a second transparent electrode layer (15) are formed above the first insulating layer (102), the second insulating layer (103) is located between the first transparent electrode layer (14) and the second transparent electrode layer (15), the first transparent electrode layer (14) is located below or above the second transparent electrode layer (15), the first transparent electrode layer (14) is etched to form a patterned common electrode (141), and the second transparent electrode layer (15) is etched to form a patterned pixel electrode (151); And / or, the pads include a third pad layer (173) covering the upper surface of the second pad layer (172), and the patterned third pad layer (173) is formed when the first transparent electrode layer (14) or the second transparent electrode layer (15) is etched. And / or, the pads include a fourth pad layer (174) located between the first pad layer (171) and the second pad layer (172), and the patterned fourth pad layer (174) is formed when the second metal layer (13) is etched.

7. The method for fabricating an array substrate according to claim 5, characterized in that, include: The protective layer (161) is located on the upper surfaces of the data line (131), the source (132), and the drain (133); And / or, the pixel electrode (151) is formed by etching and conductor-forming the second metal oxide semiconductor layer (16); And / or, after etching and conductor treatment of the second metal oxide semiconductor layer (16), a second active layer (162) is formed on the upper surface of the first active layer (121), and the source (132) and the drain (133) are connected through the first active layer (121) and the second active layer (162).

8. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1-4.

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