Regulator circuit

Abstract

The application relates to the power management technical field and discloses a voltage stabilizer circuit, which comprises a first comparator circuit, an oscillator circuit and a charge pump circuit. The first comparator circuit is configured to output a control logic signal according to a reference voltage and a first feedback voltage, so as to control the working state of a subsequent circuit. The oscillator circuit is configured to generate a two-phase clock signal under the control of the control logic signal of the first comparator circuit. The charge pump circuit is configured to generate a pulse high voltage under the control of the two-phase clock signal of the oscillator circuit. A power tube is connected with the output end of the charge pump circuit to output a voltage. A voltage dividing network is connected with the output end of the power tube and is configured to divide the output voltage of the power tube to provide the first feedback voltage for the first comparator circuit. The circuit controls the state of the subsequent circuit through the output result of the first comparator. Thus, the standby power consumption of the voltage stabilizer circuit is reduced.

Description

Technical Field

[0001] This application relates to the field of power management technology, such as a voltage regulator circuit. Background Technology

[0002] Low dropout regulators (LDOs) are commonly used in power management circuits as internal power supplies for other analog circuits, or as standalone chips for external power supply. LDOs convert external power supply voltages into lower, more stable voltages. Simultaneously, LDOs automatically adjust the output current of the power transistor according to load changes, maintaining a stable output voltage. When the input and output voltage differences are small, LDOs exhibit high conversion efficiency and a high power supply rejection ratio. LDOs can be categorized into PMOS regulators and NMOS regulators depending on the power transistor used.

[0003] Compared to PMOS regulators, NMOS regulators offer faster transient response, greater load capacity, and better line regulation. However, to ensure the power transistor maintains a certain gate-source voltage even with a small input-output voltage difference, an additional charge pump circuit is needed to raise the gate voltage of the NMOS power transistor. This increases the overall power consumption of the circuit. Summary of the Invention

[0004] To provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. This summary is not intended as a general commentary, nor is it intended to identify key / important components or describe the scope of protection of these embodiments, but rather as a prelude to the detailed description that follows.

[0005] This disclosure provides a voltage regulator circuit to reduce power consumption.

[0006] In some embodiments, the voltage regulator circuit includes:

[0007] The first comparator circuit is configured to output a control logic signal based on a reference voltage and a first feedback voltage to control the operating state of the subsequent circuit.

[0008] The oscillator circuit is configured to generate a two-phase clock signal under the control of the control logic signal of the first comparator circuit;

[0009] The charge pump circuit is configured to generate pulsed high voltage under the control of a two-phase clock signal from an oscillator circuit;

[0010] The power transistor is connected to the output terminal of the charge pump circuit to output voltage;

[0011] A voltage divider network, connected to the output of the power transistor, is configured to divide the output voltage of the power transistor to provide a first feedback voltage for the first comparator circuit.

[0012] The voltage regulator circuit provided in this disclosure can achieve the following technical effects:

[0013] In this embodiment, a voltage divider network divides the output voltage of the voltage regulator circuit and feeds it back to a first comparator. The first comparator controls the operating state of the oscillator based on the magnitude of the first feedback voltage and the reference voltage. Whether the oscillator is operating controls whether the charge pump provides a suitable gate voltage to the power transistor. Thus, the output of the first comparator controls the state of the subsequent circuitry, thereby reducing the standby power consumption of the voltage regulator circuit.

[0014] The above general description and the description below are exemplary and illustrative only and are not intended to limit this application. Attached Figure Description

[0015] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations and drawings do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are shown as similar elements. The drawings are not to be scaled. And wherein:

[0016] Figure 1 This is a schematic diagram of a voltage regulator circuit provided in an embodiment of this disclosure;

[0017] Figure 2 This is a schematic diagram of another voltage regulator circuit provided in an embodiment of this disclosure;

[0018] Figure 3 This is a schematic diagram of the structure of an enable control circuit for an oscillator circuit provided in an embodiment of this disclosure;

[0019] Figure 4 This is a schematic diagram of an oscillator circuit provided in an embodiment of this disclosure;

[0020] Figure 5 This is a schematic diagram of a charge pump circuit provided in an embodiment of this disclosure;

[0021] Figure 6 This is a schematic diagram of the structure of a current limiting control circuit provided in an embodiment of this disclosure;

[0022] Figure 7 This is a schematic diagram of a comparator circuit provided in an embodiment of this disclosure.

[0023] Figure label:

[0024] 10: Bandgap reference circuit; 20: First comparator circuit; 30: Oscillator circuit; 40: Charge pump circuit; 50: Power transistor; 60: Voltage divider network; 70: Current limiting control circuit; 80: Second comparator circuit. Detailed Implementation

[0025] To provide a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for illustrative purposes only and are not intended to limit the embodiments of this disclosure. In the following technical description, for ease of explanation, several details are used to provide a full understanding of the disclosed embodiments. However, one or more embodiments may still be implemented without these details. In other cases, well-known structures and devices may be simplified in their depiction to simplify the drawings.

[0026] The terms "first," "second," etc., used in the specification, claims, and accompanying drawings of this disclosure are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this disclosure described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0027] In this disclosure, the terms "upper," "lower," "inner," "middle," "outer," "front," and "rear," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for better description of the embodiments of this disclosure and their implementations, and are not intended to limit the indicated devices, elements, or components to having a specific orientation, or to require them to be constructed and operated in a specific orientation. Furthermore, some of the aforementioned terms may be used to indicate other meanings besides orientation or positional relationship; for example, the term "upper" may in some cases indicate a dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in the embodiments of this disclosure according to the specific circumstances.

[0028] Furthermore, the terms "set up," "connect," and "fix" should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this disclosure according to the specific circumstances.

[0029] Unless otherwise stated, the term "multiple" means two or more.

[0030] In this embodiment of the disclosure, the character " / " indicates that the objects before and after it are in an "or" relationship. For example, A / B means: A or B.

[0031] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0032] It should be noted that, unless otherwise specified, the embodiments and features described in the present disclosure can be combined with each other.

[0033] Combination Figure 1 As shown, this embodiment of the present disclosure provides a voltage regulator circuit, including a first comparator circuit 20, an oscillator circuit 30, a charge pump circuit 40, a power transistor 50, and a voltage divider network 60. The first comparator circuit 20 is configured to output a control logic signal based on a reference voltage and a first feedback voltage to control the operating state of subsequent circuits. The oscillator circuit 30 is configured to generate a two-phase clock signal under the control of the control logic signal of the first comparator circuit 20. The charge pump circuit 40 is configured to generate a pulsed high voltage under the control of the two-phase clock signal of the oscillator circuit 30. The power transistor 50 is connected to the output terminal of the charge pump circuit 40 to output a voltage. The voltage divider network 60 is connected to the output terminal of the power transistor 50 and is configured to divide the output voltage of the power transistor to provide a first feedback voltage to the first comparator circuit.

[0034] Here, the voltage regulator circuit switches between standby and active states during normal operation. In standby mode, it is necessary to minimize the circuit's power consumption. Therefore, in standby mode, the oscillator circuit and charge pump circuit are kept in a stopped state, which helps reduce the power consumption of the voltage regulator circuit. In this embodiment, the control logic signal output by the first comparator controls the operating state of the subsequent circuits to reduce standby power consumption.

[0035] Specifically, the power transistor 50 in the voltage regulator circuit is an NMOS transistor, and its output voltage V OUT12 This is the output voltage of the voltage regulator circuit. This output voltage is divided by a voltage divider network to generate the first feedback voltage V. FB1 The first feedback voltage is fed back to the first comparator circuit COMP120. The first comparator circuit compares it with the reference voltage V. REF The comparison is performed, and the output logic control signal is used to control the subsequent circuits (i.e., the oscillator circuit and the charge pump circuit). As an example, the non-inverting input of the first comparator circuit COMP120 is connected to the reference voltage V. REF The inverting input is connected to the first feedback voltage V after voltage division. FB1When the first feedback voltage obtained at the non-inverting input of the comparator circuit is greater than the reference voltage (V... FB1 >V REF When the comparator circuit outputs a high level, the oscillator circuit and charge pump circuit operate, increasing the gate voltage of the power transistor until the regulator output reaches the predetermined voltage value V. OUT12 When the first feedback voltage obtained at the non-inverting input of the comparator circuit is greater than the reference voltage (V... FB1 <V REF When the comparator circuit outputs a low level, the oscillator circuit and charge pump circuit stop working. Specifically, the control logic signal output by the first comparator circuit 20 can be used as the enable control signal for subsequent circuits. This controls whether the oscillator circuit 30 works. When the oscillator circuit 30 is not working, it cannot provide a two-phase clock signal to the charge pump circuit 40, so the charge pump circuit also does not work. In this way, the operating states of the oscillator circuit 30 and the charge pump circuit 40 are controlled.

[0036] In this circuit, the reference voltage of the first comparator circuit 20 can be a preset voltage source. In this case, the first comparator circuit also requires an additional current source to provide bias current to ensure that the comparator can operate normally. Alternatively, the reference voltage can be provided by a bandgap reference circuit. In this case, the bias current required for the operation of the comparator circuit can also be provided by the current source generated by the bandgap reference circuit 10. That is, the voltage output terminal of the bandgap reference circuit 10 provides the reference voltage for the comparator, and the current output terminal provides the bias current for the comparator.

[0037] The voltage regulator circuit provided in this embodiment divides the output voltage of the voltage regulator circuit through a voltage divider network and feeds it back to a first comparator. The first comparator controls the operating state of the oscillator based on the magnitude of the first feedback voltage and the reference voltage. Whether the oscillator is operating controls whether the charge pump provides a suitable gate voltage to the power transistor. Thus, the output of the first comparator controls the state of the subsequent circuitry, thereby reducing the standby power consumption of the voltage regulator circuit.

[0038] Combination Figure 2 Optionally, the voltage regulator circuit also includes a current limiting control circuit 70. The current limiting control circuit 70 is connected to the output of the charge pump circuit 40 and to the power transistor P. NMOS The output of 50 is connected to and configured to pull down the output voltage of the charge pump circuit 40 and the output voltage of the power transistor 50.

[0039] Here, while reducing standby power consumption, the voltage regulator circuit also needs to ensure the stability of its output voltage. Therefore, a current-limiting control circuit is used to pull down the output voltage of the charge pump and the power transistor, controlling the output voltage ripple. This reduces the ripple of the charge pump regulator's output voltage, ensuring its accuracy. Thus, the voltage regulator circuit achieves its voltage regulation function while reducing standby power consumption.

[0040] Optionally, the voltage regulator circuit also includes a second comparator circuit 80. The second comparator circuit 80 is connected to the current limiting control circuit 70 and is configured to operate according to a reference voltage V. REF Second feedback voltage V FB2 Output control logic signals to control the operating state of the current limiting control circuit. Among these, the second feedback voltage V... FB2 Provided by a voltage divider network.

[0041] Understandably, the current limiting control circuit 70 is used to pull down the output voltage of the charge pump circuit 40 and the power transistor 50. Therefore, when the voltage regulator circuit is in standby mode, the current limiting control circuit 70 is in a stopped state, which further helps reduce the standby power consumption of the entire circuit. Thus, a second comparator circuit 80 is provided to control the operating state of the current limiting control circuit 70, i.e., to control its on or off state. The reference current source of the second comparator circuit 80 is the same as that of the first comparator circuit 20, and will not be described again here. The second feedback voltage also comes from the feedback voltage of the voltage divider network, but the values ​​of the first and second feedback voltages are different.

[0042] As an example, the non-inverting input of the second comparator COMP280 is connected to the second feedback voltage V, which is divided by a voltage divider network. FB2 The inverting input is connected to the reference voltage V output by the bandgap reference circuit. REF The output of the second comparator circuit is connected to the input of the current limiting control circuit. When the second feedback voltage obtained at the non-inverting input of the second comparator is less than the reference voltage (V... FB2 <V REF When the current limiting control circuit is in a low-level state, the comparator outputs a low-level signal. Under this low-level control, the current limiting control circuit is in a stopped state. When the second feedback voltage obtained at the non-inverting input of the comparator is greater than the reference voltage (V... FB2 >V REF When the current limiting control circuit is activated, the comparator outputs a high level, and the current limiting control circuit is in the activated state. This achieves voltage regulation while further reducing the standby power consumption of the voltage regulator.

[0043] Combination Figure 3 , 4As shown, optionally, the oscillator circuit 30 includes: a first enable control circuit, a bias current circuit, a waveform generation circuit, a waveform shaping circuit, and an output circuit.

[0044] The circuit includes a first enable control circuit connected to the output of the first comparator circuit to generate an enable control signal. A bias current circuit provides bias current for the oscillator circuit to start. A waveform generation circuit includes a first inverter and a second inverter, a first capacitor and a second capacitor; under the control of the enable control signal, the first inverter is used to charge and discharge the first capacitor, or the second inverter is used to charge and discharge the second capacitor, to generate a sawtooth wave. A waveform shaping circuit shapes the sawtooth wave generated by the waveform generation circuit. An output circuit outputs a two-phase clock signal under the control of the oscillator enable signal.

[0045] Here, the first enabling circuit mainly includes logic operation devices that generate an enable control signal based on the logic control signal output by the first comparator circuit. The devices in the oscillator circuit provide a start signal, enabling them to conduct. Specifically, based on the structure of the oscillator circuit, the enable control signal can be determined to be high and / or low, thus determining whether to generate one or two enable control signals. As an example, the oscillator circuit includes multiple MOSFETs; some MOSFETs require a high-level signal at their gates, while others require a low-level signal. The first enabling circuit then performs a logic operation on the logic control signal output by the first comparator circuit, generating a first enable control signal and a second enable control signal, respectively. Understandably, when only a high or low level is required, only one enable control signal is generated.

[0046] Subsequently, under the action of the bias current circuit, the oscillator circuit starts working. By controlling the first and second inverters to alternately charge and discharge the first and second capacitors, a sawtooth waveform voltage is generated. The waveform shaping circuit shapes the sawtooth waveform voltage to output a two-phase clock signal.

[0047] Combination Figure 3 Optionally, the first enable control circuit includes: a second inverter INV2, a fifth NOR gate NOR5, and a third inverter INV3. The input terminal of the second inverter INV2 is connected to the output terminal COMP of the first comparator circuit. 1OUT Connections: The first input of the fifth NOR gate (NOR5) is connected to the enable signal of the oscillator circuit, and the second input is connected to the output of the second inverter (INV2) to output the first enable control signal. The third inverter (INV3) is connected to the output of the fifth NOR gate (NOR5) to output a second enable control signal that is inverted by the first enable control signal.

[0048] As mentioned earlier, when the first comparator circuit outputs a high level (i.e., COMP),1OUT =1), the oscillator starts working. Here, the high-level signal output from the first comparator is flipped by the second inverter, changing from high to low. Then, it is connected to the oscillator circuit's enable signal EN. OSC Perform a NOT logical operation. Set EN. OSC When = 1, the oscillator circuit is enabled. Then in COMP... 1OUT When = 1, after inversion, it is connected to EN. OSC The output logic is 1 after NOR gate. This yields the first enable control signal ENP = 1, and the output signal of the fifth NOR gate is inverted to obtain the second enable control signal ENN = 0. These two enable control signals are used to control the on or off state of the devices in the oscillator circuit.

[0049] The following is combined Figure 4 The circuit and operating principle of the oscillator circuit are explained in detail. The bias current circuit includes four PMOS transistors: PM21 (second-first), PM22 (second-second-second), PM23 (second-third), and PM24 (second-fourth). All four PMOS transistors are current-mirror PMOS transistors. The sources of all four transistors (PM21, PM22, PM23, and PM24) are connected to the power supply voltage VDD, and their gates are connected to the current source I. BIAS The drain and gate of the second PMOS transistor PM21 are connected. The drains of the second PMOS transistors PM22, PM23, and PM24 are connected to the waveform generation circuit. The waveform generation circuit includes a first inverter, a second inverter, a first capacitor C1, a second capacitor C2, and second PMOS transistors PM27, PM28, NMOS transistors NM13, NM14, NM15, NM16, and NM17. The first inverter includes the second PMOS transistor PM25 and the first NMOS transistor NM11, and the second inverter includes the second PMOS transistor PM26 and the first NMOS transistor NM11. The waveform shaping circuit includes a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, and a fourth NOR gate NOR4. The output circuit includes a fourth inverter INV4 and a third NAND gate NAND3.

[0050] In detail, the source of the second PMOS transistor PM27 is connected to the drain of the second PMOS transistor PM22, and its gate is connected to the first enable control signal ENN. Its drain is connected to the sources of the second PMOS transistor PM25 and the second PMOS transistor PM26, respectively. The gates of the second PMOS transistor PM25 and the first NMOS transistor NM11 are both connected to the output of the second NOR gate. The drains of the second PMOS transistor PM25 and the first NMOS transistor NM11 are both connected to the upper plate of the first capacitor. The lower plate of the first capacitor and the source of the first NMOS transistor NM11 are grounded. The drain of the second PMOS transistor PM25 is connected to the gate of the first NMOS transistor NM13, and the source of the first NMOS transistor NM13 is grounded. The drain of the first NMOS transistor NM13 is connected to the drain of the second PMOS transistor PM23 and one end of the first NOR gate. The gate of the first three NMOS transistor NM13 is also connected to the drain of the first five NMOS transistor NM15. The source of the first five NMOS transistor NM15 is grounded, and its gate is connected to the first enable control signal ENN. The gates of the second six PMOS transistor PM26 and the first two NMOS transistor NM12 are both connected to the output of the fourth NOR gate. The drains of the second six PMOS transistor PM26 and the first two NMOS transistor NM12 are both connected to the upper plate of the second capacitor, and are also connected to the gate of the first four NMOS transistor NM14 and the drain of the first six NMOS transistor NM16. The lower plate of the second capacitor, the source of the first two NMOS transistor NM12, the source of the first four NMOS transistor NM14, and the source of the first six NMOS transistor NM16 are all grounded. The gate of the first six NMOS transistor NM16 is connected to ENN. The drain of the first seven-stage NMOS transistor NM17 is connected to the drain of the first four-stage NMOS transistor NM14 and one input of the third NOR gate NOR3. The source of the first seven-stage NMOS transistor NM17 is grounded. The output signals of the first NOR gate NOR1 and the third NOR gate NOR3 serve as input signals of each other. The output of the first NOR gate also serves as an input of the second NOR gate NOR2, and the output of the third NOR gate NOR3 also serves as an input of the fourth NOR gate NOR4. Simultaneously, the output signals of the third NOR gate NOR3 and the fourth NOR gate NOR4 both serve as input signals of each other.

[0051] The working principle of the oscillator circuit: When the output signal of the first comparator circuit is high and ENsoc = 1, ENN = 0 and ENP = 1. The second seven-stage MOSFET PM27, the first five-stage NMOS transistor NM15, the first six-stage NMOS transistor NM16, and the first seven-stage NMOS transistor NM17 are turned on, while the second eight-stage PMOS transistor PM28 is turned off. After four NOR operations, the second NOR gate NOR2 outputs logic 1, and the fourth NOR gate NOR4 outputs logic 0. Then, the second five-stage MOSFET PM25 is turned on, the first one-stage NMOS transistor NM11 is turned off, the first capacitor C1 is charged, and the gate voltage of the first three-stage NMOS transistor NM13 gradually increases and eventually turns on (because the first five-stage NMOS transistor NM15 is turned on, the gate voltage of the first three-stage NMOS transistor NM13 is initially 0), causing the input signal of the first NOR gate NOR1 to flip from high to low. Simultaneously, the second PMOS transistor PM26 is turned off, the first NMOS transistor NM11 is turned on, and the second capacitor C2 discharges, causing the gate voltage of the first NMOS transistor NM14 to gradually decrease and eventually turn off, causing the input signal of the third NOR gate NOR3 to flip from low to high. Thus, the second NOR gate NOR2 outputs logic 0, and the fourth NOR gate NOR4 outputs logic 1, causing the first capacitor C1 to discharge and the second capacitor C2 to charge. This process repeats, and after logic operations by the fourth inverter INV4 and the third NOR gate NOR3, a two-phase clock signal is output. As an example, the second NOR gate NOR2 outputs logic 0, and ENsoc = 1, CLKN = 1, and CLK = 0. The second NOR gate outputs logic 1, and ENsoc = 1, CLKN = 0, and CLK = 1.

[0052] Combination Figure 5 As shown, optionally, the charge pump circuit 40 includes: a charge-discharge circuit, a transmission circuit, and a substrate voltage adjustment circuit. The charge-discharge circuit includes a third capacitor C3 and a fourth capacitor C4, which, under the control of a two-phase clock signal generated by the oscillator circuit, charge and discharge the third capacitor C3 and the fourth capacitor C4 to generate pulsed high voltage. The transmission circuit transmits the pulsed high voltage generated by the charge-discharge circuit to the next stage circuit. The substrate voltage adjustment circuit adjusts the voltage of the transmission circuit and outputs it.

[0053] Here, the charging and discharging circuit includes a third capacitor C3 and a fourth capacitor C4, with one end of each capacitor connected to a clock signal. Under the control of the two clock signals, the third capacitor C3 and the fourth capacitor C4 alternately charge and discharge, generating pulsed high voltage. The transmission circuit transmits the pulsed high voltage to the substrate voltage adjustment circuit to adjust the voltage and reduce the substrate bias effect.

[0054] Optionally, the charging and discharging circuit includes a third capacitor C3, a fourth capacitor C4, a third NMOS transistor NM31, and a third NMOS transistor NM32. The lower plate of the third capacitor C3 is connected to the second clock signal (CKLN); the lower plate of the fourth capacitor C4 is connected to the first clock signal (CKL); the drains of both the third NMOS transistor NM31 and the third NMOS transistor NM32 are connected to the power supply voltage VDD, and their gates are crossed and connected to the upper plates of the fourth capacitor C4 and the third capacitor C3, respectively. The gates are also connected to the sources of the transistors, and the substrate is grounded. The first and second clock signals are two-phase clock signals generated by the oscillator circuit.

[0055] The transmission circuit includes a third PMOS transistor PM33 and a third PMOS transistor PM34. The drains of the two transistors are connected to the upper plates of the third capacitor C3 and the fourth capacitor C4, respectively. Their gates are crossed and connected to the upper plates of the fourth capacitor and the third capacitor, respectively.

[0056] The substrate voltage adjustment circuit includes a third-fifth PMOS transistor PM35 and a third-sixth PMOS transistor PM36. The drains of the two transistors are connected to the upper plates of the third capacitor C3 and the fourth capacitor C4, respectively. The gates are crossed and connected to the upper plates of the fourth capacitor C4 and the third capacitor C3, respectively. The source is used as the output terminal. The substrate terminal is connected to the source and substrate terminal of the third-third PMOS transistor PM33 and the third-fourth PMOS transistor PM34.

[0057] The working principle of the charge pump circuit is explained here. When the first clock signal CLK of the charge pump circuit flips from low to high, the voltage on the upper plate of the fourth capacitor C4 flips from low to high, reaching twice the VDD voltage. The voltage on the upper plate of the third capacitor C3 flips from high to low, dropping to VDD. Therefore, the third NMOS transistor NM32 and the third PMOS transistor PM35 are turned off, while the third NMOS transistor NM31 and the third PMOS transistor PM36 are turned on. The fourth capacitor C4 charges the load, thus outputting twice the VDD voltage.

[0058] When the first clock signal CLK of the charge pump circuit flips from high to low, the voltage on the upper plate of the fourth capacitor C4 flips from high to low, dropping to VDD. The voltage on the upper plate of the third capacitor C3 flips from low to high, reaching twice VDD. Therefore, the third NMOS transistor NM31 and the third PMOS transistor PM36 turn off, while the third NMOS transistor NM32 and the third PMOS transistor PM35 turn on, and the third capacitor C3 charges the load.

[0059] Combination Figure 6As shown, optionally, the current limiting control circuit includes a fourth MOSFET NM41, a fourth MOSFET NM42, a fourth MOSFET NM43, a fourth MOSFET NM44, a fourth MOSFET NM45, a fourth MOSFET NM46, a fourth MOSFET NM47, a fourth MOSFET NM48, ​​a fourth MOSFET NM49, a fifth MOSFET NM50, a fifth MOSFET NM51, a fifth MOSFET NM52, a fifth MOSFET NM53, and a second enable control circuit.

[0060] The drains of the fourth NMOS transistor NM41 and the fifth NMOS transistor NM53 are both connected to the output terminal HV of the charge pump circuit. out The fourth NMOS transistor NM41, the fourth NMOS transistor NM42, the fourth NMOS transistor NM43, the fourth NMOS transistor NM44, the fourth NMOS transistor NM45, and the fourth NMOS transistor NM46 are connected in series and their gates are all connected to the third enable control signal. The fifth NMOS transistor NM53, the fifth NMOS transistor NM52, and the fifth NMOS transistor NM51 are connected in series and their gates are all connected to the fourth enable control signal. The sources of the fourth and sixth NMOS transistors NM46 and the fifth NMOS transistor NM51 are both grounded.

[0061] The drains of the fourth NMOS transistor NM48 and the fourth NMOS transistor NM47 are both connected to the output terminal of the power transistor; the fourth NMOS transistor NM48 and the fourth NMOS transistor NM47 are connected in series and their gates are both connected to the third enable control signal; the fourth NMOS transistor NM49 and the fifth NMOS transistor NM50 are connected in series and their gates are both connected to the fourth enable control signal; the sources of the fourth NMOS transistor NM47 and the fifth NMOS transistor NM50 are both grounded. The second enable control circuit includes logic operation devices to generate the third enable control signal and the fourth enable control signal.

[0062] Here, the second enable control circuit also has two input signals, one of which is the output signal COMP of the second comparator. 2OUT The other is the enable signal EN of the current limiting control circuit itself. LP After performing logical operations on these two input signals, two inverted enable control signals, a third enable control signal and a fourth enable control signal, are output. These two enable control signals then control the corresponding pull-down branches to conduct, thereby pulling down the output voltage of the charge pump and the power transistor.

[0063] Specifically, the pull-down branch includes two parallel branches, and each branch further includes a branch that pulls down the output voltage of the charge pump and a branch that pulls down the output voltage of the power transistor. The first branch connects the drain of the fourth NMOS transistor NM41 to the output voltage HV of the charge pump circuit. out The fourth NMOS transistors NM41, NM42, NM43, NM44, NM45, and NM46 are connected in series, and their gates are all connected to the third enable control signal. The source of the sixth NMOS transistor NM46 is grounded. The drain of the eighth NMOS transistor NM48 is connected to the output voltage V of the power transistor. OUT12 The drains of the fourth octet NMOS transistor NM48 and the fourth octet NMOS transistor NM47 are both connected to the output terminal of the power transistor. The fourth octet NMOS transistor NM48 and the fourth octet NMOS transistor NM47 are connected in series, and their gates are both connected to the third enable control signal. The sources of the fourth octet NMOS transistor are both grounded. When the third enable control signal is high, this branch is turned on, affecting the output voltage HV of the charge pump circuit. out and the output voltage V of the power transistor OUT12 Perform a pulldown. As an example, in the enable signal EN... LP When the signal is high, the comparator outputs the COMP signal when the output voltage ripple exceeds the set value. 2OUT The output is high, then after passing through logic gates INV5, NAND1, and INV6, it outputs a low level (i.e., the fourth enable control signal is low), and the second branch is not conducting. After passing through NAND2 and INV7, it outputs a high level (i.e., the third enable signal is high), and the NMOS transistors NM41 to NM48 in the first branch conduct. This periodically adjusts the output voltage V. OUT12 and power transistor gate voltage HV OUT The traffic is lowered to achieve the purpose of limiting the flow.

[0064] Similarly, in the second branch: the drain of the fifth NMOS transistor NM53 is connected to the output voltage HV of the charge pump circuit. out The fifth three NMOS transistors, NM53, NM52, and NM51, are connected in series, with their gates all connected to the fourth enable control signal. The source of NM51 is grounded. The drain of the fourth nine NMOS transistor, NM49, is connected to the output voltage V of the power transistor. OUT12 The fourth NMOS transistor NM49 and the fifth NMOS transistor NM50 are connected in series, and their gates are both connected to the fourth enable control signal. The source of the fifth NMOS transistor NM50 is grounded. As an example, in the enable signal EN... LP When the output voltage ripple exceeds the set value, the second comparator outputs the COMP signal when the output voltage ripple is low.2OUT The output is high, and after passing through logic gates INV5, NAND1, and INV6, it outputs a high level (i.e., the fourth enable signal is high), turning on all NMOS transistors in this branch from NM49 to NM53. After passing through NAND2 and INV7, it outputs a low level (i.e., the third enable signal is low), turning off the first branch. This periodically affects the output voltage V of the power transistor. OUT12 and the output voltage HV of the charge pump circuit OUT The traffic is lowered to achieve the purpose of limiting the flow.

[0065] It should be noted that the enable signal EN LP EN is the control signal for two operating modes. LP When the voltage level is low, the current limiting control circuit is in normal operating mode (at this time, the load current is relatively large, i.e., the output current of the voltage regulator). EN LP When the signal is high, the current limiting control circuit operates in a low-power mode (the load current is relatively small at this time).

[0066] Optionally, the second enable control circuit includes a fifth inverter INV5, a first NAND gate NAND1 connected to the fifth inverter INV5, a sixth inverter INV6 connected to the first NAND gate NAND1, a second NAND gate NAND2, and a seventh inverter INV7 connected to the second NAND gate NAND2. The output signal COMP of the first comparator circuit... 2OUT As an input signal to the first NAND gate NAND1 and the second NAND gate NAND2, the current limiting control circuit enables the signal EN. LP After passing through the fifth inverter INV5, it becomes another input signal for the first NAND gate NAND1. At the same time, the enable signal directly becomes another input signal for the second NAND gate NAND2.

[0067] Thus, the second enable control circuit outputs the COMP signal from the first comparator circuit. 2OUT The current limiting control circuit enables the signal EN. LP Under the control of [the system], two enable control signals are generated, which respectively control the two current-limiting branches.

[0068] Combination Figure 7 As shown, optionally, the first comparator circuit and the second comparator circuit adopt the same structure. The first comparator circuit will be used as an example for explanation. The first comparator circuit mainly includes: a signal input pair, a current mirror structure, and an enable transistor.

[0069] The signal input transistors include a first MOS transistor NM1 and a second NMOS transistor NM2, with their gates serving as the input terminals of the comparator. The current mirror structure includes a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5. The gate and drain of the third NMOS transistor NM3 are connected to a current source and to the gates of the fourth and fifth NMOS transistors NM4 and NM5, respectively. The drain of the fourth NMOS transistor NM4 is connected to the source of the first and second NMOS transistors NM1 and NM2. The drain of the fifth NMOS transistor NM5 is output through a first inverter. The sources of the third, fourth, and fifth NMOS transistors NM3, NM4, and NM5 are all grounded. The enable transistors include a seventh PMOS transistor PM7 and an eighth PMOS transistor PM8, with their gates connected to the comparator enable signal and their sources connected to the power supply voltage. The sixth PMOS transistor PM6 has its gate and drain connected to the drain of the first NMOS transistor NM1, and its source connected to the power supply. The ninth PMOS transistor, PM9, has its gate connected to the drain of the eighth PMOS transistor, PM8, its source connected to the power supply, and its drain connected to the drain of the fifth NMOS transistor, NM5. The tenth PMOS transistor, PM10, has its gate connected to the drain of the seventh PMOS transistor, PM7, and its drain connected to the gate of the ninth PMOS transistor, PM9, and the drain of the second NMOS transistor, NM2.

[0070] Here, the gate VP of the first NMOS transistor NM1 is connected to the first feedback voltage V. FB1 The gate of the second NMOS transistor NM2 is connected to the reference voltage V. REF When the comparator is enabled, i.e., when the gates of the seventh PMOS transistor PM7 and the eighth PMOS transistor PM8 are both low, PM7 and PM8 are turned on. Then, the sixth PMOS transistor PM6, the ninth PMOS transistor PM9, and the tenth PMOS transistor PM10 are turned on. Simultaneously, when the comparator is enabled, the third NMOS transistor NM3, the fourth NMOS transistor NM4, and the fifth NMOS transistor NM5 are turned on, and the currents in the branches containing these three NMOS transistors are proportionally mirrored. At V FB1 >V REF At this time, the drain-source current of the first NMOS transistor NM1 increases, causing the gate voltages of the sixth PMOS transistor PM6 and the tenth PMOS transistor PM10 to decrease. This, in turn, causes the gate voltage of the ninth PMOS transistor PM9 to increase, and the input voltage of the first inverter to decrease. The output voltage of the first inverter flips to a high level, thereby controlling the subsequent oscillator circuit and charge pump circuit to start operating. At V FB1 <V REFAt this time, the drain-source current of the second MOSFET NM2 increases, causing the gate voltage of the ninth PMOS transistor PM9 to decrease, and the input voltage of the first inverter to increase. The output voltage of the first inverter flips to a low level, thereby controlling the subsequent oscillator circuit and charge pump circuit to stop working.

[0071] Similarly, the operating principle of the second comparator circuit can be obtained based on the above principles to control the operating state of the current limiting control circuit. This will not be elaborated further here.

[0072] Optionally, the voltage divider network includes a first resistor R1, a second resistor R2, and a third resistor R3 connected in series. The upper end of the first resistor R1 is connected to the power transistor P. NMOS The source and output terminal V of the regulator circuit OUT12 The lower end of the second resistor R2 is connected to the inverting input of the first comparator circuit COMP1 to provide feedback voltage. The upper end of the third resistor R3 is connected to the non-inverting input of the second comparator circuit COMP2 to provide feedback voltage, and the lower end is connected to the power supply ground.

[0073] In this way, the voltage divider network divides the output voltage of the voltage regulator circuit to provide feedback voltage for the first and second comparator circuits. This, in turn, controls the operating state of the oscillator circuit and the current limiting control circuit.

[0074] The foregoing description and accompanying drawings fully illustrate embodiments of the present disclosure to enable those skilled in the art to practice them. Other embodiments may include structural and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the order of operation may vary. Parts and features of some embodiments may be included or substituted for parts and features of other embodiments. Embodiments of the present disclosure are not limited to the structures described above and shown in the accompanying drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A voltage regulator circuit, characterized in that, include: The first comparator circuit is configured to output a control logic signal based on a reference voltage and a first feedback voltage; the control logic signal serves as an enable control signal for the subsequent circuit to control its operating state; the reference voltage is connected to another input terminal of the first comparator circuit. The oscillator circuit has its input terminal connected to the output terminal of the first comparator circuit; it is configured to generate a two-phase clock signal under the control of the control logic signal of the first comparator circuit. The charge pump circuit, with its input connected to the output of the oscillator circuit, is configured to generate pulsed high voltage under the control of a two-phase clock signal from the oscillator circuit. The power transistor's gate is connected to the output terminal of the charge pump circuit, its source serves as the power transistor's output terminal to output voltage, and its drain is connected to the power supply voltage. The voltage divider network has its input terminal connected to the output terminal of the power transistor, and its first output terminal connected to one input terminal of the first comparator circuit. It is configured to divide the output voltage of the power transistor to provide a first feedback voltage for the first comparator circuit; The oscillator circuit includes: A first enable control circuit is connected to the output of a first comparator circuit to generate an enable control signal. The first enable control circuit includes: an inverter INV2, whose input is connected to the output of the first comparator circuit; a fifth NOR gate, whose first input is connected to the enable signal of the oscillator circuit and whose second input is connected to the output of the inverter INV2 to output a first enable control signal; and an inverter INV3, connected to the output of the fifth NOR gate to output a second enable control signal that is inverted from the first enable control signal. The bias current circuit provides bias current for the oscillator circuit to start up; The waveform generation circuit includes a first inverter and a second inverter, a first capacitor and a second capacitor; under the control of an enable control signal, the first inverter is used to charge and discharge the first capacitor, or the second inverter is used to charge and discharge the second capacitor, to generate a sawtooth wave. Waveform shaping circuit, which shapes the sawtooth wave generated by the waveform generation circuit; The output circuit outputs a two-phase clock signal under the control of the oscillator enable signal.

2. The circuit according to claim 1, characterized in that, The charge pump circuit includes: The charging and discharging circuit, including the third capacitor and the fourth capacitor, generates pulsed high voltage by charging and discharging the third capacitor and the fourth capacitor under the control of the two-phase clock signal generated by the oscillator circuit. The transmission circuit transmits the high-voltage pulses generated by the charging and discharging circuit to the load. The substrate voltage adjustment circuit adjusts and outputs the voltage of the transmission circuit.

3. The circuit according to claim 2, characterized in that, The charging and discharging circuit includes a third capacitor, a fourth capacitor, a third-first NMOS transistor, and a third-second NMOS transistor. The lower plate of the third capacitor is connected to the second clock signal; the lower plate of the fourth capacitor is connected to the first clock signal; the drains of the third-first and third-second NMOS transistors are both connected to the power supply voltage, and their gates are crossed and connected to the upper plates of the fourth and third capacitors, respectively. The gates are also connected to the sources of the transistors, and the substrate is grounded. The transmission circuit includes a third PMOS transistor and a third PMOS transistor. The drains of the two transistors are connected to the upper plates of the third capacitor and the fourth capacitor, respectively. Their gates are crossed and connected to the upper plates of the fourth capacitor and the third capacitor, respectively. The substrate voltage adjustment circuit includes a third fifth PMOS transistor and a third sixth PMOS transistor. The drains of the two transistors are connected to the upper plates of the third capacitor and the fourth capacitor, respectively. The gates are crossed and connected to the upper plates of the fourth capacitor and the third capacitor, respectively. The source is used as the output terminal. The substrate terminal is connected to the source and substrate terminal of the third third PMOS transistor and the third fourth PMOS transistor. The first clock signal and the second clock signal are two-phase clock signals generated by the oscillator circuit.

4. The circuit according to any one of claims 1 to 3, characterized in that, Also includes: A current-limiting control circuit is connected to the output of the charge pump and the output of the power transistor; it is configured to pull down the output voltage of the charge pump and the output voltage of the power transistor.

5. The circuit according to claim 4, characterized in that, The current limiting control circuit includes: The fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the fifth NMOS transistor, the fifth NMOS transistor, the fifth NMOS transistor, the fifth NMOS transistor, the fifth NMOS transistor, the fifth NMOS transistor, and the second enable control circuit. In this configuration, the drains of the fourth NMOS transistor and the fifth NMOS transistor are both connected to the output terminal of the charge pump; the source of the fourth NMOS transistor, the drain and source of the fourth NMOS transistor, the drain and source of the fourth NMOS transistor, the drain and source of the fourth NMOS transistor, the drain and source of the fourth NMOS transistor, the drain and source of the fourth NMOS transistor, and the drain of the fourth NMOS transistor are connected in series and their gates are all connected to the third enable control signal; the source of the fifth NMOS transistor, the drain and source of the fifth NMOS transistor, and the drain of the fifth NMOS transistor are connected in series and their gates are all connected to the fourth enable control signal; and the sources of the fourth and sixth NMOS transistors and the fifth NMOS transistor are both grounded. The drains of the fourth 8 NMOS transistor and the fourth 9 NMOS transistor are both connected to the output terminal of the power transistor; the source of the fourth 8 NMOS transistor and the drain of the fourth 7 NMOS transistor are connected and their gates are both connected to the third enable control signal; the source of the fourth 9 NMOS transistor and the drain of the fifth 0 NMOS transistor are connected and their gates are both connected to the fourth enable control signal; the sources of the fourth 7 NMOS transistor and the fifth 0 NMOS transistor are both grounded. The second enable control circuit includes logic operation devices to generate a third enable control signal and a fourth enable control signal.

6. The circuit according to claim 4, characterized in that, Also includes: The second comparator circuit has one input terminal connected to the second output terminal of the voltage divider network and the other input terminal connected to the reference voltage. The output terminal is connected to the input terminal of the current limiting control circuit; It is configured to output control logic signals based on the reference voltage and the second feedback voltage to control the operating state of the current limiting control circuit; The second feedback voltage is provided by a voltage divider network.

7. The circuit according to claim 6, characterized in that, Voltage divider networks include: The first resistor, the second resistor, and the third resistor are connected in series; The upper end of the first resistor is connected to the output terminal of the power transistor, and the lower end of the third resistor is grounded; the upper end of the second resistor is connected to an input terminal of the first comparator circuit to provide the first feedback voltage, and the upper end of the third resistor is connected to an input terminal of the second comparator circuit to provide the second feedback voltage.

8. The circuit according to claim 6, characterized in that, The first comparator circuit and the second comparator circuit have the same structure, both including: The signal input pair includes a first NMOS transistor and a second NMOS transistor, whose gates serve as the input terminals of the comparator, respectively. The current mirror structure includes a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor. The gate and drain of the third NMOS transistor are connected to a current source and to the gates of the fourth and fifth NMOS transistors. The drain of the fourth NMOS transistor is connected to the source of the first and second NMOS transistors. The drain of the fifth NMOS transistor is output through an inverter INV1. The sources of the third, fourth, and fifth NMOS transistors are all grounded. The enable transistors, including the seventh PMOS transistor and the eighth PMOS transistor, have their gates connected to the comparator enable signal and their sources connected to the power supply voltage. The sixth PMOS transistor has its gate and drain connected to the drain of the first NMOS transistor, and its source connected to the power supply voltage. The ninth PMOS transistor has its gate connected to the drain of the eighth PMOS transistor, its source connected to the power supply voltage, and its drain connected to the drain of the fifth NMOS transistor. The tenth PMOS transistor has its gate connected to the drain of the seventh PMOS transistor, and its drain connected to the gate of the ninth PMOS transistor and the drain of the second NMOS transistor; its source is connected to the power supply voltage.

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