Gate driving circuit, display panel and driving unit measurement method

Abstract

The application provides a gate drive circuit, a display panel and a drive unit measurement method. The gate drive circuit comprises a plurality of drive units and a plurality of controllable switch units. The output end of the drive unit is connected with a scan line. The output end of the drive unit is also connected with the controllable switch unit one by one. The controllable switch unit is used for collecting the scan signal output by the drive unit. By setting the corresponding controllable switch unit for each drive unit, the scan signal output by the specific drive unit can be collected based on the controllable switch unit, so that the other drive units are not affected when the drive unit is measured. Meanwhile, the collection of the scan signal is controllable through the controllable switch unit in the embodiment, so that the destructive operation on the glass device is avoided, and the related devices in the display panel are prevented from being damaged.

Description

Technical Field

[0001] This invention relates to the field of display, and more particularly to a method for measuring a gate driving circuit, a display panel, and a driving unit. Background Technology

[0002] When performing quality testing on a display panel, if a defect occurs, it is necessary to measure the scan signal of a specific row. In existing technology, an auxiliary dummy line running through all scan lines is typically added. The dummy line is isolated from the scan lines by an insulating layer. When measurement is required, a laser is used to melt away the insulating layer between the scan line to be measured and the dummy line, short-circuiting the scan line to be measured and the dummy line, thereby acquiring the corresponding scan signal. However, since the laser acts directly on the glass, the backlight needs to be removed from the glass before laser treatment, which may damage the glass. At the same time, due to the stability issues of laser control, other signal lines may be short-circuited or broken during laser treatment, causing damage. Summary of the Invention

[0003] The main objective of this invention is to propose a measurement method for gate driving circuits, display panels, and driving units, aiming to solve the problem that existing measurement methods can damage related components in the display panel during application.

[0004] To achieve the above objectives, the present invention provides a gate driving circuit, which includes multiple driving units and multiple controllable switching units. The output terminals of the driving units are connected to scan lines, and each output terminal of the driving unit is also connected to one of the controllable switching units.

[0005] The controllable switch unit is used to acquire the scanning signal output by the drive unit.

[0006] Optionally, the controllable switching unit includes a measurement switching transistor, a control signal line, and an output signal line; the source of the measurement switching transistor is connected to the output terminal of the driving unit, the drain of the measurement switching transistor is connected to the output signal line, and the gate of the measurement switching transistor is connected to the control signal line; wherein:

[0007] The measurement switch is used to output the scan signal output by the drive unit to the output signal line when the control signal line outputs an enable signal.

[0008] Optionally, the gate driving circuit includes two driving modules, each driving module including a plurality of driving units; the driving module includes a first driving module and a second driving module, wherein the driving units in the first driving module are connected to odd-numbered scan lines, and the driving units in the second driving module are connected to even-numbered scan lines.

[0009] Optionally, the controllable switching unit includes a measuring switch transistor;

[0010] The output terminal of the driving unit is connected to the source of the measurement switch transistor, the drain of the measurement switch transistor is connected to the low voltage signal line of the opposite driving module, and the gate of the measurement switch transistor is connected to the target clock signal line. The target clock signal line is the earliest clock signal line whose rising edge arrives after the current driving unit stops outputting the scan signal.

[0011] The first driving module and the second driving module are opposite driving modules to each other.

[0012] In addition, to achieve the above objectives, the present invention also provides a display panel, the display panel including the gate driving circuit described above.

[0013] Optionally, the first driving module and the second driving module are respectively disposed on both sides of the display panel; wherein, the controllable switch unit is disposed on the side of the driving module opposite to the corresponding driving unit.

[0014] Furthermore, to achieve the above objectives, the present invention also provides a driving unit measurement method, which is applied to the gate driving circuit described above, characterized in that the driving unit measurement method includes:

[0015] Identify the driver unit to be tested;

[0016] Determine the target controllable switching unit corresponding to the driving unit under test;

[0017] The target controllable switch unit acquires the scanning signal output by the drive unit under test.

[0018] Optionally, determining the driving unit to be tested includes:

[0019] Acquire full-screen display data and display the full-screen display data;

[0020] Determine the display status of each pixel row when the full-screen display data is displayed;

[0021] The driving unit corresponding to the pixel row with the abnormal display status is taken as the driving unit to be tested.

[0022] Optionally, the step of acquiring the scanning signal output by the drive unit under test through the target controllable switch unit includes:

[0023] Turn on the measurement switch transistor and output a low voltage signal to the low voltage signal line of the driving module opposite to the driving unit under test before the scanning signal is output by the driving unit under test.

[0024] When the drive unit under test outputs the scanning signal, the output of the low voltage signal to the low voltage signal line of the drive module opposite to the drive unit under test is stopped;

[0025] When the drive unit under test outputs the scanning signal, the signal on the low voltage signal line of the drive module on the opposite side of the drive unit under test is acquired to obtain the scanning signal output by the drive unit under test.

[0026] Optionally, the conduction measurement switch, and the output of a low-voltage signal to the low-voltage signal line of the driving module opposite to the driving unit under test before the scanning signal is output by the driving unit under test, includes:

[0027] The current clock signal, associated clock signal, and opposite clock signal corresponding to the driving unit under test are determined. The current clock signal is the clock signal that controls the driving unit under test. The associated clock signal is the clock signal corresponding to the driving unit that provides a charging signal to the driving unit under test. The opposite clock signal is the clock signal of the gate input of the measurement switch corresponding to the driving unit under test.

[0028] In the test module where the drive unit under test is located, the output of clock signals other than the current clock signal and the associated clock signal is stopped;

[0029] In the test module on the opposite side of the drive unit under test, the output of clock signals other than the clock signal on the opposite side is stopped, and the falling edge of the clock signal on the opposite side is extended to the falling edge of the current clock signal;

[0030] Before the rising edge of the current clock signal, a low voltage signal is output to the low voltage signal line of the driving module opposite to the driving unit under test.

[0031] This invention proposes a gate driving circuit, a display panel, and a method for measuring driving units. The gate driving circuit includes multiple driving units and multiple controllable switching units. The output terminals of the driving units are connected to scan lines, and each driving unit's output terminal is also connected to a corresponding controllable switching unit. The controllable switching unit is used to acquire the scan signals output by the driving units. By setting a corresponding controllable switching unit for each driving unit, the scan signals output by a specific driving unit can be acquired based on the controllable switching units, thus avoiding interference with other driving units during measurement. Furthermore, in this embodiment, the acquisition of scan signals is controllable through the controllable switching units, avoiding destructive operations on glass and other components, thereby preventing damage to related components in the display panel. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0033] Figure 1 This is a functional block diagram of an embodiment of the gate drive circuit of the present invention;

[0034] Figure 2 This is a circuit structure diagram of one embodiment of the gate driving circuit of the present invention;

[0035] Figure 3 This is a functional block diagram of another embodiment of the gate drive circuit of the present invention;

[0036] Figure 4 This is a circuit structure diagram of another embodiment of the gate drive circuit of the present invention;

[0037] Figure 5 This is a schematic diagram of the clock signal waveform in one embodiment of the gate drive circuit of the present invention;

[0038] Figure 6 This is a module structure diagram of an embodiment of the array display panel of the present invention;

[0039] Figure 7 This is a flowchart illustrating an embodiment of the driving unit measurement method of the present invention;

[0040] Figure 8 This is a signal waveform diagram of an embodiment of the driving unit measurement method of the present invention.

[0041] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0042] Explanation of icon numbers:

[0043] 110 drive unit T1~T4 First TFT to Fourth TFT 120 Controllable switching unit C1 First capacitor 100 First drive module TN Measurement switch tube 200 Second drive module Detailed Implementation

[0044] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0046] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0047] Furthermore, the use of terms such as "first" and "second" in this invention is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed by this invention.

[0048] This invention provides a gate driving circuit for use in a display panel. Please refer to [link / reference]. Figure 1 , Figure 1 This is a functional block diagram of an embodiment of the gate driving circuit of the present invention. In this embodiment, the gate driving circuit includes multiple driving units 110 and multiple controllable switching units 120. The output terminal of the driving unit 110 is connected to the scan line GATE, and the output terminal of the driving unit 110 is also connected to each of the controllable switching units 120 in a one-to-one correspondence; wherein:

[0049] The controllable switch unit 120 is used to acquire the scanning signal output by the drive unit 110.

[0050] Understandably, the GOA (Gate Driven on Array) circuit is connected to the pixel unit through the scan line GATE; each driving unit 110 is connected to a scan line GATE, and each scan line GATE is connected to a row of pixel units. The driving unit 110 outputs a scan signal to the pixel unit through the scan line GATE. When the pixel unit receives the scan signal, it opens and writes the data signal transmitted by the data line.

[0051] The acquisition function of the controllable switch unit 120 is controllable, meaning that the controllable switch unit 120 can acquire the scanning signal or not, and whether to acquire it can be controlled based on actual needs; when acquiring the scanning signal through the controllable switch unit 120, the scanning signal output by the drive unit 110 can be directly obtained through the controllable switch unit 120.

[0052] The controllable switch unit 120 is connected to the drive unit 110 in a one-to-one correspondence. Therefore, after determining the drive unit 110 to be measured, the scan signal output by the drive unit 110 can be acquired through the controllable switch unit 120 corresponding to the drive unit 110.

[0053] This embodiment provides a corresponding controllable switch unit 120 for each drive unit 110, enabling the acquisition of scanning signals output by a specific drive unit 110 based on the controllable switch unit 120. This avoids affecting other drive units 110 when measuring a drive unit 110. At the same time, the controllable switch unit 120 in this embodiment makes the acquisition of scanning signals controllable, avoiding destructive operations on glass and other components, thereby preventing damage to related components in the display panel.

[0054] Further, see Figure 2 The controllable switching unit 120 includes a measurement switch transistor TN, a control signal line CL, and an output signal line OL; the source of the measurement switch transistor TN is connected to the output terminal of the driving unit 110, the drain of the measurement switch transistor TN is connected to the output signal line OL, and the gate of the measurement switch transistor TN is connected to the control signal line CL; wherein:

[0055] The measurement switch TN is used to output the scan signal output by the drive unit 110 to the output signal line OL when the control signal line CL outputs an enable signal.

[0056] The specific type of the measurement switch TN can be set according to actual needs. In this embodiment, the measurement switch TN is an N-type TFT. When the control signal line CL outputs a high level, the measurement switch TN is turned on, and the scanning signal output by the drive unit 110 is output to the output signal line OL through the measurement switch TN. At this time, the scanning signal output by the drive unit 110 can be acquired by detection devices such as an oscilloscope.

[0057] It should be noted that, in specific settings, a control signal line CL and an output signal line OL can be set for each controllable switch unit 120, that is, the control signal line CL, the output signal line OL, and the measurement switch transistor TN are set accordingly; alternatively, a control signal line CL and an output signal line OL can be set for multiple or all measurement switch transistors TN. In the case of line-by-line scanning, only one drive unit 110 outputs a scan signal at the same time. Therefore, during the output period corresponding to the drive unit 110 under test, the scan signal corresponding to the drive unit 110 under test can be acquired. Depending on the specific GOA circuit settings, the specific settings of the controllable switch unit 120 can also be adjusted to ensure that when the drive unit 110 under test outputs a scan signal, the output signal line OL only outputs the scan signal of the drive unit 110 under test and does not output the scan signals of other drive units 110, thereby realizing the measurement of a specific drive unit 110.

[0058] It is understood that the specific structure of the driving unit 110 can be set according to the actual application needs, such as a 4T1C (4 TFTs + 1 capacitor) circuit, an 8T1C circuit, etc., and is not limited here; this embodiment and subsequent embodiments will use 4T1C as an example for description. Specifically, the driving unit 110 includes a first TFTT1, a second TFTT2, a third TFTT3, a fourth TFTT4, and a first capacitor C1; wherein:

[0059] The source of the second TFTT2 is connected to the power signal line, the gate of the second TFTT2 is connected to the output terminal of the preceding driving unit 110, the drain of the second TFTT2 is connected to the gate of the first TFTT1, the gate of the first TFTT1 is connected to the drain of the first TFTT1 through the first capacitor C1, the source of the first TFTT1 is connected to the clock signal line, and the drain of the first TFTT1 is connected to the scan line GATE as the output terminal of the driving unit 110. The gate of the first TFTT1 is the Q point.

[0060] The drain of the first TFTT1 is also connected to the source of the third TFTT3. The drain of the third TFTT3 is connected to a low-voltage signal line. The gate of the third TFTT3 is connected to the output of the subsequent driving unit 110. The gate of the fourth TFTT4 is connected to the output of the subsequent driving unit 110. The drain of the fourth TFTT4 is connected to a low-voltage signal line. The source of the fourth TFTT4 is connected to the gate of the first TFTT1.

[0061] Wherein, the front drive unit 110 is the drive unit 110 that provides a charging signal to the current drive unit 110, and the drive unit 110 is the drive unit 110 to which the current drive unit 110 provides a charging signal;

[0062] GN is the scan signal, CLK is the clock signal, VDD is the power signal, GN-4 is the charging signal, and VGL is the low-level signal.

[0063] When the front drive unit 110 does not output a scan signal, even if the clock signal outputs a high level, the first TFTT1 will not be turned on, and the current drive unit 110 will not output a scan signal.

[0064] When the front drive unit 110 outputs a scan signal, the second TFTT2 turns on, and VDD charges the first capacitor C1 through the second TFTT2, after which the first TFTT1 turns on.

[0065] When the clock signal goes high, the high level of the clock signal is output through the first TFTT1, the current driving unit 110 outputs a scan signal, and at the same time charges the subsequent driving unit 110.

[0066] After the clock signal goes low, the current driving unit 110 stops outputting the scan signal. At the same time, the rear driving unit 110 outputs the scan signal, which turns on the third TFTT3 and the fourth TFTT4, discharges the Q point, and the current driving unit 110 ends the operation of this frame.

[0067] Furthermore, the gate driving circuit includes two driving modules, each driving module including a plurality of driving units 110; the driving module includes a first driving module 100 and a second driving module 200, wherein the driving units 110 in the first driving module 100 are connected to odd-numbered scan lines, and the driving units 110 in the second driving module 200 are connected to even-numbered scan lines.

[0068] See Figure 3In this embodiment, the gate driving circuit is a dual-sided driving circuit. The first driving module 100 and the second driving module 200 are respectively located on both sides of the display panel. The first driving module 100 and the second driving module 200 control the odd-numbered scan lines and the even-numbered scan lines respectively. The first driving module 100 and the second driving module 200 operate independently and do not affect each other.

[0069] Understandably, while the aforementioned scheme of adding control signal lines and output signal lines enables measurement of the drive unit 110, it requires additional signal lines, increasing space requirements and wiring complexity, making it inconvenient to implement. To solve this problem, this embodiment achieves measurement of the drive unit 110 without adding additional signal lines based on the dual-sided drive circuit. Specifically:

[0070] See Figure 4 The controllable switching unit 120 includes a measuring switch transistor TN;

[0071] The output terminal of the driving unit 110 is connected to the source of the measurement switch TN, the drain of the measurement switch TN is connected to the low voltage signal line of the opposite driving module, and the gate of the measurement switch TN is connected to the target clock signal line. The target clock signal line is the earliest clock signal line whose rising edge arrives after the current driving unit 110 stops outputting the scan signal.

[0072] The first driving module 100 and the second driving module 200 are opposite driving modules to each other.

[0073] In this embodiment, the driving module located on the left is the first driving module 100, and the driving module located on the right is the second driving module 200. The signals in the first driving module 100 are suffixed with L, and the signals in the second driving module 200 are suffixed with R.

[0074] Understandably, GOA typically uses multiple clock signal lines to control the driving modules. For example, the first driving module 100 might have four clock signal lines, and the second driving module 200 might have four clock signal lines. Taking the first driving module 100 as an example, the four clock signal lines sequentially control the driving units 110 in different rows. For instance, clock signal lines 1 / 2 / 3 / 4 serve as the clock signal lines for the driving units 110 corresponding to the pixels in rows 1 / 3 / 5 / 7 (in a dual-side driving system, the two driving modules drive each row alternately). Similarly, clock signal lines 1 / 2 / 3 / 4 serve as the clock signal lines for the driving units 110 corresponding to the pixels in rows 9 / 11 / 13 / 15. The clock signal line follows the same pattern; thus, it can be seen that the same clock signal line connects the driving units 110 that are 4 rows apart. In the connection, the driving units 110 adjacent to clock signal lines 1 and 3 are cascaded to realize the output of the charging signal. For example, the scanning signal output by the first row of pixels is used as the charging signal of the fifth row of pixels. Therefore, for the current row GN, the charging signal it receives comes from the driving unit 110 of row GN-4. That is, the driving unit 110 of row GN-4 is the preceding driving unit 110 of row GN, and the driving unit 110 of row GN+4 is the following driving unit 110 of row GN.

[0075] When acquiring the scan signal of the driving unit 110, it is necessary to keep the measurement switch TN on while the driving unit 110 outputs the scan signal. Simultaneously, it is also necessary to avoid interference with the charging phase of the driving unit 110. Therefore, in this embodiment, the gate of the measurement switch TN is connected to the target clock signal line. The target clock signal line is the clock signal line whose rising edge arrives earliest after the current driving unit 110 stops outputting the scan signal; see [link to relevant documentation]. Figure 5 , Figure 5 This is a schematic diagram of a clock signal under one condition. If the clock signal corresponding to the current driving unit 110 is CLK1L, then the falling edge of CLK1L corresponds to the moment when the current driving unit 110 stops outputting the scan signal. In the opposite driving module, i.e., among the clock signals with the suffix R, CLK2R is the clock signal with the earliest rising edge. However, considering the ghosting phenomenon in practical applications, the driving unit 110 may not be completely turned off at the falling edge of CLK1L. Therefore, a waiting time TW can be set, and the target clock signal line is determined after the waiting time. Figure 5 As can be seen, after the waiting time, CLK3R is the earliest clock signal to arrive with a rising edge. Therefore, the clock signal line corresponding to CLK3R is connected to the measurement switch transistor TN.

[0076] After the falling edge of GLK1L, the rising edge of CLK3R turns on the measurement switch TN. At this time, the low-voltage signal line fills the scan line of the drive unit under test 110 with a low-level signal through the measurement switch TN. It can be understood that the clock signal lines connected to the measurement switch TN of the previous drive unit 110 and the drive unit under test 110 must be different. Since the clock signal lines connected to the measurement switch TN are determined by the method, in one side of the drive module, the gate of the measurement switch TN of the drive unit 110 connected to the same clock signal line must be connected to the same clock signal line of the opposite drive module, while the gate of the drive unit 110 connected to different clock signal lines must be connected to the same clock signal line of the opposite drive module. The gate of the corresponding measurement switch TN is connected to a different clock signal line of the opposite driving module. Since the driving unit under test 110 and the preceding driving unit 110 are connected to different clock signal lines, when the measurement switch TN of the driving unit under test 110 is turned on, the measurement switch TN of the preceding driving unit 110 will not be turned on, thus not affecting the charging of the driving unit under test 110 by the preceding driving unit 110. After the driving unit under test 110 outputs a scan signal, the scan signal is output to the low voltage signal line of the opposite module through the measurement switch TN. At this time, the scan signal output by the driving unit under test 110 can be obtained by using a detection device such as an oscilloscope, thus completing the measurement.

[0077] Additionally, it should be noted that when the driving unit 110 is not required to perform measurements, the output scan signal of the driving unit 110 and the turn-on of the measurement switch TN do not occur simultaneously. That is, when the driving unit 110 outputs the scan signal, the measurement switch TN is turned off. However, due to the influence of the clock signal line connected to the gate of the measurement switch TN, the measurement switch TN will be turned on for a period of time when the driving unit 110 stops outputting the scan signal. At this time, due to the influence of the low voltage signal line, the signal of the corresponding scan line of the driving unit 110 will be pulled low, thereby making the pixel of that row turn off more completely, which plays a role in noise reduction and suppression.

[0078] This invention also protects a display panel including a gate driving circuit. The structure of the gate driving circuit can be referred to in the above embodiments, and will not be repeated here. Accordingly, since the display panel of this embodiment adopts the above-described gate driving circuit technical solution, the display panel has all the beneficial effects of the above-described gate driving circuit.

[0079] Further, see Figure 6 The first driving module 100 and the second driving module 200 are respectively disposed on both sides of the display panel; wherein, the controllable switch unit 120 is disposed on the side of the driving module opposite to the corresponding driving unit 110.

[0080] In this embodiment, the controllable switching unit 120 is used to measure the switching transistor TN as an example.

[0081] Although topologically, measuring the drive unit 110 can be achieved simply by connecting the terminals of the measurement switch TN according to the aforementioned description, in practical applications, when the gate drive circuit is a dual-sided drive, the two drive modules are independent, each with its own signal line system. As explained above, the gate and drain of the measurement switch TN need to be connected to the signal lines in the opposite drive module. If the measurement switch TN is placed on the same side as the drive unit 110, an additional set of signal lines identical to those in the opposite drive module needs to be added to the same drive module, undoubtedly increasing cost and space requirements. In addition, the newly added signal lines can only be used for measurement, resulting in low utilization. Therefore, to solve this problem, in this embodiment, the measurement switch TN is set on the opposite side of the driving module, so that the drain and gate of the measurement switch TN can be directly connected to the signal lines in the opposite side of the driving module without the need to add additional signal lines. At the same time, the scan signal output by the driving module itself will be output through the scan line. The measurement switch TN set on the opposite side of the driving module only needs to connect its source to the corresponding scan line to realize the aforementioned controllable switch unit 120 and realize the measurement of the driving unit 110.

[0082] This invention also protects a method for measuring a driving unit, which is applied to the gate driving circuit described above. See [link to relevant documentation]. Figure 7 The driving unit measurement method includes:

[0083] Step S10: Determine the driving unit to be tested;

[0084] Step S20: Determine the target controllable switching unit corresponding to the driving unit under test;

[0085] Step S30: The scanning signal output by the drive unit under test is acquired through the target controllable switch unit.

[0086] The driver unit under test is the driver unit that needs to be measured; the driver unit under test can be specified by the user, determined based on preset conditions, or executed periodically according to a preset plan.

[0087] The target controllable switch unit is a controllable switch unit connected to the output terminal of the drive unit under test.

[0088] Once the controllable switch unit is determined, the scanning signal output by the drive unit under test can be acquired through the controllable switch unit.

[0089] This embodiment sets up a corresponding controllable switch unit for each driving unit, enabling the acquisition of the scanning signal output by a specific driving unit based on the controllable switch unit. This avoids affecting other driving units when measuring a driving unit. At the same time, the controllable switch unit in this embodiment makes the acquisition of the scanning signal controllable, avoiding destructive operations on glass and other components, thereby preventing damage to related components in the display panel.

[0090] Further, step S10 includes:

[0091] Step S11: Obtain full-screen display data and display the full-screen display data;

[0092] Step S12: Determine the display status of each pixel row when the full-screen display data is displayed;

[0093] Step S13: The driving unit corresponding to the pixel row with the abnormal display state is taken as the driving unit to be tested.

[0094] Full-screen display data refers to display data where all pixels are displayed. This includes, but is not limited to, indicating a full white image, a full red image, a full blue image, and a full green image. When displaying full-screen display data, if the driving unit malfunctions, display errors will occur, such as incomplete display. Therefore, by displaying full-screen display data, abnormal pixel rows can be identified, and the driving unit corresponding to the abnormal pixel row can be used as the driving unit to be tested.

[0095] Further, step S30 includes:

[0096] Step S31: Turn on the measurement switch transistor and output a low voltage signal to the low voltage signal line of the driving module opposite to the driving unit under test before the scanning signal is output by the driving unit under test.

[0097] Step S32: When the drive unit under test outputs the scanning signal, stop outputting the low voltage signal to the low voltage signal line of the drive module opposite to the drive unit under test;

[0098] Step S33: When the drive unit under test outputs the scanning signal, the signal on the low voltage signal line of the drive module opposite to the drive unit under test is acquired to obtain the scanning signal output by the drive unit under test.

[0099] Before the drive unit under test (DUT) outputs a scan signal, the measurement switch is turned on. At this time, the low voltage of the low-voltage signal line is filled into the scan line corresponding to the DUT through the measurement switch, thereby resetting the signal in the scan line to facilitate the subsequent acquisition of the scan signal output by the DUT. It can be understood that before scanning to the row where the DUT is located, the pixel rows connected to the same scan line as the DUT and preceding the DUT have already been charged. If the measurement switch is directly turned on when the DUT outputs a scan signal, since the measurement switch is controlled by the clock signal on the opposite side, essentially all measurement switches controlled by the clock signal on the opposite side are turned on. Therefore, the signal in the previous pixel row will also be transmitted to the low-voltage signal line. Thus, it is necessary to release the signal of the previously charged pixel row. In this embodiment, all scan lines connected to the switches on both sides are filled with a low-level signal, so that when the DUT outputs a scan signal, only the scan signal output by the DUT can be transmitted to the low-voltage signal line through the measurement switch.

[0100] If the low-voltage signal line remains at a low voltage output when the drive unit under test outputs a scan signal, the scan signal cannot be acquired. Therefore, when the drive unit under test outputs a scan signal, the low-voltage signal line is controlled not to output the low-voltage signal, so that the scan signal output by the drive unit under test is transmitted to the low-voltage signal line through the measurement switch transistor. Then, the signal on the low-voltage signal line is acquired to obtain the scan signal output by the drive unit under test, thus completing the measurement.

[0101] Further, step S31 includes:

[0102] Step S311: Determine the current clock signal, associated clock signal, and opposite clock signal corresponding to the driving unit under test. The current clock signal is the clock signal that controls the driving unit under test. The associated clock signal is the clock signal corresponding to the driving unit that provides a charging signal to the driving unit under test. The opposite clock signal is the clock signal of the gate input of the measurement switch corresponding to the driving unit under test.

[0103] Step S312: In the test module where the drive unit under test is located, stop outputting clock signals other than the current clock signal and the associated clock signal;

[0104] Step S313: In the test module on the opposite side of the drive unit under test, stop outputting clock signals other than the clock signal on the opposite side, and extend the falling edge of the clock signal on the opposite side to the falling edge of the current clock signal;

[0105] Step S314: Before the rising edge of the current clock signal, output a low voltage signal to the low voltage signal line of the driving module opposite to the driving unit under test.

[0106] During measurement, the focus is on the relevant information of the driver unit under test. Therefore, to avoid signal interference, signals unrelated to the driver unit under test are stopped from being output. As explained above, for the driver unit under test, the relevant signals include the current clock signal, the associated clock signal, and the opposite clock signal. The current clock signal is used to output the scan signal, the associated clock signal is used to charge the driver unit under test, and the opposite clock signal is used to control the measurement switch. Therefore, the current clock signal, the associated clock signal, and the opposite clock signal are retained, and other clock signals are stopped from being output.

[0107] If the clock signal corresponding to the driving unit under test, i.e. the current clock signal, is CLK1L, then the clock signal corresponding to the previous driving unit, i.e. the associated clock signal, is CLK3L; and the clock signal on the opposite side is CLK3R. At this time, the output of CLK2 / 4L and CLK1 / 2 / 4R is stopped.

[0108] Depend on Figure 5 As can be seen, during normal display, CLK3R experiences a rising edge after the falling edge of CLK1L. However, it becomes a low-level signal when the next rising edge of CLK1L arrives. This means that the corresponding measurement switch is turned off when the drive unit under test outputs the scan signal. Therefore, the measurement switch will not affect the normal display of the drive unit under test. At the same time, in order to achieve measurement, CLK3R needs to be adjusted so that the measurement switch remains on until the drive unit under test completes the output scan signal. Therefore, in this embodiment, the clock signal on the opposite side is controlled to maintain a high level until the falling edge of the current clock signal, so that the measurement switch remains on during the output scan signal of the drive unit under test. The scan signal can be transmitted to the low-voltage signal line through the measurement switch to achieve the acquisition of the scan signal and complete the measurement of the drive unit under test.

[0109] See Figure 8 ,based on Figure 8 The specific process of this embodiment will be described as follows:

[0110] 1. Input full-screen display data to fully charge all row pixels and identify the abnormal driver unit under test;

[0111] 2. Determine the row S where the driver unit under test is located. Assuming that the driver module is set to work alternately with 4 clock signals, the current clock signal corresponding to the driver unit under test can be determined by the remainder of S / 4. Taking the current clock signal as CLK1L as an example.

[0112] 3. Obtain the measurement display data corresponding to the drive unit under test. The measurement display data needs to meet the following conditions: the first drive module outputs CLK1 / 3L and does not output CLK2 / 4L; the second drive module outputs CLK3R and does not output CLK1 / 2 / 4R.

[0113] 4. The CLK1 / 3L of the first drive module is outputting normally;

[0114] 5. When scanning to line S-4, the drive unit y controlled by CLK1L before line S-4 has already output a scan signal, and the corresponding pixel line has been charged and remains in the off state; at this time, the rising edge of CLK3R arrives, turns on the measurement switch corresponding to all drive units controlled by CLK1L, and charges the low voltage GND (0V) input by VGL_R into the scan lines of all drive units controlled by CLK1L;

[0115] 6. The scan lines of row S-4 in the front drive unit are not affected by CLK3R. Therefore, the front drive unit can precharge the drive unit under test normally.

[0116] 7. When the drive unit under test outputs a scan signal, keep CLK3R at a high level and simultaneously stop outputting a low voltage signal to the low voltage signal line. At this time, the scan lines of all drive units controlled by CLK1L except for row S are 0V. Only the scan signal output by the drive unit under test in row S is at a high level. The scan signal output by the drive unit under test is transmitted to the low voltage signal line VGL_R through the measurement switch. The voltage of VGL_R is measured by an oscilloscope to obtain the scan signal output by the drive unit under test.

[0117] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0118] The above are merely preferred embodiments of the present invention and do not limit the scope of the patent. Any equivalent structural or procedural transformations made based on the description and drawings of the present invention, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of the present invention.

Claims

1. A gate driving circuit, characterized in that, The gate driving circuit includes multiple driving units and multiple controllable switching units. The output terminal of each driving unit is connected to a scan line, and the output terminal of each driving unit is also connected to each of the controllable switching units in a corresponding manner. The controllable switch unit is used to acquire the scanning signal output by the drive unit; The gate driving circuit includes two driving modules, each driving module including multiple driving units; the driving module includes a first driving module and a second driving module, wherein the driving units in the first driving module are connected to odd-numbered scan lines, and the driving units in the second driving module are connected to even-numbered scan lines; The controllable switching unit includes a measuring switching transistor; The output terminal of the driving unit is connected to the source of the measurement switch transistor, the drain of the measurement switch transistor is connected to the low-voltage signal line of the opposite driving module, and the gate of the measurement switch transistor is connected to the target clock signal line. The target clock signal line is the earliest rising edge of the clock signal in the opposite driving module after the current driving unit stops outputting the scan signal. The falling edge of the opposite clock signal is extended to the falling edge of the current clock signal. The current clock signal is the clock signal that controls the current driving unit, and the opposite clock signal is the clock signal input to the gate of the measurement switch transistor corresponding to the current driving unit. The first driving module and the second driving module are opposite driving modules to each other.

2. The gate driving circuit as described in claim 1, characterized in that, The controllable switching unit includes a measurement switch transistor, a control signal line, and an output signal line; the source of the measurement switch transistor is connected to the output terminal of the driving unit, the drain of the measurement switch transistor is connected to the output signal line, and the gate of the measurement switch transistor is connected to the control signal line; wherein: The measurement switch is used to output the scan signal output by the drive unit to the output signal line when the control signal line outputs an enable signal.

3. A display panel, characterized in that, The display panel includes the gate driving circuit as described in any one of claims 1 to 2.

4. The display panel as described in claim 3, characterized in that, The first drive module and the second drive module are respectively located on both sides of the display panel; wherein, the controllable switch unit is located on the opposite side of the corresponding drive module.

5. A method for measuring a drive unit, characterized in that, The driving unit measurement method is applied to the gate driving circuit as described in any one of claims 1 to 2, characterized in that the driving unit measurement method includes: Identify the driver unit to be tested; Determine the target controllable switching unit corresponding to the driving unit under test; The target controllable switch unit acquires the scanning signal output by the drive unit under test.

6. The driving unit measurement method as described in claim 5, characterized in that, The determination of the driving unit to be tested includes: Acquire full-screen display data and display the full-screen display data; Determine the display status of each pixel row when the full-screen display data is displayed; The driving unit corresponding to the pixel row with the abnormal display status is taken as the driving unit to be tested.

7. The driving unit measurement method as described in claim 5, characterized in that, The step of acquiring the scanning signal output by the drive unit under test through the target controllable switch unit includes: Turn on the measurement switch transistor and output a low voltage signal to the low voltage signal line of the driving module opposite to the driving unit under test before the scanning signal is output by the driving unit under test. When the drive unit under test outputs the scanning signal, the output of the low voltage signal to the low voltage signal line of the drive module opposite to the drive unit under test is stopped. When the drive unit under test outputs the scanning signal, the signal on the low voltage signal line of the drive module on the opposite side of the drive unit under test is acquired to obtain the scanning signal output by the drive unit under test.

8. The driving unit measurement method as described in claim 7, characterized in that, The conduction measurement switch, before the scanning signal is output by the drive unit under test, outputs a low voltage signal to the low voltage signal line of the drive module opposite to the drive unit under test, including: The current clock signal, associated clock signal, and opposite clock signal corresponding to the driving unit under test are determined. The current clock signal is the clock signal that controls the driving unit under test. The associated clock signal is the clock signal corresponding to the driving unit that provides the charging signal to the driving unit under test. The opposite clock signal is the clock signal of the gate input of the measurement switch corresponding to the driving unit under test. In the test module where the driver unit under test is located, the output of clock signals other than the current clock signal and the associated clock signal is stopped; In the test module on the opposite side of the drive unit under test, the output of clock signals other than the clock signal on the opposite side is stopped, and the falling edge of the clock signal on the opposite side is extended to the falling edge of the current clock signal; Before the rising edge of the current clock signal, a low voltage signal is output to the low voltage signal line of the driving module opposite to the driving unit under test.

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