Gate drive circuit and display device

Abstract

The application discloses a gate driving circuit and a display device, and belongs to the technical field of display. The gate driving circuit comprises a first control module, a first output module, a second control module, a coupling module, a reset module and a second output module. The first control module controls the potentials of a first node and a second node according to a first gate input signal. The first output module outputs a first gate driving signal according to the potentials of the first node and the second node. The second control module controls the potentials of a third node and a fourth node according to a second gate input signal. The coupling module controls the potential of the fourth node according to the potential of a coupling node. The reset module resets the coupling node according to the potential of the second node. The second output module outputs a second gate driving signal according to the potentials of the third node and the fourth node. The effective level potentials of the first gate driving signal and the second gate driving signal are different. The pulse width of the effective level of the second gate driving signal is greater than the pulse width of the effective level of the first gate driving signal. The embodiment of the application is beneficial to narrow frame design.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a gate driving circuit and a display device. Background Technology

[0002] With the continuous development of display technology, the application range of display panels is becoming increasingly wide, and people's requirements for display panels are also getting higher and higher. A display panel includes pixel circuits and gate drive circuits that provide gate drive signals to the pixel circuits. As the functions of pixel circuits increase and various display technologies are integrated into the screen, the bezel width of display panels becomes larger, which is not conducive to narrow bezel designs. Summary of the Invention

[0003] This invention provides a gate driving circuit and a display device, enabling the same gate driving circuit to output two gate driving signals with different pulse potentials and different pulse widths, which is beneficial for achieving narrow bezel design.

[0004] In a first aspect, embodiments of the present invention provide a gate driving circuit, comprising:

[0005] A first control module includes a first node and a second node. The first control module is used to control the potential of the first node and the second node according to a first gate input signal.

[0006] The first output module is connected to the first node and the second node respectively, and is used to output a first gate drive signal according to the potential of the first node and the second node;

[0007] The second control module includes a third node and a fourth node, and the second control module is used to control the potential of the third node and the fourth node according to the second gate input signal;

[0008] A coupling module, connected to a coupling node, is used to couple and control the potential of the fourth node according to the potential of the coupling node;

[0009] A reset module, connected to the coupling node, is used to reset the coupling node according to the potential of the second node;

[0010] The second output module is connected to the third node and the fourth node respectively, and is used to output a second gate drive signal according to the potential of the third node and the fourth node;

[0011] Wherein, the potential of the effective level of the first gate drive signal is different from the potential of the effective level of the second gate drive signal, and the pulse width of the effective level of the second gate drive signal covers the pulse width of the effective level of the first gate drive signal.

[0012] Optionally, the gate driving circuit includes: a first clock terminal connected to a first clock signal; a second clock terminal connected to a second clock signal; a first input terminal connected to the first gate input signal; a second input terminal connected to the second gate input signal; a first power supply terminal connected to a first power supply signal; a second power supply terminal connected to the second power supply signal; a first output terminal outputting a first gate driving signal; and a second output terminal outputting a second gate driving signal.

[0013] The first control module is used to control the potential of the first node and the second node according to the first clock signal, the first power signal and the first gate input signal;

[0014] The first output module is used to control the potential of the first gate drive signal according to the second power supply signal, the second clock signal, the potential of the first node and the second node;

[0015] The second control module is used to control the potentials of the third node and the fourth node according to the second gate input signal, the first clock signal, the second clock signal, the first power supply signal, and the second power supply signal;

[0016] The coupling module is used to control the potential of the coupling node according to the potential of the fourth node and the second clock signal, and to couple the potential transition of the coupling node to the fourth node;

[0017] The reset module is used to respond to the potential of the second node and reset the coupling node using the second power signal;

[0018] The second output module is used to control the potential of the second gate drive signal according to the first power signal, the second power signal, the potential of the third node and the fourth node.

[0019] Optionally, the first control module includes:

[0020] The first input unit is connected to the first input terminal, the first clock terminal and the second node respectively, and is used to control whether the first gate input signal is transmitted to the second node according to the first clock signal.

[0021] The first potential control unit is connected to the first clock terminal, the first power supply terminal and the first node respectively, and is used to control whether the first power supply signal is transmitted to the first node according to the first clock signal.

[0022] The second potential control unit is connected to the first node, the second node and the first clock terminal respectively, and is used to control whether the first clock signal is transmitted to the first node according to the potential of the second node;

[0023] Preferably, the first input unit includes: a first transistor, the gate of the first transistor being connected to the first clock terminal, the first electrode of the first transistor being connected to the first input terminal, and the second electrode of the first transistor being connected to the second node;

[0024] The first potential control unit includes: a second transistor connected between the first power supply terminal and the first node, wherein the gate of the second transistor is connected to the first clock terminal;

[0025] The second potential control unit includes: a third transistor connected between the first clock terminal and the first node, wherein the gate of the third transistor is connected to the second node;

[0026] Preferably, the first control module further includes: a fourth transistor connected between the second terminal of the first transistor and the second node, wherein the gate of the fourth transistor is connected to the first power supply terminal; wherein the gate of the third transistor is connected to the second terminal of the first transistor;

[0027] Preferably, the first control module further includes: a fifth transistor, the gate of the fifth transistor being connected to the first power supply terminal, the first terminal of the fifth transistor being connected to the second node, and the second terminal of the fifth transistor being connected to the reset module.

[0028] Optionally, the first output module includes:

[0029] The first output unit is connected to the first node, the second power supply terminal and the first output terminal respectively, and is used to control whether the second power supply signal is output as the first gate drive signal according to the potential of the first node.

[0030] The second output unit is connected to the second node, the second clock terminal and the first output terminal respectively, and is used to control whether the second clock signal is output as the first gate drive signal according to the potential of the second node.

[0031] Preferably, the first output unit includes a sixth transistor and a first capacitor, wherein the sixth transistor is connected between the second power supply terminal and the first output terminal, the gate of the sixth transistor is connected to the first node, and the first capacitor is connected between the gate of the sixth transistor and the first electrode.

[0032] The second output unit includes a seventh transistor and a second capacitor. The seventh transistor is connected between the second clock terminal and the first output terminal. The gate of the seventh transistor is connected to the second node. The second capacitor is connected between the gate and the second terminal of the seventh transistor.

[0033] Optionally, the second control module includes:

[0034] The second input unit is connected to the second input terminal, the first clock terminal and the fourth node respectively, and is used to control whether the second gate input signal is transmitted to the fourth node according to the first clock signal;

[0035] The third potential control unit is connected to the first power supply terminal, the second input terminal, the second clock terminal and the third node respectively, and is used to control whether the first power supply signal is transmitted to the third node according to the second gate input signal and the second clock signal;

[0036] The fourth potential control unit is connected to the third node, the fourth node and the second power supply terminal respectively, and is used to control whether the second power supply signal is transmitted to the third node according to the potential of the fourth node;

[0037] Preferably, the second input unit includes: an eighth transistor, the gate of which is connected to the first clock terminal, the first terminal of which is connected to the second input terminal, and the second terminal of which is connected to the fourth node;

[0038] The third potential control unit includes a ninth transistor and a tenth transistor, which are connected in series between the first power supply terminal and the third node. The gate of the ninth transistor is connected to the second input terminal, and the gate of the tenth transistor is connected to the second clock terminal. The ninth transistor and the tenth transistor have different channel types.

[0039] The fourth potential control unit includes: an eleventh transistor connected between the second power supply terminal and the third node, wherein the gate of the eleventh transistor is connected to the fourth node;

[0040] Preferably, the second control module further includes: a twelfth transistor connected between the second terminal of the eighth transistor and the fourth node, wherein the gate of the twelfth transistor is connected to the first power supply terminal; wherein the gate of the eleventh transistor is connected to the second terminal of the eighth transistor.

[0041] Optionally, the reset module includes a thirteenth transistor connected between the second power supply terminal and the coupling node, wherein the gate of the thirteenth transistor is connected to the second node.

[0042] Optionally, the coupling module includes:

[0043] A transmission unit, connected to the fourth node, the second clock terminal, and the coupling node respectively, is used to control whether the second clock signal is transmitted to the coupling node according to the potential of the fourth node;

[0044] A coupling unit, connecting the coupling node and the fourth node respectively, is used to couple the potential transition of the coupling node to the fourth node;

[0045] Preferably, the transmission unit includes: a fourteenth transistor connected between the second clock terminal and the coupling node, wherein the gate of the fourteenth transistor is connected to the fourth node;

[0046] The coupling unit includes a third capacitor connected between the coupling node and the fourth node.

[0047] Optionally, the second output module includes:

[0048] The third output unit is connected to the third node, the second power supply terminal and the second output terminal respectively, and is used to control whether the second power supply signal is output as the second gate drive signal according to the potential of the third node.

[0049] The fourth output unit is connected to the fourth node, the first power supply terminal, and the second output terminal, respectively, and is used to control whether the first power supply signal is output as the second gate drive signal according to the potential of the fourth node.

[0050] Preferably, the third output unit includes: a fifteenth transistor and a fourth capacitor, the fifteenth transistor being connected between the second power supply terminal and the second output terminal, the gate of the fifteenth transistor being connected to the third node, and the fourth capacitor being connected between the gate of the fifteenth transistor and the first terminal;

[0051] The fourth output unit includes a sixteenth transistor connected between the first power supply terminal and the second output terminal, wherein the gate of the sixteenth transistor is connected to the fourth node.

[0052] Optionally, the gate driving circuit further includes: a potential control module, wherein the control terminal of the potential control module is connected to the fourth node, the first terminal of the potential control module is connected to a potential control signal, and the second terminal of the potential control module is connected to the first node or the second node; the potential control module is used to control whether the potential control signal is transmitted to the second terminal of the potential control module according to the potential of the fourth node;

[0053] Preferably, the potential control module includes: a seventeenth transistor connected between the first terminal and the second terminal of the potential control module, wherein the gate of the seventeenth transistor is connected to the control terminal of the potential control module;

[0054] Preferably, the first clock signal or the first gate input signal is multiplexed as the potential control signal.

[0055] In a second aspect, embodiments of the present invention also provide a display device, comprising: multiple levels of gate driving circuits as provided in any embodiment of the present invention; wherein a first gate driving signal output by the current level gate driving circuit serves as a first gate input signal connected to the next level gate driving circuit, and a second gate driving signal output by the current level gate driving circuit serves as a second gate input signal connected to the next level gate driving circuit.

[0056] Preferably, the display device further includes: a driver chip, used to transmit a first-stage first gate input signal and a first-stage second gate input signal to a first-stage gate driving circuit;

[0057] Preferably, the driver chip adjusts the pulse frequency of each of the first gate drive signals output by each of the gate drive circuits by adjusting the pulse frequency of the first gate input signal of the first stage;

[0058] The driver chip adjusts the pulse frequency of each second gate drive signal output by each gate drive circuit by adjusting the pulse frequency of the first-stage second gate input signal;

[0059] The driver chip adjusts the pulse width of each second gate drive signal output by each gate drive circuit by adjusting the pulse width of the first-stage second gate input signal.

[0060] In the gate driving circuit provided by this invention, by setting a first control module, a first output module, a second control module, a coupling module, a reset module, and a second output module, a single gate driving circuit can output two types of gate driving signals with different pulse widths and different effective voltage levels, thus meeting the driving requirements of various functional transistors in the pixel circuit. Therefore, by arranging one set of this gate driving circuit in the display panel and reasonably setting the connection relationship between each gate driving circuit and the transistors in the pixel circuit, the number of gate driving circuits required to drive the pixel circuit can be effectively reduced, which is beneficial for achieving a narrow bezel. Furthermore, in this gate driving circuit, the first control module is used to control both the first output module and the reset module. By multiplexing the second node in the output process of the two types of gate driving signals, the structure of the gate driving circuit can be simplified, further reducing the required circuit layout space. Therefore, compared with the prior art, this invention is advantageous for achieving a narrow bezel design for the display panel.

[0061] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0062] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0063] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0064] Figure 2 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0065] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0066] Figure 4 This is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention;

[0067] Figure 5 This is a schematic diagram of the driving timing of another gate driving circuit provided in an embodiment of the present invention;

[0068] Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0069] Figure 7 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0070] Figure 8 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0071] Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0072] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0073] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0074] This invention provides a gate driving circuit that can simultaneously output a gate driving signal with a high-potential pulse and a gate driving signal with a low-potential pulse, so as to meet the driving requirements of the pixel circuit by setting fewer sets of gate driving circuits, which is beneficial to reduce the screen bezel and power consumption of the display device. Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention. See also... Figure 1 The gate drive circuit includes: a first control module 10, a first output module 20, a second control module 30, a coupling module 40, a reset module 50, and a second output module 60.

[0075] The first control module 10 includes a first node N1 and a second node N2. The first control module 10 controls the potentials of the first node N1 and the second node N2 according to the first gate input signal GIN1. The first output module 20 is connected to the first node N1 and the second node N2 respectively, and outputs a first gate drive signal GOUT1 according to the potentials of the first node N1 and the second node N2. The second control module 30 includes a third node N3 and a fourth node N4. The second control module 30 controls the potentials of the third node N3 and the fourth node N4 according to the second gate input signal GIN2. The coupling module 40 is connected to a coupling node N5, and the coupling module 40 couples and controls the potential of the fourth node N4 according to the potential of the coupling node N5. The reset module 50 is connected to the coupling node N5, and the reset module 50 resets the coupling node N5 according to the potential of the second node N2. The second output module 60 is connected to the third node N3 and the fourth node N4 respectively, and outputs a second gate drive signal GOUT2 according to the potentials of the third node N3 and the fourth node N4.

[0076] For example, based on the control of the potentials of the first node N1 and the second node N2 by the first control module 10, the pulse of the first gate input signal GIN1 can be shifted and output to obtain the first gate drive signal GOUT1 in conjunction with the first output module 20. Based on the control of the potentials of the third node N3 and the fourth node N4 by the second control module 30, and the coupling control of the potential of the fourth node N4 by the coupling module 40, the pulse of the second gate input signal GIN2 can be shifted and output to obtain the second gate drive signal GOUT2 in conjunction with the second output module 60. Based on the control of the potential of the second node N2 by the first control module 10, the potential of the coupling node N5 in the coupling module 40 can be reset in a timely manner in conjunction with the reset module 50, so as to ensure that the coupling module 50 can work normally in each display frame and ensure circuit reliability. It is understood that the pulse of the first gate drive signal GOUT1 refers to the pulse of the effective level of the first gate drive signal GOUT1, and the pulse of the second gate drive signal GOUT2 refers to the pulse of the effective level of the second gate drive signal GOUT2; the content referred to by the pulse of the gate drive signal below is similar and will not be explained again.

[0077] In this design, the effective level of the first gate drive signal GOUT1 differs from the effective level of the second gate drive signal GOUT2, and the pulse width of the effective level of the second gate drive signal GOUT2 covers the pulse width of the effective level of the first gate drive signal GOUT1. For example, the first gate drive signal GOUT1 can be used as a scan signal to control the data writing process and / or initialization process of the pixel circuit; the effective level of the first gate drive signal GOUT1, for example, has a potential that controls the transistor connected to the first gate drive signal GOUT1 in the pixel circuit to turn on, and the pulse of the first gate drive signal GOUT1 is, for example, a turn-on pulse. The second gate drive signal GOUT2 can be used as a light emission control signal to control the light emission process of the pixel circuit; the effective level of the second gate drive signal GOUT2, for example, has a potential that controls the transistor connected to the second gate drive signal GOUT2 in the pixel circuit to turn off, and the pulse of the second gate drive signal GOUT2 is, for example, a cutoff pulse. For example, if all transistors in the pixel circuit are P-type transistors, then the effective level of the first gate drive signal GOUT1 is a low potential, and the effective level of the second gate drive signal GOUT2 is a high potential.

[0078] In practical applications, multiple gate drive circuits can be set in the display panel. The overlap of the pulses of the first gate drive signal GOUT1 and the second gate drive signal GOUT2 output from the same gate drive circuit can be configured as needed, and the connection relationship between each level of the gate drive circuit and the pixel circuit can be set accordingly. For example, during the pixel circuit driving process, it is required that the turn-on pulses of each scan signal are within the cut-off pulse of the light emission control signal. Therefore, the pulse of the first gate drive signal GOUT1 output from the same gate drive circuit can be set to be within the pulse of the second gate drive signal GOUT2, so that the two gate drive signals output from the same gate drive circuit can act on the same pixel circuit. Furthermore, the pulse width of the second gate drive signal GOUT2 can be set according to actual needs. For example, it can be set so that at least the pulses of the first gate drive signal GOUT1 output by the current stage and the next stage gate drive circuit are within the pulse of the second gate drive signal GOUT2 output by the current stage gate drive circuit. Then, for the same row of pixel circuits, taking a 7T1C architecture pixel circuit as an example, the current stage first gate drive signal GOUT1 can act on the gate initialization transistor in the pixel circuit, the next stage first gate drive signal GOUT1 can act on the data write transistor and threshold compensation transistor in the pixel circuit, either the current stage first gate drive signal GOUT1 or the next stage first gate drive signal GOUT1 can act on the anode reset transistor in the pixel circuit, and the current stage second gate drive signal GOUT2 can act on the two light-emitting control transistors in the pixel circuit. Therefore, only one set of cascaded gate drive circuits is needed in the display panel to meet the driving requirements of the pixel circuit, which is beneficial for achieving narrow bezels. Moreover, the reduced number of gate drive circuits also helps to reduce screen power consumption.

[0079] In the gate driving circuit provided by this embodiment of the invention, by setting a first control module 10, a first output module 20, a second control module 30, a coupling module 40, a reset module 50, and a second output module 60, a single gate driving circuit can output two types of gate driving signals with different pulse widths and different effective voltage levels, thus meeting the driving requirements of various functional transistors in the pixel circuit. Therefore, by arranging one set of this gate driving circuit in the display panel and reasonably setting the connection relationship between each gate driving circuit and the transistors in the pixel circuit, the number of gate driving circuits required to drive the pixel circuit can be effectively reduced, which is beneficial for achieving a narrow bezel. Furthermore, in this gate driving circuit, the first control module 10 is used to control both the first output module 20 and the reset module 50. By multiplexing the second node N2 in the output process of the two types of gate driving signals, the structure of the gate driving circuit can be simplified, further reducing the required layout space. Therefore, compared with the prior art, this embodiment of the invention is advantageous for achieving a narrow bezel design for the display panel.

[0080] Figure 2 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. See also... Figure 2 Based on the above embodiments, optionally, to realize the driving function of the gate driving circuit, the gate driving circuit may specifically be provided with the following external ports: a first clock terminal, connected to a first clock signal SCK1; a second clock terminal, connected to a second clock signal SCK2; a first input terminal, connected to a first gate input signal GIN1; a second input terminal, connected to a second gate input signal GIN2; a first power supply terminal, connected to a first power supply signal VGL; a second power supply terminal, connected to a second power supply signal VGH; a first output terminal, outputting a first gate driving signal GOUT1; and a second output terminal, outputting a second gate driving signal GOUT2.

[0081] The first control module 10 is connected to the first input terminal, the first clock terminal, and the first power supply terminal, respectively, and is used to control the potentials of the first node N1 and the second node N2 according to the first clock signal SCK1, the first power supply signal VGL, and the first gate input signal GIN1. The first output module 20 is connected to the first node N1, the second node N2, the second power supply terminal, the second clock terminal, and the first output terminal, respectively, and is used to control the potential of the first gate drive signal GOUT1 according to the second power supply signal VGH, the second clock signal SCK2, and the potentials of the first node N1 and the second node N2. The second control module is connected to the second input terminal, the first clock terminal, the second clock terminal, the first power supply terminal, and the second power supply terminal, respectively, and is used to control the potentials of the third node N3 and the fourth node N4 according to the second gate input signal GIN2, the first clock signal SCK1, the second clock signal SCK2, the first power supply signal VGL, and the second power supply signal VGH. The coupling module 40 is connected to coupling node N5, fourth node N4, and the second clock terminal, respectively. It controls the potential of coupling node N5 based on the potential of fourth node N4 and the second clock signal SCK2, and couples the potential transition of coupling node N5 to fourth node N4. The reset module is connected to second node N2, coupling node N5, and the second power supply terminal, respectively. It responds to the potential of second node N2 by resetting coupling node N5 using the second power supply signal VGH. The second output module is connected to third node N3, fourth node N4, the first power supply terminal, the second power supply terminal, and the second output terminal, respectively. It controls the potential of the second gate drive signal GOUT2 based on the first power supply signal VGL, the second power supply signal VGH, and the potentials of third node N3 and fourth node N4.

[0082] In this system, both the first power supply signal VGL and the second power supply signal VGH can be DC voltage signals. The potentials of the first power supply signal VGL and the second power supply signal VGH are different; for example, the first power supply signal VGL is at a low potential, and the second power supply signal VGH is at a high potential. Both the first clock signal SCK1 and the second clock signal SCK2 are clock signals that alternate between high and low potentials. The first clock signal SCK1 and the second clock signal SCK2 can have the same frequency but opposite phases. The high potential of the aforementioned clock signals can be equal to the potential of the second power supply signal VGH, and the low potential of the aforementioned clock signals can be equal to the potential of the first power supply signal VGL.

[0083] The following describes the possible structures of each functional module in the gate drive circuit, but this is not intended to limit the invention.

[0084] See Figure 2 In one embodiment, optionally, the first control module 10 includes: a first input unit 11, a first potential control unit 12, and a second potential control unit 13. The first input unit 11 is connected to a first input terminal, a first clock terminal, and a second node N2, and is used to control whether a first gate input signal GIN1 is transmitted to the second node N2 according to a first clock signal SCK1; when the first input unit 11 is turned on in response to the first clock signal SCK1, it transmits the first gate input signal GIN1 to the second node N2. The first potential control unit 12 is connected to a first clock terminal, a first power supply terminal, and the first node N1, and is used to control whether a first power supply signal VGL is transmitted to the first node N1 according to the first clock signal SCK1; when the first potential control unit 12 is turned on in response to the first clock signal SCK1, it transmits the first power supply signal VGL to the first node N1. The second potential control unit 13 is connected to the first node N1, the second node N2 and the first clock terminal respectively, and is used to control whether the first clock signal SCK1 is transmitted to the first node N1 according to the potential of the second node N2; when the potential of the second node N2 is turned on, the second potential control unit 13 transmits the first clock signal SCK1 to the first node N1.

[0085] See Figure 2In one embodiment, optionally, the first output module 20 includes: a first output unit 21 and a second output unit 22. The first output unit 21 is connected to a first node N1, a second power supply terminal, and a first output terminal, respectively, and is used to control whether a second power supply signal VGH is output as a first gate drive signal GOUT1 based on the potential of the first node N1; when the potential of the first node N1 is turned on, the first output unit 21 outputs the second power supply signal VGH as the first gate drive signal GOUT1. The second output unit 22 is connected to a second node N2, a second clock terminal, and a first output terminal, respectively, and is used to control whether a second clock signal SCK2 is output as the first gate drive signal GOUT1 based on the potential of the second node N2; when the potential of the second node N2 is turned on, the second output unit 22 outputs the second clock signal SCK2 as the first gate drive signal GOUT1.

[0086] See Figure 2 In one embodiment, optionally, the second control module 30 includes: a second input unit 31, a third potential control unit 32, and a fourth potential control unit 33. The second input unit 31 is connected to a second input terminal, a first clock terminal, and a fourth node N4, and is used to control whether the second gate input signal GIN2 is transmitted to the fourth node N4 according to the first clock signal SCK1; when the second input unit 31 responds to the first clock signal SCK1 being turned on, it transmits the second gate input signal GIN2 to the fourth node N4. The third potential control unit 32 is connected to a first power supply terminal, a second input terminal, a second clock terminal, and a third node N3, and is used to control whether the first power supply signal VGL is transmitted to the third node N3 according to the second gate input signal GIN2 and the second clock signal SCK2; when the third potential control unit 32 responds to the second gate input signal GIN2 and the second clock signal SCK2 being turned on, it transmits the first power supply signal VGL to the third node N3. The fourth potential control unit 33 is connected to the third node N3, the fourth node N4 and the second power supply terminal respectively, and is used to control whether the second power supply signal VGH is transmitted to the third node N3 according to the potential of the fourth node N4; when the potential of the fourth node N4 is turned on, the fourth potential control unit 33 transmits the second power supply signal VGH to the third node N3.

[0087] See Figure 2In one embodiment, the coupling module 40 optionally includes a transmission unit 41 and a coupling unit 42. The transmission unit 41 is connected to the fourth node N4, the second clock terminal, and the coupling node N5, respectively, and is used to control whether the second clock signal SCK2 is transmitted to the coupling node N5 according to the potential of the fourth node N4; when the potential of the fourth node N4 is turned on, the transmission unit 41 transmits the second clock signal SCK2 to the coupling node N5. The coupling unit 42 is connected to the coupling node N5 and the fourth node N4, respectively, and is used to couple the potential transition of the coupling node N5 to the fourth node N4.

[0088] See Figure 2 In one embodiment, optionally, the reset module 50 is used to control whether the second power signal VGH is transmitted to the coupling node N5 according to the potential of the second node N2; when the potential of the second node N2 is turned on, the reset module 50 transmits the second power signal VGH to the coupling node N5 to reset the coupling node N5.

[0089] See Figure 2 In one embodiment, optionally, the second output module 60 includes a third output unit 61 and a fourth output unit 62. The third output unit 61 is connected to a third node N3, a second power supply terminal, and a second output terminal, respectively, and is used to control whether the second power supply signal VGH is output as the second gate drive signal GOUT2 based on the potential of the third node N3; when the potential of the third node N3 is turned on, the third output unit 61 outputs the second power supply signal VGH as the second gate drive signal GOUT2. The fourth output unit 62 is connected to a fourth node N4, a first power supply terminal, and a second output terminal, respectively, and is used to control whether the first power supply signal VGL is output as the second gate drive signal GOUT2 based on the potential of the fourth node N4; when the potential of the fourth node N4 is turned on, the fourth output unit 62 outputs the first power supply signal VGL as the second gate drive signal GOUT2.

[0090] In summary, the gate driving circuit provided in this embodiment of the invention requires only four control signals besides the power supply signal: a first clock signal SCK1, a second clock signal SCK2, a first gate input signal GIN1, and a second gate input signal GIN2. Firstly, the required signals are relatively few, which is beneficial for achieving narrow bezels and low power consumption requirements. Secondly, the output process of the two gate driving signals is controlled by the same clock signal, which can automatically synchronize the first gate driving signal GOUT1 and the second gate driving signal GOUT2 without requiring additional adjustments to the clock signals corresponding to different types of gate driving circuits for synchronization considerations. This simplifies the control logic and improves driving reliability.

[0091] Figure 3This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. See also... Figure 3 Specifically, in the first control module 10: the first input unit 11 includes a first transistor M1, the gate of which is connected to a first clock terminal, the first electrode of which is connected to the first input terminal, and the second electrode of which is connected to the second node N2. The first potential control unit 12 includes a second transistor M2, connected between the first power supply terminal and the first node N1, with its gate connected to the first clock terminal. The second potential control unit 13 includes a third transistor M3, connected between the first clock terminal and the first node N1, with its gate connected to the second node N2. Each functional unit in the first control module 10 uses a single transistor, making the structure of the first control module 10 simple and easy to implement.

[0092] In the first output module 20: the first output unit 21 includes a sixth transistor M6 and a first capacitor C1. The sixth transistor M6 is connected between the second power supply terminal and the first output terminal. The gate of the sixth transistor M6 is connected to the first node N1. The first capacitor C1 is connected between the gate and the first terminal of the sixth transistor M6. The second output unit 22 includes a seventh transistor M7 and a second capacitor C2. The seventh transistor M7 is connected between the second clock terminal and the first output terminal. The gate of the seventh transistor M7 is connected to the second node N2. The second capacitor C2 is connected between the gate and the second terminal of the seventh transistor M7. Each functional unit in the first output module 20 uses one transistor and one capacitor, making the structure of the first output module 20 simple and easy to implement.

[0093] In the second control module 30: the second input unit 31 includes an eighth transistor M8, the gate of which is connected to the first clock terminal, the first terminal of which is connected to the second input terminal, and the second terminal of which is connected to the fourth node N4. The third potential control unit 32 includes a ninth transistor M9 and a tenth transistor M10, which are connected in series between the first power supply terminal and the third node N3. The gate of the ninth transistor M9 is connected to the second input terminal, and the gate of the tenth transistor M10 is connected to the second clock terminal; for example, the first terminal of the ninth transistor M9 is connected to the first power supply terminal, the second terminal of the ninth transistor M9 is connected to the first terminal of the tenth transistor M10, and the second terminal of the tenth transistor M10 is connected to the third node N3. The ninth transistor M9 and the tenth transistor M10 have different channel types; for example, the ninth transistor M9 is an N-type transistor, and the tenth transistor M10 is a P-type transistor. The fourth potential control unit 33 includes an eleventh transistor M11, which is connected between the second power supply terminal and the third node N3, and the gate of the eleventh transistor M11 is connected to the fourth node N4. Each functional unit in the second control module 30 uses one or two transistors, making the structure of the second control module 30 simple and easy to implement.

[0094] The reset module 50 includes a thirteenth transistor M13, connected between the second power supply terminal and the coupling node N5, with the gate of the thirteenth transistor M13 connected to the second node N2. The reset module 50 has a simple structure and is easy to implement.

[0095] In coupling module 40: transmission unit 41 includes a fourteenth transistor M14, connected between the second clock terminal and coupling node N5, with the gate of the fourteenth transistor M14 connected to the fourth node N4. Coupling unit 42 includes a third capacitor C3, connected between coupling node N5 and the fourth node N4. Each functional unit in coupling module 40 uses a single component, making the structure of coupling module 40 simple and easy to implement.

[0096] In the second output module 60: the third output unit 61 includes a fifteenth transistor M15 and a fourth capacitor C4. The fifteenth transistor M15 is connected between the second power supply terminal and the second output terminal. The gate of the fifteenth transistor M15 is connected to the third node N3. The fourth capacitor C4 is connected between the gate of the fifteenth transistor M15 and the first terminal. The fourth output unit 62 includes a sixteenth transistor M16, which is connected between the first power supply terminal and the second output terminal. The gate of the sixteenth transistor M16 is connected to the fourth node N4. Each functional unit in the second output module 60 uses one or two components, making the structure of the second output module 60 simple and easy to implement.

[0097] Figure 4This is a schematic diagram of the driving timing of a gate driving circuit provided in an embodiment of the present invention. The following is in conjunction with... Figure 3 and Figure 4 The driving process of this gate driving circuit is described in detail below. For example, the low potential of each gate input signal and each clock signal is equal to the potential of the first power supply signal VGL, and the high potential of each gate input signal and each clock signal is equal to the potential of the second power supply signal VGH; all transistors in the gate driving circuit are transistors with identical characteristics, and the threshold voltage of any transistor can be denoted as Vth. The driving process of this gate driving circuit includes:

[0098] In the first stage T1, the first gate input signal GIN1 and the first clock signal SCK1 are at low potentials, while the second gate input signal GIN2 and the second clock signal SCK2 are at high potentials. The first transistor M1 is turned on, transmitting the low potential of the first gate input signal GIN1 through it, making the potential of the second node N2 VGL-Vth. The second transistor M2 and the third transistor M3 are both turned on, transmitting the low potential of the first power supply signal VGL through the second transistor M2, and the low potential of the first clock signal SCK1 through the third transistor M3, making the potential of the first node N1 VGL-Vth. Therefore, the sixth transistor M6 and the seventh transistor M7 are both turned on, transmitting the high potential of the second power supply signal VGH through the sixth transistor M6, and the high potential of the second clock signal SCK2 through the seventh transistor M7, making the potential of the first gate drive signal GOUT1 VGH. The thirteenth transistor M13 is turned on, transmitting the second power supply signal VGH through it, resetting the coupled node N5. When the eighth transistor M8 is turned on, the high potential of the second gate input signal GIN2 is transmitted through the eighth transistor M8, making the potential of the fourth node N4 VGH, which in turn turns off the fourteenth transistor M14, the eleventh transistor M11, and the sixteenth transistor M16; at this time, the potentials across the third capacitor C3 are the same. The ninth transistor M9 is turned on, but the tenth transistor M10 is turned off, so the first power supply signal VGL cannot be transmitted to the third node N3; due to the storage function of the fourth capacitor C4, the third node N3 maintains its potential, the fifteenth transistor M15 is also turned off, and the second gate drive signal GOUT2 maintains a low potential. Therefore, in this stage, the first gate drive signal GOUT1 is at a high potential, and the second gate drive signal GOUT2 is at a low potential.

[0099] In the second stage T2, the first gate input signal GIN1, the first clock signal SCK1, and the second gate input signal GIN2 are at high potentials, while the second clock signal SCK2 is at a low potential. Both the first transistor M1 and the second transistor M2 are turned off. The potential of the second node N2 still controls the seventh transistor M7 to conduct. At this time, the low potential of the second clock signal SCK2 is transmitted through the seventh transistor M7, and the first gate drive signal GOUT1 changes to a low potential. This potential change, coupled by the second capacitor C2, further pulls down the potential of the second node N2, allowing the seventh transistor M7 to fully conduct, so that the potential of the first gate drive signal GOUT1 reaches VGL. At this time, the potential of the second node N2 is approximately equal to VGL-Vth+(VGL-VGH)*((Cgs1+1) / (Cgs1+C2+Cother)), where Cgs1 is the parasitic capacitance between the gate and the first and second terminals of the seventh transistor M7, and Cother is other parasitic capacitance related to the second node N2. The third transistor M3 is turned on, and the high potential of the first clock signal SCK1 is transmitted through the third transistor M3, making the potential of the first node N1 VGH, which in turn controls the sixth transistor M6 to turn off. The thirteenth transistor M13 is turned on, transmitting the high potential of the second power supply signal VGH to the coupling node N5. The eighth transistor M8 is turned off, and the fourth control terminal N4 maintains the high potential of the previous stage, controlling the fourteenth transistor M14, the eleventh transistor M11, and the sixteenth transistor M16 to all turn off. The ninth transistor M9 and the tenth transistor M10 are both turned on, and the low potential of the first power supply signal VGL is transmitted through the ninth transistor M9 and the tenth transistor M10, making the potential of the third node N3 VGL-Vth; the fifteenth transistor M15 is turned on, and the high potential of the second power supply signal VGH is transmitted through the fifteenth transistor M15, making the potential of the second gate drive signal GOUT2 VGH. Therefore, in this stage, the first gate drive signal GOUT1 is at a low potential, and the second gate drive signal GOUT2 is at a high potential.

[0100] In the third stage (T3), the first gate input signal GIN1, the second clock signal SCK2, and the second gate input signal GIN2 are at high potentials, while the first clock signal SCK1 is at a low potential. The first transistor M1 is turned on, transmitting the high potential of the first gate input signal GIN1, making the potential of the second node N2 VGH; the third transistor M3, the thirteenth transistor M13, and the seventh transistor M7 are all turned off. The second transistor M2 is turned on, transmitting the low potential of the first power supply signal VGL, making the potential of the first node N1 VGL-Vth; the sixth transistor M6 is turned on, transmitting the high potential of the second power supply signal VGH, making the potential of the first gate drive signal GOUT1 VGH. The eighth transistor M8 is turned on, transmitting the high potential of the second gate input signal GIN2, making the potential of the fourth node N4 VGH, thereby turning off the fourteenth transistor M14, the eleventh transistor M11, and the sixteenth transistor M16. The ninth transistor M9 is turned on, but the tenth transistor M10 is turned off, preventing the first power supply signal VGL from being transmitted to the third node N3. Due to the storage effect of the fourth capacitor C4, the third node N3 maintains the low potential of the previous stage. The fifteenth transistor M15 is turned on, and the high potential of the second power supply signal VGH is transmitted through the fifteenth transistor M15, making the potential of the second gate drive signal GOUT2 VGH. Therefore, in this stage, the first gate drive signal GOUT1 is at a high potential, and the second gate drive signal GOUT2 is at a high potential.

[0101] In stage T4, the first gate input signal GIN1 and the first clock signal SCK1 are at high potentials, while the second clock signal SCK2 is at a low potential. The second gate input signal GIN2 transitions from high to low potential during stage T4. The first transistor M1 and the second transistor M2 are both turned off. The second node N2 maintains the high potential from the previous stage, controlling the third transistor M3, the thirteenth transistor M13, and the seventh transistor M7 to turn off. Due to the storage effect of the first capacitor C1, the first node N1 maintains the low potential from the previous stage, controlling the sixth transistor M6 to turn on. The high potential of the second power supply signal VGH is transmitted through the sixth transistor M6, making the potential of the first gate drive signal GOUT1 VGH. The eighth transistor M8 is turned off, and the potential transition of the second gate input signal GIN2 is not transmitted to the fourth control terminal N4. Therefore, in this stage, the fourth control terminal N4 maintains the high potential from the previous stage, controlling the fourteenth transistor M14, the eleventh transistor M11, and the sixteenth transistor M16 to turn off. When the second gate input signal GIN2 is at a high potential, both the ninth transistor M9 and the tenth transistor M10 are turned on. The low potential of the first power supply signal VGL is transmitted through the ninth transistor M9 and the tenth transistor M10, making the potential of the third node N3 VGL-Vth. When the second gate input signal GIN2 is at a low potential, the ninth transistor M9 is turned off, blocking the transmission of the first power supply signal VGL, and the third node N3 maintains its potential. Therefore, in this fourth stage T4, the fifteenth transistor M15 is turned on, and the high potential of the second power supply signal VGH is transmitted through the fifteenth transistor M15, making the potential of the second gate drive signal GOUT2 VGH. Therefore, in this stage, the first gate drive signal GOUT1 is at a high potential, and the second gate drive signal GOUT2 is at a high potential.

[0102] In stage T5, the first gate input signal GIN1 and the second clock signal SCK2 are at high potentials, while the second gate input signal GIN2 and the first clock signal SCK1 are at low potentials. The operating states of the first transistor M1, the second transistor M2, the third transistor M3, the thirteenth transistor M13, the sixth transistor M6, and the seventh transistor M7 can be found in the description of stage T3. The potential of the first gate drive signal GOUT1 is VGH. The ninth transistor M9 and the tenth transistor M10 are both turned off. The eighth transistor M8 is turned on, and the low potential of the second gate input signal GIN2 is transmitted through the eighth transistor M8, making the potential of the fourth node N4 VGL-Vth; thus, the fourteenth transistor M14, the eleventh transistor M11, and the sixteenth transistor M16 are all turned on; the high potential of the second clock signal SCK2 is transmitted through the fourteenth transistor M14, making the potential of the coupling node N5 VGH. At this time, no potential jump occurs at the coupling node N5, and the potential difference across the capacitor C3 at the third point is the potential difference between the coupling node N5 and the fourth node N4; the second power supply signal VGH is transmitted through the eleventh transistor M11, making the potential of the third node N3 VGH, thereby controlling the fifteenth transistor M15 to turn off; the first power supply signal VGL is transmitted through the sixteenth transistor M16, making the potential of the second gate drive signal GOUT2 lower, but due to the transmission loss of the sixteenth transistor M16, the potential of the second gate drive signal GOUT2 does not reach VGL during this stage. Therefore, during this stage, the first gate drive signal GOUT1 is at a high potential, and the potential of the second gate drive signal GOUT2 begins to decrease.

[0103] In stage T6, the first gate input signal GIN1 and the first clock signal SCK1 are at high potentials, while the second gate input signal GIN2 and the second clock signal SCK2 are at low potentials. The operating states of the first transistor M1, second transistor M2, third transistor M3, thirteenth transistor M13, sixth transistor M6, and seventh transistor M7 can be found in the description of stage T4. The potential of the first gate drive signal GOUT1 is VGH. The eighth transistor M8 is turned off, and the potential of the fourth node N4 still controls the fourteenth transistor M14, eleventh transistor M11, and sixteenth transistor M16 to turn on. The low potential of the second clock signal SCK2 is transmitted through the fourteenth transistor M14, causing the potential of the coupling node N5 to drop to VGL-Vth. This potential change, coupled by the third capacitor C3, further pulls down the potential of the fourth node N4, allowing the sixteenth transistor M16 to fully turn on, and causing the potential of the second gate drive signal GOUT2 to reach VGL. Therefore, in this stage, the first gate drive signal GOUT1 is at a high potential, and the second gate drive signal GOUT2 is at a low potential.

[0104] Based on the above analysis, it can be seen that in stages T1 to T6, the low potential of the first gate drive signal GOUT1 and the high potential of the second gate drive signal GOUT2 both originate in stage T2, and the low potential phase of the first gate drive signal GOUT1 is within the high potential phase of the second gate drive signal GOUT2. In subsequent stages, the on / off states of each transistor repeat in stages T5 and T6, with the first gate drive signal GOUT1 maintaining (or outputting) a high potential, and the second gate drive signal GOUT2 maintaining (or outputting) a low potential. This continues until the potentials of the first gate input signal GIN1 and the second gate input signal GIN2 change again.

[0105] It should be noted that the above Figure 4 The document describes the driving process when a pulse (here, a low-potential pulse) is provided in the first gate input signal GIN1 and a pulse (here, a high-potential pulse) is also provided in the second gate input signal GIN2, but this is not intended to limit the invention. In other embodiments, optionally, when the first gate input signal GIN1 does not contain a pulse, the components related to the potentials of the first node N1 and the second node N2 (e.g., the first transistor M1, the second transistor M2, the third transistor M3, the thirteenth transistor M13, the sixth transistor M6, and the seventh transistor M7) maintain a long output state after the sixth stage T6, so that the first gate drive signal GOUT1 also does not contain a pulse. When the second gate input signal GIN2 does not contain a pulse, the components related to the potentials of the third node N3 and the fourth node N4 (e.g., the eighth transistor M8, the ninth transistor M9, the tenth transistor M10, the eleventh transistor M11, the fifteenth transistor M15, and the sixteenth transistor M16) maintain a long output state after the sixth stage T6, so that the second gate drive signal GOUT2 also does not contain a pulse. Therefore, since the pulse frequencies of the two gate drive signals are controlled relatively independently based on the pulse frequencies of the two gate input signals, complex display requirements with different refresh rates can be achieved by reasonably configuring the pulse frequencies of the first gate input signal GIN1 and the second gate input signal GIN2. For example... Figure 5 As shown, the pulse frequency of the first gate input signal GIN1 can be set lower than the pulse frequency of the second gate input signal GIN2 to achieve low-frequency display based on the pulse frequency of the first gate input signal GIN1. For example, the first gate drive signal GOUT1 is a scan signal controlling the data writing process, and the second gate drive signal GOUT2 is a light emission control signal, such as... Figure 2 The first type of display frame F1 is equivalent to the refresh frame of the pixel circuit. When the pulse of the second gate drive signal GOUT2 controls the light-emitting control transistor to turn off, the pulse of the first gate drive signal GOUT1 controls the pixel circuit to write data, thereby achieving data refresh; as shown... Figure 2 The second type of display frame F2 is equivalent to the holding frame of the pixel circuit. When the pulse of the second gate drive signal GOUT2 controls the light-emitting control transistor to turn off, the first gate drive signal GOUT1 has no pulse. At this time, the pixel circuit does not perform data refresh, which is equivalent to providing a black insertion stage based on the pulse of the second gate drive signal GOUT2.

[0106] It should also be noted that the pulse width of the second gate drive signal GOUT2 can be adjusted by regulating the pulse width of the second gate input signal GIN2. For example, extending the pulse width of GOUT2 can achieve the same effect. Figure 4 The pulse width of the second gate input signal GIN2 is increased so that it covers more clock cycles of the clock signal. This allows the third stage T3 and the fourth stage T4 to be repeated multiple times during the driving process of the gate drive circuit, thereby increasing the pulse width of the second gate drive signal GOUT2 accordingly.

[0107] Figure 6 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. See also... Figure 6 Based on the above embodiments, optionally, the first control module 10 further includes: a fourth transistor M4, connected between the second terminal of the first transistor M1 and the second node N2, the gate of the fourth transistor M4 being connected to the first power supply terminal, and the fourth transistor M4 being in a normally conducting state under the control of the first power supply signal VGL. The second terminal of the first transistor M1 is designated as node N6. By setting the fourth transistor M4, the extremely low potential generated by the coupling effect of the second node N2 under the second capacitor C2 can be prevented from being transmitted to node N6, thereby avoiding the impact of this extremely low potential on the transistors connected to node N6. For example, the gate of the third transistor M3 can be connected to node N6 to protect the third transistor M3.

[0108] Similarly, see Figure 7 The first control module 10 may also include a fifth transistor M5, the gate of which is connected to the first power supply terminal, the first terminal of which is connected to the second node N2, and the second terminal of which is connected to the reset module 50, for example, to the gate of the thirteenth transistor M13, so as to protect the thirteenth transistor M13.

[0109] Similarly, see Figure 6 and Figure 7Furthermore, the second control module 30 can also include a twelfth transistor M12 connected between the second terminal of the eighth transistor M8 and the fourth node N4, with its gate connected to the first power supply terminal. The second terminal of the eighth transistor M8 is designated as node N7. By configuring the twelfth transistor M12, protection can be achieved for all transistors connected to node N7. Additionally, the gate of the eleventh transistor M11 can be connected to node N7 to protect the eleventh transistor M11.

[0110] See also Figure 2 Based on the above embodiments, optionally, the gate driving circuit further includes: a potential control module 70, the control terminal of the potential control module 70 is connected to the fourth node N4, the first terminal of the potential control module 70 is connected to a potential control signal S1, and the second terminal of the potential control module 70 is connected to the first node N1 or the second node N2; the potential control module 70 is used to transmit the potential control signal S1 to the second terminal of the potential control module 70 according to whether the potential control signal S1 of the fourth node N4 is transmitted; when the potential of the fourth node N4 is turned on, the potential control module 70 transmits the potential control signal S1 to the second terminal of the potential control module 70. In this embodiment, by setting the potential control module 70, the potential of the first node N1 or the second node N2 can be stabilized as much as possible, avoiding the first node N1 or the second node N2 from floating for a long time. Figure 2 For example, the second terminal of the potential control module 70 is connected to the first node N1. The first clock signal SCK1 or the first gate input signal GIN1 can be multiplexed into the potential control signal S1 to reduce the number of external ports in the gate drive circuit and the corresponding wiring in the display panel, thus simplifying the circuit structure and layout design.

[0111] Specifically, see Figure 3 The potential control module 70 may include a seventeenth transistor M17, connected between the first and second terminals of the potential control module 70, with the gate of the seventeenth transistor M17 connected to the control terminal of the potential control module 70. This potential control module 70 has a simple structure and is easy to implement.

[0112] In one implementation, alternatively, such as Figure 3 As shown, the second terminal of the potential control module 70 can be connected to the first node N1, and the first clock signal SCK1 can be multiplexed as a potential control signal. However, this is not intended to limit the invention. In other embodiments, under this connection relationship, the first terminal of the seventeenth transistor M17 can also be connected to the first gate input signal GIN1.

[0113] In another implementation, alternatively, such as Figure 8As shown, the second terminal of the potential control module 70 can be connected to the second node N2, and the first gate input signal GIN1 can be multiplexed as a potential control signal. However, this is not intended to limit the invention. In other embodiments, under this connection relationship, the first terminal of the seventeenth transistor M17 can also be connected to the first clock signal SCK1.

[0114] In summary, this invention provides a 17T4C architecture gate driving circuit where at least some nodes share voltage, enabling simultaneous output of high and low voltage pulses. This ensures normal operation of the pixel circuit within the screen and guarantees output reliability. Compared to existing technologies that require at least one 8T2C scanning circuit to provide low-potential pulses and one 13T3C light-emitting control circuit to provide high-potential pulses, this invention requires fewer transistors (e.g., TFTs), fewer capacitors, and fewer control signals, thus significantly reducing screen bezel size and power consumption. Furthermore, in this invention, the generation of the first gate driving signal GOUT1 is controlled by the first gate input signal GIN1, making the pulse frequency of the first gate driving signal GOUT1 adjustable. The generation of the second gate driving signal GOUT2 is controlled by the second gate input signal GIN2, making both the pulse width and pulse frequency of the second gate driving signal GOUT2 adjustable. For example, by adjusting the pulse width of the second gate input signal GIN2, the high-potential output time of the second gate driving signal GOUT2 can be adjusted, making it easier to adjust the screen display effect and ensure optimal illumination.

[0115] It should be noted that the first terminal of each transistor involved in the above embodiments can be called the source or drain, and the corresponding second terminal can be called the drain or source. Since the structure of the transistors in the display panel is symmetrical, the source and drain of each transistor are not distinguished.

[0116] This invention also provides a display device, including multiple levels of gate driving circuits as provided in any embodiment of this invention, which have corresponding beneficial effects. Figure 9 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. See also: Figure 9 For example, the display device includes a display panel 1, and each gate driving circuit 100 is disposed in the non-display area NAA of the display panel 1. Multiple pixel circuits (not shown in the figure) arranged in an array can be disposed in the display area AA of the display panel 1. The gate driving circuit 100 is used to provide each pixel circuit with the gate driving signal required thereto. For example, the first gate driving signal GOUT1 can be used as a scan signal and transmitted to the pixel circuit through the scan line LS, and the second gate driving signal GOUT2 can be used as a light emission control signal and transmitted to the pixel circuit through the light emission control signal line LE.

[0117] The multi-stage gate driving circuits 100 are cascaded, specifically as follows: the first output terminal of the current stage gate driving circuit 100 is connected to the first input terminal of the next stage gate driving circuit 100, and the second output terminal of the current stage gate driving circuit 100 is connected to the second input terminal of the next stage gate driving circuit 100. In other words, the first gate driving signal GOUT1 output by the current stage gate driving circuit 100 serves as the first gate input signal for the next stage gate driving circuit 100, and the second gate driving signal GOUT2 output by the current stage gate driving circuit 100 serves as the second gate input signal for the next stage gate driving circuit 100.

[0118] See also Figure 9 Based on the above embodiments, optionally, the display device also includes a driver chip 2, and the non-display area NAA of the display panel 1 is also provided with multiple signal lines. The driver chip 2 provides the required control signals to the gate drive circuit 100 through each signal line.

[0119] Specifically, the display panel 1 can be equipped with a first input signal line LIN1 and a second input signal line LIN2. The driver chip 2 can be connected to the first input terminal of the first-stage gate drive circuit 100 via the first input signal line LIN1 to transmit the first-stage first gate input signal (i.e., the first gate input signal required by the first-stage gate drive circuit 100), and connected to the second input terminal of the first-stage gate drive circuit 100 via the second input signal line LIN2 to transmit the first-stage second gate input signal (i.e., the second gate input signal required by the first-stage gate drive circuit 100).

[0120] For example, the driver chip 2 adjusts the pulse frequency of each first gate drive signal GOUT1 output by each gate drive circuit 100 by adjusting the pulse frequency of the first-stage first gate input signal, that is, adjusting the frequency of the pulses of the effective level of the first-stage first gate input signal. And / or, the driver chip 2 adjusts the pulse frequency of each second gate drive signal GOUT2 output by each gate drive circuit 100 by adjusting the pulse frequency of the first-stage second gate input signal, that is, adjusting the frequency of the pulses of the effective level of the first-stage second gate input signal. And / or, the driver chip 2 adjusts the pulse width of each second gate drive signal GOUT2 output by each gate drive circuit 100 by adjusting the pulse width of the first-stage second gate input signal, that is, adjusting the pulse width of the pulses of the effective level of the first-stage second gate input signal.

[0121] Furthermore, the display panel 1 may include: a first power signal line LVGL, connected to the first power supply terminal of each gate drive circuit 100; and a second power signal line LVGH, connected to the second power supply terminal of each gate drive circuit 100. The driver chip 2 may transmit a first power signal to the first power signal line LVGL and a second power signal to the second power signal line LVGH.

[0122] Furthermore, the display panel 1 can be equipped with a first clock signal line LCK1 and a second clock signal line LCK2. Each stage of the gate drive circuit 100 is alternately connected to the first clock signal line 74 and the second clock signal line 75. For example, the first clock terminal of the odd-numbered stage gate drive circuit 100 is connected to the first clock signal line LCK1, and the second clock terminal is connected to the second clock signal line LCK2; the first clock terminal of the even-numbered stage gate drive circuit 100 is connected to the second clock signal line LCK2, and the second clock terminal is connected to the first clock signal line LCK1.

[0123] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0124] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A gate driving circuit, characterized in that, include: A first control module includes a first node and a second node. The first control module is used to control the potential of the first node and the second node according to a first gate input signal. The first output module is connected to the first node and the second node respectively, and is used to output a first gate drive signal according to the potential of the first node and the second node; The second control module includes a third node and a fourth node, and the second control module is used to control the potential of the third node and the fourth node according to the second gate input signal; The first clock input is connected to the first clock signal; the second clock input is connected to the second clock signal. The first input terminal is connected to the first gate input signal; The second input terminal is connected to the second gate input signal; the first power supply terminal is connected to the first power supply signal. The second power supply terminal is connected to the second power supply signal; The first output terminal outputs the first gate drive signal; The second output terminal outputs the second gate drive signal; The first control module includes: The first input unit is connected to the first input terminal, the first clock terminal and the second node respectively, and is used to control whether the first gate input signal is transmitted to the second node according to the first clock signal; A first potential control unit is connected to the first clock terminal, the first power supply terminal, and the first node, respectively, and is used to control whether the first power supply signal is transmitted to the first node according to the first clock signal; a second potential control unit is connected to the first node, the second node, and the first clock terminal, respectively, and is used to control whether the first clock signal is transmitted to the first node according to the potential of the second node. The second control module includes: The second input unit is connected to the second input terminal, the first clock terminal and the fourth node respectively, and is used to control whether the second gate input signal is transmitted to the fourth node according to the first clock signal; The third potential control unit is connected to the first power supply terminal, the second input terminal, the second clock terminal and the third node respectively, and is used to control whether the first power supply signal is transmitted to the third node according to the second gate input signal and the second clock signal; The fourth potential control unit is connected to the third node, the fourth node and the second power supply terminal respectively, and is used to control whether the second power supply signal is transmitted to the third node according to the potential of the fourth node; A coupling module, connected to a coupling node, is used to couple and control the potential of the fourth node according to the potential of the coupling node; A reset module, connected to the coupling node, is used to reset the coupling node according to the potential of the second node; The second output module is connected to the third node and the fourth node respectively, and is used to output a second gate drive signal according to the potential of the third node and the fourth node; Wherein, the potential of the effective level of the first gate drive signal is different from the potential of the effective level of the second gate drive signal, and the pulse width of the effective level of the second gate drive signal covers the pulse width of the effective level of the first gate drive signal.

2. The gate driving circuit according to claim 1, characterized in that, The first output module is used to control the potential of the first gate drive signal according to the second power signal, the second clock signal, the potential of the first node and the second node; The coupling module is used to control the potential of the coupling node according to the potential of the fourth node and the second clock signal, and to couple the potential transition of the coupling node to the fourth node; The reset module is used to respond to the potential of the second node and reset the coupling node using the second power signal; The second output module is used to control the potential of the second gate drive signal based on the first power signal, the second power signal, the potential of the third node and the fourth node.

3. The gate driving circuit according to claim 2, characterized in that, The first input unit includes: a first transistor, the gate of the first transistor being connected to the first clock terminal, the first terminal of the first transistor being connected to the first input terminal, and the second terminal of the first transistor being connected to the second node; The first potential control unit includes: a second transistor connected between the first power supply terminal and the first node, wherein the gate of the second transistor is connected to the first clock terminal; The second potential control unit includes a third transistor connected between the first clock terminal and the first node, wherein the gate of the third transistor is connected to the second node.

4. The gate driving circuit according to claim 3, characterized in that, The first control module further includes: a fourth transistor connected between the second terminal of the first transistor and the second node, wherein the gate of the fourth transistor is connected to the first power supply terminal; wherein the gate of the third transistor is connected to the second terminal of the first transistor.

5. The gate driving circuit according to claim 4, characterized in that, The first control module further includes a fifth transistor, the gate of which is connected to the first power supply terminal, the first terminal of which is connected to the second node, and the second terminal of which is connected to the reset module.

6. The gate driving circuit according to claim 2, characterized in that, The first output module includes: The first output unit is connected to the first node, the second power supply terminal and the first output terminal respectively, and is used to control whether the second power supply signal is output as the first gate drive signal according to the potential of the first node. The second output unit is connected to the second node, the second clock terminal and the first output terminal respectively, and is used to control whether the second clock signal is output as the first gate drive signal according to the potential of the second node.

7. The gate driving circuit according to claim 6, characterized in that, The first output unit includes a sixth transistor and a first capacitor. The sixth transistor is connected between the second power supply terminal and the first output terminal. The gate of the sixth transistor is connected to the first node. The first capacitor is connected between the gate of the sixth transistor and the second power supply terminal. The second output unit includes a seventh transistor and a second capacitor. The seventh transistor is connected between the second clock terminal and the first output terminal. The gate of the seventh transistor is connected to the second node. The second capacitor is connected between the gate of the seventh transistor and the first output terminal.

8. The gate driving circuit according to claim 2, characterized in that, The second input unit includes: an eighth transistor, the gate of which is connected to the first clock terminal, the first terminal of which is connected to the second input terminal, and the second terminal of which is connected to the fourth node; The third potential control unit includes a ninth transistor and a tenth transistor, which are connected in series between the first power supply terminal and the third node. The gate of the ninth transistor is connected to the second input terminal, and the gate of the tenth transistor is connected to the second clock terminal. The ninth transistor and the tenth transistor have different channel types. The fourth potential control unit includes an eleventh transistor connected between the second power supply terminal and the third node, wherein the gate of the eleventh transistor is connected to the fourth node.

9. The gate driving circuit according to claim 8, characterized in that, The second control module further includes: a twelfth transistor connected between the second terminal of the eighth transistor and the fourth node, wherein the gate of the twelfth transistor is connected to the first power supply terminal; wherein the gate of the eleventh transistor is connected to the second terminal of the eighth transistor.

10. The gate driving circuit according to claim 2, characterized in that, The reset module includes a thirteenth transistor connected between the second power supply terminal and the coupling node, wherein the gate of the thirteenth transistor is connected to the second node.

11. The gate driving circuit according to claim 2, characterized in that, The coupling module includes: A transmission unit, connected to the fourth node, the second clock terminal, and the coupling node respectively, is used to control whether the second clock signal is transmitted to the coupling node according to the potential of the fourth node; A coupling unit, connecting the coupling node and the fourth node respectively, is used to couple the potential transition of the coupling node to the fourth node.

12. The gate driving circuit according to claim 11, characterized in that, The transmission unit includes: a fourteenth transistor connected between the second clock terminal and the coupling node, wherein the gate of the fourteenth transistor is connected to the fourth node; The coupling unit includes a third capacitor connected between the coupling node and the fourth node.

13. The gate driving circuit according to claim 2, characterized in that, The second output module includes: The third output unit is connected to the third node, the second power supply terminal and the second output terminal respectively, and is used to control whether the second power supply signal is output as the second gate drive signal according to the potential of the third node. The fourth output unit is connected to the fourth node, the first power supply terminal, and the second output terminal, respectively, and is used to control whether the first power supply signal is output as the second gate drive signal according to the potential of the fourth node.

14. The gate driving circuit according to claim 13, characterized in that, The third output unit includes a fifteenth transistor and a fourth capacitor. The fifteenth transistor is connected between the second power supply terminal and the second output terminal. The gate of the fifteenth transistor is connected to the third node. The fourth capacitor is connected between the gate of the fifteenth transistor and the second power supply terminal. The fourth output unit includes a sixteenth transistor connected between the first power supply terminal and the second output terminal, wherein the gate of the sixteenth transistor is connected to the fourth node.

15. The gate driving circuit according to claim 2, characterized in that, Also includes: A potential control module, wherein the control terminal of the potential control module is connected to the fourth node, the first terminal of the potential control module is connected to a potential control signal, and the second terminal of the potential control module is connected to the first node or the second node; The potential control module is used to control whether the potential control signal is transmitted to the second end of the potential control module according to the potential of the fourth node.

16. The gate driving circuit according to claim 15, characterized in that, The potential control module includes a seventeenth transistor connected between the first and second terminals of the potential control module, wherein the gate of the seventeenth transistor is connected to the control terminal of the potential control module.

17. The gate driving circuit according to claim 16, characterized in that, The first clock signal or the first gate input signal is multiplexed into the potential control signal.

18. A display device, characterized in that, include: A multi-stage gate driving circuit as described in any one of claims 1-17; wherein, the first gate driving signal output by the current stage gate driving circuit is used as the first gate input signal for the next stage gate driving circuit, and the second gate driving signal output by the current stage gate driving circuit is used as the second gate input signal for the next stage gate driving circuit.

19. The display device according to claim 18, characterized in that, The display device further includes a driver chip for transmitting a first-stage first gate input signal and a first-stage second gate input signal to a first-stage gate driving circuit.

20. The display device according to claim 19, characterized in that, The driver chip adjusts the pulse frequency of each first gate drive signal output by each gate drive circuit by adjusting the pulse frequency of the first gate input signal of the first stage. The driver chip adjusts the pulse frequency of each second gate drive signal output by each gate drive circuit by adjusting the pulse frequency of the first-stage second gate input signal; The driver chip adjusts the pulse width of each second gate drive signal output by each gate drive circuit by adjusting the pulse width of the first-stage second gate input signal.

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