Lower electrode assembly and semiconductor process apparatus

Abstract

The application belongs to the technical field of semiconductor, and particularly relates to a lower electrode assembly and a semiconductor process equipment. The lower electrode assembly comprises a wafer bearing and an edge adjusting member arranged around the edge of the wafer bearing, the edge adjusting member comprises an insulating body and a conductive body, the conductive body is arranged on the insulating body, so that the conductive body is insulated from the wafer bearing and plasma respectively, and the conductive body comprises a plurality of conductive sections, at least two conductive sections can generate electric field strengths different from each other. The application can solve the problems that the machining precision and the installation precision of the gas inlet nozzle are high, and the process time is long.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, specifically relating to a lower electrode assembly and semiconductor process equipment. Background Technology

[0002] High-density plasma chemical vapor deposition (HDPCVD) is a very important thin film deposition process in the IC manufacturing field. Its main application and most significant advantage is gap filling. How to design a reliable chamber environment to achieve reliable and pore-free gap filling becomes a crucial factor. Among them, the film uniformity index is particularly critical, which largely determines whether the final process result can meet the process requirements.

[0003] In related technologies, semiconductor process equipment includes a process chamber and air inlet nozzles located on the side of the process chamber. Due to the inherent structure of the process chamber, the airflow distribution within the chamber is uneven, resulting in uneven plasma distribution and consequently, uneven or off-center edges in the film layer formed on the wafer. Based on this, related technologies adjust the orifice diameter and length of the air inlet nozzles to achieve a uniform airflow distribution within the process chamber, thereby ensuring a uniform plasma distribution and ultimately a uniform film layer distribution on the wafer. However, this method not only requires high precision in the machining and installation of the air inlet nozzles, but also, during the determination of the nozzle's orifice diameter and length, adjusting the position of one nozzle can affect the airflow distribution of the others, making it difficult to control the airflow distribution within the process chamber. Therefore, repeated adjustments to the orifice diameter and length of the air inlet nozzles are necessary based on the process results, leading to a prolonged process time. Summary of the Invention

[0004] The purpose of this application is to provide a lower electrode assembly and semiconductor process equipment that can solve the problems of high requirements for the processing and installation accuracy of the air inlet nozzle and long process time.

[0005] To solve the above-mentioned technical problems, this application is implemented as follows:

[0006] In a first aspect, this application discloses a lower electrode assembly, including a wafer carrier and an edge adjusting member disposed around the edge of the wafer carrier. The edge adjusting member includes an insulating body and a conductor, with the conductor disposed on the insulating body to insulate the conductor from both the wafer carrier and the plasma.

[0007] A conductor consists of multiple conductive segments, and at least two conductive segments can generate different electric field intensities.

[0008] Secondly, this application discloses a semiconductor process apparatus, including a process chamber and the aforementioned lower electrode assembly, wherein the lower electrode assembly is disposed within the process chamber.

[0009] In this embodiment, the conductor is insulated from the wafer carrier to prevent conductivity between them, thus preventing conductor failure. In use, the lower electrode assembly is located within the process chamber of the semiconductor process equipment. During the process, plasma exists within the process chamber. When the power supply is connected to the conductor, power is fed to the conductor, allowing capacitive coupling between the conductor and the plasma above it. This means an electric field exists above the conductor, and the electric field and the airflow field work together to determine the plasma distribution. Therefore, this embodiment can use the electric field generated by the conductor to act on the unevenly distributed plasma caused by the airflow field, thereby achieving uniform plasma distribution and resulting in a uniform film layer distribution on the wafer. Furthermore, this embodiment has at least two conductive segments, allowing for segmented adjustment of the plasma. This method of electric field adjustment is more flexible and allows for more targeted adjustment of the electric field intensity at different locations on the wafer edge. Therefore, this embodiment does not require adjustment of the inlet nozzle's orifice diameter and length, thus reducing the requirements for the inlet nozzle's machining and installation accuracy and shortening the process time. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the structure of the semiconductor process equipment disclosed in the embodiments of this application;

[0011] Figure 2 This is a schematic diagram of the structure of the lower electrode assembly disclosed in an embodiment of this application;

[0012] Figure 3 This is a schematic diagram of the structure of the first type of conductor and feeder disclosed in the embodiments of this application;

[0013] Figure 4 This is a schematic diagram of the structure of the second type of conductor and feeder disclosed in the embodiments of this application;

[0014] Figure 5 This is a schematic diagram of the structure of the third type of conductor and feeder disclosed in the embodiments of this application;

[0015] Figure 6 This is a schematic diagram of the structure of the fourth type of conductor disclosed in the embodiments of this application;

[0016] Figure 7 This is a schematic diagram of the structure of the fifth type of conductor disclosed in the embodiments of this application.

[0017] Explanation of reference numerals in the attached figures:

[0018] 100-Process chamber, 110-Wafer carrier, 120-Insulating ring, 130-Insulating base, 140-Connecting plate, 150-Lower electrode base, 160-Support leg, 170-Cavity venting channel, 200-Edge adjustment component, 210-Conductor, 211-First section, 212-Second section, 213-Third section, 214-Fourth section, 215-Fifth section, 216-Sixth section, 220-Feeder, 230-Insulating body, 300-Adjustment component, 410-First power supply, 420-Second power supply, 430-Third power supply, 510-Intake ring, 520-Intake nozzle, 600-Intake structure, 710-First RF coil, 720-Second RF coil, 810-Insulating layer, 820-Heating layer, 830-Cooling layer, 910-First RF power supply, 920-Second RF power supply. Detailed Implementation

[0019] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0020] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such use of data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and the number of objects is not limited; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0021] The lower electrode assembly and semiconductor process equipment provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0022] like Figures 1 to 7 As shown in the illustration, this application discloses a lower electrode assembly, including a wafer carrier 110 and an edge adjustment member 200 disposed around the edge of the wafer carrier 110. Optionally, the wafer carrier 110 may be an adsorption-type support stage or an electrostatic chuck.

[0023] The edge adjustment member 200 includes an insulating body 230 and a conductor 210, the conductor 210 being disposed on the insulating body 230 for insulatingly separating the conductor 210 from the wafer carrier 110 and the plasma, respectively.

[0024] The conductor 210 includes multiple conductive segments, at least two of which can generate different electric field intensities. Optionally, the conductor 210 can be made of a conductive material such as a metal. In the embodiments of this application, the insulating body 230 can insulatingly separate the conductor 210 from the wafer carrier 110 and the plasma, preventing the conductor 210 from becoming conductive with the wafer carrier 110 and the plasma, thus preventing the conductor 210 from failing.

[0025] In use, the lower electrode assembly of this embodiment is disposed within the process chamber 100 of the semiconductor process equipment. During the process, plasma exists within the process chamber 100. When the power supply is connected to the conductor 210, power is fed into the conductor 210. At this time, capacitive coupling can occur between the conductor 210 and the plasma above it. That is, an electric field exists above the conductor 210, and the electric field and the gas flow field work together to determine the distribution of the plasma. Therefore, this embodiment can use the electric field generated by multiple conductive segments to act on the plasma that is unevenly distributed due to the influence of the gas flow field, thereby making the plasma distribution uniform and thus making the film layer formed on the wafer uniformly distributed. In addition, this embodiment has at least two conductive segments, which can adjust the plasma segmentally. This method of adjusting the electric field is more flexible and can more specifically adjust the electric field intensity at different positions on the wafer edge. Therefore, the embodiments of this application do not require adjustment of the orifice diameter and length of the air intake nozzle 520, thus the requirements for the machining accuracy and installation accuracy of the air intake nozzle 520 are low; in addition, since there is no need to adjust the air intake nozzle 520, this application does not need to consider the impact of changes to the air intake nozzle 520 on the airflow field, thus shortening the process time.

[0026] In addition, it should be noted that during the deposition process, the difference between the film layer formed at the center and the edge of the wafer is relatively large. Therefore, in this embodiment, the conductor 210 is disposed at the edge of the wafer carrier 110. By adjusting the film layer distribution at the edge of the wafer through the conductor 210, the difference between the film layer at the center and the edge of the wafer can be reduced, and the uniformity of the film layer distribution can be improved.

[0027] In an optional embodiment, the insulating body 230 and the conductor 210 can be detachably configured, allowing for the replacement of different insulating bodies 230 and conductors 210 to further adjust the uniformity of the wafer film.

[0028] When the wafer is placed on the top surface of the wafer carrier 110, the top surface of the conductor 210 can be higher than the top surface of the wafer carrier 110. However, this arrangement of the conductor 210 above the wafer carrier 110 will affect the distribution of the airflow field near the wafer, thereby increasing the difficulty of using different conductors 210 to achieve uniform plasma distribution. Optionally, the height of the top surface of the conductor 210 is greater than the height of the top surface of the wafer carrier 110, and the distance between the top surface of the conductor 210 and the top surface of the wafer carrier 110 is less than a preset height. This preset height can be understood as follows: when the wafer is placed on the top surface of the wafer carrier 110, the top surface of the conductor 210 is not higher than the top surface of the wafer; or, the height of the top surface of the conductor 210 is less than the height of the top surface of the wafer carrier 110. The height of the top surface of the conductor 210 refers to the distance between the top surface of the conductor 210 and the ground plane, and the height of the top surface of the wafer carrier 110 refers to the distance between the top surface of the wafer support and the ground plane. In this embodiment, the top surface of the conductor 210 is not higher than the top surface of the wafer. Therefore, the conductor 210 will not affect the distribution of the gas flow field near the wafer, thereby reducing the difficulty of using different conductors 210 to make the plasma distribution uniform.

[0029] Optionally, the conductor 210 can be mounted on the wafer carrier 110 via threaded connection, snap-fit, or other methods. However, this arrangement makes replacing the conductor 210 cumbersome. In an optional embodiment, the lower electrode assembly further includes an insulating ring 120. The insulating ring 120 wraps around the outer peripheral surface of the wafer carrier 110. The top surface of the insulating ring 120 has a first groove, and the top surface of the wafer carrier 110 has a second groove. The first and second grooves together form a mounting groove, and the edge adjustment member 200 is disposed within the mounting groove. The insulating ring 120 is used for radio frequency isolation. In this embodiment, a mounting groove is formed, and the edge adjustment member 200 is movably disposed within the mounting groove. The opening of the mounting groove is located on the top surfaces of the insulating ring 120 and the wafer carrier 110. Therefore, replacing the edge adjustment member 200 only requires removing the conductor 210 disposed within the mounting groove and replacing it with another edge adjustment member 200, which makes replacing the conductor 210 more convenient.

[0030] In one optional embodiment, the coupling surfaces of at least two conductive segments have different areas, and the coupling surface of the conductive segment is the side of the conductive segment facing the plasma; and / or, the vertical distances between at least two conductive segments and the wafer carrier 110 are different, that is, at least two conductive segments have different vertical distances from the plasma. The coupling form between the conductive segment and the plasma is capacitive coupling. According to the capacitance impedance formula Z = 1 / (jωC), the smaller Z is, the stronger the capacitive coupling, and vice versa. The stronger the coupling, the greater the electric field strength between the conductive segment and the plasma. According to the capacitance calculation formula, C = εS / d, the parameters that determine the size of Z are: ε, the dielectric constant; S, the relative area of ​​the two layers; and d, the distance between the two layers. Therefore, different electric field strengths at different positions can be adjusted by adjusting the dielectric constant, area, and spacing. Where ε is the dielectric constant, in this embodiment, it is the dielectric constant of the insulating medium between the conductive segment and the plasma; S is the relative area of ​​the plates, in this embodiment, it is the area of ​​the side of the conductive segment facing the plasma; and d is the plate spacing, in this embodiment, it is the vertical distance between the conductive segment and the plasma. Therefore, this embodiment adjusts the capacitance between at least two conductive segments and the plasma by making the coupling surfaces of at least two conductive segments different or by making the vertical distance between at least two conductive segments and the plasma different, thereby adjusting the electric field strength between at least two conductive segments and the plasma.

[0031] As described above, the area of ​​the coupling surface of the conductive segment is the area of ​​the side of the conductive segment facing the plasma. Therefore, the area of ​​the coupling surface can be adjusted by adjusting the area of ​​this side. Thus, in an optional embodiment, at least two conductive segments have different lengths and / or at least two conductive segments have different widths, so that the areas of the coupling surfaces of at least two conductive segments are different. It should be noted that the length of the conductive segment is its length in its extending direction, and the width of the conductive segment is its width in the radial direction along the wafer carrier 110.

[0032] In one alternative embodiment, such as Figures 3 to 5 As shown, multiple conductive segments are spaced apart circumferentially along the wafer carrier 110, and each conductive segment extends circumferentially along the wafer carrier 110. This embodiment allows for segmented adjustment of the plasma, which not only provides a wide adjustment range but also offers greater flexibility. It should be noted that the multiple conductive segments in this embodiment are at least two segments, specifically three, four, or six segments, etc.

[0033] In addition to the previous embodiment, multiple conductive segments can also be connected sequentially. In an optional embodiment, such as... Figure 7As shown, the multiple conductive segments include a first segment 211, a second segment 212, and a third segment 213 arranged in a ring and nested sequentially. The plane containing the first segment 211 and the plane containing the third segment 213 are parallel. The vertical distance between the plane containing the first segment 211 and the wafer carrier 110 is a first distance, and the vertical distance between the plane containing the third segment 213 and the wafer carrier 110 is a second distance. The first distance is greater than or less than the second distance. The third segment 213 is positioned closer to the edge of the wafer carrier 110 than the first segment 211. It should be noted that when the first distance is greater than the second distance, the third segment 213, which is closer to the wafer carrier 110, is lower than the first segment 211. In this case, the distance between the third segment 213 and the plasma is greater than the distance between the first segment 211 and the plasma. When the first distance is less than the second distance, the third segment 213, which is closer to the wafer carrier 110, is higher than the first segment 211. In this case, the distance between the third segment 213 and the plasma is less than the distance between the first segment 211 and the plasma. This embodiment can also adjust the electric field strength at different positions on the edge of the wafer. Since multiple conductive segments are connected in sequence, only one conductive segment needs to be electrically connected to the power supply to energize multiple conductive segments, thus simplifying wiring and reducing installation time.

[0034] In addition to the above embodiment, this application also provides another embodiment in which multiple conductive segments are connected in sequence, such as... Figure 6 As shown, the multiple conductive segments include a fourth segment 214, a fifth segment 215, and a sixth segment 216 connected in sequence. The fourth segment 214 and the sixth segment 216 form a fan-shaped ring. The plane containing the fourth segment 214 is parallel to the plane containing the sixth segment 216. The vertical distance between the plane containing the fourth segment 214 and the wafer carrier 110 is the third distance, and the vertical distance between the plane containing the sixth segment 216 and the wafer carrier 110 is the fourth distance. The third distance is greater than or less than the fourth distance. The front view of the conductor 210 in this embodiment is Z-shaped or inverted Z-shaped, which allows for different electric field strengths between the multiple conductive segments and the plasma, providing more flexible adjustment. Furthermore, multiple conductive segments can be energized simply by connecting one of the conductive segments to a power source. The structure of this embodiment is particularly suitable for a side-extraction process chamber 100. The exhaust channel 170 of the side-extraction process chamber 100 is disposed on the side wall of the process chamber 100. It can be opposite to the wafer transfer port of the process chamber, or the axial direction of the exhaust channel 170 is at 90° to the axial direction of the wafer transfer port.

[0035] When the conductor 210 comprises multiple spaced conductive segments, each conductive segment needs to be wired to a power source to feed power into the conductive segment. This complicates the wiring and increases installation time. In an optional embodiment, the edge adjustment member 200 further includes a ring-shaped and conductive feed body 220. The feed body 220 is insulated from the wafer carrier 110 and is stacked insulated from the conductor 210. When the feed body 220 is energized, capacitive coupling occurs between the feed body 220 and the conductor 210. This solution can be combined with a solution where multiple conductive segments are spaced circumferentially along the wafer carrier 110, or with multiple conductive segments including a ring-shaped first segment 211, a second segment 212, and a third segment 213 connected in sequence, or with multiple conductive segments including a fourth segment 214, a fifth segment 215, and a sixth segment 216 connected in sequence. In this embodiment combined with the first scheme described above (i.e., the scheme in which multiple conductive segments are spaced apart circumferentially along the wafer carrier 110), since the feed body 220 is ring-shaped and opposite to the conductor 210, the power supply can be electrically connected to the feed body 220. Therefore, when the conductor 210 includes multiple spaced conductive segments, after the feed body 220 is energized, the feed body 220 capacitively couples multiple conductive segments, thereby capacitively coupling each conductive segment with the plasma above it. Therefore, in this embodiment, only the feed body 220 needs to be connected to the power supply, which simplifies wiring and reduces installation time.

[0036] In the case of combining this embodiment with the latter two schemes, if it is inconvenient to wire multiple conductive segments after installation due to the limitations of other components, a power supply 220 can be set up and placed in a position that is convenient for wiring. Then, the power supply 220 is electrically connected to the power source. After the power supply 220 is energized, the power supply 220 enables multiple conductive segments to be energized through capacitive coupling, thereby overcoming the problem of inconvenient wiring of multiple conductive segments.

[0037] In an optional embodiment, for multiple spaced conductive segments, the electric field strength between the conductive segments and the feed body 220 can also be adjusted by regulating the capacitance between the conductive segments and the feed body 220. At least two conductive segments have different relative areas with the feed body 220; and / or, at least two conductive segments have different vertical distances from the feed body 220; and / or, at least two conductive segments have different dielectric constants of the insulating media of the feed body 220. The coupling between the conductive segments and the feed body 220 is capacitive coupling. According to the capacitance impedance formula Z = 1 / (jωC), the smaller Z is, the stronger the capacitive coupling, and vice versa. Stronger coupling indicates a greater electric field strength between the conductive segments and the feed body 220. According to the capacitance calculation formula C = εS / d, the parameters determining the size of Z are: ε (dielectric constant), S (relative area of ​​the two layers), and d (distance between the two layers). Therefore, by adjusting the dielectric constant, area, and spacing, different electric field strengths at different locations can be adjusted. Where ε is the dielectric constant, which in this embodiment is the dielectric constant of the insulating medium between the conductive segment and the feed body 220; S is the relative area of ​​the electrode plates, which in this embodiment is the relative area between the conductive segment and the feed body 220; and d is the electrode plate spacing, which in this embodiment is the vertical distance between the conductive segment and the feed body 220. Therefore, this embodiment makes the relative areas between at least two conductive segments and the feed body 220 different, and / or makes the vertical distances between at least two conductive segments and the feed body 220 different, and / or makes the dielectric constant of the insulating medium between at least two conductive segments and the feed body 220 different, so as to adjust the capacitance between at least two conductive segments and the feed body 220, thereby making the capacitance between at least two conductive segments and the plasma different, and thus making the electric field strength between at least two conductive segments and the plasma different.

[0038] In one optional embodiment, the conductor 210 is embedded in the insulating body 230, and the conductor 210 is insulated from the wafer carrier 110 and the plasma through the insulating body 230. The insulating body 230 can insulate the conductor 210 from the wafer carrier 110 and the plasma, thereby preventing the conductor from failing after being connected to the wafer carrier 110. Of course, the conductor 210 can also be disposed in the insulating body 230 in other ways, as long as the conductor 210 is insulated from the wafer carrier 110 and the plasma respectively.

[0039] In an optional embodiment, the edge adjustment member 200 further includes an insulating member with multiple slots vertically arranged on its side surface. The insulating body 230 and the conductor 210 are separably disposed in any one of the slots. In this embodiment, the distance between the conductor 210 and the plasma can be changed by altering the positions of the insulating body 230 and the conductor 210 in the slots. Furthermore, the insulating member is annular in shape, and each slot is an annular groove extending circumferentially along the insulating member. Thus, when the conductor includes multiple spaced-apart conductive segments, each conductive segment can be disposed in the same annular groove, thereby adjusting the position of each conductive segment within the annular groove. Additionally, the conductive segments can be disposed in slots of different heights, allowing for more flexible control of the uniformity of the wafer surface film.

[0040] Conductor 210 can be connected to a power supply with constant feed parameters. In an optional embodiment, both wafer carrier 110 and conductor 210 are electrically connected to a first power supply 410. An adjustment element 300 is provided on the circuit between the first power supply 410 and conductor 210. The adjustment element 300 is used to adjust the feed parameters of conductor 210, which may include at least one of feed power and feed frequency. Optionally, the adjustment element 300 may be an adjustable capacitor or an adjustable inductor.

[0041] Alternatively, the wafer carrier 110 is electrically connected to the second power supply 420, and the conductor 210 is electrically connected to the third power supply 430, the feed parameters of the third power supply 430 being adjustable. In this embodiment, the feed parameters of the third power supply 430 itself are adjustable, and the electric field strength between the conductor 210 and the plasma can be adjusted by regulating these parameters, thereby controlling the uniformity of the film layer on the wafer surface. It should be noted that this embodiment can be combined with a scheme where the edge adjustment component 200 also includes a ring-shaped and conductive feed body 220, in which case either the first power supply 410 or the third power supply 430 is connected to the feed body 220.

[0042] This application also discloses a semiconductor process apparatus, which includes a process chamber 100 and a lower electrode assembly of any of the above embodiments, the lower electrode assembly being disposed within the process chamber 100. Optionally, the process chamber 100 is provided with an air intake ring 510 and an air intake nozzle 520, the air intake nozzle 520 being connected to the air intake ring 510; the top of the process chamber 100 is provided with an air intake structure 600 and a first radio frequency coil 710, the first radio frequency coil 710 being electrically connected to a first radio frequency power supply 910, the first radio frequency coil 710 being used to maintain the plasma within the process chamber 100; the top of the process chamber 100 is also provided with an insulating layer 810, the first radio frequency coil 710 being disposed within the insulating layer 810, a heating layer 820 being stacked on the insulating layer 810, and a cooling layer 830 being stacked on the heating layer 820. A second radio frequency coil 720 is wound around the outer periphery of the top of the process chamber 100. The second radio frequency coil 720 is electrically connected to the second radio frequency power supply 920. The second radio frequency coil 720 is used to maintain the plasma in the process chamber 100.

[0043] Furthermore, the structural parameters (e.g., dimensions) of the air intake nozzle 520 can be adjusted to regulate the flow field and further improve the uniformity of the film layer formed on the wafer. In this embodiment, since the edge adjustment member 200 can adjust the electric field strength on the wafer surface, the combination of the two adjustment methods simplifies the adjustment of the air intake nozzle 520 while achieving higher precision adjustment.

[0044] In an optional embodiment, the lower electrode assembly further includes an insulating ring 120, an insulating base 130, and a terminal block 140. The wafer carrier 110 is stacked with the insulating base 130. The insulating ring 120 surrounds the outer peripheral surface of the wafer carrier 110 and the outer peripheral surface of the insulating base 130. The terminal block 140 is a hollow cylindrical structure with an opening at the top. The wafer carrier 110, insulating ring 120, and insulating base 130 are all disposed within the terminal block 140. In this embodiment, the insulating base 130 and insulating ring 120 work together to insulatingly separate the bottom surface and outer peripheral surface of the wafer carrier 110 from the plasma within the process chamber 100. Additionally, the terminal block 140 can be used for connecting various interfaces of the lower electrode (such as He lines, Chiller lines, etc.). The terminal block 140 has a cylindrical structure that surrounds the wafer carrier 110, insulating ring 120, and insulating base 130, providing a cathode electrode for the wafer carrier 110 to generate a radio frequency bias. In addition, the cylindrical structure of the terminal block 140 facilitates the assembly of the wafer carrier 110, the insulating ring 120 and the insulating base 130 to the terminal block 140.

[0045] Optionally, cantilevered support legs can be used to house the lower electrode assembly within the process chamber 100. However, due to the lower strength of cantilever structures, the size of the support legs often needs to be increased, which increases the obstruction area of ​​the support legs on the airflow field, resulting in uneven airflow distribution. In an optional embodiment, the semiconductor process equipment also includes a lower electrode base 150 located within the process chamber 100. The lower electrode assembly is disposed on the lower electrode base 150, and the lower electrode base 150 is connected to the inner wall of the process chamber 100 via at least three spaced-apart support legs 160. In this embodiment, the at least three support legs 160 are connected via the lower electrode base 150. These at least three support legs 160 are not cantilever structures, have higher strength, and provide support together. Therefore, the size of the aforementioned at least three support legs 160 can be reduced, thereby reducing the obstruction area of ​​each support leg 160 on the airflow field and resulting in a more uniform airflow distribution.

[0046] In an optional embodiment, the bottom of the process chamber 100 is provided with a chamber evacuation channel 170 for communication with a vacuum system, and the chamber evacuation channel 170 is disposed opposite to the bottom surface of the wafer carrier 110. The process chamber 100 can be evacuated through this chamber evacuation channel 170. In this embodiment, the distance between the chamber evacuation channel 170 and the plasma at the same height within the process chamber 100 is substantially equal, thus further improving the uniformity of the airflow field.

[0047] The above embodiments of the present invention focus on describing the differences between the various embodiments. As long as the different optimization features between the various embodiments are not contradictory, they can be combined to form a better embodiment. For the sake of brevity, they will not be described in detail here.

[0048] The above description is merely an embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A lower electrode assembly, characterized in that, The device includes a wafer carrier (110) and an edge adjusting member (200) disposed around the edge of the wafer carrier (110). The edge adjusting member (200) includes an insulating body (230) and a conductor (210). The conductor (210) is disposed within the insulating body (230) to insulatingly separate the conductor (210) from the wafer carrier (110) and the plasma, respectively. The conductor (210) includes multiple conductive segments, and at least two of the conductive segments can generate different electric field intensities; The edge adjustment element (200) also includes a ring-shaped and conductive feed body (220), which is insulated from the wafer carrier (110) and is insulated from the conductor (210). When the feed body (220) is energized, capacitive coupling is generated between the feed body (220) and the conductor (210).

2. The lower electrode assembly according to claim 1, characterized in that, The lower electrode assembly also includes an insulating ring (120), which wraps around the outer periphery of the wafer carrier (110). The top surface of the insulating ring (120) is provided with a first groove, and the top surface of the wafer carrier (110) is provided with a second groove. The first groove and the second groove together form a mounting groove, and the edge adjustment member (200) is disposed in the mounting groove.

3. The lower electrode assembly according to claim 1, characterized in that, The coupling surfaces of at least two of the conductive segments have different areas; and / or, the vertical distances between at least two of the conductive segments and the wafer carrier (110) are different.

4. The lower electrode assembly according to claim 3, characterized in that, At least two of the conductive segments have different lengths and / or at least two of the conductive segments have different widths, such that the areas of the coupling surfaces of at least two of the conductive segments are different.

5. The lower electrode assembly according to claim 3, characterized in that, The plurality of conductive segments are arranged at circumferential intervals along the wafer carrier (110), and each of the conductive segments extends circumferentially along the wafer carrier (110).

6. The lower electrode assembly according to claim 3, characterized in that, The plurality of conductive segments include a first segment (211), a second segment (212), and a third segment (213) that are sequentially nested in a ring. The plane containing the first segment (211) is parallel to the plane containing the third segment (213). The vertical distance between the plane containing the first segment (211) and the wafer carrier (110) is a first distance, and the vertical distance between the plane containing the third segment (213) and the wafer carrier (110) is a second distance. The first distance is greater than or less than the second distance, and the third segment (213) is positioned closer to the edge of the wafer carrier (110) than the first segment (211).

7. The lower electrode assembly according to claim 3, characterized in that, The plurality of conductive segments include a fourth segment (214), a fifth segment (215), and a sixth segment (216) connected in sequence. The fourth segment (214) and the sixth segment (216) form a fan-shaped ring. The plane containing the fourth segment (214) is parallel to the plane containing the sixth segment (216). The vertical distance between the plane containing the fourth segment (214) and the wafer carrier (110) is a third distance, and the vertical distance between the plane containing the sixth segment (216) and the wafer carrier (110) is a fourth distance. The third distance is greater than or less than the fourth distance.

8. The lower electrode assembly according to claim 1, characterized in that, The multiple conductive segments are arranged at circumferential intervals.

9. The lower electrode assembly according to claim 8, characterized in that, The relative areas between at least two of the conductive segments and the feed body (220) are different; and / or, the vertical distances between at least two of the conductive segments and the feed body (220) are different; and / or, the dielectric constants of the insulating medium between at least two of the conductive segments and the feed body (220) are different.

10. The lower electrode assembly according to claim 1, characterized in that, Both the wafer carrier (110) and the conductor (210) are electrically connected to a first power supply (410). An adjustment element (300) is provided on the circuit between the first power supply (410) and the conductor (210). The adjustment element (300) is used to adjust the feed parameters of the conductor (210); or... The wafer carrier (110) is electrically connected to the second power supply (420), and the conductor (210) is electrically connected to the third power supply (430). The power supply parameters of the third power supply (430) are adjustable.

11. A semiconductor process apparatus, characterized in that, It includes a process chamber (100) and a lower electrode assembly as described in any one of claims 1 to 10, the lower electrode assembly being disposed within the process chamber (100).

12. The semiconductor process equipment according to claim 11, characterized in that, The lower electrode assembly further includes an insulating ring (120), an insulating base (130), and a terminal block (140). The wafer carrier (110) is stacked with the insulating base (130), and the insulating ring (120) wraps around the outer peripheral surface of the wafer carrier (110) and the outer peripheral surface of the insulating base (130). The junction box (140) is a cylindrical structure with a hollow interior and an opening at the top. The wafer carrier (110), the insulating ring (120), and the insulating base (130) are all located inside the junction box (140).

13. The semiconductor process equipment according to claim 11, characterized in that, The semiconductor process equipment also includes a lower electrode base (150) located in the process chamber (100), the lower electrode assembly being disposed on the lower electrode base (150), and the lower electrode base (150) being connected to the inner wall of the process chamber (100) via at least three spaced legs (160).

14. The semiconductor process equipment according to claim 11, characterized in that, The bottom of the process chamber (100) is provided with a chamber evacuation channel (170) for communicating with the vacuum system, and the chamber evacuation channel (170) is disposed opposite to the bottom surface of the wafer carrier (110).

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