Array substrate and display panel

Abstract

The application relates to the display field and specifically discloses an array substrate, which comprises a substrate, a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a color resistance layer and a passivation layer which are sequentially stacked on the substrate; a pixel electrode is arranged on the passivation layer; the second metal layer is provided with a data line; a first electrode layer is arranged between the color resistance layer and the pixel electrode, the first electrode layer is made of transparent material; the first electrode layer corresponds to the position of the data line; the orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the pixel electrode on the substrate; and the first electrode layer is connected to a common voltage signal. Through the above mode, the shielding metal layers on both sides of the data line are cancelled, and the pixel aperture ratio is improved.

Description

Technical Field

[0001] This application relates to the field of displays, and more particularly to an array substrate and a display panel. Background Technology

[0002] In recent years, with the upgrading and diversification of displays, the market has also put forward higher requirements for the performance of panel products, such as increasingly stringent specifications for performance indicators such as brightness, transmittance, power consumption, viewing angle, and color gamut.

[0003] Brightness is a crucial specification in LCD monitors. The most important factor determining brightness is the pixel aperture ratio, which is the ratio of the effective light-transmitting area of ​​a pixel to its total area. Backlight cannot penetrate areas such as scan lines, data lines, thin-film transistors, and storage capacitors in the display panel. Furthermore, light passing through these areas is not controlled by deflection voltage and cannot display the correct grayscale, thus belonging to non-effective light-transmitting areas. Additionally, data lines are usually shielded with metal layers on both sides to block the signal, further obstructing light and reducing the pixel aperture ratio, thus affecting the display panel's display effect.

[0004] Therefore, how to eliminate the shielding metal layers on both sides of the data cable and improve the pixel aperture ratio has become an urgent problem to be solved in this field. Summary of the Invention

[0005] This application discloses an array substrate and a display panel, the purpose of which is to eliminate the shielding metal layer on both sides of the data line and improve the pixel aperture ratio.

[0006] This application discloses an array substrate, including a substrate and a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a color resist layer, and a passivation layer stacked sequentially on the substrate. A pixel electrode is disposed on the passivation layer, a data line is formed on the second metal layer, and a first electrode layer is disposed between the color resist layer and the pixel electrode. The first electrode layer is made of a transparent material. The first electrode layer corresponds to the position of the data line. The orthogonal projection of the first electrode layer on the substrate covers the orthogonal projection of the pixel electrode on the substrate. The first electrode layer is connected to a common voltage signal.

[0007] Optionally, the array substrate is divided into a display area and a non-display area in the planar direction. The display area is a main pixel area and an auxiliary pixel area. The pixel electrode includes a main pixel electrode and an auxiliary pixel electrode. The main pixel electrode is located in the main pixel area, and the auxiliary pixel electrode is located in the auxiliary pixel area. The data line is located on both sides of the non-display area. The first metal layer has a gate line and a common line. The common line includes a first common line and a second common line, which are located on both sides of the gate line, respectively. The common line is connected to a common voltage signal. The first common line partially overlaps with the main pixel electrode to form a storage capacitor. The second common line partially overlaps with the auxiliary pixel electrode to form a storage capacitor. The array substrate further includes a first active switch, a second active switch, and a third active switch, all of which are disposed on the substrate. The source of the first active switch is connected to the data line, the second active switch and the first active switch share the same source, the drain of the first active switch is connected to the main pixel electrode, the drain of the second active switch is connected to the auxiliary pixel electrode, and the source of the third active switch is the drain of the second active switch. A first via is formed on the first insulating layer, and the drain of the third active switch is connected to the first common line through the first via.

[0008] Optionally, the array substrate is divided into a display area and a non-display area in the planar direction. The display area is a main pixel area and an auxiliary pixel area. The pixel electrode includes a main pixel electrode and an auxiliary pixel electrode. The main pixel electrode is located in the main pixel area, and the auxiliary pixel electrode is located in the auxiliary pixel area. The data line is located on both sides of the non-display area. The first metal layer has a gate line and a common line. The common line is located on the side of the gate line closer to the main pixel electrode. The common line is electrically connected to a common voltage signal. The first electrode layer includes a main body and an extension. The main body is connected to the extension. The position of the main body corresponds to that of the data line. The extension is located on the side of the gate line closer to the auxiliary pixel electrode. The extension portion overlaps with the auxiliary pixel electrode to form a storage capacitor; the array substrate further includes a first active switch, a second active switch, and a third active switch, all of which are disposed on the substrate. The source of the first active switch is connected to the data line, the second active switch and the first active switch share the same source, and the source of the third active switch is the drain of the second active switch. The drain of the first active switch is connected to the main pixel electrode, the drain of the second active switch is connected to the auxiliary pixel electrode, a first via is formed on the first insulating layer, and the drain of the third active switch is connected to the common line through the first via.

[0009] Optionally, the array substrate is divided into a display area and a non-display area in the planar direction. The display area is a main pixel area and an auxiliary pixel area. The pixel electrode includes a main pixel electrode and an auxiliary pixel electrode. The main pixel electrode is located in the main pixel area, and the auxiliary pixel electrode is located in the auxiliary pixel area. The data line is located on both sides of the non-display area. A gate line is formed on the first metal layer. The first electrode layer includes a main body, a first extension, and a second extension. The main body is connected to the first extension and the second extension, respectively. The position of the main body corresponds to that of the data line. The first extension is located on the side of the gate line closer to the main pixel electrode, and the second extension is located on the side of the gate line closer to the auxiliary pixel electrode. The first active switch overlaps with the main pixel electrode to form a storage capacitor, and the second extended portion overlaps with the auxiliary pixel electrode to form a storage capacitor. The array substrate also includes a first active switch, a second active switch, and a third active switch. The first active switch, the second active switch, and the third active switch are all disposed on the substrate. The source of the first active switch is connected to the data line. The second active switch and the first active switch share the source. The source of the third active switch is the drain of the second active switch. The drain of the first active switch is connected to the main pixel electrode. The drain of the second active switch is connected to the auxiliary pixel electrode. The drain of the third active switch is connected to the first extended portion through a second via.

[0010] Optionally, the area of ​​the first extension is larger than the area of ​​the second extension, and the overlap area between the first extension and the main pixel electrode is larger than the overlap area between the second extension and the auxiliary pixel electrode.

[0011] Optionally, the passivation layer includes a first passivation layer and a second passivation layer, the second passivation layer is located on the first passivation layer, the pixel electrode is disposed on the second passivation layer, the first electrode layer is located between the first passivation layer and the second passivation layer, and the second via is formed in the first passivation layer; the orthogonal projection area of ​​the first electrode layer on the substrate is greater than or equal to the orthogonal projection area of ​​the data line on the substrate; the first electrode layer partially overlaps with the side of the color resist layer near the data line.

[0012] Optionally, the first extension includes a first sub-extension and a second sub-extension. The first sub-extension avoids the drain of the first active switch and does not overlap with the drain of the first active switch. The second extension overlaps with the second via, and the orthographic projection of the second via is entirely within the orthographic projection of the second extension, covering the area between the second via and the main body. The main pixel electrode has a first protrusion and a second protrusion on the side near the gate line. The drain of the first active switch partially overlaps with the first protrusion. The second protrusion partially overlaps with the second sub-extension and avoids the second via. There is a gap between the second sub-extension and the drain of the first active switch. The drain of the second active switch includes a first connection trace, a second connection trace, and a drain body connected in sequence. The first connection trace is perpendicular to the second connection trace in a plane. The second connection trace is parallel to the second extension and is located below the second extension. The orthographic projection area of ​​the second extension on the substrate is larger than the orthographic projection area of ​​the second connection trace on the substrate.

[0013] Optionally, a first shielding layer is provided between the first electrode layer and the color resist layer. The first shielding layer is positioned corresponding to the data line, and the width of the first shielding layer is greater than the width of the data line.

[0014] Optionally, the first metal layer is further formed with scan lines, and a second shielding layer is disposed between the first electrode layer and the color resist layer. The second shielding layer is disposed corresponding to the position of the scan lines, and the width of the second shielding layer is greater than the width of the scan lines.

[0015] This application also discloses a display panel including a color filter substrate, the display panel further including the array substrate described above, the array substrate and the color filter substrate being disposed in a cell.

[0016] This application sets a first electrode layer above the color resist layer at the position corresponding to the data line. Since the first electrode layer is on a different layer from the pixel electrode, the width of the first electrode layer covering the data line direction can be increased without being limited or affected by the pixel electrode. This allows the orthogonal projection of the first electrode layer on the substrate to cover the orthogonal projection of the pixel electrode on the substrate. When a voltage is applied to the first electrode layer, the first electrode layer replaces the shielding metal layer originally set on both sides of the data line for data line signal shielding. This eliminates the need for the shielding metal layer originally set on both sides of the data line to avoid blocking light. Moreover, the first electrode layer is made of transparent material, so the light obliquely incident on the first electrode layer will not be blocked, and the brightness of the display area can be slightly improved, which is beneficial to improving the pixel aperture ratio. At the same time, the parallel plate capacitor formed between the pixel electrode and the first electrode layer has a shorter spacing than the parallel plate capacitor formed between the pixel electrode and the first metal layer, which can effectively increase the storage capacitance of the pixel. Attached Figure Description

[0017] The accompanying drawings are provided to further illustrate the embodiments of this application and form part of the specification. They serve to demonstrate implementation methods of this application and, together with the textual description, explain the principles of this application. Obviously, the drawings described below are merely some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort. In the drawings:

[0018] Figure 1 This is a schematic diagram of the first embodiment of the array substrate of this application;

[0019] Figure 2 This is a schematic diagram of a second embodiment of the array substrate of this application;

[0020] Figure 3 This is a schematic diagram of a third embodiment of the array substrate of this application;

[0021] Figure 4 This is a schematic diagram of the fourth embodiment of the array substrate of this application.

[0022] Figure 5 This is a cross-sectional schematic diagram of the fourth embodiment of the array substrate of this application;

[0023] Figure 6 This is a schematic diagram of the fifth embodiment of the array substrate of this application;

[0024] Figure 7 This is a schematic diagram of the sixth embodiment of the array substrate of this application;

[0025] Figure 8 This is a schematic diagram of one embodiment of the display panel of this application.

[0026] Among them, 10 is a display panel; 100 is an array substrate; 200 is a color filter substrate; 110 is a first metal layer; 111 is a scan line; 112 is a common line; 113 is a first insulating layer; 114 is a second metal layer; 115 is a data line; 116 is a second insulating layer; 117 is a gate line; 120 is a color resist layer; 130 is a passivation layer; 131 is a first passivation layer; 132 is a second via; 133 is a second passivation layer; 134 is a first via; 140 is a first electrode layer; 150 is a substrate; 160 is a pixel electrode; 161 is a first shielding layer; 162 is a second shielding layer; 170 is a first main... Active switch; 171, second active switch; 172, third active switch; 181, first common line; 182, second common line; 190, main body; 191, extension; 192, first extension; 193, second extension; 300, main pixel electrode; 310, auxiliary pixel electrode; 400, display area; 410, non-display area; 500, main pixel area; 510, auxiliary pixel area; 520, first sub-extension; 530, second sub-extension; 540, first protrusion; 550, second protrusion; 560, first connecting trace; 570, second connecting trace; 580, drain body. Detailed Implementation

[0027] The present application will now be described in detail with reference to the accompanying drawings and optional embodiments. It should be noted that, without conflict, the various embodiments or technical features described below can be arbitrarily combined to form new embodiments.

[0028] Figure 1 This is a schematic diagram of the first embodiment of the array substrate of this application, as shown below. Figure 1 As shown, this application discloses an array substrate 100, including a substrate 150, and a first metal layer 110, a first insulating layer 113, a second metal layer 114, a second insulating layer 116, a color resist layer 120, and a passivation layer 130 stacked sequentially on the substrate 150; a pixel electrode 160 is disposed on the passivation layer 130, a data line 115 is formed on the second metal layer 114, and a first electrode layer 140 is disposed between the color resist layer 120 and the pixel electrode 160. The first electrode layer 140 is made of a transparent material; the first electrode layer 140 corresponds to the position of the data line 115; the orthographic projection of the first electrode layer 140 on the substrate 150 covers the orthographic projection of the pixel electrode 160 on the substrate 150; the array substrate 150 also includes a common voltage signal, and the first electrode layer 140 is connected to the common voltage signal.

[0029] This application provides a first electrode layer 140 above the color resist layer 120 at a position corresponding to the data line 115. Since the first electrode layer 140 is on a different layer from the pixel electrode 160, the width of the first electrode layer 140 covering the data line 115 direction can be increased without being limited or affected by the pixel electrode 160. This allows the orthogonal projection of the first electrode layer 140 onto the substrate 150 to cover the orthogonal projection of the pixel electrode 160 onto the substrate 150. When a voltage is applied to the first electrode layer 140, the first electrode layer 140 replaces the shielding metal layers originally disposed on both sides of the data line 115. This is used for signal shielding of data line 115, which eliminates the need for the original shielding metal layers on both sides of data line 115 to avoid blocking light. Moreover, the first electrode layer 140 is made of transparent material, so the light shining obliquely onto the first electrode layer 140 will not be blocked, and can ultimately slightly improve the brightness of the display area, which is beneficial to improving the pixel aperture ratio. At the same time, the parallel plate capacitor formed between the pixel electrode 160 and the first electrode layer 140 has a shorter spacing than the parallel plate capacitor formed between the pixel electrode 160 and the first metal layer 110, which can effectively increase the storage capacitance of the pixel.

[0030] Specifically, the first electrode layer 140 in this application is made of the same material as the pixel electrode 160. The first electrode layer 140 may be made of a transparent oxide material, the same material as the pixel electrode 160. While light emitted from the backlight can pass normally through the transparent first electrode layer 140, the first electrode layer 140 is connected to a common voltage signal. Therefore, since the voltage of the first electrode layer 140 is the same as that of the common electrode layer of the opposite array substrate 100, the liquid crystal molecules at the corresponding positions of the first electrode layer 140 can be prevented from deflecting, thus playing a light-shielding role equivalent to a black matrix. In the case of achieving the same light-shielding effect, the transparent material can reduce unnecessary light blocking and light loss compared to a black matrix or shielding electrode layer made of a metal layer or a black material.

[0031] Furthermore, since the original shielding metal layer design has been eliminated in the array substrate 100 architecture of this application, the parasitic capacitance between the pixel electrode 160 and the data line 115 is increased. However, the storage capacitance is also increased accordingly. That is, the storage capacitance is improved without increasing crosstalk, which is beneficial to improving the brightness and quality of the product and increasing the product's market competitiveness.

[0032] It should be noted that the array substrate 100 of this application mainly includes the array substrate 100 used in large-size display panels 10 of 55 inches or larger. The architecture of the array substrate 100 generally adopts a 3T-8-chip pixel design, that is, three active switches combined with an 8-chip pixel design, so that the liquid crystal molecules at the main pixel electrode and the auxiliary pixel electrode within the same sub-pixel have different rotation angles, thereby improving the color shift at large viewing angles.

[0033] Traditional 8-chip pixels have shared voltage traces, which are connected to a shared voltage switch. This shared voltage switch is used to discharge some of the charge from the auxiliary pixel electrode through the shared voltage trace, so that the voltage of the auxiliary pixel electrode is lower than that of the main pixel electrode. This trace is usually designed as a separate trace, set on the same layer as the data line, passing through the middle of the main pixel electrode and the auxiliary pixel electrode, and connected to a common voltage to control the voltage division of the auxiliary pixel electrode. However, in this design, each shared voltage trace is made of an opaque material. The following solution is an improvement based on this structure.

[0034] Figure 2 This is a schematic diagram of a second embodiment of the array substrate of this application, as shown below. Figure 2 As shown, the array substrate 100 is divided into a display area 400 and a non-display area 410 in the planar direction. The display area 400 is divided into a main pixel area 500 and a secondary pixel area 510. The pixel electrode 160 includes a main pixel electrode 300 and a secondary pixel electrode 310. The main pixel electrode 300 is located in the main pixel area 500, and the secondary pixel electrode 310 is located in the secondary pixel area 510. Data lines 115 are located on both sides of the non-display area 410. The first metal layer 110 has a gate line 117 and a common line 112. The common line 112 includes a first common line 181 and a second common line 182, which are located on both sides of the gate line 117, respectively. The common line 112 is electrically connected to a common voltage signal. The first common line 181 partially overlaps with the main pixel electrode 300 to form a storage capacitor. The second common line 182 overlaps with the secondary pixel electrode 300 to form a storage capacitor. Ten parts overlap to form a storage capacitor; the array substrate 100 also includes a first active switch 170, a second active switch 171 and a third active switch 172, all of which are disposed on the substrate 150. The source of the first active switch 170 is connected to the data line 115, the second active switch 171 and the first active switch 170 share a common source, and the source of the third active switch 172 is the drain of the second active switch 171; the drain of the first active switch 170 is connected to the main pixel electrode 300, the drain of the second active switch 171 is connected to the auxiliary pixel electrode 310, a first via 134 is formed on the first insulating layer 113, and the drain of the third active switch 172 is connected to the first common line 181 through the first via 134.

[0035] In this embodiment, the first common line 181 and the second common line 182 are simultaneously connected to a common voltage signal, and obtain the same potential through the common voltage signal. By forming a first via 134 on the first insulating layer 113, the drain of the third active switch 172 is connected to the first common line 181 through the first via 134. The third active switch 172 provides an electrical signal to the first common line 181, so that the first common line 181 obtains the same voltage as the second common line 182, thereby pulling down the voltage of the auxiliary pixel electrode 310. In this way, the sharing voltage trace originally used to pull down the voltage of the auxiliary pixel electrode 310 can be eliminated, avoiding the blocking of the aperture area by the sharing voltage trace, which is beneficial to improving the pixel aperture ratio and thus improving the display effect of the display panel 10.

[0036] Figure 3 This is a schematic diagram of a third embodiment of the array substrate of this application; as shown Figure 3 As shown, the array substrate 100 is divided into a display area 400 and a non-display area 410 in the planar direction. The display area 400 is divided into a main pixel area 500 and a secondary pixel area 510. The pixel electrode 160 includes a main pixel electrode 300 and a secondary pixel electrode 310. The main pixel electrode 300 is located in the main pixel area 500, and the secondary pixel electrode 310 is located in the secondary pixel area 510. The data line 115 is located on both sides of the non-display area 410. The first metal layer 110 has a gate line 117 and a common line 112. The common line 112 is located on the side of the gate line 117 near the main pixel electrode 300. The common line 112 is electrically connected to a common voltage signal. The first electrode layer 140 includes a main body 190 and an extension 191. The main body 190 is connected to the extension 191. The position of the main body 190 corresponds to that of the data line 115. The extension 191 is located on the gate line 117 near the secondary pixel area. On one side of the primary pixel electrode 310, the extension 191 partially overlaps with the auxiliary pixel electrode 310 to form a storage capacitor; the array substrate 100 also includes a first active switch 170, a second active switch 171, and a third active switch 172. The first active switch 170, the second active switch 171, and the third active switch 172 are all disposed on the substrate 150. The source of the first active switch 170 is connected to the data line 115. The second active switch 171 and the first active switch 170 share a source. The source of the third active switch 172 is the drain of the second active switch 171. The drain of the first active switch 170 is connected to the primary pixel electrode 300, and the drain of the second active switch 171 is connected to the auxiliary pixel electrode 310. A first via 134 is formed on the first insulating layer 113, and the drain of the third active switch 172 is connected to the common line 112 through the first via 134.

[0037] and Figure 2The difference between this embodiment and the previous one is that the common line 112 located on the side of the gate line 117 near the auxiliary pixel electrode 310 is replaced by an extension 191. That is, the original metal layer is replaced by a transparent material. Therefore, some of the light that was originally blocked, especially oblique light, can pass through the extension 191 and finally reach the light-emitting surface, which can slightly improve the brightness of the display area. The distance between the extension 191 and the auxiliary pixel electrode 310 is smaller than the distance between the common line 112 and the auxiliary pixel electrode 310. Therefore, with the same storage capacitance, the overlap area between the extension 191 and the auxiliary pixel electrode 310 can be reduced, which can improve the pixel aperture ratio. If the overlap area remains unchanged, the storage capacitance can be increased.

[0038] Figure 4 This is a schematic diagram of the fourth embodiment of the array substrate of this application. Figure 5 This is a cross-sectional schematic diagram of the fourth embodiment of the array substrate of this application; as shown Figure 4 and Figure 5 As shown, the array substrate 100 is divided into a display area 400 and a non-display area 410 in the planar direction. The display area 400 is divided into a main pixel area 500 and a secondary pixel area 510. The pixel electrode 160 includes a main pixel electrode 300 and a secondary pixel electrode 310. The main pixel electrode 300 is located in the main pixel area 500, and the secondary pixel electrode 310 is located in the secondary pixel area 510. Data lines 115 are located on both sides of the non-display area 410. A gate line 117 is formed on the first metal layer 110. The first electrode layer 140 includes a main body 190, a first extension 192, and a second extension 193. The main body 190 is connected to the first extension 192 and the second extension 193, respectively. The main body 190 corresponds to the position of the data line 115. The first extension 192 is located on the side of the gate line 117 near the main pixel electrode 300, and the second extension 193 is located on the side of the gate line 117 near the secondary pixel electrode 300. On one side of 10, the first extension 192 partially overlaps with the main pixel electrode 300 to form a storage capacitor, and the second extension 193 partially overlaps with the auxiliary pixel electrode 310 to form a storage capacitor; the array substrate 100 also includes a first active switch 170, a second active switch 171, and a third active switch 172. The first active switch 170, the second active switch 171, and the third active switch 172 are all disposed on the substrate 150. The source of the first active switch 170 is connected to the data line 115. The second active switch 171 and the first active switch 170 share a source. The source of the third active switch 172 is the drain of the second active switch 171. The drain of the first active switch 170 is connected to the main pixel electrode 300, the drain of the second active switch 171 is connected to the auxiliary pixel electrode 310, and the drain of the third active switch 172 is connected to the first extension 192 through the second via 132.

[0039] and Figure 3Unlike the illustrated embodiment, in this embodiment, the common line 112 is completely eliminated. Therefore, when laying the gate line 117, the pressure of laying and etching caused by the common line 112 can be reduced, which is beneficial to reducing the difficulty of laying the gate line 117 and improving the yield of the gate line 117. Similarly, since the first extension 192 and the second extension 193 are made of transparent material, the amount of blocked light can be reduced, and the brightness of the display area 400 can be increased. With the same storage capacitor, the overlap area between the first extension 192 and the main pixel electrode 300, and between the second extension 193 and the auxiliary pixel electrode 310 can be reduced, which can increase the pixel aperture ratio. If the overlap area remains unchanged, the storage capacitor can be increased.

[0040] Furthermore, the area of ​​the first extension 192 is larger than the area of ​​the second extension 193, and the overlap area between the first extension 192 and the main pixel electrode 300 is larger than the overlap area between the second extension 193 and the auxiliary pixel electrode 310. This results in a larger storage capacitance between the first extension 192 and the main pixel electrode 300 than the storage capacitance between the second extension 193 and the auxiliary pixel electrode 310. This means that in the short period after the scanning phase, the larger storage capacitance can be replenished more quickly, allowing the display brightness of the main pixel area 500 to be better maintained, which is beneficial for improving the display effect of the display panel 10.

[0041] Furthermore, in this embodiment, the first extension 192 includes a first sub-extension 520 and a second sub-extension 530. The first sub-extension 520 avoids the drain of the first active switch 170 and does not overlap with the drain of the first active switch 170. The second extension 193 overlaps with the second via 132. The orthographic projection of the second via 132 is entirely located within the orthographic projection of the second extension 193 and covers the area between the second via 132 and the main body 190.

[0042] The main pixel electrode 300 has a first protrusion 540 and a second protrusion 550 on the side near the gate line 117. The drain portion of the first active switch 170 overlaps with the first protrusion 540. The second protrusion 550 partially overlaps with the second sub-extension 530 and avoids the second via 132. There is a gap between the second sub-extension 530 and the drain of the first active switch 170.

[0043] The drain of the second active switch 171 includes a first connection trace 560, a second connection trace 570 and a drain body 580 connected in sequence. The first connection trace 560 is perpendicular to the second connection trace 570 on the plane. The second connection trace 570 is parallel to the second extension 193. The second connection trace 570 is located below the second extension 193, and the orthogonal projection area of ​​the second extension 193 on the substrate 150 is greater than the orthogonal projection area of ​​the second connection trace 570 on the substrate 150.

[0044] The second protrusion 550 and the second sub-extension 530 can form a large storage capacitance, which is beneficial to improving the display effect. The second protrusion 550 avoids the second via 132, which prevents the charge discharged by the auxiliary pixel electrode 310 through the second via 132 from causing significant parasitic capacitance to the main pixel electrode 300. While increasing the storage capacitance, the stability of the main pixel electrode 300 is not reduced. In addition, the first sub-extension 520 avoids the drain of the first active switch 170. In addition to facilitating the setting of vias to connect the first active switch 170 and the pixel electrode 160, it also prevents the charge discharged by the auxiliary pixel electrode 310 through the second via 132 from causing parasitic capacitance to the drain of the first active switch 170. It should be noted that the unit resistance of metal is less than that of the main pixel electrode. If the two overlap, the voltage in the drain of the first active switch 170 may fluctuate due to the influence of parasitic capacitance, thereby affecting the display effect.

[0045] In addition, in this embodiment, the passivation layer 130 includes a first passivation layer 131 and a second passivation layer 133. The second passivation layer 133 is located on the first passivation layer 131, the pixel electrode 160 is disposed on the second passivation layer 133, the first electrode layer 140 is located between the first passivation layer 131 and the second passivation layer 133, and the second via 132 is formed in the first passivation layer 131.

[0046] This application adds a second passivation layer 133 to the film layer of the array substrate 100 to isolate the first electrode layer 140 from the pixel electrode 160, preventing the pixel electrode 160 from conducting with the first electrode layer 140. Furthermore, the design of the first passivation layer 131 and the second passivation layer 133 facilitates the formation of connection vias for the first active switch 170, the second active switch 171, and the third active switch 172, as well as a via connecting the third active switch 172 to the first electrode layer 140. This allows the first electrode layer 140 to connect to the third active switch 172 through the second via to obtain electrical signals, replacing the original voltage sharing trace design and achieving a voltage divider effect on the auxiliary pixel electrode.

[0047] Furthermore, according to the storage capacitance C = εS / d of a parallel-plate capacitor, where S represents the area of ​​the parallel plates and d is the distance between the parallel plates, increasing the area of ​​the parallel-plate capacitor plates or reducing the distance between the plates can effectively increase the storage capacitance. Based on the above principle, this application also improves the first electrode layer 140 as follows:

[0048] The projected area of ​​the first electrode layer 140 on the substrate 150 is greater than or equal to the projected area of ​​the data line 115 on the substrate 150; the first electrode layer 140 partially overlaps with the side of the color resist layer 120 near the data line 115.

[0049] Unlike the previous embodiment, in this embodiment, the width of the first electrode layer 140 is greater than or equal to the width of the data line 115. By controlling the width of the first electrode layer 140, the orthographic projection of the first electrode layer 140 on the substrate 150 can overlap with the orthographic projection of the pixel electrode 160 on the substrate 150. This ensures that a parallel capacitor is formed between the first electrode layer 140 and the pixel electrode 160 after the first electrode layer 140 is energized, while also simplifying the space occupied by the first electrode layer 140 within the film layer of the array substrate 100.

[0050] By increasing the area of ​​the first electrode layer 140, the ability of the active switch storage capacitor on the array substrate 100 to retain charge is improved, thus mitigating the leakage problem of the active switch. In the conventional active switch, the storage capacitor is the capacitor between the pixel electrode 160 and the first metal layer 110. In this application, the first electrode layer 140 acts as a capacitor plate for the common signal, and the storage capacitor of the new pixel is the capacitor formed between the pixel electrode 160 and the first electrode layer 140. Compared to reducing the distance between the capacitor plates formed between the pixel electrode 160 and the first metal layer 110 from d1 to d2, the pixel storage capacitor can be effectively increased.

[0051] Figure 6 This is a schematic diagram of the fifth embodiment of the array substrate of this application, as shown. Figure 6 As shown, Figure 6 The illustrated embodiment is based on Figure 1 As an improvement, a first shielding layer 161 is provided between the first electrode layer 140 and the color resist layer 120. The first shielding layer 161 is positioned corresponding to the data line 115, and the width of the first shielding layer 161 is greater than the width of the data line 115.

[0052] This embodiment and Figure 1Unlike the illustrated embodiment, in this embodiment, a first shielding layer 161 is added between the color resist layer 120 and the first electrode layer 140. The first shielding layer 161 is used to shield the data line 115, thereby improving the light leakage problem caused by the data line 115. The original shielding layer on the color filter substrate 200 corresponding to the data line 115 is replaced by a second shielding layer 162. This eliminates the need for the original shielding layer on the color filter substrate 200 corresponding to the data line 115. Alternatively, it can be understood as changing the shielding layer on the color filter substrate 200 corresponding to the data line 115 from the color filter substrate 200 side to the array substrate 100 side. This design helps to reduce parasitic capacitance problems such as data overload. In addition, by fabricating the second shielding layer 162 on the array substrate 100 and eliminating the corresponding shielding layer on the color filter substrate 200, the alignment accuracy of the shielding layer during the manufacturing process can be effectively improved, which is beneficial to further improving the pixel aperture ratio.

[0053] By using the first shielding layer 161 to shield the signals of the first electrode layer 140 and pixel electrode 160 above the data line 115, it is beneficial to improve the charging uniformity and chromatic crosstalk of the array substrate 100. In addition, designing the first shielding layer 161 on the side of the array substrate 100 helps to improve the product contrast, reflectivity, and oblique color mixing.

[0054] Figure 7 This is a schematic diagram of the sixth embodiment of the array substrate of this application, as shown. Figure 7 As shown, Figure 7 The illustrated embodiment is based on Figure 6 In addition to the improvements, the first metal layer 110 also forms a scan line 111, and a second shielding layer 162 is provided between the first electrode layer 140 and the color resist layer 120. The second shielding layer 162 is positioned corresponding to the scan line 111, and the width of the second shielding layer 162 is greater than the width of the scan line 111.

[0055] Unlike the previous embodiment, in this embodiment, a second shielding layer 162 is provided between the first electrode layer 140 and the color resist layer 120 at the position corresponding to the scan line 111. The second shielding layer 162 replaces the original shielding layer of the color filter substrate 200 at the position corresponding to the scan line 111. This can be understood as changing the shielding layer of the color filter substrate 200 corresponding to the scan line 111 from the side of the color filter substrate 200 to the side of the array substrate 100. This design is beneficial to reduce the problem of parasitic capacitance reduction such as data overload. In addition, by fabricating the second shielding layer 162 on the array substrate 100 and eliminating the design of the corresponding shielding layer on the color filter substrate 200, the alignment accuracy of the shielding layer in the process can be effectively improved, which is beneficial to further improve the pixel aperture ratio.

[0056] Figure 8 This is a schematic diagram of one embodiment of the display panel of this application, as shown below. Figure 8As shown, this application also discloses a display panel 10, including a color filter substrate 200. The display panel 10 also includes the aforementioned array substrate 100, and the array substrate 100 and the color filter substrate 200 are arranged in a cell. Light emitted from the backlight passes sequentially through the array substrate 100, liquid crystal, and color filter substrate 200 to achieve normal display of the display panel 10. The display panel 10 in this application is mainly for large-size displays, such as those larger than 55 inches, and adopts a 3T-8-chip pixel design. This design makes the rotation angles of the liquid crystal molecules in the four chips of the main pixel and the four chips of the auxiliary pixel within the same sub-pixel different, thereby improving viewing angle distortion.

[0057] Compared to the traditional 4-pixel display panel 10, the 8-pixel design requires two additional active switches and a voltage divider routing line. Furthermore, the data line 115 is usually shielded with a metal shielding layer on both sides to block the signal, which further obstructs the light, reduces the pixel aperture ratio, and affects the display effect of the display panel 10.

[0058] To address the aforementioned issues, this application improves the array substrate 100 of the display panel 10 by setting a first electrode layer 140 above the color resist layer 120 at a position corresponding to the data line 115. Since the first electrode layer 140 is on a different layer from the pixel electrode 160, the width of the first electrode layer 140 covering the data line 115 direction can be increased without being limited or affected by the pixel electrode 160. This allows the orthogonal projection of the first electrode layer 140 onto the substrate 150 to cover the orthogonal projection of the pixel electrode 160 onto the substrate 150. When a voltage is applied to the first electrode layer 140, the first electrode layer 140 replaces the shielding metal layers originally disposed on both sides of the data line 115. By shielding the data line 115 signal, the original shielding metal layers on both sides of the data line 115 can be eliminated to avoid the shielding metal layers blocking light. At the same time, the parallel plate capacitor formed between the pixel electrode 160 and the first electrode layer 140 has a shorter spacing than the original parallel plate capacitor formed between the pixel electrode 160 and the first metal layer 110, which can effectively increase the storage capacitance of the pixel. Furthermore, without the original shielding metal layer blocking light, and since the first electrode layer 140 is made of transparent material, even if the width of the first electrode layer 140 is increased, normal light transmission can still be guaranteed. This can effectively improve the pixel aperture ratio and further improve the display quality of the display panel 10.

[0059] It should be noted that the inventive concept of this application can form many embodiments, but due to the limited space of the application documents, they cannot all be listed. Therefore, without conflict, the embodiments described above or the technical features can be arbitrarily combined to form new embodiments. After the embodiments or technical features are combined, the original technical effect will be enhanced.

[0060] The above description, in conjunction with specific optional embodiments, provides a further detailed explanation of this application and should not be construed as limiting the specific implementation of this application to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of this application, and all such modifications or substitutions should be considered within the scope of protection of this application.

Claims

1. An array substrate, comprising a substrate, and a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, a color resist layer, and a passivation layer sequentially stacked on the substrate. Its features are: A pixel electrode is disposed on the passivation layer, a data line is formed on the second metal layer, and a first electrode layer is disposed between the color resist layer and the pixel electrode. The first electrode layer is made of a transparent material; the first electrode layer corresponds to the position of the data line. The orthographic projection of the first electrode layer on the substrate covers the orthographic projection of the pixel electrode on the substrate; the first electrode layer is connected to a common voltage signal; The array substrate is divided into a display area and a non-display area in the planar direction. The display area is a main pixel area and an auxiliary pixel area. The pixel electrode includes a main pixel electrode and an auxiliary pixel electrode. The main pixel electrode is located in the main pixel area and the auxiliary pixel electrode is located in the auxiliary pixel area. The data lines are located on both sides of the non-display area. The first metal layer has a gate line formed thereon; the first electrode layer includes a main body, a first extension and a second extension, the main body being connected to the first extension and the second extension respectively, the main body being positioned corresponding to the data line, the first extension being located on the side of the gate line closer to the main pixel electrode, the second extension being located on the side of the gate line closer to the auxiliary pixel electrode, and the first extension partially overlapping with the main pixel electrode to form a storage capacitor, and the second extension partially overlapping with the auxiliary pixel electrode to form a storage capacitor; The array substrate further includes a first active switch, a second active switch, and a third active switch. The first active switch, the second active switch, and the third active switch are all disposed on the substrate. The source of the first active switch is connected to the data line. The second active switch and the first active switch share the source. The drain of the first active switch is connected to the main pixel electrode. The drain of the second active switch is connected to the auxiliary pixel electrode. The source of the third active switch is the drain of the second active switch. The drain of the third active switch is connected to the first extension through the second via. The passivation layer includes a first passivation layer and a second passivation layer, the second passivation layer is located on the first passivation layer, the pixel electrode is disposed on the second passivation layer, the first electrode layer is located between the first passivation layer and the second passivation layer, and the second via is formed in the first passivation layer; The first extension includes a first sub-extension and a second sub-extension. The first sub-extension avoids the drain of the first active switch and does not overlap with the drain of the first active switch. The second extension overlaps with the second via. The orthographic projection of the second via is entirely within the orthographic projection of the second extension and covers the area between the second via and the main body. The main pixel electrode has a first protrusion and a second protrusion on the side near the gate line. The drain portion of the first active switch overlaps with the first protrusion. The second protrusion partially overlaps with the second sub-extension and avoids the second via. There is a gap between the second sub-extension and the drain of the first active switch. The drain of the second active switch includes a first connection trace, a second connection trace, and a drain body connected in sequence. The first connection trace is perpendicular to the second connection trace in a plane. The second connection trace is parallel to the second extension. The second connection trace is located below the second extension. The projected area of ​​the second extension on the substrate is larger than the projected area of ​​the second connection trace on the substrate.

2. The array substrate as described in claim 1, characterized in that, The area of ​​the first extension is greater than the area of ​​the second extension, and the overlap area between the first extension and the main pixel electrode is greater than the overlap area between the second extension and the auxiliary pixel electrode.

3. The array substrate as described in claim 2, characterized in that, The passivation layer includes a first passivation layer and a second passivation layer, with the second passivation layer located on top of the first passivation layer. The pixel electrode is disposed on the second passivation layer, the first electrode layer is located between the first passivation layer and the second passivation layer, and the second via is formed in the first passivation layer; The projected area of ​​the first electrode layer on the substrate is greater than or equal to the projected area of ​​the data line on the substrate; The first electrode layer partially overlaps with the color resist layer on the side closest to the data line.

4. The array substrate as described in claim 3, characterized in that, A first shielding layer is provided between the first electrode layer and the color resist layer. The first shielding layer is positioned corresponding to the data line, and the width of the first shielding layer is greater than the width of the data line. The first shielding layer shields the data line.

5. The array substrate as described in claim 4, characterized in that, The first metal layer also has a scan line, and a second shielding layer is disposed between the first electrode layer and the color resist layer. The second shielding layer is disposed corresponding to the position of the scan line, and the width of the second shielding layer is greater than the width of the scan line. The second shielding layer shields the scan line.

6. A display panel, comprising a color filter substrate, characterized in that, The display panel further includes an array substrate as described in any one of claims 1 to 5, wherein the array substrate and the color filter substrate are disposed in a cell-to-cell configuration.

Images