Display panel, display screen and electronic device

Abstract

The application relates to a display panel, a display screen and an electronic device. The display panel comprises a display area and a non-display area arranged around the display area, the non-display area comprising a fan-out area and a special-shaped area adjacent to the fan-out area; the display panel further comprises a pixel circuit, a plurality of data signal lines, a plurality of scanning signal lines, a plurality of first fan-out wires and a plurality of second fan-out wires, the scanning signal lines comprising corresponding transmission line parts and winding parts, each data signal line, each transmission line part and each first fan-out wire being located in the display area, each second fan-out wire being located in the fan-out area, the second fan-out wire being connected with the data signal line through the first fan-out wire; and the plurality of winding parts are located in the special-shaped area, wherein at least two winding parts belonging to different scanning signal lines are located in a plurality of film layers respectively. The display panel can realize narrow-frame design of the fan-out area position and narrow-frame design at the special-shaped area, and improve the display ratio of the display panel.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a display panel, display screen and electronic device. Background Technology

[0002] With the continuous development of technology, people have higher and higher requirements for the appearance of display products. Full-screen displays have become popular in the market, making it particularly important to reduce the bezels of the display screen and increase the screen-to-body ratio.

[0003] Currently, narrow bezel designs are mainly achieved by compressing signal trace dimensions. However, the space for compressing signal trace dimensions is limited, and compressing signal trace dimensions increases manufacturing complexity and reduces yield. Summary of the Invention

[0004] Therefore, it is necessary to provide a display panel, display screen, and electronic device that can achieve narrow bezel design in the fan-out area and narrow bezel design in the irregular area, so as to avoid some areas being relatively prominent and ensure the overall coordination and overall appearance of the display panel.

[0005] In a first aspect, embodiments of this application provide a display panel, including: a display area and a non-display area disposed around the display area, wherein the non-display area includes a fan-out area and an irregularly shaped area adjacent to the fan-out area;

[0006] The display panel further includes a pixel circuit, multiple data signal lines, multiple scan signal lines, multiple first fan-out traces, and multiple second fan-out traces. Each scan signal line includes a correspondingly connected transmission line portion and a winding portion. Each of the data signal lines, each of the transmission line portions, and each of the first fan-out traces are located in the display area, and each of the second fan-out traces is located in the fan-out area. The second fan-out traces are connected to the data signal lines through the first fan-out traces.

[0007] Multiple winding portions are located within the irregular region. The scanning signal line is used to provide a scanning signal to the pixel circuit, and the data signal line is used to provide a data signal to the pixel circuit. The pixel circuit drives the light-emitting element to emit light based on the received scanning signal and data signal. At least two winding portions belonging to different scanning signal lines are located in multiple film layers.

[0008] Secondly, embodiments of this application also provide a display screen, including a cover plate and a display panel as described in the first aspect.

[0009] Thirdly, embodiments of this application also provide an electronic device, including a display screen as described in the second aspect.

[0010] The display panel, display screen, and electronic device provided in this application embodiment include a display area and a non-display area surrounding the display area. The non-display area includes a fan-out area and an irregularly shaped area adjacent to the fan-out area. Since each of the data signal lines, each of the transmission lines, and each of the first fan-out traces are located in the display area, and each of the second fan-out traces is located in the fan-out area, and the second fan-out traces are connected to the data signal lines within the display area through the first fan-out traces, the length of the fan-out traces located in the fan-out area can be reduced compared to related technologies. That is, the length of the second fan-out traces can be less than the length of the fan-out traces in related technologies, thereby achieving a narrow bezel design in the fan-out area. Since the data signal lines are not wound in the irregularly shaped area, there is free space for winding in the irregularly shaped area. Therefore, each winding part can be located in multiple film layers, and the winding part can use multiple film layers for wiring, achieving a narrow bezel design in the irregularly shaped area. By designing the narrow bezels in the fan-out area and the irregularly shaped area, the display ratio of the display panel can be increased, and the overall visual appeal of the display panel can be improved. Attached Figure Description

[0011] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application;

[0012] Figure 2 This is a schematic diagram of the wiring within the display area provided in an embodiment of this application;

[0013] Figure 3 This is a cross-sectional schematic diagram of a display panel in an irregularly shaped area according to an embodiment of this application;

[0014] Figure 4 This is a cross-sectional schematic diagram of a display panel in the display area provided in an embodiment of this application;

[0015] Figure 5 This is a schematic diagram of the planar structure of a display panel provided in an embodiment of this application;

[0016] Figure 6 This is a schematic diagram of the pixel circuit provided in an embodiment of this application;

[0017] Figure 7 This is a schematic diagram of the pixel circuit provided in another embodiment of this application;

[0018] Figure 8 A schematic diagram of the planar structure of a display panel provided in another embodiment of this application;

[0019] Figure 9 A schematic diagram of the planar structure of a display panel provided in yet another embodiment of this application;

[0020] Figure 10 A schematic diagram of the planar structure of a display panel provided in yet another embodiment of this application;

[0021] Figure 11 A schematic diagram of the planar structure of a display panel provided in yet another embodiment of this application;

[0022] Figure 12 A schematic diagram of the planar structure of a display panel provided in yet another embodiment of this application;

[0023] Figure 13 This is a schematic diagram of the structure of a display screen provided in an embodiment of this application;

[0024] Figure 14 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0025] Explanation of reference numerals in the attached figures:

[0026] 11-Display area, 101-Substrate, 102-First insulating layer, 103-Second insulating layer, 104-Third insulating layer, 105-Interlayer insulating layer, 106-First planarization layer, 107-Second planarization layer, 108-Third planarization layer, 109-Pixel definition layer, 1011-Fourth insulating layer, 1012-Low-temperature polysilicon active layer, 1013-Oxide active layer, 1014-Anode layer, 110-Pixel circuit, 1101-Data writing module 1102 - Threshold compensation module, 1103 - First initialization module, 1104 - Second initialization module, 1105 - Third initialization module, 1106 - First light emission control module, 1107 - Second light emission control module, 111 - Data signal line, 112 - Scan signal line, 11201 - Transmission line section, 11202 - Winding section, 1121 - First scan signal line, 11211 - First transmission line section, 11212 - First winding section, 1122 - ... Second scan signal line, 11221 - Second transmission line section, 11222 - Second winding section, 1123 - Third scan signal line, 11231 - Third transmission line section, 11232 - Third winding section, 1124 - Fourth scan signal line, 11241 - Fourth transmission line section, 11242 - Fourth winding section, 1125 - Fifth scan signal line, 11251 - Fifth transmission line section, 11252 - Fifth winding section, 113 - First sector output line, 12 - Non-display area 121-Binding area, 1211-Display driver chip, 122-Fan-out area, 1221-Second fan-out trace, 123-Irregular area, 124-Gate driving unit, 1241-First gate driving unit, 1242-Second gate driving unit, 1243-Third gate driving unit, 1244-Fourth gate driving unit, 1245-Fifth gate driving unit, 10-Display panel, 100-Display screen, 1100-Cover plate, 1000-Electronic device. Detailed Implementation

[0027] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a thorough and complete understanding of the disclosure of this application.

[0028] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0029] When describing positional relationships, unless otherwise specified, when an element, such as a layer, film, or substrate, is referred to as being "on" another element, it may be directly on the other element or there may be intermediate elements present. Furthermore, when a layer is referred to as being "below" another layer, it may be directly below it or there may be one or more intermediate elements present. It is also understood that when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intermediate elements present.

[0030] When using the terms “including,” “having,” and “comprising” as described herein, another component may be added unless explicitly qualifying terms such as “only,” “consisting of,” etc. are used. Unless otherwise stated, singular terms may include plural forms and should not be construed as having a quantity of one.

[0031] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this application, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0032] It should also be understood that, in interpreting an element, although not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of a particular value as determined by a person skilled in the art. For example, "approximately," "about," or "substantially" can mean within one or more standard deviations, without limitation herein.

[0033] Furthermore, in the instruction manual, the phrase "planar distribution diagram" refers to the diagram when the target part is viewed from above, and the phrase "cross-sectional diagram" refers to the diagram when the target part is viewed from the side as a cross-section taken by vertically cutting the target part.

[0034] Furthermore, the accompanying drawings are not drawn to a 1:1 scale, and the relative dimensions of the components are shown in the drawings only as examples and not necessarily to actual scale.

[0035] As described in the background section, narrow bezel designs are primarily achieved by compressing signal trace dimensions. However, the space for compressing signal trace dimensions is limited, and compressing signal trace dimensions increases manufacturing complexity and reduces yield.

[0036] Based on the aforementioned technical problems, the inventors discovered that by connecting the fan-out traces and data signal lines within the display area, the trace length in the fan-out area can be reduced, which is beneficial for achieving a narrower bottom bezel. Furthermore, since the data signal lines are not wound around the irregularly shaped areas on both sides of the fan-out area, there is free space for winding in these areas. Therefore, each winding portion can be located in multiple film layers, allowing the winding portion to utilize multiple film layers for routing, thus achieving a narrow bezel design in the irregularly shaped areas. Based on this, the inventors further developed the technical solution of the embodiments of this application. Specifically, the display panel provided in this application embodiment includes: a display area and a non-display area surrounding the display area, the non-display area including a fan-out area and an irregularly shaped area adjacent to the fan-out area; the display panel also includes a pixel circuit, multiple data signal lines, multiple scan signal lines, multiple first fan-out traces and multiple second fan-out traces, the scan signal lines including correspondingly connected transmission line portions and winding portions, each data signal line, each transmission line portion and each first fan-out trace being located in the display area, each second fan-out trace being located in the fan-out area, and the second fan-out traces being connected to the data signal lines through the first fan-out traces; multiple winding portions being located within the irregularly shaped area, the scan signal lines providing scan signals to the pixel circuit, the data signal lines providing data signals to the pixel circuit, the pixel circuit driving the light-emitting element to emit light based on the received scan signals and data signals, wherein at least two winding portions belonging to different scan signal lines are respectively located in multiple film layers.

[0037] The aforementioned display panel includes a display area and a non-display area surrounding the display area. The non-display area includes a fan-out area and an irregularly shaped area adjacent to the fan-out area. Since each of the data signal lines, each of the transmission lines, and each of the first fan-out traces are located in the display area, and each of the second fan-out traces is located in the fan-out area, with the second fan-out traces connected to the data signal lines within the display area via the first fan-out traces, the length of the fan-out traces located in the fan-out area can be reduced compared to related technologies. Specifically, the length of the second fan-out traces can be less than the length of the fan-out traces in related technologies, thereby achieving a narrow bezel design in the fan-out area. Furthermore, since the data signal lines are not wound in the irregularly shaped area, there is free space for winding in the irregularly shaped area. Therefore, each winding portion can be located in multiple film layers, allowing the winding portion to use multiple film layers for routing, achieving a narrow bezel design in the irregularly shaped area. By designing narrow bezels in the fan-out area and the irregularly shaped area, the display ratio of the display panel can be increased, improving the overall visual appeal of the display panel.

[0038] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0039] Figure 1 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application; Figure 2 This is a schematic diagram of the wiring within the display area 11 provided in an embodiment of this application. (In conjunction with...) Figure 1 and Figure 2 As shown, the display panel provided in this application embodiment includes: a display area 11 and a non-display area 12 disposed around the display area 11. The non-display area 12 includes a fan-out area 122 and an irregularly shaped area 123 adjacent to the fan-out area 122.

[0040] The display panel also includes a pixel circuit 110, multiple data signal lines 111, multiple scan signal lines 112, multiple first fan-out traces 113, and multiple second fan-out traces 1221. The scan signal lines 112 include correspondingly connected transmission line portions 11201 and winding portions 11202. The transmission line portions 11201 of each data signal line 111 and each scan signal line 112 and each first fan-out trace 113 are located in the display area 11. The winding portions 11202 of the multiple scan signal lines 112 are located in the irregular area 123. Each second fan-out trace 1221 is located in the fan-out area 122. The second fan-out traces 1221 are connected to the data signal lines 111 through the first fan-out traces 113.

[0041] In the application, the non-display area 12 may also include a bonding area 121, and a fan-out area 122 is located between the bonding area 121 and the display area 11. The bonding area 121 contains a display driver chip 1211, which is connected to each of the second fan-out traces 1221. It can be understood that the display driver chip 1211 outputs a data signal to the second fan-out trace 1221, which is then transmitted via the second fan-out trace 1221 and the first fan-out trace 113 to the data signal line 111, and finally to the pixel circuit 110 via the data signal line 111.

[0042] In related technologies, the display panel has a display area and a fan-out area. The display panel includes fan-out traces and data signal lines. Part of the data signal lines are located in the display area and part are located in the fan-out area. The fan-out traces are located in the fan-out area and are connected to the data signal lines in the fan-out area, resulting in a larger width of the fan-out area, which in turn results in a wider bottom bezel of the display panel.

[0043] In this embodiment, the first fan-out trace 113 is connected to the data signal line 111 within the display area 11, which shortens the length of the fan-out trace within the fan-out area 122. This means the second fan-out trace 1221 can be shorter, thereby narrowing the width of the fan-out area 122 and preventing the data signal line 111 from winding around in the irregular area 123, leaving unused winding space in the irregular area 123. The area of ​​the fan-out area 122 is a key factor determining the width of the bottom bezel of the display panel. Therefore, in this embodiment, the display panel can achieve a narrower bottom bezel by reducing the length of the second fan-out trace 1221.

[0044] Based on this, multiple winding portions 11202 are located within the irregular region 123. The scanning signal line 112 provides scanning signals to the pixel circuit 110, and the data signal line 111 provides data signals to the pixel circuit 110. The pixel circuit 110 drives the light-emitting element to emit light based on the received scanning signal and data signal. At least two winding portions 11202 belonging to different scanning signal lines are located in multiple film layers respectively.

[0045] It is understandable that since the data signal line 111 is not wound in the irregular area 123, there is free space for winding in the irregular area 123. Therefore, each winding part 11202 can be located in multiple film layers, allowing the winding part 11202 to use multiple film layers for routing, thus achieving the narrow bezel design at the irregular area 123. Furthermore, by designing the narrow bezel at the fan-out area 122 and the narrow bezel at the irregular area 123, the display ratio of the display panel can be increased. In addition, it can prevent the bezel area of ​​the irregular area 123 from protruding excessively relative to the fan-out area 122, ensuring the overall harmony and visual appeal of the display panel.

[0046] The aforementioned display panel includes a display area 11 and a non-display area 12 surrounding the display area 11. The non-display area 12 includes a bonding area 121, a fan-out area 122, and irregularly shaped areas 123 located on both sides of the fan-out area 122. The fan-out area 122 is located between the bonding area 121 and the display area 11. The display area 11 is provided with multiple data signal lines 111, multiple scan signal lines 112, and multiple first fan-out traces 113. The fan-out area 122 is provided with multiple second fan-out traces 1221, which pass through the first fan-out traces 113. The first fan-out trace 113 is connected to the data signal line 111. Since the first fan-out trace 113 is connected to the data signal line 111 within the display area 11, the trace length in the fan-out area 122 can be reduced, thereby achieving a narrow bezel design in the fan-out area 122. Because the data signal line 111 is not wound in the irregular area 123, there is free space for winding in the irregular area 123. Therefore, each winding portion 11202 can be located in multiple film layers, allowing the winding portion 11202 to use multiple film layers for routing, thus achieving a narrow bezel design in the irregular area 123. By designing a narrow bezel in the fan-out area 122 and a narrow bezel in the irregular area 123, relatively protruding areas can be avoided, ensuring the overall coordination and aesthetic appeal of the display panel.

[0047] In one embodiment, the multiple scan signal lines 112 include various types of scan signal lines 112, and different types of scan signal lines 112 are used to transmit different scan signals.

[0048] It is understood that the pixel circuit 110 includes various types of transistors, and different types of scan signal lines 112 are connected to the gates of corresponding types of transistors to control the on / off state of the corresponding transistors. Various types of winding portions 11202 are connected to various corresponding types of transmission line portions 11201, allowing scan signals to be transmitted to the corresponding type of transmission line portion 11201, so that scan signals can be output to the pixel circuit 110 through the transmission line portion 11201. Furthermore, by placing at least two winding portions 11202 belonging to different scan signal lines 112 in different film layers, the scan signal lines 112 can be routed using multiple film layers in the irregular region 123, reducing the area occupied by the winding portions 11202 in the irregular region 123. This allows for compression of the bezel area corresponding to the irregular region 123, achieving a narrow bezel design at the location of the irregular region 123.

[0049] Figure 3 This is a cross-sectional schematic diagram of a display panel in the irregular region 123 according to an embodiment of this application. In one embodiment, as... Figure 3As shown, the display panel includes a substrate and a first gate layer GE1, a second gate layer GE2, a third gate layer GE3, a first source layer SD1, and a second source layer SD2, sequentially located away from the substrate. Each winding portion 11202 is located in multiple layers of the first gate layer GE1, the second gate layer GE2, the third gate layer GE3, the first source layer SD1, and the second source layer SD2. The first gate layer GE1, the second gate layer GE2, the third gate layer GE3, the first source layer SD1, and the second source layer SD2 are conductive layers, and may be metal conductive layers.

[0050] In applications, the scan signal lines can be divided into multiple parts according to their type, so that the winding portions 11202 belonging to different types of scan signal lines 112 are located in different film layers. For example, the winding portion 11202 of the first type of scan signal line 112 is located in the first gate layer GE1, and the winding portion 11202 of the second type of scan signal line 112 is located in the second gate layer GE2.

[0051] Among them, such as Figure 3 As shown, substrate 101 may include multiple film layers. For example, substrate 101 may include a substrate and a buffer layer. No specific limitations are made here regarding the film layers included in substrate 101. A first insulating layer 102 may be disposed between substrate 101 and the first gate layer GE1. A second insulating layer 103 may be disposed between the first gate layer GE1 and the second gate layer GE2. A third insulating layer 104 may be disposed between the second gate layer GE2 and the third gate layer GE3. An interlayer insulating layer 105 may be disposed between the third gate layer GE3 and the first source layer SD1. A first planarization layer 106 may be disposed between the first source layer SD1 and the second source layer SD2. A second planarization layer 107 may be disposed on the exposed surfaces of the first planarization layer 106 and the second source layer SD2.

[0052] Taking a display panel using LTPO (Low Temperature Polycrystalline Oxide) technology as an example, the pixel circuit 110 of the display panel includes a storage capacitor Cst, a low temperature polycrystalline silicon transistor and a metal oxide transistor. The gate of the low temperature polycrystalline silicon transistor and the first plate of the storage capacitor Cst can be located in the first gate layer GE1, the second plate of the storage capacitor Cst can be located in the second gate layer GE2, the metal oxide transistor can be a top-bottom dual-gate structure, the gate of the metal oxide transistor can be located in the second gate layer GE2 and the third gate layer GE3, and some signal lines can be located in the first source layer SD1 or the second source layer SD2.

[0053] Figure 4 This is a cross-sectional schematic diagram of the display panel in the display area according to an embodiment of this application. Figure 4As shown, the display panel includes a substrate 101 and multiple stacked film layers on the surface of the substrate 101. Specifically, the display panel may further include a low-temperature polysilicon active layer 1012, an oxide active layer 1013, a fourth insulating layer 1011, a third planarization layer 108, an anode layer 1014, and a pixel definition layer 109. The substrate 101 may include multiple film layers; for example, the substrate 101 may include a substrate and a buffer layer. No specific limitations are placed on the film layers included in the substrate 101. A low-temperature polysilicon active layer 1012 may be disposed between the substrate 101 and the first insulating layer 102. The first insulating layer 102 may be disposed on the surface of the substrate 101 and the low-temperature polysilicon active layer 1012 away from the substrate 101. A first gate layer GE1 is disposed between the first insulating layer 102 and the second insulating layer 103. A second gate layer GE2 may be disposed between the second insulating layer 103 and the third insulating layer 104. An oxide active layer 1013 is located on the surface of the third insulating layer 104 away from the substrate 101. A fourth insulating layer 1011 is disposed on the surface of the oxide active layer 1013 and the third insulating layer 104 away from the substrate 101. An interlayer insulating layer 105 is disposed on the surface of the fourth insulating layer 1011 away from the substrate 101. The interlayer insulating layer 105 is located away from the substrate. A first source layer SD1 may be disposed on the surface of substrate 101. A first planarization layer 106 may be disposed on the surface of interlayer insulating layer 105 and the first source layer SD1 away from substrate 101. A second source layer SD2 may be disposed on the surface of the first planarization layer 106 away from substrate 101. A second planarization layer 107 may be disposed on the surface of the first planarization layer 106 and the second source layer SD2 away from substrate 101. The second source layer SD2 may also be disposed on the surface of the second planarization layer 107 away from substrate 101. A third planarization layer 108 may be disposed on the surface of the second planarization layer 107 and the second source layer SD2 away from substrate 101. An anode layer 1014 and a pixel definition layer 109 may be disposed on the surface of the third planarization layer 108 away from substrate 101.

[0054] In this embodiment, by having at least two winding portions 11202 belonging to different scan signal lines 112 located in multiple layers of the first gate layer GE1, the second gate layer GE2, the third gate layer GE3, the first source layer SD1, and the second source layer SD2, the scan signal lines 112 are routed in the irregular region 123 using multiple film layers, thereby reducing the area occupied by the winding portions 11202 of the scan signal lines 112 in the irregular region 123 and achieving a narrow bezel design at the location of the irregular region 123.

[0055] Figure 5 This is a schematic diagram of the planar structure of a display panel provided in one embodiment of this application. In one embodiment, such as... Figure 5As shown, the multiple scan signal lines 112 include multiple first scan signal lines 1121, and the first scan signal lines 1121 include a first transmission line portion 11211 and a first winding portion 11212 that are connected accordingly.

[0056] The first winding portion 11212 is used to transmit a first scan signal to the first transmission line portion 11211. The first transmission line portion 11211 is used to provide the first scan signal to the pixel circuit 110. The first scan signal affects the data writing of the pixel circuit 110.

[0057] Figure 6 This is a schematic diagram of the structure of a pixel circuit 110 provided in an embodiment of this application; Figure 7 This is a schematic diagram of a pixel circuit 110 provided in another embodiment of this application. In applications, such as… Figure 6 and Figure 7 As shown, the pixel circuit 110 may include: a driving transistor T3, a storage capacitor Cst, and a data writing module 1101. The first terminal of the data writing module 1101 is used to receive data signals, the second terminal of the data writing module 1101 is connected to the first terminal of the driving transistor T3, and the control terminal of the data writing module 1101 is used to receive a first scan signal. It can be understood that the first scan signal is used to control the on / off state of the data writing module 1101, and since the data signal needs to pass through the data writing module 1101 before it can be input into the pixel circuit 110, the first scan signal can affect the data writing process of the pixel circuit 110.

[0058] It should be noted that, Figure 6 In this code, P_Gate is the first scan signal, N_Gate is the second scan signal, H_Reset is the third scan signal, N_Reset is the fourth scan signal, EM is the light emission control signal, ELVDD is the first power supply signal, ELVSS is the second power supply signal, Vinit1 is the first initialization signal, Vinit2 is the second initialization signal, Vinit3 is the third initialization signal, and data is the data signal. Figure 7 In this code, PGate is the first scan signal, NGate is the second scan signal, H_Reset is the third scan signal, P_Reset is the fourth scan signal, EM is the light emission control signal, ELVDD is the first power supply signal, ELVSS is the second power supply signal, Vinit1 is the first initialization signal, Vinit2 is the second initialization signal, Vinit3 is the third initialization signal, and data is the data signal.

[0059] It is understood that after receiving the first scan signal, the first winding section 11212 transmits the first scan signal to the first transmission line section 11211, thereby providing the first scan signal to the pixel circuit 110 through the first transmission line section 11211 and controlling the data writing process of the pixel circuit 110.

[0060] In one embodiment, such as Figure 3 and Figure 5 As shown, the first transmission line portion 11211 is located in the first gate layer GE1, and the first winding portion 11212 is located in the third gate layer GE3.

[0061] In the application, the data writing module 1101 includes a data writing transistor T4. A first scan signal line 1121 is connected to the gate of the data writing transistor T4. The data writing transistor T4 is typically a low-temperature polysilicon transistor (LTPS). As mentioned earlier, the gate of the LPS is located in the first gate layer GE1. Therefore, to facilitate the connection between the first scan signal line 1121 and the gate of the data writing transistor T4, the first scan signal line 1121 is located in the first gate layer GE1. The first winding portion 11212 can be wound around the irregular region 123 and then connected to the first transmission line portion 11211 to transmit the first scan signal to the first transmission line portion 11211. Therefore, the first winding portion 11212 can be located in a different film layer than the first transmission line portion 11211. For example, the first winding portion 11212 can be located in the third gate layer GE3.

[0062] It should be noted that the first winding portion 11212 being located in the third gate layer GE3 is an example of this embodiment. In practice, the first winding portion 11212 can also be located in other film layers, such as the second gate layer GE2.

[0063] In one embodiment, such as Figure 5 As shown, multiple first gate driving units 1241 are respectively provided in the irregular regions 123 on both sides of the fan-out region 122. Each first gate driving unit 1241 is connected to a first transmission line 11211 via a first winding part 11212. The first gate driving unit 1241 is used to output the first scan signal.

[0064] It is understood that multiple first gate driving units 1241 are respectively provided in the irregular areas 123 on both sides of the fan-out area 122. Each first gate driving unit 1241 is connected to a first transmission line 11211 via a first winding part 11212. Thus, bilateral driving can be achieved through the first gate driving units 1241 on both sides of the fan-out area 122. Moreover, the first gate driving units 1241 all adopt a 1-to-1 design, thereby ensuring the driving capability of the first gate driving units 1241 and improving the display effect.

[0065] Figure 8A schematic diagram of the planar structure of a display panel provided in another embodiment of this application. In one embodiment, such as Figure 8 As shown, the multiple scan signal lines 112 include multiple second scan signal lines 1122, and the second scan signal lines 1122 include correspondingly connected second transmission line portions 11221 and second winding portions 11222.

[0066] The second winding portion 11222 is used to transmit the second scan signal to the second transmission line portion 11221. The second transmission line portion 11221 is used to provide the second scan signal to the pixel circuit 110. The second scan signal affects the gate potential of the driving transistor T4 of the pixel circuit 110.

[0067] Based on the above embodiments, such as Figure 6 and Figure 7 As shown, the pixel circuit 110 may further include a threshold compensation module 1102. The first terminal of the threshold compensation module 1102 is connected to the second terminal of the driving transistor T3, and the second terminal of the threshold compensation module 1102 is connected to the gate of the driving transistor T3. The control terminal of the threshold compensation module 1102 is used to receive a second scan signal. It can be understood that the second scan signal is used to control the on / off state of the threshold compensation module 1102. Since the data signal needs to pass through the data writing module 1101 and the threshold compensation module 1102 before it can be written to the gate of the driving transistor, the first scan signal can affect the gate of the driving transistor in the pixel circuit 110.

[0068] It is understood that after the second winding part 11222 receives the second scan signal, it transmits the second scan signal to the second scan signal line 1122, thereby providing the second scan signal to the pixel circuit 110 through the second scan signal line 1122, and cooperating with the first scan signal to control the data writing process of the pixel circuit 110.

[0069] In one embodiment, such as Figure 3 and Figure 8 As shown, the second transmission line portion 11221 is located in the second gate layer GE2 and the third gate layer GE3, and the second winding portion 11222 is located in the first gate layer GE1.

[0070] In the application, the threshold compensation module 1102 includes a threshold compensation transistor T2. The second scan signal line 1122 is connected to the gate of the threshold compensation transistor T2. The threshold compensation transistor T2 is usually a metal oxide transistor, and metal oxide transistors often have a top-bottom dual-gate structure. The top and bottom dual gates of the metal oxide transistor are located in the third gate layer GE3 and the second gate layer GE2, respectively. Therefore, in order to facilitate the connection between the second transmission line portion 11221 and the gate of the threshold compensation transistor T2, the second transmission line portion 11221 is located in the second gate layer GE2 and the third gate layer GE3. The second winding portion 11222 can be connected to the second scan signal line 1122 after winding in the irregular region 123, and transmit the second scan signal to the second transmission line portion 11221. Therefore, the second winding portion 11222 can be located in other film layers different from the second transmission line portion 11221. For example, the second winding portion 11222 can be located in the first gate layer GE1. In conjunction with the aforementioned embodiment, the first winding portion 11212 is located in the third gate layer GE3. Thus, the first winding portion 11212 and the second winding portion 11222 are located in different layers, so that the winding portion 1231 of the irregular region 123 uses multiple film layers for wiring, thereby realizing the narrow bezel design at the irregular region 123.

[0071] It should also be noted that the second winding portion 11222 being located in the first gate layer GE1 is an example of this embodiment. The second winding portion 11222 can also be located in other film layers, such as the third gate layer GE3.

[0072] In one embodiment, such as Figure 8 As shown, a plurality of second gate driving units 1242 are also provided in the irregular region 123 on the first side of the fan-out region 122. Each second gate driving unit 1242 is connected to two second transmission line sections 11221 via two second winding sections 11222. The second gate driving unit 1242 is used to output a second scan signal.

[0073] It is understood that multiple second gate driving units 1242 are provided in the irregular area 123 on the first side of the fan-out region 122. Each second gate driving unit 1242 is connected to two second transmission line sections 11221 via two second winding sections 11222. The second gate driving unit 1242 adopts a 1-drive-2 design, thereby reducing the number of second gate driving units 1242 in the irregular area 123 on the first side of the fan-out region 122. This can reduce the area occupied by the second gate driving unit 1242 in the irregular area 123 on the first side of the fan-out region 122, which is beneficial to narrowing the corresponding frame of the irregular area 123 on the first side of the fan-out region 122.

[0074] Figure 9 This is a schematic diagram of the planar structure of a display panel provided in another embodiment of this application. In one embodiment, such as Figure 9As shown, the multiple scan signal lines 112 include multiple third scan signal lines 1123, and the third scan signal lines 1123 include a third transmission line portion 11231 and a third winding portion 11232 that are connected accordingly.

[0075] The third winding section 11232 is used to output the third scanning signal to the third transmission line section 11231. The third scanning signal affects the initialization of the first electrode potential of the driving transistor T3 in the pixel circuit 110 and the anode potential of the light-emitting element.

[0076] Based on the foregoing embodiments, such as Figure 6 and Figure 7 As shown, the pixel circuit 110 may further include: a first initialization module 1103 and a second initialization module 1104. The first terminal of the first initialization module 1103 is used to receive a first initialization signal, the second terminal of the first initialization module 1103 is connected to the first electrode of the driving transistor T3, and the control terminal of the first initialization module 1103 is used to receive a third scan signal. The first terminal of the second initialization module 1104 is used to receive a second initialization signal, the second terminal of the second initialization module 1104 is connected to the anode of the light-emitting element, and the control terminal of the second initialization module 1104 is also used to receive the third scan signal. In the first initialization stage, the first initialization module 1103 and the second initialization module 1104 are respectively turned on in response to the third scan signal. The first initialization signal is written to the first electrode of the driving transistor T3 through the first initialization module 1103 to initialize the potential of the first electrode of the driving transistor T3. The second initialization signal is written to the anode of the light-emitting element through the second initialization module 1104 to initialize the potential of the anode of the light-emitting element. Therefore, the second scan signal affects the initialization of the first electrode potential of the driving transistor and the anode potential of the light-emitting element in the pixel circuit 110.

[0077] It can be understood that after the third winding section 11232 receives the third scan signal, it transmits the third scan signal to the third transmission line section 11231 for connection, thereby providing the third scan signal to the pixel circuit 110 through the third transmission line section 11231, and controlling the initialization process of the first pole potential of the driving transistor and the anode potential of the light-emitting element in the pixel circuit 110.

[0078] In one embodiment, such as Figure 3 and Figure 9 As shown, the third transmission line portion 11231 is located in the first gate layer GE1, and the third winding portion 11232 is located in the second source layer SD2.

[0079] The first initialization module 1103 includes a first initialization transistor T8, and the second initialization module 1104 includes a second initialization transistor T7. A third scan signal line 1123 is connected to the gates of the first initialization transistor T8 and the second initialization transistor T7, respectively. The first initialization transistor T8 and the second initialization transistor T7 are typically low-temperature polysilicon transistors. Therefore, the gates of the first initialization transistor T8 and the second initialization transistor T7 are located in the first gate layer GE1. To facilitate the connection of the third transmission line portion 11231 to the gates of the first initialization transistor T8 and the second initialization transistor T7, the third transmission line portion 11231 is located in the first gate layer GE1. The third winding portion 11232 can be wound around the irregular region 123 and then connected to the third transmission line portion 11231 to transmit the third scan signal to the third transmission line portion 11231. Therefore, the third winding portion 11232 can be located in a different film layer than the third transmission line portion 11231. For example, the third winding portion 11232 can be located in the second source layer SD2. In conjunction with the above embodiment, the first winding portion 11212 is located in the third gate layer GE3, and the second winding portion 11222 can be located in the first gate layer GE1. Thus, the first winding portion 11212, the second winding portion 11222, and the third winding portion 11232 are located in different layers, so that the winding portion 1231 uses at least three film layers for wiring, thereby realizing the narrow bezel design at the irregular region 123.

[0080] It should be noted that the third winding portion 11232 being located in the second source layer SD2 is one example of this embodiment. The third winding portion 11232 can also be located in other film layers, such as the first source layer SD1. It should also be noted that the impedance difference between the gate layer and the source layer is significant, with the impedance of the source layer being greater than that of the gate layer. The gates of the transistors in the pixel circuit 110 are often located in the gate layer; therefore, the portion of the scan signal line 112 located in the display area 11 is also located in the gate layer. In this embodiment, since the third scan signal affects the initialization process of the first electrode potential of the driving transistor T3 and the anode potential of the light-emitting element in the pixel circuit 110, its impact on the gate potential of the driving transistor T3 is relatively small. In this case, the third winding portion 11232 can be located in the source layer, and further, it can be located in the second source layer SD2.

[0081] In one embodiment, such as Figure 9 As shown, a plurality of third gate driving units 1243 are also provided in the irregular region 123 on the first side of the fan-out region 122. Each third gate driving unit 1243 is connected to two third transmission line sections 11231 via two third winding sections 11232. The third gate driving unit 1243 is used to output a third scan signal.

[0082] It is understood that multiple third gate driving units 1243 are provided in the irregular area 123 on the first side of the fan-out region 122. Each third gate driving unit 1243 is connected to two third transmission line sections 11231 via two third winding sections 11232. The third gate driving unit 1243 adopts a 1-drive-2 design, thereby reducing the number of third gate driving units 1243 in the irregular area 123 on the first side of the fan-out region 122. This reduces the area occupied by the third gate driving unit 1243 in the irregular area 123 on the first side of the fan-out region 122, which is beneficial to narrowing the corresponding frame of the irregular area 123 on the first side of the fan-out region 122.

[0083] Figure 10 A schematic diagram of the planar structure of a display panel provided in yet another embodiment of this application; Figure 11 This is a schematic diagram of the planar structure of a display panel provided in another embodiment of this application. In one embodiment, such as Figure 10 and Figure 11 As shown, the multiple scan signal lines 112 include multiple fourth scan signal lines 1124, and the fourth scan signal lines 1124 include a fourth transmission line portion 11241 and a fourth winding portion 11242 that are connected accordingly.

[0084] The fourth winding section 11242 is used to transmit the fourth scan signal to the fourth transmission line section 11241. The fourth scan signal affects the initialization of the gate potential of the driving transistor T3 of the pixel circuit 110.

[0085] Based on the foregoing embodiments, such as Figure 6 and Figure 7 As shown, the pixel circuit 110 may further include a third initialization module 1105. The first terminal of the third initialization module 1105 is used to receive a third initialization signal, the second terminal of the third initialization module 1105 is connected to the gate of the driving transistor T3, and the control terminal of the third initialization module 1105 is used to receive a fourth scan signal. During the second initialization stage, the third initialization module 1105 is turned on in response to the fourth scan signal, and the third initialization signal is written to the gate of the driving transistor T3 through the third initialization module 1105, thereby initializing the gate potential of the driving transistor T3. Therefore, the third scan signal affects the initialization of the gate potential of the driving transistor T3 in the pixel circuit 110.

[0086] It can be understood that after the fourth winding section 11242 receives the fourth scan signal, it transmits the fourth scan signal to the fourth transmission line section 11241, thereby providing the fourth scan signal to the pixel circuit 110 through the fourth transmission line section 11241, and realizing the initialization of the gate potential of the driving transistor T3 in the pixel circuit 110.

[0087] In one embodiment, such as Figure 6 and Figure 10As shown, the transistor connected to the fourth scan signal line 1124 in the pixel circuit 110 is a metal-oxide transistor. The fourth transmission line portion is located in the second gate layer GE2 and the third gate layer GE3, and the fourth winding portion 11242 is located in the first gate layer GE1.

[0088] In the application, the third initialization module 1105 includes a third initialization transistor T1. The fourth scan signal line 1124 is connected to the gate of the third initialization transistor T1. When the third initialization transistor T1 is a metal-oxide-semiconductor (MOS) transistor, since MOS transistors often have a top-bottom dual-gate structure, with the top and bottom gates of the MOS transistor located at the third gate layer GE3 and the second gate layer GE2, respectively, the fourth transmission line portion 11241 is located at the second gate layer GE2 and the third gate layer GE3 to facilitate the connection between the fourth scan signal line 1124 and the gate of the third initialization transistor T1. The fourth winding portion 11242 can be wound around the irregular region 123 and then connected to the fourth transmission line portion 11241 to transmit the fourth scan signal to the fourth transmission line portion 11241. Therefore, the fourth winding portion 11242 may be located in other film layers, unlike the fourth transmission line portion 11241. For example, the fourth winding portion 11242 may be located in the first gate layer GE1. In conjunction with the aforementioned embodiments, the first winding portion 11212 may be located in the third gate layer GE3, the second winding portion 11222 may be located in the first gate layer GE1, and the third winding portion 11232 may be located in the second source layer SD2, so that the winding portion 1231 uses at least three film layers for wiring, thereby realizing the narrow bezel design at the irregular region 123.

[0089] In one embodiment, such as Figure 7 and Figure 11 As shown, the transistor connected to the fourth scan signal line 1124 in the pixel circuit 110 is a low-temperature polysilicon transistor. The fourth scan signal line 1124 is located in the first gate layer GE1, and the fourth winding portion 11242 is located in the second gate layer GE2.

[0090] In the application, the third initialization module 1105 includes a third initialization transistor T1. The fourth scan signal line 1124 is connected to the gate of the third initialization transistor T1. When the third initialization transistor T1 is a low-temperature polysilicon transistor, since the gate of the low-temperature polysilicon transistor is located in the first gate layer GE1, the fourth transmission line portion 11241 is located in the first gate layer GE1 to facilitate the connection between the fourth scan signal line 1124 and the gate of the third initialization transistor T1. The fourth winding portion 11242 can be wound around the irregular region 123 and then connected to the fourth transmission line portion 11241 to transmit the fourth scan signal to the fourth transmission line portion 11241. Therefore, the fourth winding portion 11242 can be located in a different film layer than the fourth transmission line portion. For example, the fourth winding portion 11242 can be located in the second gate layer GE2. In conjunction with the aforementioned embodiments, the first winding portion 11212 is located in the third gate layer GE3, the second winding portion 11222 can be located in the first gate layer GE1, and the third winding portion 11232 can be located in the second source layer SD2, so that the winding portion 1231 uses at least four film layers for wiring, thereby realizing the narrow bezel design at the irregular region 123.

[0091] In one embodiment, such as Figure 10 and Figure 11 As shown, a plurality of fourth gate driving units 1244 are also provided in the irregular region 123 on the second side of the fan-out region 122. Each fourth gate driving unit 1244 is connected to two fourth scan signal lines 1124 via two fourth winding portions 11242. The fourth gate driving unit 1244 is used to output the fourth scan signal.

[0092] It is understood that multiple fourth gate driving units 1244 are provided in the irregular area 123 on the second side of the fan-out region 122. Each fourth gate driving unit 1244 is connected to two fourth scan signal lines 1124 via two fourth winding portions 11242. The fourth gate driving unit 1244 adopts a 1-drive-2 design, thereby reducing the number of fourth gate driving units 1244 in the irregular area 123 on the second side of the fan-out region 122. This can reduce the area occupied by the fourth gate driving units 1244 in the irregular area 123 on the second side of the fan-out region 122, which is beneficial to narrowing the corresponding frame of the irregular area 123 on the second side of the fan-out region 122.

[0093] Figure 12 This is a schematic diagram of the planar structure of a display panel provided in another embodiment of this application. In one embodiment, such as Figure 12 As shown, the multiple scan signal lines 112 include multiple fifth scan signal lines 1125, and the fifth scan signal lines 1125 include a fifth transmission line portion 11251 and a fifth winding portion 11252 that are connected accordingly.

[0094] The fifth winding section 11252 is used to transmit the light emission control signal to the fifth transmission line section 11251, and the light emission control signal affects the light emission of the light emission element.

[0095] Based on the foregoing embodiments, such as Figure 6 and Figure 7 As shown, the pixel circuit 110 may further include: a first light-emitting control module 1106 and a second light-emitting control module 1107. The first terminal of the first light-emitting control module 1106 is used to receive a first power supply signal, the second terminal of the first light-emitting control module 1106 is connected to the first electrode of the driving transistor T3, and the control terminal of the first light-emitting control module 1106 is used to receive a light-emitting control signal. The second terminal of the second light-emitting control module 1107 is connected to the second electrode of the driving transistor T3, the second terminal of the second light-emitting control module 1107 is connected to the anode of the light-emitting element, and the control terminal of the second light-emitting control module 1107 is used to receive a light-emitting control signal. During the light-emitting stage, the first light-emitting control module 1106 and the second light-emitting control module 1107 are turned on, the first power supply signal is applied to the anode of the light-emitting element, and the light-emitting element emits light. Therefore, the light-emitting control signal affects the light emission of the light-emitting element.

[0096] It is understood that after receiving the light emission control signal, the fifth winding section 11252 transmits the light emission control signal to the fifth transmission line section 11251, thereby providing the light emission control signal to the pixel circuit 110 through the fifth transmission line section 11251, and realizing the light emission control of the light emission element.

[0097] In one embodiment, such as Figure 3 and Figure 12 As shown, the fifth transmission line portion 11251 is located in the first gate layer GE1, and the fifth winding portion 11252 is located in the second source layer SD2.

[0098] In the application, the first light-emitting control module 1106 includes a first light-emitting control transistor T5, and the second light-emitting control module 1107 includes a second light-emitting control transistor T6. A fifth scan signal line 1125 is connected to the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6, respectively. The first light-emitting control transistor T5 and the second light-emitting control transistor T6 are both low-temperature polysilicon transistors. Therefore, the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are located in the first gate layer GE1. To facilitate the connection of the fifth scan signal line 1125 to the gates of the first light-emitting control transistor T5 and the second light-emitting control transistor T6, the fifth transmission line portion 11251 is also located in the first gate layer GE1. The fifth winding portion 11252 can be wound around the irregular region 123 and then connected to the fifth transmission line portion 11251 to transmit the light-emitting control signal to the fifth transmission line portion 11251. Therefore, the fifth winding portion 11252 can be located in other film layers. For example, the fifth winding portion 11252 can be located in the second source layer SD2. In conjunction with the aforementioned embodiments, the first winding portion 11212 is located in the third gate layer GE3, the second winding portion 11222 can be located in the first gate layer GE1, the third winding portion 11232 can be located in the second source layer SD2, and the fourth winding portion 11242 can be located in the first gate layer GE1 or the second gate layer GE2, so that the winding portion 1231 uses at least three film layers for wiring, realizing the narrow bezel design at the irregular region 123.

[0099] In one embodiment, such as Figure 12 As shown, a plurality of fifth gate driving units 1245 are also provided in the irregular region 123 on the second side of the fan-out region 122. Each fifth gate driving unit 1245 is connected to two fifth transmission line sections 11251 via two fifth winding sections 11252. The fifth gate driving unit 1245 is used to output light emission control signals.

[0100] It is understood that multiple fifth gate driving units 1245 are provided in the irregular region 123 on the second side of the fan-out region 122. Each fifth gate driving unit 1245 is connected to two fifth transmission line sections 11251 via two fifth winding sections 11252. Thus, the fifth gate driving unit 1245 adopts a 1-drive-2 design, thereby reducing the number of fifth gate driving units 1245 in the irregular region 123 on the second side of the fan-out region 122. This reduces the area occupied by the fifth gate driving unit 1245 in the irregular region 123 on the second side of the fan-out region 122, which is beneficial to narrowing the corresponding frame of the irregular region 123 on the second side of the fan-out region 122.

[0101] In conjunction with the layout of the gate driving unit in the aforementioned embodiments, the first winding portion 11212, the second winding portion 11222, and the third winding portion 11232 are located in the irregular region 123 on the first side of the fan-out region 122. The first winding portion 11212 can be located in the third gate layer GE3, the second winding portion 11222 can be located in the first gate layer GE1, and the third winding portion 11232 can be located in the second source layer SD2. Therefore, the winding portion 1231 in the irregular region 123 on the first side of the fan-out region 122 uses three film layers for wiring to achieve a narrow bezel design in the irregular region 123 on the first side of the fan-out region 122. The first winding portion 11212, the fourth winding portion 11242, and the fifth winding portion 11252 are located in the irregular region 123 on the second side of the fan-out region 122. The fourth winding portion 11242 can be located in the first gate layer GE1 or the second gate layer GE2, and the fifth winding portion 11252 can be located in the second source layer SD2. This allows the winding portion 1231 in the irregular region 123 on the second side of the fan-out region 122 to also use three film layers for wiring, thereby realizing the narrow bezel design in the irregular region 123 on the second side of the fan-out region 122.

[0102] Based on the above embodiments, in applications, such as... Figure 6 and Figure 7 As shown, the pixel circuit 110 can be an 8T1C pixel circuit 110. The data writing module 1101 may include a data writing transistor T4, the threshold compensation module 1102 may include a threshold compensation transistor T2, the first initialization module 1103 includes a first initialization transistor T8, the second initialization module 1104 includes a second initialization transistor T7, the third initialization module 1105 includes a third initialization transistor T1, the first light emission control module 1106 includes a first light emission control transistor T5, and the second light emission control module 1107 includes a second light emission control transistor T6. Therefore, the 8T1C pixel circuit 110 may include: a driving transistor T3, a storage capacitor Cst, a data writing transistor T4, a threshold compensation transistor T2, a first initialization transistor T8, a second initialization transistor T7, a third initialization transistor T1, a first light emission control transistor T5, and a second light emission control transistor T6.

[0103] The driving transistor T3 is used to provide driving current to the light-emitting element.

[0104] The first terminal of the storage capacitor Cst is used to receive the first power supply signal, and the second terminal of the storage capacitor Cst is connected to the gate of the driving transistor T3.

[0105] The first terminal of the data writing transistor T4 is used to receive data signals, the second terminal of the data writing transistor T4 is connected to the first terminal of the driving transistor T3, the gate of the data writing module 1101 is connected to the first scan signal line 1121, and the gate of the data writing module 1101 is used to receive the first scan signal.

[0106] The first terminal of the threshold compensation transistor T2 is connected to the second terminal of the driving transistor T3, the second terminal of the threshold compensation transistor T2 is connected to the gate of the driving transistor T3, the gate of the threshold compensation transistor T2 is connected to the second scan signal line 1123, and the gate of the threshold compensation transistor T2 is used to receive the second scan signal.

[0107] The first terminal of the first initialization transistor T8 is used to receive the first initialization signal. The second terminal of the first initialization transistor T8 is connected to the first terminal of the driving transistor T3. The gate of the first initialization transistor T8 is connected to the third scan signal line 1123. The gate of the first initialization transistor T8 is used to receive the third scan signal.

[0108] The first terminal of the second initialization transistor T7 is used to receive the second initialization signal, the second terminal of the second initialization transistor T7 is connected to the anode of the light-emitting element, the gate of the second initialization transistor T7 is connected to the third scan signal line, and the gate of the second initialization transistor T7 is used to receive the third scan signal.

[0109] The first terminal of the third initialization transistor T1 is used to receive the third initialization signal. The second terminal of the third initialization transistor T1 is connected to the gate of the driving transistor T3 or the first terminal of the threshold compensation transistor T2. The gate of the third initialization transistor T1 is connected to the fourth scan signal line 1124. The gate of the third initialization transistor T1 is used to receive the fourth scan signal.

[0110] The first terminal of the first light-emitting control transistor T5 is used to receive the first power supply signal. The second terminal of the first light-emitting control transistor T5 is connected to the first terminal of the driving transistor T3. The gate of the first light-emitting control transistor T5 is connected to the fifth scan signal line 1125. The gate of the first light-emitting control transistor T5 is used to receive the light-emitting control signal.

[0111] The first terminal of the second light-emitting control transistor T6 is connected to the gate of the driving transistor T3, the second terminal of the second light-emitting control transistor T6 is connected to the anode of the light-emitting element, the gate of the second light-emitting control transistor T6 is connected to the fifth scan signal line 1125, and the gate of the second light-emitting control transistor T6 is used to receive the light-emitting control signal.

[0112] In the first initialization phase, the first initialization transistor T8 and the second initialization transistor T7 are turned on in response to the third scan signal. The first initialization signal is written to the first terminal of the driving transistor T3 through the first initialization transistor T8 to initialize the first terminal of the driving transistor T3. The second initialization signal is written to the anode of the light-emitting element through the second initialization transistor T7 to initialize the anode of the light-emitting element. Therefore, the second scan signal affects the potential of the first terminal of the driving transistor T3 and the anode potential of the light-emitting element in the pixel circuit 110.

[0113] If the second terminal of the third initialization transistor T1 is connected to the first terminal of the threshold compensation transistor T2, then in the second initialization stage, the third initialization transistor T1 turns on in response to the fourth scan signal, and the threshold compensation transistor T2 turns on in response to the second scan signal. The third initialization signal is written to the gate of the driving transistor T3 through the first initialization transistor T8 and the threshold compensation transistor T2 to initialize the gate potential of the driving transistor T3. Therefore, the third scan signal affects the initialization of the gate potential of the driving transistor T3 in the pixel circuit 110.

[0114] If the second terminal of the third initialization transistor T1 is connected to the gate of the driving transistor T3, then in the second initialization stage, the third initialization transistor T1 turns on in response to the fourth scan signal. The third initialization signal is written to the gate of the driving transistor T3 through the third initialization transistor T1 to initialize the gate potential of the driving transistor T3. Therefore, the third scan signal affects the initialization of the gate potential of the driving transistor T3 in the pixel circuit 110.

[0115] During the data writing phase, the data writing transistor T4 is turned on in response to the first scan signal, and the threshold compensation transistor T2 is turned on in response to the second scan signal. The data signal is written to the gate of the driving transistor T3 via the data writing transistor T4 and the threshold compensation transistor T2. It can be understood that the first scan signal is used to control the on / off state of the data writing transistor T4, and the second scan signal is used to control the on / off state of the threshold compensation transistor T2. Therefore, the first and second scan signals can affect the data writing process of the pixel circuit 110.

[0116] During the light-emitting stage, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 are turned on in response to the light-emitting control signal. The first power supply signal is applied to the anode of the light-emitting element, and the second power supply signal is applied to the cathode of the light-emitting element, driving the light-emitting element to emit light. Therefore, the light-emitting control signal affects the light emission of the light-emitting element.

[0117] It should be noted that, Figure 6 and Figure 7The pixel circuit 110 shown is only an example of the pixel circuit 110 of this application and does not constitute a limitation on the pixel circuit 110 of this application. The pixel circuit 110 of this application can also be a pixel circuit 110 with other structures, such as the 7T1C pixel circuit.

[0118] In one embodiment, such as Figure 1 As shown, a plurality of gate driving units 124 are provided in the irregular region 123. The plurality of gate driving units 124 are arranged along the edge of the irregular region 123. The gate driving units 124 are connected to the winding part 11202 and are used to output scanning signals to the winding part 11202.

[0119] It is understandable that arranging multiple gate driving units 124 along the edge of the irregular region 123 can make the gap between the gate driving units 124 smaller, thereby increasing the density of the gate driving units 124 and avoiding excessive area occupation caused by unreasonable positioning of the gate driving units 124, which is conducive to narrowing the corresponding frame of the irregular region 123.

[0120] In one embodiment, such as Figure 1 As shown, the difference between the width of the fan-out area 122 and the width of the irregular area 123 is within a preset range, wherein the width of the fan-out area 122 is the dimension in the perpendicular direction of the edge line of the fan-out area 122.

[0121] The lower limit of the preset range can be 0, and the upper limit can be a value close to 0, so that the width of the fan-out area 122 is close to the width of the irregular area 123.

[0122] It is understandable that when the difference between the width of the fan-out area 122 and the width of the irregular area 123 is large, the overall coordination between the irregular area 123 and the bottom bezel is poor, resulting in a poor overall visual experience for the user. However, based on the aforementioned solution, this embodiment controls the difference between the width of the fan-out area 122 and the width of the irregular area 123 within a preset range. This allows for the design of a narrow bezel at the position of the fan-out area 122 and at the position of the irregular area 123, and avoids some areas from protruding relatively, thus ensuring the overall coordination and overall visual experience of the display panel.

[0123] In one embodiment, such as Figure 3 As shown, the orthographic projection of the first source layer SD1 on the substrate 101 covers the orthographic projections of the first gate layer GE1, the second gate layer GE2, and the third gate layer GE3 on the substrate 101.

[0124] In applications, the first source layer SD1 is often used as the routing layer for certain signal lines. The first source layer SD1 is connected to a fixed voltage signal, with constant capacitance and voltage difference, thus keeping signal interference constant and effectively removing interference while retaining valid signal data. For example, a first power signal line can be located on the first source layer to transmit the first power signal ELVDD. In this case, the first source layer is connected to the first power signal ELVDD, and the first source layer SD1 serves as both the routing layer and the shielding layer for the first power signal line. It should be noted that in other examples, the first source layer SD1 can also be used as the routing layer for other types of signal lines, such as a second power signal line to transmit the second power signal ELVSS. In this case, the first source layer is connected to the second power signal ELVSS.

[0125] Since the orthographic projection of the first source layer SD1 on the substrate 101 covers the orthographic projections of the first gate layer GE1, the second gate layer GE2 and the third gate layer GE3 on the substrate 101, the first source layer SD1 can serve as a shielding layer to shield the interference of the signal lines located on the gate layer.

[0126] In one embodiment, such as Figure 3 As shown, the orthographic projections of the second gate layer GE2 and the third gate layer GE3 on the substrate 101 do not overlap.

[0127] It is understandable that since the orthographic projections of the second gate layer GE2 and the third gate layer GE3 on the substrate 101 do not overlap, the orthographic projections of the first trace located on the second gate layer GE2 and the second trace located on the third gate layer GE3 on the substrate 101 also do not overlap, thereby avoiding crosstalk between the first trace and the second trace and ensuring the stability of the signals transmitted by the first trace and the second trace. The first trace can be any trace located on the second gate layer GE2, and the second trace can be any trace located on the third gate layer GE3.

[0128] In one embodiment, such as Figure 1 As shown, the overall outline of the non-display area 12 is a rounded rectangle, and the irregular area 123 is the rounded corner area on both sides of the fan-out area 122.

[0129] It is understood that the overall outline of the non-display area 12 is a rounded rectangle, and the fan-out area 122 is located within the rectangular area of ​​this rounded rectangle. The irregular area 123 is located in the rounded corner areas on both sides of the fan-out area 122. By making the irregular area 123 the rounded corner areas on both sides of the fan-out area 122, the smoothness of the edge lines of the display panel can be ensured, which is beneficial to improving the visual effect of the display panel. In addition, the rounded corner area of ​​the irregular area 123 is also conducive to the arrangement of multiple gate driving units 124 along the edge of the irregular area 123, which can make the gap between the gate driving units 124 smaller, thereby increasing the density of the gate driving units 124 and avoiding the excessive area occupied by the gate driving units 124 due to unreasonable positioning. This is conducive to achieving the narrowing of the bezel corresponding to the irregular area 123.

[0130] Figure 13 This is a schematic diagram of the structure of a display screen 100 provided in one embodiment of this application. This application also provides a display screen 100; please refer to [link / reference]. Figure 13 The display screen 100 includes a cover plate 1100 and the display panel 10 provided in the aforementioned embodiments. The cover plate 1100 may be disposed on the light-emitting side of the display panel 10 to protect the display panel 10.

[0131] Based on the same concept, this application also provides an electronic device. Figure 14 This is a schematic diagram of the structure of an electronic device 1000 provided in an embodiment of this application, as shown below. Figure 14 As shown, the electronic device 1000 includes the display screen 100 in the above embodiments. Since the display screen 100 includes a cover plate 1100 and the display panel 10 provided in the aforementioned embodiments, the electronic device 1000 also has the beneficial effects of the display panel 10 in the above embodiments. The similarities can be understood with reference to the explanation of the display panel 10 above, and will not be repeated below.

[0132] The electronic device 30 provided in this application embodiment can be... Figure 14 The mobile phone shown can also be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop monitors, tablets, digital cameras, smart bracelets, smart glasses, in-vehicle displays, industrial control equipment, medical displays, touch interactive terminals, etc. This application does not specifically limit these categories. The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as the combination of these technical features does not contradict each other, it should be considered within the scope of this specification.

[0133] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0134] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A display panel, characterized in that, The display panel includes: a display area and a non-display area surrounding the display area, wherein the non-display area includes a fan-out area and an irregularly shaped area adjacent to the fan-out area; The display panel further includes a pixel circuit, multiple data signal lines, multiple scan signal lines, multiple first fan-out traces, and multiple second fan-out traces. Each scan signal line includes a correspondingly connected transmission line portion and a winding portion. Each of the data signal lines, each of the transmission line portions, and each of the first fan-out traces are located in the display area, and each of the second fan-out traces is located in the fan-out area. The second fan-out traces are connected to the data signal lines through the first fan-out traces. Multiple winding portions are located within the irregular region. The scanning signal line is used to provide a scanning signal to the pixel circuit. The data signal line is not wound in the irregular region. The data signal line is used to provide a data signal to the pixel circuit. The pixel circuit drives the light-emitting element to emit light based on the received scanning signal and data signal. At least two winding portions belonging to different scanning signal lines are located in multiple film layers.

2. The display panel according to claim 1, characterized in that, The multiple scan signal lines include various types of scan signal lines, with different types of scan signal lines used to transmit different scan signals.

3. The display panel according to claim 1, characterized in that, The display panel includes a substrate and a first gate layer, a second gate layer, a third gate layer, a first source layer, and a second source layer, which are sequentially located away from the substrate. At least two winding portions belonging to different scan signal lines are respectively located in multiple layers of the first gate layer, the second gate layer, the third gate layer, the first source layer, and the second source layer.

4. The display panel according to claim 3, characterized in that, The plurality of scan signal lines include a plurality of first scan signal lines, each of which includes a first transmission line portion and a first winding portion connected accordingly; The first winding portion is used to transmit a first scan signal to the first transmission line portion, and the first transmission line portion is used to provide the first scan signal to the pixel circuit. The first scan signal affects the data writing of the pixel circuit.

5. The display panel according to claim 4, characterized in that, The first transmission line portion is located in the first gate layer, and the first winding portion is located in the third gate layer.

6. The display panel according to claim 4, characterized in that, Multiple first gate driving units are respectively provided in the irregular regions on both sides of the fan-out region. Each first gate driving unit is connected to a first transmission line via a first winding portion. The first gate driving unit is used to output the first scan signal.

7. The display panel according to claim 3, characterized in that, The plurality of scan signal lines include a plurality of second scan signal lines, wherein the second scan signal lines include correspondingly connected second transmission line portions and second winding portions; The second winding portion is used to transmit the second scan signal to the second scan signal line, and the second transmission line portion is used to provide the second scan signal to the pixel circuit. The second scan signal affects the gate potential of the driving transistor in the pixel circuit.

8. The display panel according to claim 7, characterized in that, The second transmission line portion is located in the second gate layer and the third gate layer, and the second winding portion is located in the first gate layer.

9. The display panel according to claim 7, characterized in that, The irregular region on the first side of the fan-out region is further provided with a plurality of second gate driving units. Each second gate driving unit is connected to two second transmission lines via two second winding portions. The second gate driving unit is used to output the second scan signal.

10. The display panel according to claim 3, characterized in that, The plurality of scanning signal lines include a plurality of third scanning signal lines, wherein each third scanning signal line includes a correspondingly connected third transmission line portion and a third winding portion; The third winding portion is connected to the third transmission line portion. The third winding portion is used to output a third scan signal to the third transmission line portion. The third transmission line portion is used to provide the third scan signal to the pixel circuit. The third scan signal affects the initialization of the first electrode potential of the driving transistor and the anode potential of the light-emitting element in the pixel circuit.

11. The display panel according to claim 10, characterized in that, The third transmission line portion is located in the first gate layer, and the third winding portion is located in the second source layer.

12. The display panel according to claim 10, characterized in that, The irregular region on the first side of the fan-out area is further provided with a plurality of third gate driving units. Each third gate driving unit is connected to two third transmission lines via two third winding portions. The third gate driving unit is used to output the third scan signal.

13. The display panel according to claim 3, characterized in that, The plurality of scanning signal lines include a plurality of fourth scanning signal lines, wherein each fourth scanning signal line includes a correspondingly connected fourth transmission line portion and a fourth winding portion; The fourth winding portion is connected to the fourth transmission line portion. The fourth winding portion is used to transmit a fourth scan signal to the fourth transmission line portion. The fourth transmission line portion is used to provide the fourth scan signal to the pixel circuit. The fourth scan signal affects the initialization of the gate potential of the pixel circuit driving transistor.

14. The display panel according to claim 13, characterized in that, The transistor connected to the fourth scan signal line in the pixel circuit is a metal-oxide transistor. The fourth transmission line portion is located in the second gate layer and the third gate layer, and the fourth winding portion is located in the first gate layer.

15. The display panel according to claim 13, characterized in that, The transistor connected to the fourth scan signal line in the pixel circuit is a low-temperature polysilicon transistor, the fourth transmission line portion is located in the first gate layer, and the fourth winding portion is located in the second gate layer.

16. The display panel according to claim 13, characterized in that, The irregular region on the second side of the fan-out region is further provided with a plurality of fourth gate driving units. Each fourth gate driving unit is connected to two fourth transmission lines via two fourth winding portions. The fourth gate driving unit is used to output the fourth scan signal.

17. The display panel according to claim 3, characterized in that, The plurality of scanning signal lines include a plurality of fifth scanning signal lines, wherein each fifth scanning signal line includes a correspondingly connected fifth transmission line portion and a fifth winding portion; The fifth winding portion is connected to the fifth transmission line portion. The fifth winding portion is used to transmit the light emission control signal to the fifth transmission line portion. The fifth transmission line portion is used to provide the light emission control signal to the pixel circuit. The light emission control signal affects the light emission of the light-emitting element.

18. The display panel according to claim 17, characterized in that, The fifth scan signal line is located in the first gate layer, and the fifth winding portion is located in the second source layer.

19. The display panel according to claim 17, characterized in that, The irregular region on the second side of the fan-out area is further provided with a plurality of fifth gate driving units. Each fifth gate driving unit is connected to two fifth transmission lines via two fifth winding sections. The fifth gate driving unit is used to output the light emission control signal.

20. The display panel according to claim 1, characterized in that, The irregular region is provided with multiple gate driving units, which are arranged along the edge of the irregular region. The gate driving units are connected to the winding part and are used to output the scanning signal to the winding part.

21. The display panel according to claim 1, characterized in that, The difference between the width of the fan-out area and the width of the irregular area is within a preset range, wherein the width of the fan-out area is the dimension in the perpendicular direction of the edge line of the fan-out area.

22. The display panel according to claim 3, characterized in that, The orthographic projection of the first source layer on the substrate covers the orthographic projections of the first gate layer, the second gate layer, and the third gate layer on the substrate.

23. The display panel according to claim 3, characterized in that, The orthographic projections of the second gate layer and the third gate layer on the substrate do not overlap.

24. The display panel according to claim 1, characterized in that, The overall outline of the non-display area is a rounded rectangle, and the irregular area is the rounded corner area on both sides of the fan-out area.

25. A display screen, characterized in that, Includes a cover plate and a display panel as claimed in any one of claims 1 to 24.

26. An electronic device, characterized in that, Including the display screen as described in claim 25.

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