Gate driver and display device

Abstract

A gate driver and a display device are provided. A low-resolution area is provided in a portion of a display area, and an optical sensor is provided on a side of the low-resolution area opposite a surface of a display image of the low-resolution area, such that the display device displays an image on the low-resolution area and performs sensing using the optical sensor. Different gate lines are used to drive the low-resolution area and a high-resolution area surrounding the low-resolution area. Image compensation for the low-resolution area is easily performed to reduce or eliminate image quality differences between the low-resolution area and the surrounding area.

Description

[0001] This application is a divisional application of the original patent application No. 202010550187.8 (filed on June 16, 2020, entitled "Gate Driver and Display Device"). Technical Field

[0002] The implementation methods relate to gate drivers and display devices. Background Technology

[0003] With the development of the information society, the demand for display devices for displaying images is increasing. In this regard, display devices such as liquid crystal displays (LCDs) and organic light-emitting diode (OLEDs) displays have recently been widely used.

[0004] Such a display device may include a display panel having multiple gate lines, multiple data lines, and multiple sub-pixels, as well as various driving circuits for driving the gate lines, data lines, etc. Additionally, the display panel may include a display area having multiple sub-pixels for displaying images and a non-display area located outside the display area, with signal lines, etc., disposed in the non-display area.

[0005] Here, depending on the type of display device, the display device may include a camera sensor, proximity sensor, etc. (hereinafter referred to as "optical sensor") disposed in the non-display area. When the optical sensor is disposed in the non-display area, the ability to reduce the size of the non-display area in the display panel is limited.

[0006] To overcome this problem, methods have been attempted to place optical sensors and other components required for the display device within a portion of the display area of ​​the display panel. However, because the optical sensors are located within the display area, the image quality displayed on that area may be reduced. Summary of the Invention

[0007] The embodiment provides a scheme for enabling optical sensors required for a display device to be placed in the display area of ​​a display panel while preventing degradation of the quality of the image displayed on the display panel.

[0008] The implementation provides a scheme for minimizing the image quality difference between an area where an optical sensor is provided and an area where no optical sensor is provided in the display area of ​​a display panel.

[0009] According to one aspect, an embodiment provides a display device including a display area comprising a first area and a second area, the first area having a first resolution, and the second area located to one side of the first area and having a second resolution higher than the first resolution. In some cases, the display area may further include a third area located to the other side of the first area and having a second resolution.

[0010] Here, the display device may further include at least one optical sensor disposed in a region overlapping with the first region and located on a surface of the first region opposite to the surface on which the image is displayed.

[0011] The display device may include: a plurality of first gate lines electrically connected to circuit elements disposed in sub-pixels of a first region and extending in a first direction; and a plurality of second gate lines electrically connected to circuit elements disposed in sub-pixels of a second region and extending in a second direction intersecting the first direction.

[0012] Furthermore, the first gate driver that drives multiple first gate lines can be located on the first side of the display area, and the second gate driver that drives multiple second gate lines can be located on a second side of the display area that is different from the first side.

[0013] Alternatively, the display device may include: a plurality of first gate lines electrically connected to circuit elements disposed in sub-pixels of a first region and insulated from circuit elements disposed in sub-pixels of a second region; and a plurality of second gate lines insulated from circuit elements disposed in sub-pixels of the first region and electrically connected to circuit elements disposed in sub-pixels of at least one region of the second region.

[0014] In this configuration, the first gate line and the second gate line can extend in a single direction. Furthermore, the first gate driver driving the first gate line and the second gate driver driving the second gate line can be located on a single side of the display area.

[0015] According to another aspect, an embodiment provides a gate driver comprising: a first gate driver that drives a plurality of first gate lines electrically connected to circuit elements disposed in a sub-pixel of a first region having a first resolution; and a second gate driver that drives a plurality of second gate lines electrically connected to circuit elements disposed in a sub-pixel of a second region having a second resolution higher than the first resolution, the plurality of second gate lines extending in a direction intersecting the plurality of first gate lines.

[0016] According to an exemplary embodiment, by reducing the resolution of a specific area of ​​the display panel to increase the transmittance of that specific area, an optical sensor can be placed on a surface opposite to the image display surface of the low-resolution area, thereby enabling sensing.

[0017] Therefore, the ratio of the display area in the display panel can be maximized, and sensing and image display using optical sensors can be performed in specific areas of the display area.

[0018] Furthermore, since the low-resolution region equipped with the optical sensor and the high-resolution region without the optical sensor can be driven by separate gate lines, compensation for the low-resolution region can be performed, thereby minimizing the image quality difference between the region equipped with the optical sensor and the surrounding region. Attached Figure Description

[0019] The above and other objects, features and advantages of this disclosure will become clearer from the following detailed description taken in conjunction with the accompanying drawings, wherein:

[0020] Figure 1 A schematic structure of a display device according to an embodiment is shown;

[0021] Figure 2 The circuit structure of each sub-pixel and the driving time of the sub-pixel are shown in the display device according to an embodiment.

[0022] Figure 3 A structure is shown in which sub-pixels and gate lines are disposed in the display area of ​​a display device according to an embodiment, wherein an optical sensor is disposed in the display area;

[0023] Figure 4 and Figure 5 The diagram illustrates a structure in the display area of ​​a display device in which gate lines for driving sub-pixels in a first region and sub-pixels in regions other than the first region are provided, according to an embodiment.

[0024] Figure 6 and Figure 7 This illustrates another structure, according to an embodiment, in which sub-pixels of a first region and gate lines for driving sub-pixels of other regions besides the first region are arranged in the display area of ​​a display device;

[0025] Figure 8 It shows Figure 7 The specific structure of case 4 shown; and

[0026] Figures 9A to 9C The arrangement structure of sub-pixels in a first region of the display area of ​​a display device according to an embodiment is shown. Detailed Implementation

[0027] In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that may be implemented are illustrated by way of illustration, and wherein the same reference numerals and symbols may be used to denote the same or similar components even when the same reference numerals and symbols are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, descriptions of well-known functions and components incorporated herein will be omitted where it is determined that detailed descriptions of such functions and components may obscure the subject matter of some embodiments of the invention. Terms such as “comprising,” “having,” “containing,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of other components unless the term is used in conjunction with the term “only.” As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0028] Terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” are used herein to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but merely to distinguish the corresponding element from the others.

[0029] When referring to the first element as "connected to or linked to," "in contact with," or "overlapping" with the second element, it should be interpreted that not only can the first element be "directly connected to or linked to" or "directly in contact with or overlap" the second element, but a third element can also be "inserted" between the first and second elements, or the first and second elements can be "connected to or linked to," "in contact with," or "overlapping" with each other via a fourth element. Here, the second element can be included in at least one of two or more elements that are "connected to or linked to," "in contact with," or "overlap" with each other.

[0030] When time-related terms such as “after,” “following,” “after,” or “before” are used to describe a process or operation of an element or structure, or a flow or step in an operation, processing, or manufacturing method, these terms may be used to describe a discontinuous or non-sequential process or operation, unless the terms “directly” or “immediately” are used together.

[0031] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical values ​​or corresponding information of an element or feature (e.g., level, range, etc.) include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0032] Figure 1A schematic configuration of a display device 100 according to an embodiment is shown.

[0033] Reference Figure 1 The display device 100 according to the embodiment may include: a display panel 110 in which a plurality of sub-pixels SP are arranged; and a gate driver 120, a data driver 130, a controller 140, etc. for driving the display panel 110.

[0034] The display panel 110 may include a display area A / A and a non-display area N / A. The display area A / A has a plurality of sub-pixels SP arranged to display an image. The non-display area N / A is located outside the display area, and signal lines and the like are arranged in the non-display area N / A.

[0035] Multiple gate lines GL and multiple data lines DL can be set in the display area A / A of the display panel 110, and multiple sub-pixels SP can be set in the area where the gate lines GL and data lines DL intersect.

[0036] Each subpixel SP may include a light-emitting device ED, and two or more subpixels SP may constitute a single pixel.

[0037] The gate driver 120 is controlled by the controller 140 and controls the driving time of multiple sub-pixels SP by sequentially outputting scan signals to multiple gate lines GL disposed in the display panel 110.

[0038] The gate driver 120 may include one or more gate driver integrated circuits (GDICs) and may be located on one or both sides of the display panel 110, depending on the driving method.

[0039] The data driver 130 receives image data from the controller 140 and converts the image data into analog data voltage. Additionally, the data driver 130 outputs the data voltage to each data line DL at the time a scan signal is applied through the gate line GL, causing the sub-pixel SP to exhibit a luminous intensity corresponding to the image data.

[0040] The data driver 130 may include one or more source driver integrated circuits (SDICs).

[0041] The controller 140 provides various control signals to the gate driver 120 and the data driver 130 to control the operation of the gate driver 120 and the data driver 130.

[0042] The controller 140 controls the gate driver 120 to output a scan signal at a time point defined by the frame. The controller 140 receives image data from an external source, converts the image data into a data signal format readable by the data driver 130, and outputs the converted image data to the data driver 130.

[0043] In addition to image data, the controller 140 also receives various timing signals from external sources (e.g., a host system). Timing signals may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, an input data enable signal DE, a clock signal CLK, etc.

[0044] The controller 140 can generate various control signals based on various timing signals received from external sources, and output the control signals to the gate driver 120 and the data driver 130.

[0045] For example, the controller 140 outputs various gating control signals GCS (including gating start pulse GSP, gating shift clock signal GSC, gating output enable signal GOE, etc.) to control the gate driver 120.

[0046] Here, the strobe start pulse (GSP) controls the start time of operation for one or more gate controllers (GDICs) of the gate driver 120. The strobe shift clock (GSC) is a clock signal typically input to one or more GDICs to control the shift time of the scan signal. The strobe output enable signal (GOE) specifies the timing information for one or more GDICs.

[0047] In addition, the controller 140 outputs various data control signals DCS (including source start pulse SSP, source sampling clock SSC, source output enable signal SOE, etc.) to control the data driver 130.

[0048] Here, the source start pulse SSP controls the data sampling start time of one or more SDICs in the data driver 130. The source sampling clock SSC is a clock signal that controls the sampling time of the data in each SDIC. The source output enable signal SOE controls the output time of the data driver 130.

[0049] The display device 100 may also include a power management integrated circuit (PMIC) that supplies various forms of voltage or current to the display panel 110, gate driver 120, data driver 130, etc., or controls various types of voltage or current to be supplied thereto.

[0050] In addition to the gate line GL and the data line DL, voltage lines that provide various signals or voltages can be set on the display panel 110. Light-emitting devices (EDs) and transistors for driving the EDs can be set in each sub-pixel SP.

[0051] Figure 2 The circuit structure of each sub-pixel SP in the display device 100 according to the embodiment and the driving time of the sub-pixel SP are shown.

[0052] Reference Figure 2 The light-emitting device ED can be disposed in the sub-pixel SP of the display panel 110. Furthermore, the driving transistor DRT that drives the light-emitting device ED by current control can be disposed in the sub-pixel SP.

[0053] The light-emitting device ED set in the sub-pixel SP can be an organic light-emitting diode (OLED), and in some cases, it can be a light-emitting diode (LED), a micro light-emitting diode (μLED), etc.

[0054] Furthermore, in addition to the driving transistor DRT, one or more transistors can be provided in the sub-pixel SP. Storage capacitors such as Cstg, used to maintain the voltage of the gate node of the driving transistor DRT, can also be provided in the sub-pixel SP.

[0055] Figure 2 A 7T1C structure is shown, comprising seven transistors (including a driving transistor DRT) and one storage capacitor Cstg disposed in a sub-pixel SP. However, the structure of the sub-pixel SP in the display device 100 according to the embodiment is not limited to this. Furthermore, although Figure 2 The sub-pixel SP is shown to be implemented as a P-type metal-oxide-semiconductor (PMOS) transistor, but at least one transistor disposed in the sub-pixel SP can be implemented as an N-type metal-oxide-semiconductor (NMOS).

[0056] A light-emitting device (ED) may include an anode electrically connected to a driving transistor (DRT) and a cathode that provides a base voltage (Vss) to it.

[0057] The driving transistor DRT can be electrically connected to the driving voltage line DVL through which the driving voltage Vdd is applied and to the light-emitting device ED. Additionally, the driving transistor DRT can be electrically connected to the data line DL, through which the data voltage Vdata is applied. Furthermore, the gate node of the driving transistor DRT can be electrically connected to the storage capacitor Cstg and the initialization voltage line IVL.

[0058] The first transistor T1 can be controlled by the scan signal SCAN(N) and can be electrically connected to the first node N1 and the second node N2 of the driving transistor DRT. The first transistor T1 can control the voltage obtained by compensating the data voltage Vdata with the threshold voltage Vth of the driving transistor DRT to be applied to the gate node of the driving transistor DRT.

[0059] The second transistor T2 can be controlled by the scan signal SCAN(N-1) and is electrically connected to the first node N1 of the driving transistor DRT and the initialization voltage line IVL. The second transistor T2 can be used to initialize the voltage of the gate node of the driving transistor DRT.

[0060] The third transistor T3 can be controlled by the scan signal SCAN(N) and is electrically connected to the third node N3 of the drive transistor DRT and the data line DL. Additionally, the fourth transistor T4 can be controlled by the scan signal EM and is electrically connected to the third node N3 of the drive transistor DRT and the drive voltage line DVL.

[0061] The fifth transistor T5 can be controlled by the scan signal EM and is electrically connected to the second node N2 of the driving transistor DRT and the light-emitting device ED. The fifth transistor T5 can control the emission time of the light-emitting device ED.

[0062] The sixth transistor T6 can be controlled by the scan signal SCAN(N) and is electrically connected to the anode of the light-emitting device ED and the initialization voltage line IVL. The sixth transistor T6 can be used to initialize the voltage of the anode of the light-emitting device ED.

[0063] The description describes a driving method for subpixels SP, which can drive subpixels SP such that their driving period is divided into an initialization period, a data writing period, and an emission period during a single image frame period.

[0064] During the initialization period, a scan signal SCAN(N-1) with a low level can be provided to the sub-pixel SP, thereby turning on the second transistor T2. With the second transistor T2 turned on, an initialization voltage Vin1 can be applied to the gate node of the driving transistor DRT.

[0065] After initialization is complete, during the data writing period, a high-level scan signal SCAN(N-1) and a low-level scan signal SCAN(N) can be provided to the sub-pixel SP. Additionally, the second transistor T2 can be turned off, while the first transistor T1, the third transistor T3, and the sixth transistor T6 can be turned on.

[0066] When the first transistor T1 is turned on, the first node N1 and the second node N2 of the driving transistor DRT are electrically connected.

[0067] Furthermore, when the third transistor T3 is turned on, the data voltage Vdata can be applied to the first node N1, i.e., the gate node, of the driving transistor DRT through the driving transistor DRT and the first transistor T1. At this time, the voltage obtained by reflecting the threshold voltage Vth of the driving transistor DRT onto the data voltage Vdata can be applied to the gate node of the driving transistor DRT, so that compensation for the threshold voltage of the driving transistor DRT can be performed.

[0068] Furthermore, as the sixth transistor T6 is turned on during the data write period, the anode of the light-emitting device (ED) can be initialized using the initialization voltage Vini. That is, during the data write period, the operation of applying a voltage to the gate node of the driving transistor DRT and the operation of initializing the anode of the light-emitting device (ED) can be performed simultaneously.

[0069] During the light-emitting period, a high-level scan signal SCAN(N-1) and a high-level scan signal SCAN(N) can be provided to the sub-pixel SP, and a low-level scan signal EM can be provided to the sub-pixel SP. Therefore, the first transistor T1, the third transistor T3, and the sixth transistor T6 can be turned off, while the fourth transistor T4 and the fifth transistor T5 can be turned on.

[0070] When the fourth transistor T4 is turned on, the driving voltage Vdd can be provided to the third node N3 of the driving transistor DRT. The voltage difference between the first node N1 and the third node N3 of the driving transistor DRT can be generated by the data voltage Vdata and the driving voltage Vdd, so that the current in response to the data voltage Vdata can flow through the driving transistor DRT.

[0071] When the fifth transistor T5 is turned on, a current that is a response to the data voltage Vdata can be supplied to the light-emitting device ED, and the light-emitting device ED can exhibit a light intensity corresponding to the data voltage Vdata.

[0072] These subpixels SP can be arranged at a predetermined distance from each other in the display area A / A of the display panel 110, or the same number of subpixels SP can be arranged in a unit area, so that the display panel 110 has a uniform resolution.

[0073] In some cases, subpixels SP can be configured such that a portion of the display area A / A has a different resolution level. In this case, the transmittance of the area with lower resolution can be increased, and an optical sensor or similar device can be placed in the area with increased transmittance to perform sensing. That is, the display area A / A can include an area that houses an optical sensor while displaying an image.

[0074] Figure 3 The diagram illustrates a structure in which sub-pixels SP and gate lines GL are disposed in a display area A / A of a display device 100 according to an embodiment, wherein an optical sensor is disposed in the display area A / A.

[0075] Reference Figure 3 The display panel 110 may include a display area A / A in which a plurality of sub-pixels SP are provided to display images and a non-display area N / A located outside the display area A / A.

[0076] Display area A / A may include a first area A1 having a first resolution. The first area A1 may be located in the upper central portion of display area A / A, and in some cases, may be located at the boundary adjacent to display area A / A.

[0077] In addition, the portion of display area A / A other than the first area A1 may have a second resolution higher than the first resolution.

[0078] For example, a second region A2 with a second resolution can be located on one side of the first region A1. A third region A3 with a second resolution can be located on the other side of the first region A1.

[0079] The first region A1, the second region A2, and the third region A3 can be regions driven by the same gate line GL.

[0080] Additionally, the remaining portion of display area A / A besides the first area A1, the second area A2, and the third area A3 can be referred to as the fourth area A4. The fourth area A4 can have the same second resolution as the second area A2 and the third area A3.

[0081] The first region A1 has a lower resolution than the second region A2, the third region A3, and the fourth region A4. For example... Figure 3 As shown, a portion of the first region A1 may be a transparent region. Furthermore, when the second region A2, etc., includes a transparent region, the ratio of the transparent region in the first region A1 may be greater than the ratio of the transparent region in the second region A2, etc.

[0082] Since the first region A1 includes a transparent area and has relatively high transmittance, optical sensors such as camera sensors or proximity sensors can be placed in the first region A1.

[0083] For example, an optical sensor can be disposed on a surface of the display panel 110 opposite to the surface on which the image is displayed. Such an optical sensor can be located in an area overlapping with the first area A1 of the display area A / A.

[0084] Because the optical sensor is located in the first region A1, which has high transmittance, it can perform sensing simultaneously on a surface opposite to the surface displaying the image. Furthermore, since the optical sensor is located in the display area A / A, it prevents the non-display area N / A from being enlarged by an optical sensor otherwise disposed therein.

[0085] As described above, the embodiments provide a method for easily placing an optical sensor in the display area A / A by reducing the resolution of a portion of the display area A / A and increasing its transmittance.

[0086] Furthermore, regions with a first resolution and regions with a second resolution within the display area A / A can be driven using different gate lines (GL). In this way, a scheme can be provided to minimize image quality differences between regions with different resolutions by performing independent data compensation based on the regions.

[0087] Figure 4 and Figure 5 The diagram illustrates a structure in which a gate line GL for driving sub-pixels SP in the first region A1 and sub-pixels SP in regions other than the first region A1 is provided in the display area A / A of the display device 100, according to an embodiment.

[0088] Reference Figure 4 The display area A / A of the display panel 110 may include a first area A1 with a first resolution and a second area A2, a third area A3 and a fourth area A4 with a second resolution higher than the first resolution.

[0089] A first gate driver 121 can be disposed on one side of the display area A / A to drive multiple first gate lines GL1 connected to the sub-pixels SP in the first area A1. A second gate driver 122 can be disposed to drive multiple second gate lines GL2 connected to the second area A2, the third area A3, and the fourth area A4.

[0090] Here, the first gate line GL1 and the second gate line GL2 can extend in a single direction (e.g., horizontal direction). Furthermore, the first gate line GL1 and the second gate line GL2 can overlap with at least one of the first region A1, the second region A2, and the third region A3 located above the display region A / A.

[0091] For example, the first gate line GL1 may overlap with the first region A1, the second region A2, and the third region A3. Furthermore, the first gate line GL1 may be electrically connected to circuit elements disposed in the sub-pixels SP of the first region A1, but not to circuit elements disposed in the sub-pixels SP of the second region A2 and the third region A3.

[0092] Furthermore, the second gate line GL2 may overlap with the first region A1, the second region A2, and the third region A3. Additionally, the second gate line GL2 may be electrically connected to circuit elements disposed in the sub-pixels SP of the second region A2 and the third region A3, rather than to circuit elements disposed in the sub-pixels SP of the first region A1.

[0093] Here, the resolution of the first region A1 is lower than that of the second region A2 or the third region A3. Therefore, the number of first gate lines GL1 used to drive the sub-pixels SP of the first region A1 can be less than the number of second gate lines GL2 used to drive the sub-pixels SP of the second region A2 and the third region A3. That is, the maximum distance between adjacent first gate lines GL1 can be greater than the maximum distance between adjacent second gate lines GL2.

[0094] As described above, the gate line GL used to drive the first region A1 with a first resolution can be set separately from the gate line GL used to drive the second region A2 and the third region A3 with a second resolution higher than the first resolution.

[0095] Therefore, the sub-pixels SP of the second region A2 and the third region A3 can be driven by scan signals G(1), G(2), G(3), etc., output from the second gate driver 122. Since the sub-pixels SP of the first region A1 are driven by scan signals G(k), G(k+1), etc., the sub-pixels SP of the first region A1 can be driven independently of the sub-pixels SP of the second region A2.

[0096] Since the sub-pixels SP of the second region A2 and the third region A3 drive the sub-pixels SP of the first region A1 independently, the compensation for the data voltage Vdata provided to the sub-pixels SP of the first region A1 can be performed separately from the compensation for the data voltage Vdata provided to the sub-pixels SP of the second region A2 or the third region A3.

[0097] For example, the level of the data voltage Vdata provided to the sub-pixel SP of the first region A1 can be set to be higher than the level of the data voltage Vdata provided to the sub-pixel SP of the second region A2, etc.

[0098] Because the data voltage Vdata supplied to the sub-pixels SP of the first region A1 is at a higher level, the brightness of the first region A1, whose resolution is lower than that of the second region A2 or the third region A3, can be increased. Therefore, the difference in image quality between the first region A1 and the image quality displayed by the second region A2, etc., can be reduced or eliminated.

[0099] In addition, the first gate line GL1 and the second gate line GL2 can be set in the upper part of the display area A / A, and various structures depend on the arrangement of the first gate driver 121 and the second gate driver 122.

[0100] Reference Figure 5In scenario 1, the second gate line GL2 can be placed only in the fourth region A4, located below the display region A / A. Alternatively, the second gate line GL2 can be electrically connected to circuit elements disposed in the sub-pixel SP of the fourth region A4.

[0101] The first gate line GL1 and the second gate line GL2 can be disposed in the second region A2 and the third region A3 in the upper region of the display region A / A. Here, the second gate line GL2 can be electrically connected to the circuit elements disposed in the sub-pixels SP of the second region A2 and the third region A3. Alternatively, the first gate line GL1 may not be electrically connected to the circuit elements disposed in the sub-pixels SP of the second region A2 and the third region A3. That is, the first gate line GL1 can be configured to extend through the second region A2 and the third region A3 without being electrically connected to the circuit elements disposed in the sub-pixels SP of the second region A2 and the third region A3.

[0102] The first gate line GL1 and the second gate line GL2 can be disposed in the first region A1 of the display area A / A. The first gate line GL1 can be electrically connected to a circuit element disposed in a sub-pixel SP of the first region A1. Furthermore, the second gate line GL2 can be configured to extend through the first region A1 without being electrically connected to a circuit element disposed in a sub-pixel SP of the first region A1.

[0103] like Figure 5 As shown in Case 1, since the first gate line GL1 of the sub-pixel SP driving the first region A1 is set separately, the difference between the image quality of the first region A1 with lower resolution and the image quality of the surrounding region can be reduced or eliminated.

[0104] Furthermore, the second gate line GL2, which drives the sub-pixels SP of the second region A2 and the third region A3, extends through the first region A1 between the second region A2 and the third region A3. The scan signals driving the sub-pixels SP of the second region A2 and the third region A3 can be provided in a dual-feed manner. That is, the scan signals driving the second gate line GL2 can be provided from both sides of the display area A / A to prevent differences in the waveform of the scan signals depending on the position of the sub-pixels SP.

[0105] In addition, to further improve the transmittance of the first region A1, gate lines GL can be set to drive the sub-pixels SP of the second region A2 and the third region A3 respectively.

[0106] Reference Figure 5 In Case 2, in the same manner as Case 1, only the second gate line GL2 can be set in the fourth region A4, and the first gate line GL1 and the second gate line GL2 can be set in the second region A2 and the third region A3.

[0107] Here, only the first gate line GL1 can be set in the first region A1, but there is no second gate line GL2 that can be set in the first region A1.

[0108] That is, the second gate line GL2 driving the second region A2 can be set separately from the second gate line GL2 driving the third region A3. Therefore, the sub-pixel SP of the second region A2 can be electrically connected to a different gate line GL than the gate line to which the sub-pixel SP of the third region A3 is electrically connected, and can be driven by a different gate driver 120 than the gate driver driving the sub-pixel SP of the third region A3.

[0109] As described above, since the second gate line GL2 used to drive the second region A2 is provided separately from the second gate line GL2 used to drive the third region A3, no second gate line GL2 can be provided in the first region A1. Furthermore, removing the second gate line GL2 that passes through the first region A1 can further increase the transmittance of the first region A1.

[0110] Furthermore, according to the embodiment, the first gate line GL1 for driving the first region A1 of the display region A / A can extend in a direction intersecting with the second gate line GL2, thereby further facilitating the driving of the first region A1 and the placement of the first gate driver 121.

[0111] Figure 6 and Figure 7 Another structure according to an embodiment is shown, wherein sub-pixels SP of the first region A1 and gate lines GL for driving sub-pixels SP of other regions besides the first region A1 are provided in the display area A / A of the display device 100.

[0112] Reference Figure 6 The display area A / A of the display panel 110 may include a first area A1 with a first resolution and a second area A2, a third area A3 and a fourth area A4 with a second resolution higher than the first resolution.

[0113] The first gate driver 121 that drives the sub-pixel SP of the first region A1 can be disposed on the first side (e.g., above) of the display region A / A. Additionally, the second gate driver 122 that drives the second region A2, the third region A3, and the fourth region A4 can be disposed on the second side (e.g., to the left) of the display region A / A.

[0114] Since the first gate driver 121 is positioned above the display area A / A, the area to the left of the display area A / A where the second gate driver 122 is located does not require an additional area for placing the first gate driver 121. Therefore, a single first gate driver 121 can be easily configured to drive the first area A1.

[0115] Furthermore, since the first gate driver 121 is disposed above the display area A / A, the first gate line GL1, which connects to the circuit elements disposed in the sub-pixel SP of the first area A1, can extend in a single direction (e.g., the vertical direction). Additionally, the second gate line GL2, used to drive the second area A2 and the third area A3, can extend in a direction intersecting the first gate line GL1 (e.g., the horizontal direction).

[0116] Since the first gate line GL1, which is connected to the circuit element in the sub-pixel SP of the first region A1 located in the upper central part of the display region A / A, extends in the vertical direction, the first gate line GL1 may not be provided in the second region A2 or the third region A3.

[0117] That is, the first gate line GL1, which is set separately to drive the first region A1, can be set only in the first region A1. Therefore, the first gate line GL1 does not need to be set in the second region A2, etc.

[0118] In addition, since the first region A1 is driven by a separately configured first gate line GL1, compensation for the data voltage Vdata provided to the sub-pixel SP of the first region A1 can be performed separately, thereby reducing or eliminating the difference between the image quality of the first region A1 and the image quality of the surrounding region.

[0119] Here, the second gate line GL2 can be electrically connected to circuit elements disposed in the sub-pixels SP of the second region A2 and the third region A3. Therefore, the second gate line GL2 can be disposed in the second region A2 and the third region A3, and can overlap with the first region A1 located between the second region A2 and the third region A3. Alternatively, the second gate line GL2 may not be electrically connected to the circuit elements disposed in the sub-pixels SP of the first region A1.

[0120] Reference Figure 7 In scenario 3, the second gate line GL2 is set in the fourth region A4, located at the lower part of the display area A / A. The second gate line GL2 can also be set in the second region A2 and the third region A3, located in the upper region of the display area A / A. Therefore, the second region A2, the third region A3, and the fourth region A4 can be driven by the second gate line GL2.

[0121] The first gate line GL1 can be disposed in the first region A1 of the display area A / A. Furthermore, the first gate line GL1 can extend in a direction intersecting the second gate line GL2, and can be electrically connected to circuit elements disposed in the sub-pixel SP of the first region A1.

[0122] The second gate line GL2 can be disposed in the first region A1, and may not be electrically connected to the circuit elements disposed in the sub-pixel SP of the first region A1. That is, the second gate line GL2 can extend in a direction intersecting the first gate line GL1 in the first region A1, so as to extend through the first region A1.

[0123] Since the first gate line GL1 and the second gate line GL2 extend in the first region A1 along the direction of intersection, at least a portion of the first gate line GL1 can be set on a different layer than the second gate line GL2.

[0124] For example, the portion of the first gate line GL1, excluding the portion of the gate of the circuit element formed in the sub-pixel SP of the first region A1, can be disposed on the layer where the data line DL is disposed. Therefore, short circuits can be prevented in the region where the first gate line GL1 intersects with the second gate line GL2.

[0125] Since the first gate line GL1 and the second gate line GL2 extend in the intersecting direction, it is convenient to arrange the first gate driver 121 and the first gate line GL1 for driving the first region A1. In addition, the second gate line GL2 for driving the second region A2 and the third region A3 can be provided with a structure that can operate in a dual-feed manner.

[0126] Additionally, refer to Figure 7 In scenario 4, the first gate line GL1 can extend in the first region A1 of the display area A / A in a direction intersecting with the second gate line GL2. The first gate line GL1 can be electrically connected to circuit elements disposed in the sub-pixel SP of the first region A1.

[0127] Here, since the first region A1 includes a transparent region and has a low resolution, the first gate line GL1 can be set only in a portion of the first region A1, depending on the shape of the sub-pixel SP set in the first region A1.

[0128] Additionally, no second gate line GL2 can be set in the first region A1. The second gate line GL2 can be set such that the second gate line GL2 used to drive the second region A2 is set separately from the second gate line GL2 used to drive the third region A3, and no second gate line GL2 is set in the first region A1.

[0129] Since there is no second gate line GL2 that can be set in the first region A1, the transmittance of the first region A1 can be further improved, and the first gate line GL1 and the second gate line GL2 can be set on the same layer.

[0130] Figure 8 It shows Figure 7 The specific structure of case 4 shown.

[0131] Reference Figure 8 In the second region A2 and the third region A3 in the upper region of the display area A / A, the second gate line GL2, through which scan signals SCAN(N-1), SCAN(N) and EM are applied, can extend in the horizontal direction.

[0132] In the first region A1, a first gate line GL1, through which scan signals SCAN(N-1), SCAN(N), and EM are applied, can extend in a vertical direction intersecting with a second gate line GL2. Alternatively, no second gate line GL2 can be provided in the first region A1.

[0133] Since the gate line GL used to drive the first region A1 with low resolution and high transmittance is set separately from the gate line GL used to drive the second region A2 and the third region A3 with high resolution and low transmittance, it is beneficial to compensate for the data in the first region A1, thereby reducing or eliminating the image quality difference between the first region A1 and the surrounding regions.

[0134] Furthermore, since the first gate line GL1 for driving the first region A1 extends in a direction that intersects with the second gate line GL2, it is advantageous to arrange the first gate driver 121 and the first gate line GL1 for driving the first region A1.

[0135] Furthermore, in some cases, the second gate line GL2 can be set only in regions other than the first region A1, thereby further improving the transmittance of the first region A1.

[0136] Here, considering factors such as transmittance, image quality, and the arrangement of the gate line GL, the sub-pixels SP of the first region A1 with low resolution to increase transmittance can be set in various forms.

[0137] Figures 9A to 9C The arrangement structure of sub-pixels SP in the first region A1 of the display area A / A of the display device 100 according to an embodiment is shown.

[0138] Reference Figure 9A In the first region A1, sub-pixels SP can be set at low resolution to have high transmittance, enabling sensing operations using optical sensors.

[0139] For example, such as Figure 9A As shown, in the case where a single red sub-pixel R SP, a single blue sub-pixel B SP, and two green sub-pixels G SP constitute a single pixel, the light-emitting device and the like can be set in only four (4) of the sixteen (16) pixels to display the image.

[0140] In this configuration, the first gate line GL1 can be configured to extend through the area where image display pixels are located. Alternatively, a second gate line GL2 can be configured not only to extend through the image display pixels but also through the transparent area.

[0141] As described above, increasing the ratio of transparent areas in the first region A1 can improve the sensing performance of an optical sensor positioned to overlap with the first region A1.

[0142] In addition, the ratio of image display pixels in the first region A1 can be increased by a negligible value to improve the image quality of the first region A1, while still allowing sensing using an optical sensor.

[0143] Reference Figure 9B and Figure 9C The light-emitting device can be placed in eight (8) of the 16 pixel areas to display the image.

[0144] exist Figure 9B In the illustration, pixels equipped with light-emitting devices are connected in the horizontal direction. This pixel structure is applicable to situations where the first gate line GL1 and the second gate line GL2 extend in a single direction, as described in one of the above-mentioned arrangement structures.

[0145] In addition, Figure 9C In the illustration, pixels equipped with light-emitting devices are connected in the vertical direction. This pixel structure can be applied to situations where the first gate line GL1 and the second gate line GL2 extend in an intersecting direction, that is, the first gate line GL1 extends to intersect with the second gate line GL2.

[0146] exist Figure 9B or Figure 9C In the illustration, when the second gate line GL2 is set separately in the second region A2 and the third region A3 but not in the first region A1, a structure can be provided in which neither the first gate line GL1 nor the second gate line GL2 is set in the transparent region of the first region A1. Therefore, the transmittance of the first region A1 can be maximized while the reduction in the resolution of the first region A1 can be minimized.

[0147] According to the embodiment described above, since the low-resolution area is set in a portion of the display area A / A, the display device 100 can have an optical sensor that is set in the low-resolution area and is capable of performing sensing. The optical sensor is located on a surface of the low-resolution area opposite to the image display surface of the low-resolution area.

[0148] Therefore, the optical sensor required for the display device 100 can be easily installed in the display panel 110, while preventing the increase of the non-display area N / A of the display panel 110.

[0149] In addition, since the first gate line GL1 used to drive the low-resolution region is set separately from the second gate line GL2 used to drive the high-resolution surrounding region, it is beneficial to compensate for the low-resolution region, thereby reducing or eliminating the image quality difference between the low-resolution region and the high-resolution region.

[0150] Furthermore, the arrangement in which the first gate line GL1 for driving the low-resolution region extends in a direction intersecting with the second gate line GL2 for driving the high-resolution surrounding region facilitates the replacement of the separately configured first gate driver 121 and first gate line GL1 for driving the low-resolution region.

[0151] The foregoing description has been provided to enable any person skilled in the art to implement and use the technical ideas of the invention, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and drawings provide examples of the technical ideas of the invention and are for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical ideas of the invention. Therefore, the scope of the invention is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of the invention should be interpreted based on the appended claims, and all technical ideas within their equivalents should be interpreted as being included within the scope of the invention.

[0152] Cross-references to related applications

[0153] This application claims priority to Korean Patent Application No. 10-2019-0117716, filed on September 24, 2019, which is incorporated herein by reference for all purposes as if fully set forth herein.

Claims

1. A display device, the display device comprising: The display area includes a first area and a second area, the first area having a first resolution, and the second area located to one side of the first area and having a second resolution higher than the first resolution; Multiple first gate lines, the multiple first gate lines being electrically connected to circuit elements disposed in sub-pixels of the first region and extending in a first direction; as well as Multiple second gate lines, which are insulated from circuit elements disposed in sub-pixels of the first region and electrically connected to circuit elements disposed in sub-pixels of the second region, and extend in the first direction. Some of the multiple second gate lines overlap with the first region.

2. The display device according to claim 1, wherein, The display area also includes a third area, which is located on the other side of the first area and has the second resolution.

3. The display device according to claim 2, wherein, The plurality of first gate lines are insulated from the circuit elements disposed in the sub-pixels of the third region, and The plurality of second gate lines are electrically connected to circuit elements disposed in the sub-pixels of the third region.

4. The display device according to claim 2, wherein, A portion of the plurality of first gate lines overlaps with at least one of the second region and the third region.

5. The display device according to claim 2, wherein, At least one sub-pixel of the first region, the second region, and the third region overlaps with the plurality of first gate lines or the plurality of second gate lines.

6. The display device according to claim 2, wherein, The maximum distance between two adjacent first gate lines among the plurality of first gate lines is greater than the maximum distance between two adjacent second gate lines among the plurality of second gate lines.

7. The display device according to claim 2, wherein, The plurality of second gate lines are electrically connected to circuit elements disposed in the sub-pixels of the second region and the third region.

8. The display device according to claim 2, wherein, The plurality of second gate lines are electrically connected to the circuit elements disposed in the sub-pixels of the second region and are insulated from the circuit elements disposed in the sub-pixels of the third region. The display device further includes a plurality of third gate lines, which are electrically connected to circuit elements disposed in sub-pixels of the third region and disposed in regions other than the first region and the second region.

9. The display device according to claim 8, wherein, The multiple second gate lines are set separately from the multiple third gate lines.

10. The display device according to claim 9, wherein, The multiple second gate lines and the multiple third gate lines are not set in the first region.

11. The display device according to claim 8, wherein, The multiple second gate lines are set in areas other than the first region and the third region.

12. The display device according to claim 1, further comprising at least one optical sensor disposed in the first region.

13. The display device according to claim 1, wherein, The first region includes a transparent region.

14. A gate driver, the gate driver comprising: A first gate driver drives a plurality of first gate lines electrically connected to circuit elements disposed in a sub-pixel of a first region having a first resolution; as well as A second gate driver drives multiple second gate lines that are electrically connected to circuit elements disposed in a sub-pixel of a second region having a second resolution higher than the first resolution. The plurality of second gate lines extend in the same direction as the plurality of first gate lines. The second gate driver is insulated from the circuit elements disposed in the sub-pixel of the first region, and Some of the multiple second gate lines overlap with the first region.

15. The gate driver according to claim 14, wherein, The second gate driver drives the plurality of second gate lines, which are electrically connected to circuit elements disposed in a sub-pixel of a third region located on the other side of the first region and having the second resolution.

16. The gate driver of claim 14, further comprising a third gate driver driving a plurality of third gate lines electrically connected to circuit elements disposed in a sub-pixel of a third region located on the other side of the first region and having the second resolution.

17. The gate driver of claim 16, wherein, The third gate driver is insulated from the circuit elements disposed in the sub-pixels of the first region.

18. The gate driver of claim 16, wherein, The third gate driver is insulated from the circuit elements disposed in the sub-pixel of the second region.

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