Display device

Abstract

A display device includes a substrate, a pixel array, and a first gate driving circuit. The pixel array is formed on the substrate. The pixel array includes a plurality of gate lines and a plurality of connection lines. The plurality of gate lines extends along a first direction. The plurality of connection lines extends along a second direction different from the first direction. The first gate driving circuit includes a plurality of first dummy scan drivers and a first start stage scan driver to a first end stage scan driver. The plurality of first dummy scan drivers and the first start stage scan driver to the first end stage scan driver are sequentially arranged on the substrate in a same direction as a first signal transmission direction.

Description

Technical Field

[0001] The present invention relates to a display device, and more particularly to a display device made of a substrate suitable for cutting in various proportions. Background Technology

[0002] Today, display panels are widely used, and there are increasing demands for their resolution and bezel width. However, gate drivers, traditionally designed on the left and right sides of the substrate, cannot support arbitrary cutting requirements. Therefore, providing a display device that solves these problems is an important issue in this field. Summary of the Invention

[0003] The purpose of this invention is to provide a display device to solve at least one of the above-mentioned problems.

[0004] This disclosure provides a display device. The display device includes a substrate, a pixel array, and a first gate driving circuit. The pixel array is formed on the substrate. The pixel array includes a plurality of gate lines and a plurality of interconnect lines. The plurality of gate lines extend along a first direction. The plurality of interconnect lines extend along a second direction other than the first direction. The first gate driving circuit includes a plurality of first dummy scan drivers and a first start-level scan driver to a first end-level scan driver. The plurality of first dummy scan drivers and the first start-level scan drivers to the first end-level scan drivers are sequentially arranged on the substrate in a direction that is the same as the first signal transmission direction.

[0005] This disclosure provides a display device. The display device includes a substrate, a pixel array, a first gate driving circuit, and a second gate driving circuit. The pixel array is formed on the substrate. The pixel array includes a plurality of gate lines and a plurality of connecting lines. The plurality of gate lines extend along a first direction. The plurality of connecting lines extend along a second direction opposite to the first direction. The first gate driving circuit is formed on the substrate and includes a first start-stage scan driver to a first end-stage scan driver and a plurality of first dummy scan drivers, wherein the first start-stage scan driver to the first end-stage scan driver are respectively connected to the plurality of gate lines via the plurality of connecting lines, and wherein the plurality of first dummy scan drivers and the first start-stage scan drivers to the first end-stage scan drivers are sequentially arranged on the substrate in a direction that is the same as the first signal transmission direction. The second gate driving circuit is formed on the substrate. The second gate driving circuit includes a second start-stage scan driver to a second end-stage scan driver and a plurality of second dummy scan drivers, wherein the second start-stage scan driver to the second end-stage scan driver and the plurality of second dummy scan drivers are sequentially arranged on the substrate in a direction that is the same as the second signal transmission direction, and wherein the second signal transmission direction is opposite to the first signal transmission direction.

[0006] In summary, the substrate of the display device disclosed herein can meet various size cutting requirements and has a narrow bezel effect, thereby reducing manufacturing costs and improving product adaptability. Attached Figure Description

[0007] To make the above and other objects, features, advantages and embodiments of this disclosure more apparent and understandable, the accompanying drawings are described below:

[0008] Figure 1 This is a schematic diagram of a display device according to some embodiments of the present disclosure.

[0009] Figure 2 This is a schematic diagram of a substrate of a display device according to some embodiments of the present disclosure.

[0010] Figures 3 to 10 This is a schematic diagram showing substrates cut to different proportions according to some embodiments of the present disclosure.

[0011] Figure 11 This is a schematic diagram of a display device according to some embodiments of the present disclosure.

[0012] Figure 12 This is a schematic diagram of pixel circuitry in a pixel array on a substrate according to some embodiments of the present disclosure.

[0013] Figure 13 as well as Figure 14 This is a schematic diagram of a scan driver according to some embodiments of the present disclosure.

[0014] Figure 15 This is a schematic diagram of a scan driver according to some embodiments of the present disclosure.

[0015] Figure 16 This is a schematic diagram of a display device according to some embodiments of the present disclosure.

[0016] Figure 17 This is a schematic diagram of a display device according to some embodiments of the present disclosure.

[0017] Figure 18 This is a schematic diagram of a scan driver according to some embodiments of the present disclosure.

[0018] Figure 19 This is a schematic diagram of the display cycle of a display device according to some embodiments of the present disclosure.

[0019] The attached figures are labeled as follows:

[0020] 100, 200i, 200j, 300: Display devices

[0021] 110, 210a, 210b, 210c1, 210c2: Substrate

[0022] 210d1, 210d2, 210e, 210f, 210i, 210j: substrate

[0023] 310, 310a, 310b, 310c1, 310c2: Substrate

[0024] 310d1, 310d2, 310e, 310f: base plate

[0025] 120, 220i, 220j, 320: Pixel array

[0026] 410, 510: Pull-up control circuit

[0027] 420, 520: Pull-up circuit

[0028] 430, 440, 530, 540: Pull-down circuits

[0029] 450, 460, 550, 560: Pull-down control circuit

[0030] F1, F2: Flexible circuit boards

[0031] SD1, SD2: Source Drivers

[0032] FLS1, FLS2: Fan-out cabling

[0033] DRu1, DRu2, DRu3, DRb1, DRIb2, DRb3: Drive circuit

[0034] GSD1, GSD2, GSD3: Source Driver Group

[0035] SD11, SD12, SD31, SD32, SD41: Source Driver

[0036] SD11~SD1m, SD21~SD2m, SD31~SD3m: Source drivers

[0037] G1~G2q, Gb1~Gbk, GDb1~GDbz: Scan driver

[0038] Gu1~Guk,GDu1~GDuz: Scan driver

[0039] G1~G2n,GLs,G1~Gy: Gate lines

[0040] L1~L2n, Ls, Lds, L1~Ly, Ld1~Ldz: Connecting lines

[0041] D1~D2p, D1, D2: Data cable

[0042] Dh: Horizontal direction

[0043] Dv: Vertical direction

[0044] TFT: Transistor

[0045] Td: Driving transistor

[0046] LED: Light-emitting element

[0047] VDD: System high voltage terminal

[0048] VSS, VSSQ: System low voltage terminal

[0049] P11~Py1, P12~Py2: Pixel circuit

[0050] Dst1, Dst2: Signal transmission direction

[0051] SC1~SCy, SCd1~SCdz, SCa: Control signals

[0052] STV: Start Signal

[0053] PDS: During scanning

[0054] PEM: During luminescence

[0055] S1: First side

[0056] S2: Second side

[0057] T11~T12, T21, T32~T34: Transistors

[0058] T41~T45, T51~T56, T61~T65: Transistors

[0059] P(n), K(n): Voltage regulator nodes

[0060] Q(n): Operation node

[0061] Q(n-6), Q(n-2), S(n): Nodes

[0062] HC1, HC7, LC1, LC2: Clock signals

[0063] Sr: Voltage regulation signal

[0064] Vf: Preset voltage

[0065] CUT1, CUT2: Cut lines

[0066] DC: Direct current signal

[0067] TL: Reset Cable

[0068] SL: Voltage Regulator Wiring Detailed Implementation

[0069] The following detailed description provides examples in conjunction with the accompanying drawings. However, the provided examples are not intended to limit the scope of this disclosure, and the description of the structural operation is not intended to limit the order of execution. Any structure resulting from the recombination of elements and producing an apparatus with equivalent functionality is within the scope of this disclosure. Furthermore, the illustrations are for illustrative purposes only and are not drawn to their original dimensions. For ease of understanding, the same or similar elements will be designated with the same symbols in the following description.

[0070] Unless otherwise specified, the terms used throughout this specification and claims generally have their ordinary meaning in the context of this art, the disclosure, and the specific content. Furthermore, the terms “comprising,” “including,” “having,” “containing,” etc., as used herein, are open-ended terms, meaning “including but not limited to.” Additionally, the term “and / or” as used herein includes any one or more of the related listed items and all combinations thereof.

[0071] Please see Figure 1 , Figure 1 This is a schematic diagram of a display device 100 according to some embodiments of the present disclosure. Figure 1 As shown, the display device 100 includes a substrate 110, scan drivers G1 to G2q, a pixel array 120, and source drivers SD11 and SD12. In some embodiments, the scan drivers G1 to G2q are implemented using gate-on-array (GOA) technology and formed in the element layout area of ​​the substrate 110. In some embodiments, placing the scan drivers G1 to G2q and the source drivers SD11 and SD12 on the same side of the substrate 110 can achieve the effect of a narrow bezel.

[0072] In some embodiments, source drivers SD11 and SD12 can be packaged on flexible printed circuit boards F1 and F2 using chip-on-film (COF) technology. In some embodiments, source drivers SD11 and SD12 are respectively fan-out connected to the line fan-out of the component layout areas of scan drivers G1 to Gq and Gq+1 to G2q on substrate 110 via multiple fan-out traces FLS1 and FLS2.

[0073] In some embodiments, since the patterns of the transmission lines (e.g., data lines DL1-DL2p and connecting lines L1-L2q), pixels, and scan drivers G1-G2q in the pixel array 120 are repetitive, manufacturing costs can be reduced by exposing different exposure areas with the same exposure pattern using appropriate photomasks. In some embodiments, in order to ensure that the wiring in each exposure area can fan out and connect to each source driver (e.g., source drivers SD11 and SD22), the same number of scan drivers are interspersed between the data lines connected to the multiple fan-out traces electrically connected to each source driver.

[0074] For example, source driver SD11 is electrically connected to data lines DL1 to DLp on the component layout area of ​​scan drivers G1 to Gq via multiple fan-out traces FLS1. As another example, source driver SD12 is electrically connected to data lines DLp+1 to DL2p on the component layout area of ​​scan drivers Gq+1 to G2q via multiple fan-out traces FLS2.

[0075] In some embodiments, gate lines GL1 to GL2q extend along a first direction (e.g., horizontal direction Dh), and data lines DL1 to DL2p extend along a second direction (e.g., vertical direction Dv). In some embodiments, scan drivers G1 to G2q are arranged along the horizontal direction Dh. In some embodiments, connecting lines L1 to Lq extending along the vertical direction Dv connect the corresponding gate lines GL1 to GLq to the scan drivers G1 to Gq. Similarly, connecting lines Lq+1 to L2q connect the corresponding gate lines GLq+1 to GL2q to the scan drivers Gq+1 to G2q.

[0076] Please see Figure 2 . Figure 2 This is a schematic diagram of the substrate 110 of a display device 100 according to some embodiments of the present disclosure. Figure 2 As shown, the first side S1 of the substrate 110 has three gate drive circuits GDb1 to GDb3. In some embodiments, more or fewer gate drive circuits may be provided depending on the horizontal resolution of the substrate 110, thereby avoiding impedance voltage drop caused by long gate lines.

[0077] In some embodiments, the component layout region of a gate drive circuit (e.g., gate drive circuit DRb1) is fan-out mated with a plurality of source drivers (e.g., m source drivers). To meet the aforementioned exposure and mating requirements, the total number of scan drivers (e.g., scan drivers Gb1-Gbk and GDb1-GDbz) in a gate drive circuit (e.g., gate drive circuit DRb1) is a multiple of the number of the m source drivers. In other words, the number of the plurality of source drivers is a factor of the total number of scan drivers (e.g., scan drivers Gb1-Gbk and GDb1-GDbz) in a gate drive circuit (e.g., gate drive circuit DRb1).

[0078] In some embodiments, it is assumed that the total number of gate lines GLs on substrate 110 is "k". To drive k gate lines GLs, the gate drive circuit DRb1 will have at least k scan drivers Gb1 to Gbk. In some cases, the number "k" is usually not divisible by the aforementioned number of m source drivers, causing the k scan drivers to be unable to be evenly distributed among the data lines connected by the fan-out traces of the m source drivers. Therefore, scan drivers GDb1 to GDbz are additionally configured in the gate drive circuit DRb1 so that the total number of scan drivers (e.g., scan drivers Gb1 to Gbk and GDb1 to GDbz) in a gate drive circuit (e.g., gate drive circuit DRb1) is a multiple of the aforementioned number of m source drivers.

[0079] For example, m (e.g., 5) source drivers are connected to the component layout area of ​​the gate drive circuit DRb1, and the substrate 110 has k (e.g., 1456) gate lines GLs. In some embodiments, the substrate 110 can be cut at various ratios to obtain a substrate with a desired size. In some embodiments, to accommodate various ratio cuts, a cutting space needs to be reserved, and the total number of gate lines GLs on the substrate 110 needs to be greater than the maximum number of gate lines actually scanned. For example, if a substrate with a vertical resolution of 1440 pixels (or two substrates with a vertical resolution of 720 pixels) is to be cut, a cutting space of 16 pixels in the vertical direction needs to be reserved, so the substrate 110 contains 1456 gate lines GLs, of which 16 gate lines can be understood as dummy gate lines. In some embodiments, the gate drive circuit DRb1 is configured with at least 1456 scan drivers to drive the 1456 gate lines GLs. In some embodiments, since 1456 cannot be evenly distributed among the data lines connected by the fan-out traces of the five source drivers, the total number of scan drivers Gb1 to Gbk and GDb1 to GDbz included in the gate drive circuit DRb1 is set to be greater than the number of gate lines GLs on the substrate 110 (e.g., 1456) and divisible by the number of source drivers (e.g., 5). In some embodiments, the number of scan drivers included in the gate drive circuit DRb1 is 1520, and the 1520 scan drivers are evenly distributed among the lines (e.g., data lines) connected by the fan-out traces of the five source drivers. In this case, 304 drivers are allocated among the data lines connected by the fan-out traces of one source driver.

[0080] In some embodiments, one source driver drives 320 pixel channels (960 sub-pixels). In some embodiments, five source drivers drive 1600 pixel channels, and the five source drivers are connected to the component layout area of ​​a gate driver circuit DRb1, which includes a total of 1520 scan drivers Gb1 to Gbk and GDb1 to GDbz.

[0081] In some embodiments, connection lines Ls electrically connect scan drivers Gb1 to Gbk to the corresponding gate lines GLs. In some embodiments, scan drivers GDb1 to GDbz correspond to the corresponding connection lines Lds. In some embodiments, connection lines Lds are electrically isolated from the pixel array 120, that is, connection lines Lds do not electrically connect scan drivers GDb1 to GDbz to the pixel array 120. In some embodiments, connection lines Lds can be understood as dummy connection lines.

[0082] In some embodiments, scan drivers GDb1 to GDbz can be understood by a dummy scanner, and scan drivers Gb1 to Gbk can be understood by a start-stage scan driver to a tail-stage scan driver. In some embodiments, scan driver Gb1 is a start-stage scan driver, and scan driver Gbk is a tail-stage scan driver. In some embodiments, scan drivers GDb1 to GDbz and scan drivers Gb1 to Gbk are sequentially arranged on the first side S1 of substrate 110 along the same direction as the signal transmission direction Dst1.

[0083] In some embodiments, the configuration of gate drive circuits DRb2 and DRb3 is similar to that of gate drive circuit DRb1, and the connection relationship between gate drive circuits DRb2 and DRb3 and gate line GLs via corresponding connection lines is similar to that between gate drive circuit DRb1 and gate line GLs via connection lines Ls, which will not be described again here.

[0084] In some embodiments, gate drive circuits DRb1 to DRb3 and gate drive circuits DRu1 to DRu3 are disposed on opposite sides of substrate 110 (e.g., the first side S1 and the second side S2 of substrate 110). In some embodiments, since gate drive circuits DRb1 to DRb3 and DRu1 to DRu3 are provided on opposite sides of substrate 110, substrates cut from either the upper or lower sides (the first side S1 and the second side S2) of the substrate can be driven.

[0085] In some embodiments, the gate drive circuit DRu1 has at least k scan drivers Gu1 to Guk to drive k gate lines GLs. In some embodiments, the component layout area of ​​the gate drive circuit DRu1 is used to interface with m source drivers. In some cases, the number "k" is often not divisible by the number of m source drivers, causing the k scan drivers to be unable to be evenly distributed among the data lines connected by the fan-out traces of the m source drivers. Therefore, scan drivers GDu1 to GDuz are additionally configured in the gate drive circuit DRu1 so that the total number of scan drivers (e.g., scan drivers Gu1 to Guk and GDu1 to GDuz) in a gate drive circuit (e.g., the gate drive circuit DRu1) is a multiple of the number of m source drivers.

[0086] In some embodiments, connection lines Ls electrically connect scan drivers Gu1 to Guk to their respective gate lines GLs. In some embodiments, scan drivers GDu1 to GDuz correspond to their respective connection lines Lds. In some embodiments, connection lines Lds are electrically isolated from the pixel array 120, that is, connection lines Lds do not electrically connect scan drivers GDb1 to GDbz to the pixel array 120. In some embodiments, connection lines Lds can be understood as dummy connection lines.

[0087] In some embodiments, scan drivers GDu1 to GDuz can be understood by a dummy scanner, and scan drivers Gu1 to Guk can be understood by a start-level scan driver to a tail-level scan driver. In some embodiments, scan driver Gu1 is a start-level scan driver, and scan driver Guk is a tail-level scan driver. In some embodiments, scan drivers Gu1 to Guk and scan drivers GDu1 to GDuz are sequentially arranged on the second side S2 of substrate 110 along the same direction as signal transmission direction Dst1. In some embodiments, signal transmission direction Dst1 is opposite to signal transmission direction Dst2.

[0088] In some embodiments, the configuration of gate drive circuits DRu2 and DRu3 is similar to that of gate drive circuit DRu1, and the connection relationship between gate drive circuits DRu2 and DRu3 and gate line GLs via corresponding connection lines is similar to that between gate drive circuit DRu1 and gate line GLs via connection lines Ls, which will not be repeated here.

[0089] It is worth noting that in each of the gate drive circuits DRb1 to DRb3 on the first side S1 of the substrate 110, the dummy scan drivers (scan drivers GDb1 to GDbz) and the start-stage scan drivers to the end-stage scan drivers (scan drivers Gb1 to Gbk) are arranged along the signal transmission direction Dst1, and the dummy scan drivers (scan drivers GDb1 to GDbz) are arranged before the start-stage scan drivers to the end-stage scan drivers (scan drivers Gb1 to Gbk). In each of the gate drive circuits DRu1 to DRu3 on the second side S2 of the substrate, the start-stage scan drivers to the end-stage scan drivers (scan drivers Gu1 to Guk) and the dummy scan drivers (scan drivers GDu1 to GDuz) are arranged along the signal transmission direction Dst2, and the dummy scan drivers (scan drivers GDu1 to GDuz) are arranged after the start-stage scan drivers to the end-stage scan drivers (scan drivers Gu1 to Guk). In this way, the connecting line Ls can completely connect the gate drive circuits DRb1 and DRu3 on both sides (first side S1 and second side S2) from the start-stage scan driver to the tail-stage scan driver (scan driver Gb1~Gbk and Gu1~Guk) to the gate line GLs.

[0090] Please see Figure 3 , Figures 3 to 10 The diagram shows substrate 110 cut to different proportions according to some embodiments of the present disclosure. In some embodiments, the size of substrate 110 is 5120*1456 pixels. In other embodiments, substrate 110 may be implemented with other suitable sizes, and the present invention is not limited thereto.

[0091] like Figure 3 and Figure 4 As shown, a substrate can be cut from the top and bottom sides of the substrate 110 respectively (for example, substrate 210a or 210b can be cut from the first side S1 of the substrate 110, and substrate 310a or 310b can be cut from the second side S2 of the substrate 110). In some embodiments, the dimensions of substrates 210a and 310a are 3840 pixels * 720 pixels. In some embodiments, the dimensions of substrates 210b and 310b are 3840 pixels * 540 pixels. In other embodiments, the cut substrates can be implemented with other suitable dimensions, and the present invention is not limited thereto.

[0092] like Figure 5 and Figure 6As shown, two substrates can be cut from the top and bottom sides of the substrate 110 respectively (for example, substrates 210c1-210c2 or 210d1-210d2 can be cut from the first side S1 of the substrate 110, and substrates 310c1-310c2 or 310d1-310d2 can be cut from the second side S2 of the substrate 110). In some embodiments, the dimensions of substrates 210c1-210c2 and 310c1-310c2 are 1920 pixels * 720 pixels. In some embodiments, the dimensions of substrates 210d1-210d2 and 310d1-310d2 are 1920 pixels * 540 pixels. In other embodiments, the cut substrates can be implemented with other suitable dimensions, and the present invention is not limited thereto.

[0093] like Figure 7 and Figure 8 As shown, a substrate can be cut from one side of substrate 110 (for example, substrate 210e or 210f can be cut from the first side S1 of substrate 110). In some embodiments, substrate 210e has a size of 5140 pixels * 1440 pixels. In some embodiments, substrate 210f has a size of 3840 pixels * 1080 pixels. In other embodiments, the cut substrate can be implemented with other suitable sizes, and the present invention is not limited thereto.

[0094] like Figure 9 and Figure 10 As shown, a substrate can be cut from one side of substrate 110 (for example, substrate 310e or 310f can be cut from the second side S2 of substrate 110). In some embodiments, substrate 310e has a size of 5140 pixels * 1440 pixels. In some embodiments, substrate 310f has a size of 3840 pixels * 1080 pixels. In other embodiments, the cut substrate can be implemented with other suitable sizes, and the present invention is not limited thereto.

[0095] Please see Figure 11 , Figure 11 This is a schematic diagram of a display device 200i according to some embodiments of the present disclosure. In some embodiments, the substrate 210i of the display device 200i is self-... Figure 2 The first side S1 of the substrate 110 is cut out, therefore Figures 3 to 8 The arrangement of the scan drivers for each of the middle substrates 210a to 210f is similar to Figure 11 The arrangement of scan drivers in the gate drive circuit on substrate 210i.

[0096] like Figure 11As shown, the display device 200a includes a substrate 210i, gate driving circuits DRb1 to DRb3, a pixel array 220i, source driver groups GSD1 to GSD2, and source drivers SD31 to SD32. In some embodiments, the gate driving circuit DRb1 includes scan drivers GDb1 to GDbz, Gb1 to Gby, and Gby+1 to Gbk. In some embodiments, scan drivers GDb1 to GDbz are dummy scan drivers, and scan drivers Gb1 to Gby are start-level scan drivers to end-level scan drivers, wherein scan driver Gb1 is the start-level scan driver, and scan driver Gby is the end-level scan driver. In some embodiments, the scan drivers are dummy scan drivers. In some embodiments, scan drivers GDb1 to GDbz (dummy scan drivers) and scan drivers Gb1 to Gby (start-level scan drivers to end-level scan drivers) are sequentially arranged along the signal transmission direction Dst1 on the first side S1 of the substrate 210i.

[0097] In some embodiments, pixel array 220i includes gate lines GL1 to GLy and connecting lines Ld1 to Ldz, L1 to Ly, and Ly+1 to Lk. In some embodiments, the vertical resolution of pixel array 220i is determined by the number of gate lines GL1 to GLy. In some embodiments, connecting lines Ld1 to Ldz are dummy connecting lines, and connecting lines L1 to Ly connect scan drivers Gb1 to Gby to the corresponding gate lines GL1 to GLy. In some embodiments, gate lines GL1 to GLy are arranged sequentially on substrate 210i in the vertical direction based on their distance from gate driving circuit DRb1 from near to far, and connecting lines L1 to Ly connect gate lines GL1 to GLy sequentially to scan drivers Gb1 to Gby according to their distance from gate driving circuit DRb1 from near to far. For example, connection line L1 connects the gate line GL1, which is closest to the gate drive circuit DRb1, to the scan driver Gb1; connection line L2 connects the gate line GL2, which is the second closest to the gate drive circuit DRb1, to the scan driver Gb2; and connection line L3 connects the gate line GL3, which is the third closest to the gate drive circuit DRb1, to the scan driver Gb3. Figure 11As shown. In other embodiments, the connection lines L1 to Ly are interleaved to connect the gate lines GL1 to GLy to the scan drivers Gb1 to Gby according to their distance from the gate drive circuit DRb1 from near to far, and the invention is not limited thereto. For example, suppose that every three gate lines are connected to the gate drive circuit in an interleaved order, the gate line closest to the gate drive circuit is connected to the start-stage scan driver via a connection line, the third closest gate line is connected to the second-stage scan driver via another connection line, and the next closest gate line is connected to the third-stage scan driver via yet another connection line. Similarly, the fourth closest gate line is connected to the fourth-stage scan driver via another connection line, the sixth closest gate line is connected to the fifth-stage scan driver via another connection line, and the fifth closest gate line is connected to the sixth-stage scan driver via yet another connection line, and so on.

[0098] In some embodiments, the configuration of the gate drive circuit DRb2 is similar to that of the gate drive circuit DRb1, and the connection relationship of the gate drive circuit DRb2 to the gate lines GL1 to GLy via the corresponding connection lines is similar to that of the gate drive circuit DRb1 to the gate lines GL1 to GLy via the connection lines L1 to Lu, which will not be described again here.

[0099] In some embodiments, the source driver group GSD1 is used to interface with the component layout area of ​​the gate driver circuit DRb1. In some embodiments, the source driver group GSD1 includes m source drivers SD11 to SD1m. In some embodiments, in order for the fan-out traces of the m source drivers SD11 to SD1m to be fully interfaced with the component layout area of ​​the gate driver circuit DRb1, the total number of all scan drivers GDb1 to GDbz and Gb1 to Gbk in the gate driver circuit DRb1 is a multiple of the stated "m". In other words, the stated "m" is a factor of the total number of all scan drivers GDb1 to GDbz and Gb1 to Gbk in the gate driver circuit DRb1.

[0100] In some embodiments, q scan drivers (e.g., 304 scan drivers) are interspersed between each of the lines connected to the source drivers SD11 to SD1m, and each of the source drivers SD11 to SD1m is used to drive p pixel channels (e.g., 320 pixel channels or 960 sub-pixel channels).

[0101] In some embodiments, the display device 200i includes source driver groups GSD1 to GSD2 and source drivers SD31 to SD32. Source driver group GSD1 includes five source drivers SD11 to SD1m, and source driver group GSD2 includes five source drivers SD21 to SD2m, with each of the aforementioned source drivers driving 320 pixel channels. In other words, the horizontal resolution of the display device 200i is 3840 pixels. In other embodiments, the horizontal resolution of the display device 200i may vary depending on the size of the substrate 210i and the number of source drivers configured accordingly; this invention is not limited thereto.

[0102] Please see Figure 12 , Figure 12 This is a schematic diagram of pixel circuits P11 to Py2 in pixel array 220i on substrate 210i according to some embodiments of the present disclosure. Figure 12 As shown, the pixel array 220i includes pixel circuits P11 to Py1 and P12 to Py2.

[0103] In some embodiments, gate lines G1-G3 and data lines D1-D2 determine the column and row number of the pixel circuits. For example, data line D1 connects pixel circuits P11-Py1 in the first row to source driver SD1, and data line D2 connects pixel circuits P12-Py2 in the second row to source driver SD1. Gate line G1 connects pixel circuits P11-P12 in the first column to scan driver GOA1 via connection line L1, and gate line G2 connects pixel circuits P21-P22 in the second column to scan driver GOA2 via connection line L2. Gate line Gy connects pixel circuits Py1-Py2 in the Yth column to the corresponding scan driver via connection line Ly.

[0104] In some embodiments, each of the pixel circuits P11-Py1 and P12-Py2 includes a transistor TFT, a driving transistor Td, and a light-emitting element LED. The transistor TFT is used to set the data voltage to the gate terminal of the driving transistor Td. In some embodiments, the driving transistor Td and the light-emitting element LED are electrically coupled between the system high voltage terminal VDD and the system low voltage terminal VSS. In some embodiments, the conduction level of the driving transistor Td is determined according to the potential of the gate terminal of the driving transistor Td, so as to control the driving current from the system high voltage terminal VDD through the driving transistor Td and the light-emitting element LED to the system low voltage terminal VSS, thereby controlling the brightness of the light-emitting element LED.

[0105] Please see Figure 11 , Figure 13 as well as Figure 14 . Figure 13 as well as Figure 14 This is a schematic diagram of scan drivers Gn and GDn according to some embodiments of the present disclosure. In some embodiments, scan driver Gn outputs a scan signal SCa to the corresponding connection line La. In some embodiments, scan driver GDn is not activated.

[0106] In some embodiments, each of the scan drivers Gb1 to Gby (start-level scan driver to tail-level scan driver) of the display device 200i can be composed of... Figure 13 The scan driver Gn is implemented, and each of the scan drivers GDb1~GDbz and Gby+1~Gbk (virtual scan drivers) can be implemented by... Figure 14 The scan driver Gn is implemented.

[0107] like Figure 13 As shown, the scan driver Dn includes pull-up control circuit 410, pull-up circuit 420, pull-down control circuit 450 and 460, pull-down circuit 430 and pull-down circuit 440.

[0108] In some embodiments, by applying a voltage from node Q(n-6) to the gate of transistor T12 in pull-up control circuit 410, transistor T12 is turned on, and a clock signal HC7 is transmitted to the gate of transistor T11 to turn on transistor T11, thereby transmitting the system high voltage terminal VDD to operating node Q(n) via transistor T11. In some embodiments, node S(n) is located at the junction of the gate of transistor T11 and one end of transistor T12.

[0109] In some embodiments, when the transistor T21 in the pull-up circuit 420 is turned on according to the potential of the operating node Q(n), the clock signal HC1 is transmitted to the connection line La via the transistor T21, so that the scan driver Gn outputs the clock signal HC1 as the scan signal SCa.

[0110] In some embodiments, the scan signal SCa is transmitted via a connection line (e.g., connection line L1) to a connected gate line (e.g., gate line GL1), thereby turning on the transistor TFTs of pixel circuits P11 and P22 in the same column of pixel array 220i, and then transmitting corresponding data voltages to the gate terminals of the driving transistors Td in pixel circuits P11 and P22 via data lines D1 and D2, such as... Figure 11 as well as Figure 12 As shown.

[0111] In some embodiments, transistor T52 is turned on by applying the potential of operating node Q(n) to the gate of transistor T52 in pull-down control circuit 450, and the potential of system low voltage terminal VSSQ is transmitted to the gate of transistor T53 via transistor T52 to turn off transistor T53. In some embodiments, transistor T51 is turned on by applying clock signal LC1 to the gate of transistor T51 in pull-down control circuit 450, and the clock signal LC1 is transmitted to the gate of transistor T53 via transistor T51 to turn on transistor T53, and the clock signal LC1 is transmitted to the voltage regulator node P(n) via transistor T53, thereby pulling up the potential of voltage regulator node P(n) to turn on transistors T32 to T34 in pull-down circuit 430, thereby performing voltage regulation operation.

[0112] In some embodiments, by applying the potentials of nodes Q(n-2) and Q(n) to the gate terminals of transistors T55 and T52 respectively, transistors T55 or T52 are turned on, and the potential of the system low voltage terminal VSSQ is transmitted to the gate terminal of transistor T53 via transistors T55 or T52, thereby turning off transistor T53. In some embodiments, by applying the potentials of nodes Q(n-2) and Q(n) to the gate terminals of transistors T56 and T54 respectively, transistors T56 and T54 are turned on, and the potential of the system low voltage terminal VSSQ is transmitted to the voltage regulator node P(n) via transistors T56 and T54, thereby turning off transistors T32 to T34 in the pull-down circuit 430.

[0113] In some embodiments, when the potential of the regulated node P(n) has an enable level, transistor T32 is turned on, causing the potential of the system low-voltage terminal VSSQ to be transmitted to the operating node Q(n) via transistor T32, thereby turning off transistor T21. At this time, the scan driver Gn outputs the voltage of the system low-voltage terminal VSS as the scan signal SCa.

[0114] In some embodiments, the pull-down control circuit 460 changes the potential of the voltage regulator node K(n) according to the clock signal LC2, so that the pull-down circuit 440 operates according to the voltage regulator node K(n). In some embodiments, transistors T61 to T66 in the pull-down control circuit 460 are similar to transistors T51 to T56 in the pull-down control circuit 450, and transistors T42 to T44 in the pull-down circuit 440 are similar to transistors T32 to T34 in the pull-down circuit 430, which will not be described in detail here.

[0115] In some embodiments, by applying control signals ST and S(n+6) to transistors T45 and T41 respectively, transistors T45 and T41 are turned on, so that the potential of the system voltage terminal VSSQ is transmitted to the operating node Q(n) via transistors T45 or T41, thereby turning off transistor T21.

[0116] like Figure 14 As shown, the scan driver GDn includes pull-up control circuits 510, 520, 550 and 560, and pull-down control circuits 530 and 540. Compared to Figure 13 The difference between the scan driver Gn and the scan driver GDn is that the pull-up control circuit 510 is electrically isolated from the wires used to transmit the clock signal HC7 and the system high voltage terminal VDD, and the pull-up circuit 520 is electrically isolated from the wires used to transmit the clock signal HC1, so that the pull-up control circuit 510 and the pull-up circuit 520 are not activated. In some embodiments, the first terminals of transistors T12 and T11 of the pull-up control circuit 510 and transistor T21 of the pull-up circuit 520 are floating conductive. In other embodiments, the first terminals of transistors T12 and T11 of the pull-up control circuit 510 and transistor T21 of the pull-up circuit 520 are used to receive a preset voltage Vf. In still other embodiments, the pull-down control circuits 550 and 560 and the pull-down circuits 530 and 540 of the scan driver GDn are activated to output a regulated signal Sr to the corresponding connection line Lb, but the invention is not limited thereto. Figure 14 The other detailed circuit connections of the scan driver GDn are similar. Figure 13 The detailed circuit connections of the scan driver GD are not described here.

[0117] Please see Figure 15 , Figure 15 This is a schematic diagram of scan drivers GDb1 to GDbz and Gb1 to Gby according to some embodiments of this disclosure. In some embodiments, Figure 11 The gate drive circuit DRb1 of the display device 200i, and its scan drivers GDb1~GDbz and Gb1~Gby are all made of... Figure 13The scan driver Gn is implemented in this configuration. In this case, the continuity line TL between scan drivers GDb1~GDbz and scan drivers Gb1~Gby can be cut along the cutting line CUT1 using laser cutting technology, electrically isolating the continuity line TL between scan drivers GDb1~GDbz and scan drivers Gb1~Gby, and providing the start signal STV to scan driver Gb1, making scan drivers Gb1~Gby sequentially the start-stage scan driver to the end-stage scan driver. In some embodiments, scan drivers Gb1~Gby output scan signals SC1~SCy to the corresponding gate lines G1~Gy via connection lines L1~Ly, respectively. It should be noted that the continuity line TL between scan drivers GDb1~GDbz and scan drivers Gb1~Gby may contain more continuity lines (e.g., 7 lines), which depends on the signal configuration period of the scan drivers. In this case, all the connecting lines between the scan drivers GDb1 to GDbz and the scan drivers Gb1 to Gby can be cut along the cutting line CUT1 using laser cutting technology. Therefore, the present invention is not limited thereto.

[0118] Please see Figure 16 , Figure 16 This is a schematic diagram of a display device 200j according to some embodiments of the present disclosure. Figure 16 As shown, the display device 200j includes a substrate 210j, a pixel array 220j, and gate driving circuits GDb1 to GDb3 and GDu1 to GDu3.

[0119] In some embodiments, gate drive circuits GDb1 to GDb3 are disposed on the first side S1 of substrate 220j, and the scan drivers GDb1 to GDbz (dummy scan drivers) and scan drivers Gb1 to Gbk (start-stage scan drivers to tail-stage scan drivers) of each of the gate drive circuits GDb1 to GDb3 are sequentially arranged on the first side S1 of substrate 220j in the same direction as the signal transmission direction Dst1. In some embodiments, gate drive circuits GDu1 to GDu3 are disposed on the second side S2 of substrate 220j, and the scan drivers Gu1 to Guk (start-stage scan drivers to tail-stage scan drivers) and scan drivers GDu1 to GDuz (dummy scan drivers) of each of the gate drive circuits GDu1 to GDu3 are sequentially arranged on this side S2 of substrate 220j in the same direction as the signal transmission direction Dst2.

[0120] In some embodiments, the substrate 210j of the display device 200j is an uncut substrate. In some embodiments, the substrate 210j of the display device 200j corresponds to Figure 2 The substrate 210j in the display device 200j. In some embodiments, the elements on the substrate 210j of the display device 200j are arranged similarly / equally. Figure 2 The arrangement of components on substrate 110 is not described in detail here.

[0121] In some embodiments, if the display device 200j directly uses the uncut substrate 210j, only the gate driving circuit on one side needs to be scanned, so the gate driving circuit on the other side can be electrically isolated from the connection line Ls. For example, the outputs of the gate driving circuits DRu1 to DRu3 on the second side S2 of the substrate 210j can be cut off from the connection line Ls along the cutting line CUT2, and the gate driving circuits DRb1 to DRb3 on the first side S1 can be used to scan the gate line GLs. As another example, the outputs of the gate driving circuits DRb1 to DRb3 on the first side S1 of the substrate can be cut off from the connection line along the horizontal direction, and the gate driving circuits DRb1 to DRb3 on the second side S2 can be used to scan the gate line GLs.

[0122] In some embodiments, the output terminals of some of the scan drivers GDb1 to GDbz (dummy scan drivers) can be electrically connected to the voltage regulator trace SL to stabilize the potential of the connection line Lds (dummy connection line).

[0123] Please see Figure 17 , Figure 17 This is a schematic diagram of a display device 300 according to some embodiments of the present disclosure. Figure 17 As shown, the substrate 310 of the display device 300 is self- Figure 2 The second side S2 of the substrate 110 is cut out, therefore Figures 3 to 6 as well as Figures 9 to 10 The arrangement of the scan drivers for each of the middle substrates 310a to 310f is similar to... Figure 11 The arrangement of scan drivers in the gate drive circuit on substrate 310.

[0124] like Figure 11As shown, the display device 300 includes a substrate 310, gate driving circuits DRu1 to DRu3, a pixel array 320, source driver groups GSD1 to GSD3, and source driver SD41. In some embodiments, the gate driving circuit DRu1 includes scan drivers Gu1 to Guy, Guy+1 to Guk, and GDu1 to GDuz. In some embodiments, scan drivers GDu1 to GDuz are dummy scan drivers, and scan drivers Gu1 to Guy are start-level scan drivers to end-level scan drivers, wherein scan driver Gu1 is the start-level scan driver, and scan driver Guy is the end-level scan driver. In some embodiments, scan drivers Guy+1 to Guk are dummy scan drivers. In some embodiments, scan drivers Gu1 to Guy (start-level scan drivers to end-level scan drivers) and scan drivers GDu1 to GDuz (dummy scan drivers) are sequentially arranged along the signal transmission direction Dst2 on the second side S2 of the substrate 310.

[0125] In some embodiments, the pixel array 320 includes gate lines GL1 to GLy and connecting lines Ld1 to Ldz, L1 to Ly, and Ly+1 to Lk. In some embodiments, connecting lines Ld1 to Ldz are dummy connecting lines, and connecting lines L1 to Ly connect scan drivers Gb1 to Gby to the corresponding gate lines GL1 to GLy. In some embodiments, connecting lines L1 to Ly sequentially connect gate lines GL1 to GLy to scan drivers Gu1 to Guy according to the distance of gate lines GL1 to GLy from the gate driving circuit DRu1 from near to far. In other embodiments, connecting lines L1 to Ly partially interleave the connection of gate lines GL1 to GLy to scan drivers Gu1 to Guy according to the distance of gate lines GL1 to GLy from the gate driving circuit DRu1 from near to far, and the invention is not limited thereto.

[0126] In some embodiments, the source driver group GSD1 is used to interface with the component layout area of ​​the gate drive circuit DRu1. In some embodiments, the source driver group GSD1 includes m source drivers SD11 to SD1m. In some embodiments, in order for the fan-out traces of the m source drivers SD11 to SD1m to be fully interfaced with the component layout area of ​​the gate drive circuit DRu1, the total number of all scan drivers GDu1 to GDuz and Gu1 to Guk in the gate drive circuit DRb1 is a multiple of the stated "m". In other words, the stated "m" is a factor of the total number of all scan drivers GDu1 to GDuz and Gu1 to Guk in the gate drive circuit DRu1.

[0127] In some embodiments, q scan drivers (e.g., 304 scan drivers) are interspersed between each of the lines connected to the source drivers SD11 to SD1m, and each of the source drivers SD11 to SD1m is used to drive p pixel channels (e.g., 320 pixel channels or 960 sub-pixel channels).

[0128] In some embodiments, the display device 300 includes source driver groups GSD1 to GSD3 and source driver SD41. Each of the source driver groups GSD1 to GSD3 includes five source drivers, and each of the aforementioned source drivers is used to drive 320 pixel channels. In other words, the horizontal resolution of the display device 300 is 5120 pixels. In other embodiments, the horizontal resolution of the display device 300 may vary depending on the size of the substrate 310 and the number of source drivers configured accordingly, and the present invention is not limited thereto.

[0129] Please see Figure 18 as well as Figure 19 . Figure 18 This is a schematic diagram of scan drivers Gu1 to Guk and GD1 to GDuz according to some embodiments of the present disclosure. Figure 19 This is a schematic diagram of the display cycle of a display device 300 according to some embodiments of the present disclosure.

[0130] In some embodiments, Figure 17 In the gate drive circuit DRu1, each of the scan drivers Gu1~Guy, Guy+1~Guk, and GDu1~GDuz can be generated by... Figure 13The scan driver Gn is implemented. That is, the scan drivers Gu1 to Guy (start-level scan driver to tail-level scan driver) output scan signals SC1 to SCk, and the scan drivers Guy+1 to Guk and GDu1 to GDuz (dummy scan drivers) output scan signals SCy+1 to SCk and SCd1 to SCdz. In this case, the scan signals SCy+1 to SCk and SCd1 to SCdz generated by the scan drivers Guy+1 to Guk and GDu1 to GDuz (dummy scan drivers) can be set at the enable voltage time during the vertical blanking period of the display device 300, thereby preventing the pixel array 310 from being scanned. In some embodiments, a display cycle of the display device 300 includes a progressive scan period and a vertical blanking period. In some embodiments, the scan drivers Gu1 to Guy (start-level scan driver to tail-level scan driver) scan the gate lines G1 to Gy during the progressive scan period. In some embodiments, the length of the vertical blanking period is longer than the product of the total number of scan drivers GDu1 to GDuz (dummy scan drivers) and a horizontal scan period. In other embodiments, the length of the vertical blanking period is longer than the product of the total number of scan drivers Guy+1 to Guk and GDu1 to GDuz (dummy scan drivers) and a horizontal scan period. In some embodiments, the scan signals SC1 to SCk output by scan drivers Gu1 to Guy have an enable level in PDS during the scan period of the corresponding pixel column, thereby scanning the pixel array 320. In some embodiments, each pixel column of the display device 300 emits light row by row during the emission period EM. In other embodiments, each pixel column of the display device 300 emits light simultaneously, and the present invention is not limited thereto.

[0131] In other embodiments, Figure 17 In the gate drive circuit DRu1, each of the scan drivers Gu1~Guy, Guy+1~Guk, and GDu1~GDuz can be generated by... Figure 13 The scan driver Gn is implemented. Before entering the operation period of the scan drivers Guy+1~Guk and GDu1~GDuz (dummy scan drivers), the potential of each clock signal (e.g., clock signals HC1 and HC7) can be changed to a disabled level (e.g., a low logic level) to prevent the scan drivers Guy+1~Guk and GDu1~GDuz (dummy scan drivers) from operating.

[0132] In some other embodiments, Figure 17 In the gate drive circuit DRu1, each of the scan drivers Gu1 to Guy (start-stage scan driver to tail-stage scan driver) can be... Figure 13 The scan driver Gn is implemented in the system, and Figure 17The scan drivers Guy+1 to Guk and GDu1 to GDuz (dummy scan drivers) in the gate drive circuit DRu1 can be generated by... Figure 14 The scan driver GDn is implemented to make the dummy scan driver inactive.

[0133] In summary, the display devices 100, 200i, 200j, and 300 provided in this disclosure meet the exposure and docking requirements between the source driver and the scan driver on the array, and have a narrow bezel effect. Furthermore, the substrate 110 can be cut to various sizes, thereby reducing manufacturing costs and improving product adaptability.

[0134] Although this disclosure has been described above with reference to embodiments, it is not intended to limit this disclosure. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A display device, comprising: One substrate; A pixel array, formed on the substrate, includes: Multiple gate lines extending along a first direction; and Multiple connecting lines extend along a second direction different from the first direction; and A first gate driving circuit is formed on the substrate. The first gate driving circuit includes a first start-stage scan driver to a first end-stage scan driver and a plurality of first dummy scan drivers, wherein the first start-stage scan driver to the first end-stage scan driver are respectively connected to a plurality of gate lines via a plurality of connection lines. The plurality of the first dummy scan drivers and the first start-level scan driver to the first tail-level scan driver are sequentially arranged on the substrate in the same direction as a first signal transmission direction; Each of the plurality of the first dummy scan drivers includes: A pull-up control circuit, electrically isolated from a signal line corresponding to a first clock signal, so that the pull-up control circuit is not activated; and A pull-up circuit is electrically isolated from a signal line of a second clock signal corresponding to the pull-up circuit, and the control terminal of the pull-up circuit is electrically coupled to the pull-up control circuit so that the pull-up circuit does not operate. The display device further includes: a second gate driving circuit, wherein the second gate driving circuit and the first gate driving circuit are formed on opposite sides of the substrate; the second gate driving circuit includes a second start-level scan driver to a second end-level scan driver and a plurality of second dummy scan drivers, wherein the second start-level scan driver to the second end-level scan driver respectively correspond to the plurality of gate lines. The second start-stage scan driver to the second end-stage scan driver and a plurality of second dummy scan drivers are sequentially arranged on the substrate in the same direction as a second signal transmission direction, and the second signal transmission direction is opposite to the first signal transmission direction.

2. The display device of claim 1, wherein the plurality of the first dummy scan drivers are electrically isolated from the continuation lines from the first start-level scan driver to the first end-level scan driver.

3. The display device of claim 1, wherein the plurality of connection lines are sequentially connected to the first start-stage scan driver to the first end-stage scan driver according to the distance between the plurality of gate lines and the first gate driving circuit from near to far.

4. The display device as claimed in claim 1, further comprising: A first source driver group includes a plurality of first source drivers, wherein the plurality of first source drivers are fan-out connected to a first element layout region of the first gate drive circuit, and wherein the number of the plurality of first source drivers is a factor of the total number of the first start-stage scan driver to the first end-stage scan driver of the first gate drive circuit and the plurality of first dummy scan drivers.

5. The display device of claim 1, wherein the second start-stage scan driver to the second tail-stage scan driver are electrically isolated from the plurality of gate lines.

6. The display device of claim 1, wherein the second start-stage scan driver to the second end-stage scan driver are electrically connected to the plurality of gate lines, wherein a display cycle of the display device includes a progressive scan period and a vertical blanking period, wherein the second start-stage scan driver to the second end-stage scan driver scan the plurality of gate lines during the progressive scan period, wherein the plurality of second dummy scan drivers are enabled during the vertical blanking period, and wherein the duration of the vertical blanking period is greater than the product of a horizontal scan period and the number of the plurality of second dummy scan drivers.

7. The display device of claim 1, wherein before entering the operation period of the plurality of second dummy scan drivers, the potential of each clock signal can be changed to a disable level so that the plurality of second dummy scan drivers are not operated.

8. The display device of claim 1, further comprising: Multiple dummy connection lines, each corresponding to a multiple dummy scan driver, wherein the multiple dummy connection lines are used to receive DC signals.

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